A vertical D-MOSFET with trench isolation and improved channel structure and its preparation method

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method. The MOSFET comprises a plurality of juxtaposed MOS cells, each of which includes a drain, a source, a gate, a gate oxide layer, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P+ layer, a P well layer, and an N well layer. The gate has a triangular cross-sectional profile, and a polysilicon capping layer is deposited at the junction of the gate and the gate oxide layer. The gate oxide has a semi-elliptical cross-sectional profile, and the polysilicon capping layer has a triangular cross-sectional profile. The present invention optimizes the electric field distribution and carrier migration path by designing the gate cross-sectional profile to be triangular and controlling the gate oxide layer to be semi-elliptical. The triangular gate can reduce electric field concentration at the gate edge, reducing the risk of breakdown.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method thereof. Background Art

[0002] Unlike the lateral current path of traditional planar MOSFETs, the source, gate, and drain of vertical D-MOSFETs are stacked vertically, allowing current to flow vertically from the surface source to the bottom drain. Trench isolation involves etching deep trenches in the silicon substrate and filling them with insulating materials such as silicon dioxide (SiO2) or polysilicon.

[0003] An existing patent discloses an air-gap isolation structure for a trench MOSFET and its manufacturing method (publication number CN115966463A). The manufacturing method includes: forming a trench extending from the upper surface of an epitaxial layer of a first doping type into the interior thereof; forming a second dielectric layer within the trench, the second dielectric layer comprising a first portion covering the top sidewalls of the trench and a second portion located below the first portion; and forming a gate conductor within the cavity formed by the second dielectric layer surrounding the trench. The technology disclosed in this patent results in electric field concentration at the edges due to the gate design, and the trench isolation structure does not adequately suppress parasitic capacitance, resulting in an inadequately optimized carrier migration path, which limits the device's withstand voltage capability and dynamic performance. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a vertical D-MOSFET with trench isolation and improved channel structure and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a vertical D-MOSFET with trench isolation and an improved channel structure is provided, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell includes a drain, a source, a gate, a gate oxide layer, and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P+ layer, a P well layer, and an N well layer, wherein the gate has a triangular cross-sectional profile, and a polysilicon capping layer is deposited at the junction of the gate and the gate oxide layer; and wherein the gate oxide has a semi-elliptical cross-sectional profile.

[0006] Furthermore, the cross-sectional profile of the polysilicon covering layer is triangular, wherein extension layers are deposited on the edges of both sides of the polysilicon covering layer.

[0007] Furthermore, the material of the extension layer is titanium nitride or tantalum nitride.

[0008] Furthermore, the grid further includes a comb-shaped grid, wherein the comb-shaped grid includes seven longitudinal teeth and a transverse beam for connecting the seven longitudinal teeth.

[0009] Furthermore, a lower convex gate is formed downward at the junction of the N substrate layer and the N diffusion layer by ion implantation, wherein the cross-sectional height of the lower convex gate in the middle of a single MOS cell is higher than the cross-sectional height of the lower convex gates at both sides.

[0010] Furthermore, an upper recessed gate is formed upward at the junction of the N substrate layer and the N diffusion layer by ion implantation, wherein the cross-sectional height of the upper recessed gate in the middle of a single MOS cell is lower than the cross-sectional heights of the upper recessed gates at both sides.

[0011] Furthermore, a field oxide layer is deposited in the middle of a single MOS cell and located at the junction of the drain and the N substrate layer.

[0012] Furthermore, the lower convex gate or the upper concave gate is formed into a P-type structure layer by implanting boron element.

[0013] A method for preparing a vertical D-MOSFET with trench isolation and improved channel structure, the specific steps comprising:

[0014] S1. Based on the N substrate layer, an N diffusion layer, a P+ layer, a P well layer and an N well layer are sequentially formed by epitaxial growth technology;

[0015] S2, etching deep trenches on the surface of the semiconductor epitaxial layer and filling them with silicon dioxide to form trench isolation structures;

[0016] S3, forming a gate with a triangular cross-sectional profile in the gate region by photolithography and dry etching processes, and controlling the cross-sectional shape of the gate oxide layer to be a semi-elliptical shape;

[0017] S4, depositing a polysilicon capping layer at the junction of the gate and the gate oxide layer, and etching the polysilicon capping layer to form a triangular cross-sectional profile;

[0018] S5, depositing titanium nitride or tantalum nitride material on both sides of the polysilicon cover layer to form an extension layer;

[0019] S6, forming an upper concave gate with a low center and high sides by upward tilted ion implantation of boron elements;

[0020] S7. In the middle region of a single MOS cell, a field oxide layer is deposited at the junction of the drain and the N substrate layer.

[0021] The present invention provides a vertical D-MOSFET with trench isolation and improved channel structure and a preparation method. Compared with the existing technology, this method achieves the following effects:

[0022] 1. The present invention optimizes the electric field distribution and carrier migration path by designing the cross-sectional profile of the gate into a triangle and controlling the gate oxide layer to be semi-elliptical. The triangular gate can reduce the electric field concentration at the gate edge and reduce the breakdown risk.

[0023] 2. The present invention can enhance the electric field uniformity of the channel region by designing a semi-elliptical gate oxide layer, thereby reducing the on-resistance and increasing the switching speed. In addition, this structure significantly improves the current driving capability and reliability of the device.

[0024] 3. The present invention enhances the mechanical stability of the gate structure through the polysilicon capping layer. The high conductivity of the extension layer reduces the contact resistance. At the same time, the chemical inertness of the nitride inhibits interface oxidation, thereby reducing leakage current and improving the high-temperature stability of the device.

[0025] 4. The present invention forms a lower convex gate at the junction of the N substrate and the N diffusion layer through ion implantation, forming gradient doping in the vertical direction, thereby enhancing the longitudinal migration efficiency of carriers. At the same time, the middle high convex area can disperse the electric field strength and reduce the local breakdown probability, thereby improving the device's voltage resistance and conduction uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of Example 1 of the present invention;

[0027] Figure 2 This is a schematic diagram of Example 2 of the present invention;

[0028] Figure 3 This is a schematic diagram of Example 3 of the present invention;

[0029] Figure 4 This is a schematic diagram of Example 4 of the present invention;

[0030] Figure 5 This is a schematic diagram of Example 5 of the present invention;

[0031] Figure 6 This is a schematic diagram of Example 6 of the present invention.

[0032] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Polysilicon capping layer; 5. Gate oxide layer; 6. N substrate layer; 7. N diffusion layer; 8. P+ layer; 9. P well layer; 10. N well layer; 11. Extension layer; 12. Lower convex gate; 13. Upper concave gate; 14. Field oxide layer; 31. Comb gate. DETAILED DESCRIPTION

[0033] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1-6As shown, a method for preparing a vertical D-MOSFET with trench isolation and improved channel structure includes the following steps:

[0035] Step 1: Based on the N substrate layer 6, an N diffusion layer 7, a P+ layer 8, a P well layer 9, and an N well layer 10 are sequentially formed using epitaxial growth techniques. The N diffusion layer, P+ layer, P well layer, and N well layer are grown layer by layer on the N-type substrate using epitaxial growth techniques, with precise control of the doping concentration and thickness of each layer to form a vertical multi-layer doped structure. The N diffusion layer 7 creates a low-resistance current path, the P+ layer 8 provides high-concentration hole injection, and the P well layer 9 and N well layer 10 form a PN junction to optimize the carrier migration path. Furthermore, through layered epitaxial growth, precise matching of the doped regions is ensured, reducing the resistance of the vertical current path and improving carrier migration efficiency, thereby enhancing the device's conduction capability and current density.

[0036] Step 2: Deep trenches are etched into the surface of the semiconductor epitaxial layer and filled with silicon dioxide to form trench isolation structures. Deep reactive ion etching (DRIE) is used to form deep trenches in the epitaxial layer, which are then filled with silicon dioxide insulating material to physically isolate adjacent MOS cells. The high insulating properties of silicon dioxide effectively block lateral leakage currents. Deep trench isolation also significantly reduces parasitic capacitance and crosstalk between cells, improving breakdown voltage and device integration while enhancing withstand voltage stability, making it suitable for high-power applications.

[0037] Step 3: A triangular gate 3 is formed in the gate region through photolithography and dry etching, and the cross-sectional shape of the gate oxide 5 is controlled to be semi-elliptical. A photolithography mask is used to define the gate region, and a triangular gate structure is formed through dry etching (such as plasma etching). The gate oxide 5 is controlled to be semi-elliptical through an oxidation process. The triangular gate 3 has smooth edges, and the semi-elliptical oxide 5 has a gradient thickness distribution. Furthermore, the triangular gate 3 reduces electric field edge concentration, lowering the risk of breakdown. The semi-elliptical gate oxide 5 optimizes electric field uniformity in the channel region, reducing on-resistance and increasing switching speed, significantly enhancing device dynamic performance.

[0038] Step 4: Deposit a polysilicon capping layer 4 at the junction of the gate 3 and the gate oxide layer 5, and use an etching process to give it a triangular cross-sectional profile. Chemical vapor deposition (CVD) is used to deposit a polysilicon layer at the interface between the gate 3 and the gate oxide layer 5, and anisotropic etching is performed to form a triangular cross-sectional profile. The polysilicon capping layer 4 fills the interfacial gap, improving the interface contact. It also enhances the mechanical stability of the gate structure and reduces the interface contact resistance. The triangular cross-sectional profile further optimizes the electric field distribution, suppresses gate edge leakage current, and improves high-temperature operation reliability.

[0039] Step 5: Titanium nitride or tantalum nitride is deposited on both sides of the polysilicon capping layer 4 to form an extension layer 11. Highly conductive titanium nitride (TiN) or tantalum nitride (TaN) is deposited on both sides of the polysilicon capping layer 4 by physical vapor deposition (PVD) to form the extension layer 11. Nitride materials have high chemical stability and low resistance. Furthermore, the extension layer reduces the contact resistance between the gate and source / drain electrodes, improving current transfer efficiency. The chemical inertness of nitrides inhibits interfacial oxidation, reducing leakage current and enhancing the device's high-temperature tolerance.

[0040] Step 6: An upper recessed gate 13 is formed by upwardly angled ion implantation of boron. Using an angled ion implantation technique, boron is implanted at a specific angle at the interface between the N substrate layer 6 and the N diffusion layer 7, forming a P-type upper recessed gate 13 with a low doping concentration in the center and high concentrations on the sides. The low-doping region in the center alleviates electric field crowding near the drain, reducing leakage current. The high-doping regions on the sides enhance the gate's control over the channel, speeding up switching response while also improving dynamic characteristics and withstand voltage.

[0041] Step 7: Deposit a field oxide layer 14 in the middle region of a single MOS cell, at the junction of the drain 1 and the N substrate layer 6. Using a local oxidation process (LOCOS), field oxide layer 14 (SiO2) is grown in the middle region between the drain and N substrate layers 6, providing lateral isolation and covering potential parasitic capacitance areas. Field oxide layer 14 suppresses parasitic capacitance and leakage current between the drain and substrate, optimizing high-frequency performance. It also works in conjunction with the upper recessed gate 13 structure to disperse the electric field strength, improving the device's withstand voltage stability and high-frequency response efficiency.

[0042] Example 1

[0043] like Figure 1 As shown, according to one aspect of the present invention, a vertical D-MOSFET with trench isolation and an improved channel structure is provided. The device comprises several juxtaposed MOS cells. Each MOS cell includes a drain 1, a source 2, a gate 3, a gate oxide 5, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 6, an N diffusion layer 7, a P+ layer 8, a P well layer 9, and an N well layer 10. The gate 3 has a triangular cross-sectional profile, and a polysilicon cap layer 4 is deposited at the junction of the gate 3 and the gate oxide 5. The gate oxide 5 has a semi-elliptical cross-sectional profile. By designing the gate 3 to have a triangular cross-sectional profile and controlling the gate oxide 5 to have a semi-elliptical shape, the electric field distribution and carrier migration path are optimized. The triangular gate 3 reduces electric field concentration at the gate 3 edge, reducing the risk of breakdown, while the semi-elliptical gate oxide 5 enhances electric field uniformity in the channel region, thereby reducing on-resistance and increasing switching speed. This structure significantly improves the current drive capability and reliability of the device.

[0044] Example 2

[0045] like Figure 2 As shown, the cross-sectional profile of the polysilicon capping layer 4 is triangular, with extension layers 11 deposited on both sides of the polysilicon capping layer 4. The extension layer 11 is made of either titanium nitride or tantalum nitride. A polysilicon capping layer 4 with a triangular cross-section is introduced at the junction of the gate 3 and the gate oxide layer 5, and titanium nitride / tantalum nitride extension layers 11 are deposited on both sides of the polysilicon capping layer 4. The polysilicon capping layer 4 enhances the mechanical stability of the gate structure, while the high conductivity of the extension layer reduces contact resistance. The chemical inertness of the nitride inhibits interfacial oxidation, thereby reducing leakage current and improving the high-temperature stability of the device.

[0046] Example 3

[0047] like Figure 3 As shown, the gate 3 also includes a comb-shaped gate 31, which includes seven longitudinal teeth and transverse beams connecting the seven longitudinal teeth. The comb-shaped gate structure, consisting of seven longitudinal teeth and transverse connecting beams, increases the effective control area of ​​the gate. The distribution of the longitudinal teeth optimizes the lateral diffusion of current in the channel, reducing the hot spot effect caused by uneven current density, while the transverse beams enhance the overall structural strength of the gate 3. This design significantly improves the current carrying capacity and switching efficiency of the device.

[0048] Example 4

[0049] like Figure 4 As shown, a lower convex gate 12 is formed downward at the junction of the N substrate layer 6 and the N diffusion layer 7 through ion implantation. The cross-sectional height of the lower convex gate 12 in the middle of a single MOS cell is higher than that of the lower convex gates 12 on either side. Lower convex gate 12 is a P-type structural layer formed by implanting boron. Ion implantation forms the lower convex gate 12 at the junction of the N substrate 6 and the N diffusion layer 7, with the cross-sectional height of the middle region being higher than that of the two sides. This structure creates a vertical gradient doping, enhancing the efficiency of longitudinal carrier migration. The high convex region in the middle disperses the electric field strength, reducing the probability of local breakdown, thereby improving the device's withstand voltage capability and conduction uniformity.

[0050] Example 5

[0051] like Figure 5As shown, an upper recessed gate 13 is formed upward at the junction of the N substrate layer 6 and the N diffusion layer 7 through ion implantation. The cross-sectional height of the upper recessed gate 13 in the center of a single MOS cell is lower than that of the upper recessed gates 13 on either side. The upper recessed gate 13 is a P-type structure layer formed by implanting boron. Upward ion implantation is used to form the upper recessed gate 13 structure, with a lower center and higher sides. This design creates an asymmetric electric field distribution in the horizontal direction. The lowered center region alleviates electric field crowding near the drain 1, while the higher sides enhance the gate 3's ability to control the channel, thereby reducing leakage and improving the device's dynamic response characteristics.

[0052] Example 6

[0053] like Figure 6 As shown, an upper recessed gate 13 is formed upward at the junction of the N substrate layer 6 and the N diffusion layer 7 through ion implantation, wherein the cross-sectional height of the upper recessed gate 13 in the middle of a single MOS cell is lower than the cross-sectional height of the upper recessed gate 13 on both sides, and a field oxide layer 14 is deposited in the middle of the single MOS cell and at the junction of the drain 1 and the N substrate layer 6. The field oxide layer 14 is deposited in the middle region where the drain 1 and the N substrate layer 6 intersect. Combined with the upper recessed gate 13 structure, the field oxide layer 14 provides additional lateral isolation, suppressing the parasitic capacitance and leakage current between the drain 1 and the N substrate layer 6. At the same time, the upper recessed gate 13 structure with a low center and the field oxide layer 13 synergistically optimize the electric field distribution, significantly improving the high-frequency performance and withstand voltage stability of the device.

[0054] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A vertical D-MOSFET with trench isolation and improved channel structure, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain (1), a source (2), a gate (3), a gate oxide layer (5) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (6), an N diffusion layer (7), a P+ layer (8), a P well layer (9) and an N well layer (10), characterized in that: The cross-sectional profile of the gate (3) is triangular, and a polysilicon covering layer (4) is deposited at the junction of the gate (3) and the gate oxide layer (5); the cross-sectional profile of the gate oxide layer (5) is semi-elliptical; The cross-sectional profile of the polysilicon covering layer (4) is triangular, wherein the edges on both sides of the polysilicon covering layer (4) are deposited to form an extension layer (11); The material of the extension layer (11) is titanium nitride or tantalum nitride.

2. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1, wherein: The grid (3) further comprises a comb-shaped grid (31), wherein the comb-shaped grid (31) comprises seven longitudinal teeth and a transverse beam for connecting the seven longitudinal teeth.

3. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1, wherein: A lower convex gate (12) is formed downwardly at the junction of the N substrate layer (6) and the N diffusion layer (7) by ion implantation, wherein the cross-sectional height of the lower convex gate (12) in the middle of a single MOS cell is higher than the cross-sectional height of the lower convex gate (12) at both sides; The lower convex gate (12) is a P-type structural layer formed by injecting boron elements.

4. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1, wherein: An upper recessed gate (13) is formed upwardly at the junction of the N substrate layer (6) and the N diffusion layer (7) by ion implantation, wherein the cross-sectional height of the upper recessed gate (13) in the middle of a single MOS cell is lower than the cross-sectional height of the upper recessed gate (13) at both sides; The upper recessed gate (13) is a P-type structural layer formed by injecting boron elements.

5. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 4, wherein: A field oxide layer (14) is deposited in the middle of a single MOS cell and located at the junction of the drain (1) and the N substrate layer (6).

6. A method for preparing a vertical D-MOSFET with trench isolation and improved channel structure, characterized in that: The vertical D-MOSFET with trench isolation and improved channel structure as claimed in any one of claims 4 to 5, wherein the method for preparing the vertical D-MOSFET with trench isolation and improved channel structure comprises the following steps: S1, based on the N substrate layer (6), an N diffusion layer (7), a P+ layer (8), a P well layer (9) and an N well layer (10) are sequentially formed by epitaxial growth technology; S2, etching deep trenches on the surface of the semiconductor epitaxial layer and filling them with silicon dioxide to form trench isolation structures; S3, forming a gate (3) with a triangular cross-sectional profile in the gate region by photolithography and dry etching processes, and controlling the cross-sectional shape of the gate oxide layer (5) to be a semi-elliptical shape; S4, depositing a polysilicon capping layer (4) at the junction of the gate (3) and the gate oxide layer (5), and etching the polysilicon capping layer (4) to form a triangular cross-sectional profile; S5, depositing titanium nitride or tantalum nitride material on both sides of the polysilicon cover layer (4) to form an extension layer (11); S6, forming an upper concave gate (13) with a low center and high sides by upward tilted ion implantation of boron elements; S7. In the middle region of a single MOS cell, a field oxide layer (14) is deposited at the junction of the drain (1) and the N substrate layer (6).

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