Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, the semiconductor device comprises a semiconductor body of a first conduction type, and the semiconductor body comprises a first surface and a second surface; the semiconductor body further comprises a JEFT region of the first conductivity type and a first region, and the JEFT region and the first region are located on the first surface. The gate insulating layer is located on the first surface, the gate insulating layer comprises a first part and a second part, the first part covers at least part of the JEFT region, and the second part covers at least part of the first region; the thickness of the first part is larger than that of the second part in the direction perpendicular to the first surface; and the gate structure is positioned on one side, far away from the semiconductor body, of the gate insulating layer. By increasing the thickness of the gate insulating layer in the JEFT region of the MOSFET, the breakdown voltage of the JEFT region is enhanced, the starting capacitance of the device is reduced, and the starting speed of the device is increased.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] The planar MOSFET is a double-diffused MOS structure, whose channel is formed by a double-diffusion process and has the ability to withstand high voltages. It is the most widely used SiC MOSFET structure. Historically, in order to develop SiC MOSFETs with lower on-resistance and more advanced technology, the planar-gate SiC MOSFET has mainly gone through three process design iterations, including a central implanted P+ region, a split-gate design, and a buffer-gate design, which can reduce the gate-drain capacitance and improve the switching power loss of the device. At present, the specific on-resistance of the planar SiC MOSFET is still higher than the theoretical value. One reason is that the electron mobility at the SiC and SiO2 interface is extremely low, resulting in a high channel resistance. Another reason is that the JEFT width is relatively narrow and the doping concentration of the N-type drift region is relatively low, resulting in a high JEFT resistance. Nevertheless, some companies' planar SiC MOSFETs have also achieved remarkable results and breakthroughs in further reducing the on-resistance. Since the channel of the planar SiC MOSFET structure is formed on the (001) crystal plane, the channel mobility is relatively low. At the same time, the structure also has a JEFT region, making it difficult to further reduce the on-resistance of the device, and the conduction and switching losses are also relatively high. Moreover, the gate oxide thickness in the JEFT region of the SiC MOSFET is relatively thin, making it easy to form an electric field breakdown point. Summary of the Invention

[0003] This application provides a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle, which are used to reduce the turn-on capacitance of the device and increase the turn-on speed of the device.

[0004] To achieve the above object, the embodiments of this application provide the following technical solutions: On the one hand, a semiconductor device is provided, including a semiconductor body, which is set to the first conduction type. The semiconductor body further includes a first surface and a second surface that are oppositely arranged; the semiconductor body further includes a JEFT region that is set to the first conduction type, and the JEFT region is arranged on the first surface. The semiconductor body further includes a first region that is set to the first conduction type, and the first region is arranged on the first surface. The semiconductor body further includes a well region that is set to the second conduction type, and the well region is arranged on the first surface, and at least part of the well region is located between the first region and the JEFT region.

[0005] The gate insulating layer is disposed on the first surface. The gate insulating layer includes a first part and a second part. The first part covers at least a portion of the JEFT region, and the second part covers at least a portion of the first region. Along the direction perpendicular to the first surface, the thickness of the first part is greater than the thickness of the second part.

[0006] The gate structure is disposed on the side of the gate insulating layer away from the semiconductor body. The source electrode is disposed on the first surface.

[0007] The drain electrode is disposed on the second surface.

[0008] In the embodiments of the present application, the semiconductor device is a planar power MOSFET device. The gate insulating layer includes a first part and a second part. The first part covers at least a portion of the JEFT region, and the second part covers at least a portion of the first region. Along the direction perpendicular to the first surface, the thickness of the first part is greater than the thickness of the second part. By thickening the gate insulating layer above the JEFT region, the breakdown voltage of the region where the JEFT region is located is enhanced, the reliability of the device is improved, at the same time, the turn-on capacitance of the device is reduced, the turn-on speed of the device is increased, and the switching loss is reduced, thereby improving the overall efficiency of the device.

[0009] In some embodiments, the semiconductor body further includes a second region which is set to the second conductive type, and the second region is disposed on the first surface.

[0010] The semiconductor device further includes a Schottky metal layer disposed between the semiconductor body and the source electrode, and the Schottky metal layer forms a Schottky contact with the second region.

[0011] In some embodiments, the semiconductor device further includes an ohmic contact layer disposed between the semiconductor body and the Schottky metal layer. The ohmic contact layer forms ohmic contacts with the first region and the second region; the ohmic contact layer includes a through opening, and the opening exposes a portion of the second region. The Schottky metal layer is in electrical contact with the ohmic contact layer, and the Schottky metal layer forms a Schottky contact with the second region through the opening.

[0012] On the other hand, the embodiments of the present application further provide a method for manufacturing a semiconductor device, including forming a semiconductor body which is set to the first conductive type and includes a first surface and a second surface which are oppositely disposed; the semiconductor body further includes a JEFT region which is set to the first conductive type, and the JEFT region is disposed on the first surface; the semiconductor body further includes a first region which is set to the first conductive type, and the first region is disposed on the first surface; the semiconductor body further includes a well region which is set to the second conductive type, and the well region is disposed on the first surface, and at least a portion of the well region is located between the first region and the JEFT region.

[0013] A gate insulating layer is formed on the first surface. The gate insulating layer includes a first part and a second part. The first part covers at least part of the JEFT region, and the second part covers at least part of the first region. Along the direction perpendicular to the first surface, the thickness of the first part is greater than that of the second part.

[0014] A gate structure is formed on the side of the gate insulating layer away from the semiconductor body.

[0015] A source electrode is formed on the first surface.

[0016] A drain electrode is formed on the second surface.

[0017] In some embodiments, the material of the semiconductor body includes silicon carbide. Forming the gate insulating layer includes forming the first part, and the first part covers at least part of the JEFT region.

[0018] The semiconductor body is subjected to a first thermal oxidation treatment to form the second part on the first surface.

[0019] In some embodiments, forming the first part includes forming a single-crystalline silicon layer covering the first surface.

[0020] Part of the single-crystalline silicon layer is removed, and the remaining part covers at least part of the JEFT region.

[0021] The remaining part of the single-crystalline silicon layer is subjected to a second thermal oxidation treatment to form the first part, and the temperature of the second thermal oxidation treatment is lower than that of the first thermal oxidation treatment.

[0022] In some embodiments, the semiconductor body further includes a second region configured as a second conductivity type, and the second region is disposed on the first surface.

[0023] After forming the gate structure and before forming the source electrode, the manufacturing method further includes: Forming an interlayer dielectric layer that covers the gate structure and the first surface.

[0024] Forming a first contact hole in the interlayer dielectric layer, and the first contact hole exposes the first region and the second region.

[0025] Forming an ohmic contact layer in the first contact hole, and the ohmic contact layer makes an ohmic contact with the first region and the second region.

[0026] Forming a second contact hole in the interlayer dielectric layer, and the second contact hole exposes the ohmic contact layer and the second region.

[0027] Forming a Schottky metal layer in the second contact hole, the Schottky metal layer is in electrical contact with the ohmic contact layer, and the Schottky electrode makes a Schottky contact with the second region.

[0028] After forming the source electrode, the source electrode is in electrical contact with the Schottky metal layer. In an embodiment of the present application, a gate insulating layer is formed on the first surface. The gate insulating layer includes a first part and a second part. The first part covers at least part of the JEFT region, and the second part covers at least part of the first region. Along the direction Z perpendicular to the first surface, the thickness of the first part is greater than that of the second part. By thickening the thickness of the gate insulating layer in the MOSFET JEFT region, the breakdown voltage of the JEFT region is enhanced, the reliability of the device is improved, at the same time, the turn-on capacitance of the device is reduced, the turn-on speed of the device is increased, and the switching loss is reduced, improving the overall efficiency of the device.

[0029] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments. The substrate is used to carry the semiconductor device.

[0030] In yet another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as described in any of the above embodiments. The semiconductor device is electrically connected to the circuit board.

[0031] In yet another aspect, an embodiment of the present application further provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0032] The above power module, power conversion circuit, and vehicle have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the description of the embodiments in conjunction with the following drawings, where: Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application; Figure 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application; Figures 3 to 12 is a diagram of each step of manufacturing a semiconductor device provided by an embodiment of the present application; Figure 13 is a schematic structural diagram of a power module provided by an embodiment of the present application; Figure 14 is a schematic structural diagram of a power conversion circuit provided by an embodiment of the present application; Figure 15 is a schematic structural diagram of a vehicle provided by an embodiment of the present application. Detailed implementation manners

[0034] The following will clearly and completely describe the technical solutions in some embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to".

[0036] Hereinafter, the terms "first" and "second" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0037] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected, or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0038] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0039] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0040] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] Examples of the embodiments are shown in the drawings, where the same or similar reference numerals throughout denote the same or similar elements or elements having the same or similar functions. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.

[0042] The planar MOSFET is a double-diffused MOS structure, whose channel is formed by a double-diffusion process and has the ability to withstand high voltages. It is the most widely used SiC MOSFET structure. Historically, in order to develop SiC MOSFETs with lower on-resistance and more advanced features, planar-gate SiC MOSFETs have mainly gone through three process design iterations, including a central implanted P+ region, a split-gate design, and a buffer-gate design, which can reduce the gate-drain capacitance and improve the switching power loss of the device. At present, the specific on-resistance of planar SiC MOSFETs is still higher than the theoretical value. One reason is that the electron mobility at the SiC and SiO2 interface is extremely low, resulting in a high channel resistance. Another reason is that the JEFT width is relatively narrow and the doping concentration of the N-type drift region is relatively low, resulting in a high JEFT resistance. Nevertheless, some companies have also achieved remarkable results and breakthroughs in further reducing the on-resistance of planar SiC MOSFETs. Since the channel of the planar SiC MOSFET structure is formed on the (001) crystal plane, the channel mobility is relatively low. At the same time, the structure also has a JEFT region, making it difficult to further reduce the on-resistance of the device, and the conduction and switching losses are also relatively high. Moreover, the gate oxide thickness in the JEFT region of SiC MOSFETs is relatively thin, making it easy to form an electric field breakdown point.

[0043] To address the above problems, an embodiment of the present application provides a semiconductor device, as Figure 1 shown, Figure 1 is a schematic structural diagram of a semiconductor device 10 provided by an embodiment of the present application.

[0044] As Figure 1 shown, the semiconductor device 10 includes a semiconductor body 101 set to a first conductivity type, and the semiconductor body 101 includes a first surface P1 and a second surface P2 disposed opposite to each other; the semiconductor body 101 further includes a JEFT region 114 set to the first conductivity type, and the JEFT region 114 is disposed on the first surface P1; the semiconductor body 101 further includes a first region 103 set to the first conductivity type, and the first region 103 is disposed on the first surface P1; the semiconductor body 101 further includes a well region 113 set to a second conductivity type, and the well region 113 is disposed on the first surface P1, and at least a part of the well region 113 is located between the first region 103 and the JEFT region 114.

[0045] In the embodiments of the present application, the semiconductor body 101 and the first region 103 are both of the first conduction type, and the well region 113 is of the second conduction type. Exemplarily, the first conduction type is N-type and the second conduction type is P-type. Based on this, the first region 103, the well region 113, and the semiconductor body 101 form an NPN junction.

[0046] Continuing to refer to Figure 1 , the semiconductor device 10 further includes a gate insulating layer 104. The gate insulating layer 104 is disposed on the first surface P1. The gate insulating layer 104 includes a first portion 1041 and a second portion 1042. The first portion 1041 covers at least a part of the JEFT region 114, and the second portion 1042 covers at least a part of the first region 103. Along the direction Z perpendicular to the first surface P1, the thickness of the first portion 1041 is greater than the thickness of the second portion 1042, that is, the gate insulating layer 104 is a film layer with non-uniform thickness.

[0047] Continuing to refer to Figure 1 , the semiconductor device 10 further includes a gate structure 105, a source electrode 108, and a drain electrode 112. The gate structure 105 is disposed on the side of the gate insulating layer 104 away from the semiconductor body 101. The source electrode 108 is disposed on the first surface P1. The drain electrode 112 is disposed on the second surface P2. The gate structure 105, the source electrode 103, and the drain electrode 112 form three electrodes of the semiconductor device 10.

[0048] In the embodiments of the present application, the semiconductor device 10 is a planar power MOSFET device. The gate insulating layer 104 includes a first portion 1041 and a second portion 1042. The first portion 1041 covers at least a part of the JEFT region 114, and the second portion 1042 covers at least a part of the first region 103. Along the direction Z perpendicular to the first surface P1, the thickness of the first portion 1041 is greater than the thickness of the second portion 1042. By thickening the gate insulating layer 104 above the JEFT region 114, the breakdown voltage of the region where the JEFT region 114 is located is enhanced, the reliability of the device is improved, at the same time, the turn-on capacitance of the device is reduced, the turn-on speed of the device is increased, and the switching loss is reduced, thereby improving the overall efficiency of the device.

[0049] In some embodiments, as Figure 1 shown, the semiconductor body 101 further includes a second region 102 which is set to be of the second conduction type. The second region 102 is disposed on the first surface P1. Exemplarily, P-type ions are implanted in the second region 102, which can also be referred to as a "P+ contact region".

[0050] The semiconductor device 10 further includes a Schottky metal layer 107 disposed between the semiconductor body 101 and the source electrode 108. The Schottky metal layer 107 forms a Schottky contact with the second region 102. The Schottky metal layer 107, the second region 102, the semiconductor body 101, and the drain electrode 112 form a junction barrier Schottky diode. The cells of the junction barrier Schottky diode and the cells of the MOSFET jointly occupy the active region of the device, realizing the integration of the junction barrier Schottky diode and the planar power MOSFET device. Moreover, the junction barrier Schottky diode has characteristics such as low resistance and fast switching speed, which helps to improve the performance of the semiconductor device 10.

[0051] In some embodiments, as Figure 1 shown, the semiconductor device 10 further includes an ohmic contact layer 111 disposed between the semiconductor body 101 and the Schottky metal layer 107. The ohmic contact layer 111 forms an ohmic contact with the first region 103 and the second region 102. The ohmic contact layer 111 reduces the contact resistance and improves the conductivity of the device.

[0052] Exemplarily, by transmitting a turn-on voltage to the gate structure 105, when the semiconductor device 10 conducts forward and the operating current is small, the operating current flows from the source electrode 103 through the ohmic contact layer 111, the first region 103, the well region 113, the JEFT region 114, and the semiconductor body 101 to reach the drain electrode 112.

[0053] As Figure 1 shown, the ohmic contact layer 111 includes a through-opening D3. The opening D3 exposes a part of the second region 102. The Schottky metal layer 107 is in electrical contact with the ohmic contact layer 111, and the Schottky metal layer 107 forms a Schottky contact with the second region 102 through the opening D3, thereby realizing a specific rectifying function.

[0054] In this application, by integrating the Schottky barrier diode and the MOSFET on the same chip, the functional integration of the two devices is realized. This design not only reduces the space occupied by the device, but also improves the integration degree and efficiency of the device. The integrated device combines the advantages of the Schottky barrier diode and the MOSFET, and has characteristics such as low forward voltage drop, high switching speed, low switching loss, and high input impedance. This enables the device to have higher performance and efficiency in power electronics applications. The integrated device reduces the number of external components, simplifies the circuit design, reduces the system complexity and cost. At the same time, it also improves the reliability and stability of the system.

[0055] On the other hand, the embodiment of this application also provides a method for manufacturing a semiconductor device, as Figure 2 shown, Figure 2 is a flowchart of a method for manufacturing a semiconductor device provided by the embodiment of this application, Figures 3 to 12These are the diagrams of the steps for fabricating a semiconductor device provided by the embodiments of the present application.

[0056] As Figure 2 shown, the fabrication method includes the following steps S10 to S50: Step S10: As Figure 3 shown, a semiconductor body 101 is formed. The semiconductor body 101 is set to a first conductivity type. The semiconductor body 101 includes a first surface P1 and a second surface P2 that are oppositely arranged. The semiconductor body 101 further includes a JEFT region 114 that is set to the first conductivity type, and the JEFT region 114 is disposed on the first surface P1. The semiconductor body 101 further includes a first region 103 that is set to the first conductivity type, and the first region 103 is disposed on the first surface P1. The semiconductor body 101 further includes a well region 113 that is set to a second conductivity type, and the well region 113 is disposed on the first surface P1, and at least a part of the well region 113 is located between the first region 103 and the JEFT region 114.

[0057] Exemplarily, as Figure 3 shown, the conductivity type of the semiconductor body 101 is N-type. On the first surface P1 of the semiconductor body 101, a mask is formed by a photolithography process, an ion implantation region is defined, and P+ ion implantation is performed to form the well region 113. After removing the mask, a mask is formed again by a photolithography process, an ion implantation region is defined, and N+ ion implantation is performed to form the first region 103.

[0058] Exemplarily, the semiconductor body 101 further includes a second region 102 that is set to a second conductivity type, and the second region 102 is disposed on the first surface P1. For example, P-type ions are implanted into the second region 102, and the second region 102 can also be referred to as a "P+ contact region".

[0059] Step S20: As Figures 4 to 6 shown, a gate insulating layer 104 is formed on the first surface P1. The gate insulating layer 104 includes a first part 1041 and a second part 1042. The first part 1041 covers at least a part of the JEFT region, and the second part 1042 covers at least a part of the first region 103. Along the direction Z perpendicular to the first surface P1, the thickness of the first part 1041 is greater than the thickness of the second part 1042.

[0060] Exemplarily, the material of the semiconductor body 101 includes silicon carbide. Step S20: Forming the gate insulating layer 104 includes the following steps S201 to S202: S201: As Figures 4 to 5 shown, the first part 1041 is formed, and the first part 1041 covers at least a part of the JEFT region 114.

[0061] S202: As Figure 6As shown, a first thermal oxidation treatment is performed on the semiconductor body 101, and a second part 1042 is formed on the first surface P1.

[0062] Exemplarily, as Figure 6 shown, a first thermal oxidation treatment is performed on the semiconductor body 101. During the thermal oxidation treatment, silicon atoms on the surface of silicon carbide combine with oxygen atoms to form a dense silicon oxide layer on the first surface P1, which is the second part 1042 of the gate insulating layer 104.

[0063] For example, the above step S201: forming the first part 1041 includes the following steps S2011 to S2013: Step S2011: As Figure 4 shown, a single-crystalline silicon layer 115 covering the first surface P1 is formed.

[0064] Exemplarily, as Figure 4 shown, a single-crystalline silicon layer 115 is uniformly deposited on the first surface P1 of the semiconductor body 101 by techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0065] Step S2012: As Figure 5 shown, a part of the single-crystalline silicon layer 115 is removed, and the remaining part covers at least a part of the JEFT region 114.

[0066] S2013: As Figure 5 shown, a second thermal oxidation treatment is performed on the remaining part of the single-crystalline silicon layer 115 to form the first part 1041, and the temperature of the second thermal oxidation treatment is lower than that of the first thermal oxidation treatment.

[0067] Exemplarily, as Figure 5 shown, through processes such as photolithography and etching, a part of the single-crystalline silicon layer 115 is removed, and the remaining part covering at least a part of the JEFT region 114 is retained. Through thermal oxidation treatment, the remaining part of the single-crystalline silicon layer 115 forms silicon oxide, which is the first part 1041.

[0068] Step S30: As Figure 7 and Figure 8 shown, a gate structure 105 is formed, and the gate structure 105 is located on the side of the gate insulating layer 104 away from the semiconductor body 101.

[0069] Exemplarily, as Figure 7 shown, a conductive material is deposited on the gate insulating layer 104 by physical vapor deposition (PVD) or chemical vapor deposition (CVD). As Figure 8 shown, the required gate structure 105 is formed through a patterning process.

[0070] Exemplarily, after step S30 and before step S40, the preparation method of the present application further includes the following steps S31 to S35: Step S31: As Figure 8 shown, an interlayer dielectric layer 106 is formed, and the interlayer dielectric layer 106 covers the gate structure 105 and the first surface P1.

[0071] Exemplarily, as Figure 8 shown, a layer of insulating material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), is deposited on the gate structure 105 and the first surface P1 by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The interlayer dielectric layer 106 plays a role of electrical isolation and protection in the semiconductor device, helps prevent short circuits between different conductive layers, and enhances the stability and reliability of the device.

[0072] Step S32: As Figure 9 shown, a first contact hole D1 is formed in the interlayer dielectric layer 106, and the first contact hole D1 exposes the first region 103 and the second region 102.

[0073] Exemplarily, as Figure 9 shown, through photolithography and etching processes, such as dry etching or wet etching, a first contact hole D1 is formed in the interlayer dielectric layer 106, and the first contact hole D1 exposes the first region 103 and the second region 102. The main function of the first contact hole D1 is to provide an electrical connection path, enabling the subsequent formed metal interconnect layer to achieve electrical connection with the first region 103 and the second region 102 through this hole.

[0074] Step S33: As Figure 10 shown, an ohmic contact layer 111 is formed in the first contact hole D1, and the ohmic contact layer 111 forms an ohmic contact with the first region 103 and the second region 102.

[0075] Exemplarily, as Figure 10 shown, a layer of ohmic contact material is deposited in the first contact hole D1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Commonly used materials include metals such as titanium, aluminum, nickel, etc. and their alloys, as well as certain metal silicides such as titanium silicide, cobalt silicide, etc. The main function of the ohmic contact layer 111 is to provide a low-resistance electrical connection path to ensure that current can flow smoothly between the metal interconnect layer and the first region 103 and the second region 102.

[0076] Step S34: As Figure 11 shown, a second contact hole D2 is formed in the interlayer dielectric layer 106, and the second contact hole D2 exposes the ohmic contact layer 111 and the second region 102.

[0077] Exemplarily, asFigure 11 As shown, a second contact hole D2 is formed in the interlayer dielectric layer 106 by using photolithography and etching processes. The second contact hole D2 exposes the ohmic contact layer 111 and the second region 102. The second contact hole D2 is used to achieve electrical connection between different conductive layers inside the semiconductor device 10.

[0078] Step S35: As Figure 11 shown, a Schottky metal layer 107 is formed in the second contact hole D2. The Schottky metal layer 107 is in electrical contact with the ohmic contact layer 111, and the Schottky metal layer 107 forms a Schottky contact with the second region 102.

[0079] Exemplarily, as Figure 11 shown, a layer of Schottky metal layer material, such as nickel (Ni), platinum (Pt), palladium (Pd), etc., is deposited in the second contact hole D2 by using physical vapor deposition (PVD), chemical vapor deposition (CVD) or other deposition techniques. The Schottky metal layer 107 is in electrical contact with the ohmic contact layer 111 to ensure smooth current transmission, and at the same time forms a Schottky contact with the second region 102 to achieve a rectifying function.

[0080] Step S40: As Figure 11 shown, a source electrode 108 is formed on the first surface P1.

[0081] Exemplarily, a layer of source electrode material, such as aluminum (Al), copper (Cu), nickel (Ni), etc., is deposited on the first surface P1 by methods such as sputtering and evaporation. The source electrode 108 is in electrical contact with the Schottky metal layer 107.

[0082] Step S50: As Figure 12 shown, a drain electrode 112 is formed on the second surface P2.

[0083] Exemplarily, as Figure 12 shown, a layer of drain electrode material, such as aluminum (Al), copper (Cu), nickel (Ni), etc., is deposited on the second surface P2 by methods such as sputtering and evaporation.

[0084] Exemplarily, after step S40 and before step S50, the preparation method of the present application further includes the following steps S41 to S42: Step S41: A passivation layer 109 is formed, such as Figure 12As shown, a uniform passivation layer 109 is deposited on the surface of the device by methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The material of the passivation layer 109 includes silicon dioxide (SiO2), silicon nitride (Si3N4), etc. The passivation layer 109 is used to protect the surface of the semiconductor device 10 from being polluted and corroded by the external environment, and at the same time reduce the surface leakage current. An opening is formed in the passivation layer 109 through photolithography and etching processes to expose the source electrode for electrical connection to the external circuit.

[0085] Step S42: Form an insulating layer 110. As Figure 12 shown, an insulating layer 110 is covered on the surface of the device by methods such as spin coating, spraying or printing. The material of the insulating layer 110 is polyimide (PI), and a curing treatment is performed to provide additional protection and support for the semiconductor device 10.

[0086] In the embodiment of the present application, a gate insulating layer 104 is formed on the first surface P1. The gate insulating layer 104 includes a first part 1041 and a second part 1042. The first part 1041 covers at least part of the JEFT region, and the second part 1042 covers at least part of the first region 103. Along the direction Z perpendicular to the first surface P1, the thickness of the first part 1041 is greater than the thickness of the second part 1042. By thickening the thickness of the gate insulating layer 104 of the MOSFET JEFT region 114, the breakdown voltage of the JEFT region 114 is enhanced, the reliability of the device is improved, at the same time the on-capacitance of the device is reduced, the on-speed of the device is increased, and the switching loss is reduced, improving the overall efficiency of the device.

[0087] On the other hand, the embodiment of the present application also provides a power module. Figure 13 It is a schematic structural diagram of the power module provided by the embodiment of the present application.

[0088] As Figure 13 shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments. The substrate 201 is used to carry the semiconductor device 10.

[0089] Exemplarily, the power module 200 can be used as a power amplifier, a power converter, a power controller, a power management module or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is a device used to control the power flow. The power management module is used to manage the power supply to ensure stable and efficient distribution of the power to different parts of the electronic device. The power regulator is used to regulate the power output to meet the requirements of specific applications.

[0090] On the other hand, embodiments of the present application also provide a power conversion circuit. Figure 14 It is a schematic structural diagram of the power conversion circuit provided by the embodiments of the present application.

[0091] As Figure 14 shown, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion, or power factor correction.

[0092] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit. Among them, the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0093] On the other hand, embodiments of the present application also provide a vehicle. Figure 15 It is a schematic structural diagram of the vehicle provided by the embodiments of the present application.

[0094] As Figure 15 shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiments. After the power conversion circuit 300 converts alternating current into direct current, converts alternating current into alternating current, converts direct current into direct current, or converts direct current into alternating current, it is input to the load 401 to supply power to the load 401.

[0095] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application who thinks of changes or substitutions should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body, which is set to a first conduction type and includes a first surface and a second surface that are oppositely arranged; the semiconductor body further includes a JEFT region set to the first conduction type, and the JEFT region is disposed on the first surface; the semiconductor body further includes a first region set to the first conduction type, and the first region is disposed on the first surface; the semiconductor body further includes a well region set to a second conduction type, the well region is disposed on the first surface, and at least a part of the well region is located between the first region and the JEFT region; A gate insulating layer, which is disposed on the first surface, and the gate insulating layer includes a first part and a second part, the first part covers at least a part of the JEFT region, and the second part covers at least a part of the first region; Along the direction perpendicular to the first surface, the thickness of the first part is greater than the thickness of the second part; A gate structure, which is disposed on the side of the gate insulating layer away from the semiconductor body; A source electrode, which is disposed on the first surface; A drain electrode, which is disposed on the second surface.

2. The semiconductor device according to claim 1, wherein, The semiconductor body further includes a second region set to the second conduction type, and the second region is disposed on the first surface; The semiconductor device further includes a Schottky metal layer disposed between the semiconductor body and the source electrode, and the Schottky metal layer forms a Schottky contact with the second region.

3. The semiconductor device according to claim 2, wherein The semiconductor device further includes an ohmic contact layer disposed between the semiconductor body and the Schottky metal layer, and the ohmic contact layer forms an ohmic contact with the first region and the second region; The ohmic contact layer includes a through opening, the opening exposes a part of the second region, the Schottky metal layer is in electrical contact with the ohmic contact layer, and the Schottky metal layer forms a Schottky contact with the second region through the opening.

4. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a semiconductor body, the semiconductor body is set to a first conduction type and includes a first surface and a second surface that are oppositely arranged; the semiconductor body further includes a JEFT region set to the first conduction type, and the JEFT region is disposed on the first surface; the semiconductor body further includes a first region set to the first conduction type, and the first region is disposed on the first surface; the semiconductor body further includes a well region set to a second conduction type, the well region is disposed on the first surface, and at least a part of the well region is located between the first region and the JEFT region; Forming a gate insulating layer on the first surface, the gate insulating layer includes a first part and a second part, the first part covers at least a part of the JEFT region, and the second part covers at least a part of the first region; Along the direction perpendicular to the first surface, the thickness of the first part is greater than the thickness of the second part; Forming a gate structure, and the gate structure is located on the side of the gate insulating layer away from the semiconductor body; Forming a source electrode on the first surface; Forming a drain electrode on the second surface.

5. The preparation method according to claim 4, characterized in that, The material of the semiconductor body includes silicon carbide, and forming the gate insulating layer includes: Form a first part, where the first part covers at least a portion of the JEFT region; Perform a first thermal oxidation process on the semiconductor body to form a second part on the first surface.

6. The preparation method according to claim 5, wherein Forming the first part includes: Form a single-crystalline silicon layer covering the first surface; Remove a portion of the single-crystalline silicon layer, and the remaining portion covers at least a portion of the JEFT region; Perform a second thermal oxidation process on the remaining portion of the single-crystalline silicon layer to form the first part; the temperature of the second thermal oxidation process is lower than the temperature of the first thermal oxidation process.

7. The preparation method according to claim 4, wherein The semiconductor body further includes a second region configured to be of a second conductivity type, and the second region is disposed on the first surface; After forming the gate structure and before forming the source, the manufacturing method further includes: Form an interlayer dielectric layer that covers the gate structure and the first surface; Form a first contact hole in the interlayer dielectric layer, and the first contact hole exposes the first region and the second region; Form an ohmic contact layer in the first contact hole, and the ohmic contact layer forms an ohmic contact with the first region and the second region; Form a second contact hole in the interlayer dielectric layer, and the second contact hole exposes the ohmic contact layer and the second region; Form a Schottky metal layer in the second contact hole, the Schottky metal layer is in electrical contact with the ohmic contact layer, and the Schottky metal layer forms a Schottky contact with the second region; After forming the source, the source is in electrical contact with the Schottky metal layer.

8. A power module, characterized in that, Includes: At least one semiconductor device as described in any one of claims 1 to 3; A substrate for carrying the semiconductor device.

9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 3, and the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that, Includes: A load and the power conversion circuit as described in claim 9, where the power conversion circuit is configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

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