Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to separate source / drain regions included in at least one pair of two adjacent first transistors which are distributed at intervals in the length direction of a gate stack structure in the semiconductor device through a first isolation structure. The semiconductor device includes a semiconductor substrate, at least two first transistors, and a first isolation structure. The at least two first transistors are arranged on the semiconductor substrate at intervals in the first direction. The first direction is parallel to the length direction of the gate stack structure included in the first transistor. The first isolation structure is arranged between the source / drain regions of at least one pair of adjacent two first transistors.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Compared with planar transistors, fin field-effect transistors and gate-all-around transistors have advantages such as higher gate control ability. Based on this, when the transistors included in a semiconductor device adopt fin field-effect transistors or gate-all-around transistors, the working performance of the semiconductor device can be improved. In addition, in the actual manufacturing process, source / drain etching and epitaxial processes are often used to form the source / drain regions included in the first transistor to meet the requirements of improving the formation quality of the source / drain regions and / or providing stress to the channel region through the epitaxial source / drain regions in actual application scenarios;

[0003] However, with the miniaturization of the contact pitch (CPP), the distance between two adjacent drain etching structures becomes smaller, and it is easy for the source / drain regions included in two adjacent transistors along the length direction of the gate stack structure to be combined together after source / drain epitaxy, which is likely to cause functional failure. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to separate the source / drain regions included in at least a pair of adjacent two first transistors spaced apart along the length direction of the gate stack structure in the semiconductor device through a first isolation structure, prevent functional failure of the semiconductor device, and be beneficial to the semiconductor device having good electrical performance.

[0005] To achieve the above object, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, at least two first transistors, and a first isolation structure. The at least two first transistors are arranged on the semiconductor substrate at intervals along a first direction. The first direction is parallel to the length direction of the gate stack structure included in the first transistor. The first isolation structure is disposed between the source / drain regions included in at least a pair of adjacent two first transistors.

[0006] In the case of adopting the above technical solution, the semiconductor device provided by the present invention includes a first isolation structure disposed between the source / drain regions included in at least a pair of adjacent two first transistors along the first direction. The first isolation structure is made of a non-conductive isolation material and is a non-conductive structure. Therefore, in the actual manufacturing process, after forming the source / drain etching structure and before epitaxially growing the source / drain regions, a first isolation structure is formed between two adjacent source / drain etching structures. Even if the contact pitch (CPP) in the semiconductor device is miniaturized, the source / drain regions included in at least a pair of adjacent two first transistors spaced apart along the length direction of the gate stack structure in the semiconductor device can be separated by the first isolation structure, which is beneficial to the semiconductor device having good electrical performance.

[0007] In one example, along the thickness direction of the semiconductor substrate, the first isolation structure includes a first isolation portion and a second isolation portion located on the first isolation portion. The materials of the first isolation portion and the second isolation portion are different.

[0008] In the case of adopting the above technical solution, during the actual manufacturing process, after forming the source / drain etching structure and before the epitaxial source / drain region, a first isolation material for manufacturing the first isolation portion can be formed first, and the first isolation material surrounds a first opening for manufacturing the second isolation portion. Then, after forming the second isolation portion in the first opening, according to the characteristic that the material of the second isolation portion is different from that of the first isolation portion, an etchant with selective etching can be used to remove the remaining first isolation material under the protection of the mask structure and the second isolation portion without using an additional mask structure, which is beneficial to improving the manufacturing efficiency of semiconductor devices and reducing the manufacturing cost.

[0009] In one example, the first transistor is a gate-all-around transistor, and the first transistor further includes an inner sidewall, and the inner sidewall is disposed between the gate stack structure and the source / drain region respectively. Moreover, the material of the first isolation portion is the same as the material of the inner sidewall included in the first transistor.

[0010] In the case of adopting the above technical solution, the material of the first isolation portion located below in the first isolation structure is the same as the material of the inner sidewall included in the first transistor. Based on this, during the actual manufacturing process, the first isolation portion can be formed simultaneously while forming the first isolation material for manufacturing the inner sidewall included in the first transistor, and the formation width of the source / drain region in the first direction can be adjusted by the thickness of the portion of the formed first isolation material located between the source / drain etching structures (i.e., controlling the width of the second isolation portion in the first direction). Next, according to the different materials of the first isolation portion and the second isolation portion, the first isolation material can be selectively etched, and only the portion for manufacturing the inner sidewall and the first isolation portion remains. Then, at least a pair of adjacent and isolated source / drain regions are formed in the released region. While improving the manufacturing efficiency of semiconductor devices, it can also meet the purpose of separating two adjacent source / drain regions in the first direction. Even if the contact pitch per gate (CPP) in the semiconductor device is scaled down, the electrical insulation between two source / drain regions in the first direction can be achieved through the first isolation structure, preventing the semiconductor device from malfunctioning.

[0011] In one example, the thickness of the first isolation portion along the thickness direction of the semiconductor substrate is greater than the width of the inner sidewall included in the adjacent first transistor along the first direction.

[0012] In one example, the first transistor is a gate-all-around transistor, and the first transistor further includes an inner sidewall, and the inner sidewall is disposed between the gate stack structure and the source / drain region respectively. At least part of the material included in the first isolation structure is the same as the material of the inner sidewall.

[0013] In one example, along a first direction, a source / drain region included in a first transistor adjacent to a first isolation structure is aligned with a sidewall of the first isolation structure.

[0014] In one example, a height of the first isolation structure is greater than a height of a source / drain region included in an adjacent first transistor.

[0015] In one example, the first transistor further includes a source / drain contact structure; the source / drain contact structure is located on the source / drain region and is aligned with a sidewall of the first isolation structure.

[0016] In one example, along the first direction, a width of the first isolation structure is greater than or equal to 5 nm and less than or equal to 15 nm.

[0017] In one example, along the first direction, a pitch of gate stack structures included in two first transistors located on two sides of the first isolation structure is less than or equal to 60 nm.

[0018] In one example, the semiconductor device further includes an insulating dielectric layer covering at least two first transistors. There is an interface between the insulating dielectric layer and the first isolation structure.

[0019] In one example, the semiconductor device further includes a second isolation structure and a second transistor. The second transistor is disposed above at least two first transistors. The second isolation structure is disposed between a source / drain region included in the second transistor and a source / drain region included in the first transistor.

[0020] In a second aspect, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: First, forming at least two fin structures spaced apart along a first direction on a semiconductor substrate, and forming a mask structure spanning the fin structures. Next, etching away portions of the fin structures exposed outside the mask structure; and forming a first isolation structure between at least a pair of adjacent remaining fin structures. Next, epitaxially growing source / drain regions on two sides of the remaining fin structures; at least a pair of adjacent source / drain regions spaced apart along the first direction are isolated by the first isolation structure. Next, etching away at least part of the mask structure; and forming a channel region from the remaining fin structures. Next, forming a gate stack structure around the channel region to obtain at least two first transistors. The first direction is parallel to a length direction of the gate stack structure.

[0021] In one example, along a thickness direction of the semiconductor substrate, each fin structure includes at least one semiconductor stack. Each semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. And, the forming the channel region from the remaining fin structures includes: removing each remaining sacrificial layer to form a channel region from the remaining channel layers.

[0022] In one example, a first isolation structure is formed between at least a pair of adjacent remaining fin structures, including: forming a first isolation material between at least a pair of adjacent remaining fin structures; the first isolation material encloses a first opening. Next, a second isolation portion is formed within the first opening; the materials of the first isolation material and the second isolation portion are different. Next, under the protection of the mask structure and the second isolation portion, the first isolation material is selectively etched; after the selective etching, the portion of the first isolation material remaining below the second isolation portion forms a first isolation portion; the first isolation structure includes the first isolation portion and the second isolation portion.

[0023] In one example, in the case where the fin structure includes at least one layer of semiconductor stack, after etching away the portion of the fin structure exposed outside the mask structure and before forming the second isolation portion within the first opening, the manufacturing method of the semiconductor device includes: removing the edge portions along both sides of the remaining sacrificial layer in a first direction to form a second opening; forming the first isolation material within the second opening and between at least a pair of adjacent remaining fin structures simultaneously. And after the selective etching, the portion of the first isolation material remaining within the second opening forms an inner sidewall.

[0024] In one example, forming the first isolation material within the second opening and between at least a pair of adjacent remaining fin structures simultaneously, and forming the second isolation portion within the first opening includes: forming a first isolation material that fills the second opening and extends to cover between at least a pair of adjacent remaining fin structures and on the mask structure. Next, forming a second isolation material that fills the first opening and extends to cover on the corresponding first isolation material of the mask structure. Next, planarizing the second isolation material and the first isolation material to expose the top of the mask structure; after the planarization, the remaining second isolation material forms the second isolation portion.

[0025] In one example, after etching away the portion of the fin structure exposed outside the mask structure and before epitaxially growing source / drain regions on both sides of the remaining fin structures, the manufacturing method of the semiconductor device includes: removing the edge portions along both sides of the remaining sacrificial layer in a first direction to form a second opening. Next, while forming the inner sidewall within the second opening, forming at least a part of the first isolation structure between at least a pair of adjacent remaining fin structures.

[0026] In one example, after forming source / drain regions on both sides of the remaining fin structures and before removing at least a part of the mask structure, the manufacturing method of the semiconductor device further includes: forming an insulating dielectric layer covering at least two first transistors; there is an interface between the insulating dielectric layer and the first isolation structure.

[0027] In one example, after forming an insulating dielectric layer covering at least two first transistors, the method for manufacturing a semiconductor device further includes: etching away the portion of the insulating dielectric layer located on at least a part of the source / drain regions to form contact holes, and one side wall of the contact holes along a first direction exposes a first isolation structure; and forming a source / drain contact structure in the contact holes.

[0028] For the beneficial effects of the second aspect and its various implementation manners in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0030] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure One ;

[0031] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Two ;

[0032] Figure 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Three ;

[0033] Figure 4 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Four ;

[0034] Figure 5 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Five ;

[0035] Figure 6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Six ;

[0036] Figure 7 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Seven ;

[0037] Figure 8 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention during the manufacturing process Figure Eight ;

[0038] Figure 9Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Nine ;

[0039] Figure 10 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten ;

[0040] Figure 11 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten One;

[0041] Figure 12 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Two;

[0042] Figure 13 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Three;

[0043] Figure 14 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Four;

[0044] Figure 15 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Five;

[0045] Figure 16 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Six.

[0046] Reference numerals: 11 is a semiconductor substrate, 12 is a first transistor, 13 is a gate stack structure, 14 is a first isolation structure, 15 is a source / drain region, 16 is a first isolation portion, 17 is a second isolation portion, 18 is an inner sidewall, 19 is a channel region, 20 is an insulating dielectric layer, 21 is a source / drain contact structure, 22 is a shallow trench isolation structure, 23 is a gate sidewall, 24 is a fin structure, 25 is a mask structure, 26 is a sacrificial layer, 27 is a channel layer, 28 is a second opening, 29 is a first isolation material, 30 is a first opening, 31 is a second isolation material. Detailed implementation manners

[0047] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0048] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where certain details are enlarged for clearer expression and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual requirements.

[0049] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0050] Furthermore, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0051] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] Compared with planar transistors, fin field-effect transistors and gate-all-around transistors have advantages such as higher gate control ability. Based on this, when the transistors included in a semiconductor device adopt fin field-effect transistors or gate-all-around transistors, the operating performance of the semiconductor device can be improved. In addition, in the actual manufacturing process, source / drain etching and epitaxial processes are often used to form the source / drain regions included in the first transistor to meet the requirements of improving the quality of source / drain region formation and / or providing stress to the channel region through the epitaxial source / drain regions in practical application scenarios;

[0053] However, with the scaling down of the contact gate pitch (CPP), the spacing between two adjacent drain etching structures becomes smaller, and it is easy for the source / drain regions included in two adjacent transistors along the length direction of the gate stack structure to be combined together after source / drain epitaxy, which is likely to cause functional failure.

[0054] To solve the above technical problems, embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. Among them, in the semiconductor device provided by the embodiments of the present invention, at least a pair of adjacent source / drain regions included in two first transistors spaced apart along the length direction of the gate stack structure in the semiconductor device are separated by a first isolation structure, preventing the semiconductor device from functional failure and being conducive to the semiconductor device having good electrical performance.

[0055] In a first aspect, embodiments of the present invention provide a semiconductor device. As Figure 14 and Figure 15 shown, the semiconductor device includes: a semiconductor substrate 11, at least two first transistors 12, and a first isolation structure 14. The at least two first transistors 12 are arranged at intervals on the semiconductor substrate 11 along a first direction. The first direction is parallel to the length direction of the gate stack structure 13 included in the first transistor 12. The first isolation structure 14 is disposed between the source / drain regions 15 included in at least a pair of adjacent two first transistors 12.

[0056] In the case of adopting the above technical solution, as Figure 14 and Figure 15 shown, the semiconductor device provided by the embodiments of the present invention includes a first isolation structure 14 disposed between the source / drain regions 15 included in at least a pair of adjacent two first transistors 12 along the first direction. The first isolation structure 14 is manufactured and formed by using a non-conductive isolation material and is a non-conductive structure. Therefore, in the actual manufacturing process, after forming the source / drain etching structure and before epitaxially growing the source / drain region 15, the first isolation structure 14 is formed between two adjacent source / drain etching structures. Even if the contact gate pitch (CPP) in the semiconductor device is scaled down, the first isolation structure 14 can separate at least a pair of adjacent source / drain regions 15 included in two first transistors spaced apart along the length direction of the gate stack structure 13 in the semiconductor device, preventing the semiconductor device from functional failure and being conducive to the semiconductor device having good electrical performance.

[0057] In an actual application process, the semiconductor substrate may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a silicon-on-insulator substrate on which no structures are formed.

[0058] Exemplarily, the above-mentioned semiconductor substrate may also be a semiconductor substrate on which some structures are formed. For example: in the case where the first transistor included in the semiconductor device provided by the embodiment of the present invention is applied to a transistor located in the second layer or a higher layer in an integrated circuit, the above-mentioned semiconductor substrate may include a semiconductor substrate, a lower-layer device formed on the semiconductor substrate, and an interlayer dielectric layer for isolating the lower-layer device, etc.

[0059] For the above-mentioned first transistor, in terms of device type, the first transistor may be a fin field-effect transistor or a gate-all-around transistor. Of course, it may also be any other transistor that needs to be disposed on the semiconductor substrate.

[0060] In terms of structure, the specific structure of the first transistor may be determined according to the device type and is not specifically limited herein.

[0061] Exemplarily, in the case where the first transistor is a fin field-effect transistor, the first transistor may include a channel region, source / drain regions, and a gate stack structure. The source / drain regions are disposed on both sides of the channel region along the length direction. The gate stack structure is disposed on the outer periphery of the channel region. The gate stack structure may include a gate dielectric layer and a gate electrode located on the gate dielectric layer.

[0062] Exemplarily, as Figure 14 and Figure 15 shown, in the case where the first transistor is a gate-all-around transistor, each first transistor 12 may include a channel region 19, source / drain regions 15, and a gate stack structure 13. The source / drain regions 15 are disposed on both sides of the channel region 19 along the length direction. The gate stack structure 13 surrounds the outer periphery of the channel region 19. Among them, the number of layers of nanostructures included in the channel region 19 in the embodiment of the present invention is not specifically limited. The channel region may include only one layer of nanostructures, or, as Figure 14 and Figure 15 shown, may also include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate 11. The gate stack structure 13 may include a gate dielectric layer and a gate electrode located on the gate dielectric layer. Among them, the gate dielectric layer surrounds the outer periphery of each layer of nanostructures and is formed on a part of the semiconductor substrate 11 corresponding to the gate electrode formation region.

[0063] The materials of the above-mentioned channel region and source / drain regions may include any semiconductor material such as silicon, silicon germanium, or germanium. The material of the gate dielectric layer may be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the above-mentioned gate may be a conductive material such as TiN, TaN, or TiSiN.

[0064] Optionally, as Figure 14 and Figure 15 shown, along the first direction, the source / drain region 15 included in the first transistor 12 adjacent to the first isolation structure 14 is aligned with the sidewall of the first isolation structure 14. Since the first isolation structure 14 is formed first and then the source / drain region 15 is formed, the sidewall of the source / drain region 15 must be conformal with the sidewall of the first isolation structure 14.

[0065] In some cases, as Figure 14 and Figure 15 shown, the first transistor 12 may further include gate sidewalls 23. The gate sidewalls 23 are disposed on both sides of the gate stack structure 13 along the length direction, so as to facilitate the formation of the gate stack structure 13 and electrically isolate the gate stack structure 13 from conductive structures such as the source / drain contact structure 21, thereby improving the electrical reliability of the semiconductor device. Among them, the material of the gate sidewalls 23 may include any insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.

[0066] Optionally, in the case where the first transistor is a gate-all-around transistor, the gate-all-around transistor may further include inner sidewalls 18. The inner sidewalls 18 are disposed between the gate stack structure 13 and the source / drain regions 15 respectively. The material of the inner sidewalls 18 may include any insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0067] In terms of the distribution of different first transistors, the embodiment of the present invention does not specifically limit the number of first transistors spaced apart along the first direction on the semiconductor substrate, and the spacing between the gate stack structures included in the first transistors adjacent along the first direction.

[0068] Exemplarily, along the first direction, the spacing between the gate stack structures included in the two first transistors located on both sides of the first isolation structure may be less than or equal to 60 nm.

[0069] Of course, along the first direction, the spacing between the gate stack structures included in the two first transistors located on both sides of the first isolation structure may also be set to a larger or smaller value.

[0070] In addition, in the actual application process, among two adjacent first transistors along the first direction, it is possible that the source region included in one first transistor is adjacent to the source region included in the other first transistor, or the source region included in one first transistor is adjacent to the drain region included in the other first transistor.

[0071] For the above-mentioned first isolation structure, as for the first direction, the width of the first isolation structure can be determined according to the spacing of the gate stack structures included in the two first transistors located on both sides of the first isolation structure, the width requirements of adjacent source / drain regions along the first direction, and the anti-leakage requirements for adjacent source / drain regions along the first direction. No specific limitation is made here.

[0072] Exemplarily, along the first direction, the width of the first isolation structure is greater than or equal to 5 nm and less than or equal to 15 nm. For example: the width of the first isolation structure can be 5 nm, 7 nm, 9 nm, 10 nm, 12 nm, 14 nm, or 15 nm, etc. In the direction parallel to the semiconductor substrate and perpendicular to the first direction (the second direction), the first isolation structure extends along the second direction.

[0073] In terms of height, the height of the first isolation structure can be equal to the height of the source / drain region included in the adjacent first transistor. Or, as Figure 14 and Figure 15 shown, the height of the first isolation structure 14 can also be greater than the height of the source / drain region 15 included in the adjacent first transistor 12, so as to ensure that while the adjacent source / drain regions 15 can be isolated, it is also beneficial to electrically insulate the adjacent source / drain contact structures 21, further preventing the failure of the semiconductor device function.

[0074] In one example, as Figure 16 shown, the first transistor 12 further includes a source / drain contact structure 21; the source / drain contact structure 21 is located on the source / drain region 15. Based on this, when the height of the first isolation structure 14 is greater than the height of the source / drain region 15 included in the adjacent first transistor 12, along the first direction, the source / drain contact structure 21 included in the first transistor 12 adjacent to the first isolation structure 14 can be aligned with the sidewall of the first isolation structure 14. Since the first isolation structure 14 naturally isolates the adjacent source / drain regions 15, there is no need to specifically form a contact hole and then fill it to form a contact. The source / drain contact structure 21 can be directly formed on the source / drain region 15, simplifying the process, eliminating the photolithography process, and improving the performance of the device.

[0075] Or, according to the actual wiring requirements, the source / drain contact structures included in the first transistors adjacent to the first isolation structure can also be electrically connected together.

[0076] In terms of materials, the embodiments of the present invention do not specifically limit the materials of the first isolation structure, as long as the source / drain regions included in two adjacent first transistors along the first direction can be separated by the first isolation structure. Exemplarily, the first isolation structure can be a dielectric isolation structure.

[0077] For example: The materials of the first isolation structure can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride, etc.

[0078] Exemplarily, when the first transistor is a gate-all-around transistor and the first transistor further includes an inner sidewall, at least part of the materials included in the first isolation structure can be the same as the materials of the inner sidewall. In this case, at least part of the first isolation structure can be formed while manufacturing the inner sidewall. Then, under the protection of the corresponding mask structure, the isolation materials for manufacturing the inner sidewall are selectively etched, so that the remaining parts of the isolation materials form the inner sidewall and at least part of the first isolation structure, which is beneficial to simplifying the manufacturing process of semiconductor devices.

[0079] Specifically, it can be that the materials of all regions of the first isolation structure are the same as the materials of the inner sidewall, or it can also be that the materials of some regions in the first isolation structure are the same as the materials of the inner sidewall (in this case, the part of the first isolation structure with the same material as the inner sidewall can be close to the semiconductor substrate or away from the semiconductor substrate).

[0080] In terms of structure, the first isolation structure can be a single-layer structure, that is, the materials of each region of the first isolation structure along the thickness direction of the semiconductor substrate can be the same. Or, the first isolation structure can also be a stacked structure composed of multiple dielectric layers.

[0081] Exemplarily, as Figure 14 and Figure 15 shown, along the thickness direction of the semiconductor substrate 11, the first isolation structure 14 can include a first isolation part 16 and a second isolation part 17 located on the first isolation part 16. Among them, the materials of the first isolation part 16 and the second isolation part 17 are different. In this case, as Figures 4 to 9 shown, in the actual manufacturing process, after forming the source / drain etching structure and before epitaxial source / drain regions 15, the first isolation material 29 for manufacturing the first isolation part 16 can be formed first, and the first isolation material 29 encloses a first opening 30 for manufacturing the second isolation part 17. Then, after forming the second isolation part 17 in the first opening 30, according to the characteristic that the materials of the second isolation part 17 and the first isolation part 16 are different, an etchant with selective etching can be used to remove the remaining first isolation material 29 under the protection of the mask structure 25 and the second isolation part 17, without using an additional mask structure, which is beneficial to improving the manufacturing efficiency of semiconductor devices and reducing the manufacturing cost.

[0082] Specifically, the materials and thicknesses of the first isolation portion and the second isolation portion in the embodiments of the present invention are not specifically limited and can be set according to the structure of the first transistor and actual requirements.

[0083] Exemplarily, the materials of the first isolation portion and the second isolation portion can be any two non-conductive isolation materials that are different from each other. For example, when the material of the first isolation portion is silicon oxide, the material of the second isolation portion can include silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride, etc.

[0084] Exemplarily, when the first transistor is a gate-all-around transistor and the first transistor further includes an inner sidewall, the material of the first isolation portion can be the same as the material of the inner sidewall included in the first transistor. In this case, the material of the first isolation portion located below in the first isolation structure is the same as the material of the inner sidewall included in the first transistor. Based on this, during the actual manufacturing process, as Figures 4 to 9 shown, while forming the first isolation material 29 for manufacturing the inner sidewall 18 included in the first transistor 12, the first isolation portion 16 can be formed together, and the formation width of the source / drain region 15 in the first direction can be regulated by the thickness of the portion of the formed first isolation material 29 located between the source / drain etching structures (i.e., controlling the width of the second isolation portion 17 in the first direction). Next, according to the different materials of the first isolation portion 16 and the second isolation portion 17, the first isolation material 29 can be selectively etched, and only the portion thereof for manufacturing the inner sidewall 18 and the first isolation portion 16 remains. Then, at least a pair of adjacent and isolated two source / drain regions 15 are formed in the released region. While improving the manufacturing efficiency of the semiconductor device, it can also meet the purpose of separating the two source / drain regions 15 adjacent in the first direction. Even when the contact pitch (CPP) in the semiconductor device is scaled down, the electrical insulation between the two source / drain regions 15 in the first direction can be achieved through the first isolation structure 14, preventing the semiconductor device from malfunctioning.

[0085] Specifically, the material of the first isolation portion can refer to the material of the inner sidewall included in the first transistor described above. The material of the second isolation portion can include any insulating dielectric material different from the materials of the first isolation portion and the inner sidewall. For example, when the materials of the first isolation portion and the inner sidewall are silicon oxide, the material of the second isolation portion can include silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride, etc.

[0086] In addition, as Figure 14 and Figure 15 shown, the thickness of the first isolation portion in the thickness direction of the semiconductor substrate can be greater than the width of the inner sidewall included in the adjacent first transistor in the first direction; or, it can also be equal to the width of the inner sidewall included in the adjacent first transistor in the first direction.

[0087] Wherein, when the thickness of the first isolation portion in the thickness direction of the semiconductor substrate is greater than the width of the inner sidewall included in the adjacent first transistor in the first direction, the manufacturing of the inner sidewall and the first isolation structure can be achieved only by simply increasing the deposition thickness of the first isolation material for manufacturing the first isolation portion and the inner sidewall, simplifying the manufacturing process. When the thickness of the first isolation portion in the thickness direction of the semiconductor substrate is equal to the width of the inner sidewall included in the adjacent first transistor in the first direction, at this time, the second isolation portion can be patterned, or another dielectric material can be formed after manufacturing the first isolation material and before forming the second isolation portion, so as to control the width of the second isolation portion in the first direction through the manufacturing of the other dielectric material; in this case, the first isolation structure may further include a third dielectric portion located between the first isolation portion and the second isolation portion, and the material of the third dielectric portion is different from the materials of the second isolation portion and the first isolation portion.

[0088] Of course, the material of the first isolation portion may also be different from the material of the inner sidewall. At this time, the first isolation material for manufacturing the first isolation portion can be formed after forming the inner sidewall, so as to improve the applicability of the semiconductor device provided by the embodiments of the present invention in different application scenarios.

[0089] In one example, as Figure 14 and Figure 15 shown, the semiconductor device may further include an insulating dielectric layer 20 covering at least two first transistors 12, so as to protect the source / drain regions 15 from the etching and cleaning operations for removing at least part of the mask structure 25 and the sacrificial layer 26, and improve the yield of the first transistors 12. There is an interface between the insulating dielectric layer 20 and the first isolation structure 14.

[0090] The material of the insulating dielectric layer may include any one of insulating materials such as silicon oxide, silicon oxynitride or silicon oxynitride, and no specific limitation is made here.

[0091] In one example, the semiconductor device may further include a second isolation structure and a second transistor. The second transistor is disposed above at least two first transistors. The second isolation structure is disposed between the source / drain regions included in the second transistor and the source / drain regions included in the first transistor, so as to improve the integration degree of the semiconductor device.

[0092] Among them, the second transistor can be any kind of transistor such as a fin field-effect transistor or the first transistor, as long as it can form a CFET device with the first transistor located below it. The conduction types of the second transistor and the first transistor located below it can be the same or different. In addition, it can be that the source region included in the second transistor is disposed above the source region included in the first transistor located below it, or it can be that the source region included in the second transistor is disposed above the drain region included in the first transistor located below it.

[0093] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The following will describe the manufacturing process according to Figures 1 to 16 the perspective view or cross-sectional view of the operations shown. Specifically, the method for manufacturing the semiconductor device includes the following steps:

[0094] First, as Figure 1 and Figure 2 shown, at least two fin structures 24 are formed on the semiconductor substrate 11 at intervals along a first direction, and a mask structure 25 is formed across the fin structures 24.

[0095] Among them, the structure and material of the semiconductor substrate can refer to the foregoing, and will not be elaborated here.

[0096] In addition, it can be understood that the above fin structures are used to manufacture the channel regions included in the first transistor. Therefore, the specific structure of the fin structures can be determined according to the device type of the first transistor and the structure of the channel regions included in the first transistor.

[0097] Exemplarily, when the first transistor is a fin field-effect transistor, the fin structure can be a single-layer structure, or the specific structure of the fin structure can be determined according to the structure of the channel regions included in the first transistor along the thickness direction of the semiconductor substrate.

[0098] Exemplarily, when the first transistor is a gate-all-around transistor, as Figure 1 and Figure 2As shown, along the thickness direction of the semiconductor substrate 11, each fin structure 24 includes at least one layer of semiconductor stack. Each layer of semiconductor stack includes a sacrificial layer 26 and a channel layer 27 located on the sacrificial layer 26. Among them, the channel layer included in the fin structure is used to fabricate the channel region included in the first transistor. Therefore, the material and number of layers of the channel layer included in the fin structure can be set according to the material of the channel region included in the first transistor described above and the number of layers of nanostructures included in the channel region, which will not be elaborated here. As for the sacrificial layer, the remaining sacrificial layer will be removed subsequently to form a void for filling the gate stack structure. Therefore, the thickness of the sacrificial layer can be determined according to the thickness of the gate stack structure. The material of the sacrificial layer can include any semiconductor material different from the material of the channel layer. For example, when the material of the channel layer is silicon, the material of the sacrificial layer can include silicon germanium or germanium, etc. Another example: when the material of the channel layer is silicon germanium or germanium, the material of the sacrificial layer can include silicon.

[0099] Regarding the above-mentioned mask structure, the material of the mask structure can be set according to actual needs, as long as it can play a mask protection role subsequently.

[0100] Exemplarily, the mask structure can only include a sacrificial gate. The material of the sacrificial gate can include materials such as polysilicon that are easy to remove.

[0101] Exemplarily, the mask structure can include a sacrificial gate and gate sidewalls, and the gate sidewalls are located on both sides of the sacrificial gate along the length direction. The material of the gate sidewalls can refer to the foregoing.

[0102] Alternatively, the above-mentioned mask structure can also include a gate oxide layer, a sacrificial gate located on the gate oxide layer, and gate sidewalls located on both sides of the sacrificial gate along the length direction. The material of the gate oxide layer can include materials such as silicon oxide.

[0103] In the actual manufacturing process, taking the first transistor as a gate-all-around transistor as an example for illustration: Processes such as epitaxy can be used to form sacrificial layers and channel layers that are alternately stacked along the thickness direction of the semiconductor substrate. Then, processes such as photolithography and etching are used to pattern the above-mentioned sacrificial layers, channel layers, and part of the semiconductor substrate to form fins. Next, as Figure 1 shown, processes such as deposition and etching can be used to form a shallow trench isolation structure 22 for defining the active region between adjacent fins. The top height of the shallow trench isolation structure 22 is less than or equal to the bottom height of the sacrificial layer 26 located at the bottom layer. Among them, the part of the fin exposed outside the shallow trench isolation structure 22 is the fin structure 24. Next, a mask material covering the semiconductor substrate 11 can be formed by a deposition process. Then, as Figure 2 and Figure 3 shown, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure 25.

[0104] It should be noted that when the semiconductor device does not include the above-mentioned shallow trench isolation structure, only the sacrificial layer and the channel layer can be patterned. And a fin structure can be directly obtained after the patterning process.

[0105] Next, as Figure 4 shown, processes such as dry etching or wet etching can be used to etch away the portions of the fin structure that are exposed outside the mask structure 25.

[0106] Next, if the first transistor to be manufactured is a gate-all-around transistor and the gate-all-around transistor further includes inner sidewalls, as Figure 5 shown, processes such as dry etching or wet etching can be used to remove the edge portions on both sides of the remaining sacrificial layer 26 along the first direction to form a second opening 28.

[0107] It should be noted that when the first transistor is a non-gate-all-around transistor, or when the first transistor is a gate-all-around transistor and does not include inner sidewalls, there is no need to form a second opening, and subsequent operations can be directly carried out.

[0108] Next, as Figure 9 shown, a first isolation structure 14 is formed between at least a pair of adjacent remaining fin structures.

[0109] In the actual manufacturing process, it can be determined according to the specific structure and material of the first isolation structure, as well as the specific structure and material of the first transistor, and no specific limitation is made here.

[0110] Exemplarily, processes such as chemical vapor deposition can be used to form a first isolation material covering the mask structure and between at least a pair of adjacent remaining fin structures. Then, processes such as chemical mechanical polishing are used to planarize the first isolation material so that the top of the first isolation material is flush with the top of the mask structure. Next, processes such as lithography are used to form an etching mask on the remaining first isolation material. Then, under the protection of the etching mask and the mask structure, the first isolation material is etched so that the remaining first isolation material forms a first isolation structure.

[0111] Exemplarily, if the first transistor to be manufactured is a gate-all-around transistor and the gate-all-around transistor further includes inner sidewalls, the first isolation material can be formed simultaneously in the second opening and between at least a pair of adjacent remaining fin structures. And, under the protection of the etching mask and the mask structure, after selective etching, the portion of the first isolation material remaining in the second opening forms inner sidewalls, and the portion of the first isolation material remaining between adjacent remaining fin structures forms at least part of the first isolation structure.

[0112] Exemplarily, if the manufactured first isolation structure includes a first isolation portion and a second isolation portion, forming the first isolation structure between at least one pair of adjacent remaining fin structures may include: As Figure 6 shown, processes such as chemical vapor deposition can be used to form a first isolation material 29 between at least one pair of adjacent remaining fin structures; the first isolation material 29 encloses a first opening 30. Next, as Figure 8 shown, processes such as chemical vapor deposition can be used to form a second isolation portion 17 within the first opening; the material of the first isolation material 29 is different from that of the second isolation portion 17. Next, as Figure 9 shown, processes such as dry etching or wet etching can be used, and under the protection of the mask structure 25 and the second isolation portion 17, the first isolation material 29 is selectively etched; after the selective etching, the portion of the first isolation material 29 remaining below the second isolation portion 17 forms a first isolation portion 16.

[0113] Among them, if in the manufactured first transistor, the material of the inner sidewall is the same as that of the first isolation portion, after removing the edge portions on both sides of the remaining sacrificial layer along the first direction to form a second opening, as Figure 6 shown, the first isolation material 29 can be formed simultaneously within the second opening and between at least one pair of adjacent remaining fin structures. In this case, as Figure 9 shown, under the protection of the mask structure 25 and the second isolation portion 17, after the first isolation material 29 is selectively etched, the portion of the first isolation material remaining within the second opening forms an inner sidewall 18.

[0114] Specifically, as Figure 6 shown, processes such as chemical vapor deposition can be used to first form a first isolation material 29 that at least extends and covers between at least one pair of adjacent remaining fin structures and on the mask structure 25. The thickness of the first isolation material 29 can be greater than the width of the second opening 28 along the first direction, and at this time, the first opening 30 can be enclosed only by the first isolation material 29. Next, as Figure 7 shown, processes such as chemical vapor deposition are used to form a second isolation material 31 that fills the first opening and extends and covers the first isolation material of the corresponding mask structure 25. Next, as Figure 8 shown, processes such as chemical mechanical polishing can be used to planarize the second isolation material and the first isolation material to expose the top of the mask structure 25. After the planarization process, the remaining second isolation material forms a second isolation portion 17.

[0115] Alternatively, as described above, when the first isolation structure further includes a third dielectric portion, and / or when the thickness of the first isolation material is less than or equal to the width of the second opening along the first direction, after forming the first isolation material and before forming the second isolation material, a third dielectric material can be formed on the first isolation material by processes such as chemical vapor deposition. At this time, the second notch is jointly surrounded by the first isolation material and the third dielectric material. Finally, processes such as chemical mechanical polishing are used to planarize the third dielectric material, the second isolation material, and the first isolation material, and the remaining third dielectric material forms the third dielectric portion. It should be noted that if the third dielectric portion is formed, under the protection of the mask structure and the second isolation portion, when selectively etching the first isolation material, it is also necessary to remove the third dielectric portion exposed outside the second isolation portion.

[0116] Next, as Figure 10 shown, processes such as epitaxy are used to epitaxially grow source / drain regions 15 on both sides of the remaining fin structure.

[0117] Exemplarily, as Figure 11 shown, after forming source / drain regions 15 on both sides of the remaining fin structure, processes such as chemical vapor deposition and planarization can be used to form an insulating dielectric layer 20 covering at least two first transistors 12. There is an interface between the insulating dielectric layer 20 and the first isolation structure 14. The top of the insulating dielectric layer 20 is flush with the top of the mask structure 25. The material of the insulating dielectric layer 20 can refer to the previous text and will not be elaborated here.

[0118] Next, as Figure 12 and Figure 13 shown, processes such as dry etching or wet etching can be used to etch away at least part of the mask structure; and the remaining fin structure forms a channel region.

[0119] It should be noted that whether to remove all of the mask structure or only part of the mask structure can be determined according to the specific structure of the mask structure. For example: when the mask structure only includes a sacrificial gate or only includes a sacrificial gate and a gate oxide layer, it is necessary to remove all of the mask structure. When the mask structure includes a sacrificial gate and a gate sidewall, the gate sidewall needs to be retained, that is, only part of the mask structure is removed.

[0120] In addition, the operation of forming the remaining fin structure into a channel region can be determined according to the type of the first transistor. For example: when the first transistor is a fin field effect transistor, after removing at least part of the mask structure and exposing the remaining fin structure, the remaining fin structure forms a channel region.

[0121] For another example, in the case where the first transistor is a gate-all-around transistor, processes such as dry etching or wet etching are required to etch away the remaining sacrificial layer so that the remaining channel layer forms a channel region.

[0122] Next, as Figure 14 and Figure 15 shown, processes such as atomic layer deposition can be used to form a gate stack structure 13 on the outer periphery of the channel region to obtain at least two first transistors 12. The first direction is parallel to the length direction of the gate stack structure 13.

[0123] For the specific structure, material of the gate stack structure 13 and the spacing between the gate stack structures 13 of adjacent first transistors 12, reference can be made to the foregoing, and details will not be elaborated herein.

[0124] Next, processes such as selective etching can be used to etch away the part of the insulating dielectric layer located on at least part of the source / drain region to form a contact hole, and one side wall of the contact hole along the first direction exposes the first isolation structure. Next, as Figure 16 shown, processes such as physical vapor deposition can be used to form a source / drain contact structure 21 electrically connected to the source / drain region 15 included in the first transistor 12 in the contact hole.

[0125] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and details will not be elaborated herein.

[0126] In the above description, no detailed description is made of technical details such as the patterning and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. with the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0127] The embodiments of the present invention have been described above. However, these embodiments are only for more clearly explaining, rather than limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate; At least two first transistors, spaced apart in a first direction on the semiconductor substrate; The first direction is parallel to the length direction of the gate stack structure included in the first transistor; And a first isolation structure, disposed between source / drain regions included in at least a pair of adjacent two of the first transistors.

2. The semiconductor device according to claim 1, wherein Along the thickness direction of the semiconductor substrate, the first isolation structure includes a first isolation portion and a second isolation portion located on the first isolation portion; the materials of the first isolation portion and the second isolation portion are different.

3. The semiconductor device according to claim 2, wherein, The first transistor is a gate-all-around transistor, and the first transistor further includes inner sidewalls, which are disposed between the gate stack structure and the source / drain regions respectively; The material of the first isolation portion is the same as the material of the inner sidewalls included in the first transistor.

4. The semiconductor device according to claim 3, wherein The thickness of the first isolation portion in the thickness direction of the semiconductor substrate is greater than the width of the inner sidewalls included in the adjacent first transistors in the first direction.

5. The semiconductor device according to claim 1, wherein The first transistor is a gate-all-around transistor, and the first transistor further includes inner sidewalls, which are disposed between the gate stack structure and the source / drain regions respectively; At least a part of the material included in the first isolation structure is the same as the material of the inner sidewalls.

6. The semiconductor device according to claim 1, wherein Along the first direction, the source / drain regions included in the first transistors adjacent to the first isolation structure are aligned with the sidewalls of the first isolation structure.

7. The semiconductor device according to claim 1, wherein The height of the first isolation structure is greater than the height of the source / drain regions included in the adjacent first transistors.

8. The semiconductor device according to claim 7, wherein, The first transistor further includes source / drain contact structures; the source / drain contact structures are located on the source / drain regions and are aligned with the sidewalls of the first isolation structure.

9. The semiconductor device according to claim 1, wherein Along the first direction, the width of the first isolation structure is greater than or equal to 5 nm and less than or equal to 15 nm; And / or, along the first direction, the spacing between the gate stack structures included in the two first transistors located on both sides of the first isolation structure is less than or equal to 60 nm.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an insulating dielectric layer covering the at least two first transistors; there is an interface between the insulating dielectric layer and the first isolation structure.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second isolation structure and a second transistor; the second transistor is disposed above the at least two first transistors; the second isolation structure is disposed between the source / drain regions included in the second transistor and the source / drain regions included in the first transistors.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming at least two fin structures spaced apart in a first direction on a semiconductor substrate, and forming a mask structure spanning the fin structures; Etching away the portions of the fin structures exposed outside the mask structure; And forming a first isolation structure between at least a pair of adjacent remaining fin structures; Epitaxially growing source / drain regions on both sides of the remaining fin structures; at least a pair of adjacent two source / drain regions spaced apart in the first direction are isolated by the first isolation structure; Etching away at least a part of the mask structure; And causing the remaining fin structures to form channel regions; A gate stack structure is formed on the outer periphery of the channel region to obtain at least two first transistors; The first direction is parallel to the length direction of the gate stack structure.

13. The manufacturing method of the semiconductor device according to claim 12, characterized in that, Along the thickness direction of the semiconductor substrate, each fin structure includes at least one semiconductor stack; each semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer; The step of forming the remaining fin structures into a channel region includes: removing the remaining sacrificial layer of each layer to form the channel region with the remaining channel layer.

14. The manufacturing method of the semiconductor device according to claim 12 or 13, characterized in that, Forming a first isolation structure between at least a pair of adjacent remaining fin structures includes: Forming a first isolation material between at least a pair of adjacent remaining fin structures; the first isolation material surrounds a first opening; Forming a second isolation portion in the first opening; the material of the first isolation material is different from that of the second isolation portion; Under the protection of the mask structure and the second isolation portion, selectively etching the first isolation material; after the selective etching, the remaining portion of the first isolation material below the second isolation portion forms a first isolation portion; the first isolation structure includes the first isolation portion and the second isolation portion.

15. The manufacturing method of the semiconductor device according to claim 14, wherein, In the case where the fin structure includes the at least one semiconductor stack, after etching away the portion of the fin structure exposed outside the mask structure and before forming the second isolation portion in the first opening, the manufacturing method of the semiconductor device includes: removing the edge portions of the remaining sacrificial layer on both sides along the first direction to form a second opening; forming the first isolation material in the second opening and between at least a pair of adjacent remaining fin structures simultaneously; After the selective etching, the remaining portion of the first isolation material in the second opening forms an inner sidewall.

16. The manufacturing method of the semiconductor device according to claim 15, characterized in that, Forming the first isolation material in the second opening and between at least a pair of adjacent remaining fin structures simultaneously, and forming the second isolation portion in the first opening includes: Forming the first isolation material that fills the second opening and extends to cover between at least a pair of adjacent remaining fin structures and on the mask structure; Forming a second isolation material that fills the first opening and extends to cover on the first isolation material corresponding to the mask structure; Performing a planarization process on the second isolation material and the first isolation material to expose the top of the mask structure; after the planarization process, the remaining second isolation material forms the second isolation portion.

17. The manufacturing method of the semiconductor device according to claim 13, characterized in that, After etching away the portion of the fin structure exposed outside the mask structure and before epitaxially growing source / drain regions on both sides of the remaining fin structures, the manufacturing method of the semiconductor device includes: Removing the edge portions of the remaining sacrificial layer on both sides along the first direction to form a second opening; While forming the inner sidewall in the second opening, forming at least a part of the first isolation structure between at least a pair of adjacent remaining fin structures.

18. The manufacturing method of the semiconductor device according to claim 12, characterized in that, After forming source / drain regions on both sides of the remaining fin structures, before removing at least a part of the mask structure, the method for manufacturing a semiconductor device further includes: Forming an insulating dielectric layer covering the at least two first transistors; there is an interface between the insulating dielectric layer and the first isolation structure.

19. The manufacturing method of the semiconductor device according to claim 18, characterized in that, After forming the insulating dielectric layer covering the at least two first transistors, the method for manufacturing a semiconductor device further includes: Etching away the part of the insulating dielectric layer located on at least a part of the source / drain regions to form contact holes, and one side wall of the contact holes along the first direction exposes the first isolation structure; and forming source / drain contact structures in the contact holes.

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