Semiconductor device forming method and semiconductor device

Abstract

The invention provides a forming method of a semiconductor device and the semiconductor device. The method comprises the following steps: depositing a gate oxide layer with a high dielectric constant on a preset substrate; forming a decomposable film side wall layer on the side wall of the groove; depositing a metal gate electrode material to form a metal gate electrode in the groove, and removing the gate oxide layer above the interlayer dielectric layer; depositing a porous thin film layer, etching the gate oxide layers on the side walls of the two sides of the groove and the interlayer dielectric layer in contact with the gate oxide layers, and filling metal to form a contact hole electrode in contact with the source-drain active region; and performing an annealing process to decompose the decomposable film side wall layer and volatilize the decomposable film side wall layer through the porous film layer, so that an air layer is formed on the decomposable film side wall layer between the contact hole and the metal gate electrode. According to the invention, the gate oxide layer with a high dielectric constant between the contact hole and the metal gate electrode is replaced by the air layer with a low dielectric constant, so that the stray capacitance between the metal gate electrode and the source-drain contact hole electrode is reduced, and the RC delay is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device and a semiconductor device. Background Art

[0002] In semiconductor processes, the delay caused by the action of resistance (R) and capacitance (C) (hereinafter simply referred to as RC delay) will affect the performance and power consumption of the chip. Reducing the RC delay can improve the chip speed, reduce the chip power consumption, improve the signal integrity of the chip, and also increase the chip integration to improve the timing margin. In order to reduce the RC delay, it is necessary to reduce the parasitic capacitance between the metal gate electrode and the contact hole electrode of the semiconductor device, so as to achieve the purpose of reducing the RC delay.

[0003] In related metal gate electrode manufacturing technologies, there is usually a high-k gate oxide layer and an interlayer dielectric layer between the contact hole and the metal gate electrode. However, the high-k gate oxide layer between the contact hole and the metal gate electrode has an extremely high dielectric constant, which greatly increases the parasitic capacitance between the contact hole and the metal gate electrode and increases the RC delay. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a method for forming a semiconductor device and a semiconductor device, which can minimize the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrode of the semiconductor device, thereby reducing the RC delay.

[0005] In order to achieve the above object, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a method for forming a semiconductor device, including:

[0007] Depositing a high-k gate oxide layer on a preset substrate; wherein, the preset substrate includes a substrate, an interface layer above the active region of the substrate, and an interlayer dielectric layer at a position where the interface layer is not formed, and the height of the interface layer is less than the height of the interlayer dielectric layer to form a trench;

[0008] Forming a decomposable thin film sidewall layer on the sidewall of the trench;

[0009] Depositing a metal gate electrode material to form a metal gate electrode in the trench, and removing the gate oxide layer above the interlayer dielectric layer;

[0010] Depositing a porous thin film layer, etching the gate oxide layer on both sidewalls of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and filling with metal to form a contact hole electrode in contact with the source / drain active region;

[0011] Perform an annealing process to decompose the sidewall layer of the decomposable film and volatilize it through the porous film layer, so as to form an air layer between the contact hole and the sidewall layer of the decomposable film between the metal gate electrodes.

[0012] Furthermore, the embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein forming the sidewall layer of the decomposable film on the sidewall of the trench includes:

[0013] Deposit a decomposable film layer above the gate oxide layer;

[0014] Perform anisotropic etching on the decomposable film layer to form the sidewall layer of the decomposable film attached to the sidewall of the trench.

[0015] Furthermore, the embodiment of the present invention provides a second possible implementation manner of the first aspect, wherein depositing the metal gate electrode material to form a metal gate electrode in the trench and removing the gate oxide layer above the interlayer dielectric layer includes:

[0016] Deposit the metal gate electrode material, and perform chemical mechanical polishing on the metal gate electrode material and the gate oxide layer until the interlayer dielectric layer is exposed to form the metal gate electrode.

[0017] Furthermore, the embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein before depositing the gate oxide layer with a high dielectric constant on the preset substrate, it further includes:

[0018] Form the interface layer and the replacement gate layer in sequence at the active region position of the substrate;

[0019] Deposit the interlayer dielectric layer at the position on the surface of the substrate where the interface layer and the replacement gate layer are not formed;

[0020] Remove the replacement gate layer buried in the interlayer dielectric layer to form a trench, and obtain the preset substrate.

[0021] Furthermore, the embodiment of the present invention provides a fourth possible implementation manner of the first aspect, wherein the porous film layer is a silicon dioxide-based porous film layer.

[0022] Furthermore, the embodiment of the present invention provides a fifth possible implementation manner of the first aspect, wherein the material of the sidewall layer of the decomposable film includes an ultraviolet light decomposable film.

[0023] Furthermore, the embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein the material of the interface layer includes silicon oxide or silicon oxynitride.

[0024] Further, a seventh possible implementation manner of the first aspect is provided in an embodiment of the present invention, wherein the material of the alternative gate layer includes amorphous silicon gate.

[0025] Further, an eighth possible implementation manner of the first aspect is provided in an embodiment of the present invention, wherein the material of the interlayer dielectric layer includes silicon oxide.

[0026] In a second aspect, an embodiment of the present invention further provides a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device according to any one of the first aspect.

[0027] An embodiment of the present invention provides a method for manufacturing a semiconductor device and a semiconductor device. The method includes: depositing a gate oxide layer with a high dielectric constant on a preset substrate; wherein the preset substrate includes a substrate, an interface layer above the active region of the substrate, and an interlayer dielectric layer at a position where the interface layer is not formed, and a trench is formed with the height of the interface layer being less than that of the interlayer dielectric layer; forming a decomposable thin film sidewall layer on the sidewall of the trench; depositing a metal gate electrode material to form a metal gate electrode in the trench, and removing the gate oxide layer above the interlayer dielectric layer; depositing a porous thin film layer, etching the gate oxide layer on both sidewalls of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and filling the metal to form a contact hole electrode in contact with the source-drain active region; performing an annealing process to decompose the decomposable thin film sidewall layer and volatilize it through the porous thin film layer, so as to form an air layer between the contact hole and the metal gate electrode with the decomposable thin film sidewall layer. The present invention forms a decomposable thin film sidewall layer on the sidewall of the trench, and performs an annealing process after forming the metal gate electrode and the contact hole, so that the decomposable thin film sidewall layer decomposes and volatilizes through the porous thin film layer to form an air layer, replacing the gate oxide layer with a high dielectric constant between the contact hole and the metal gate electrode with an air layer with a low dielectric constant, reducing the parasitic capacitance between the metal gate electrode and the source-drain contact hole electrode of the semiconductor device, and thus reducing the RC delay.

[0028] Other features and advantages of the embodiments of the present invention will be described in the following specification, or, some features and advantages can be inferred from the specification without doubt, or can be known by implementing the above technologies of the embodiments of the present invention.

[0029] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specific embodiments are given, and detailed descriptions are made in conjunction with the accompanying drawings as follows. Description of the Drawings

[0030] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figures 1a to 1e Shows the flowchart of fabricating a related metal gate electrode;

[0032] Figure 2 Shows the flowchart of a method for forming a semiconductor device provided by an embodiment of the present invention;

[0033] Figures 3a to 3e Shows the flowchart of fabricating a semiconductor device provided by an embodiment of the present invention;

[0034] Figure 4 Shows the schematic diagram of depositing a decomposable thin film layer provided by an embodiment of the present invention;

[0035] Figures 5a to 5i Shows the flowchart of forming another conductor device provided by an embodiment of the present invention. Specific Embodiments

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will describe the technical solutions of the present invention with reference to the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0037] Currently, the RC delay directly affects the performance, power consumption, reliability, and cost of the chip. For example, reducing the RC delay can increase the speed at which the signal reaches the destination, enabling the chip to operate at a higher working frequency and improving the chip's processing speed; a lower RC delay indicates that the circuit can complete operations in a shorter time, and reducing the RC delay can also reduce power consumption; reducing the RC delay can also reduce signal attenuation and distortion, improving signal integrity, ensuring the reliability of data transmission, reducing the RC delay can also allow more circuits to be integrated on a smaller chip area, improving the chip's integration density; reducing the RC delay can also make the circuit design have a higher fault tolerance and be more easily meet the timing requirements. Therefore, reducing the RC delay is one of the core objectives of semiconductor process improvement.

[0038] Regarding the related metal gate electrode manufacturing technology, refer to Figures 1a to 1e the related metal gate electrode manufacturing flowchart shown. An interface layer 102 and an amorphous silicon dummy gate 103 are sequentially formed on the active region 101 of the semiconductor substrate 100. As Figure 1bAs shown, an interlayer dielectric layer (ILD) 104 is deposited on the surface of the semiconductor substrate 100 at positions where the interface layer 102 and the amorphous silicon dummy gate 103 are not formed, and the deposited height of the interlayer dielectric layer 104 is flush with the amorphous silicon dummy gate 103. As Figure 1c shown, the amorphous silicon dummy gate 103 is removed from the buried interlayer dielectric layer 104 to form a trench. As Figure 1d shown, a material of a gate oxide layer with a high dielectric constant and a metal gate electrode is deposited. When depositing, the gate oxide layer with a high dielectric constant also covers the surface of the interlayer dielectric layer 104, and the metal gate electrode material covers the surface of the gate oxide layer with a high dielectric constant. Chemical mechanical polishing (CMP) is performed on the metal gate electrode material and the gate oxide layer with a high dielectric constant in sequence until the interlayer dielectric layer 104 is exposed, forming a gate oxide layer 105 with a high dielectric constant and a metal gate electrode 106. As Figure 1e shown, the interlayer dielectric layer 104 is etched above the active regions 101 on both sides of the metal gate electrode 106 to form source / drain contact hole electrodes 107.

[0039] From Figure 1e it can be seen that there is a gate oxide layer 105 with a high dielectric constant and an interlayer dielectric layer 104 between the contact hole 107 and the metal gate electrode 106. The gate oxide layer 105 with a high dielectric constant has an extremely high dielectric constant, greatly increasing the parasitic capacitance between the contact hole 107 and the metal gate electrode 106, increasing the RC delay, resulting in a series of problems such as signal delay, increased dynamic power consumption, signal distortion and crosstalk, serious heating, and serious noise coupling in the formed semiconductor device.

[0040] To improve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device and a semiconductor device, and the following is a detailed introduction to the embodiment of the present invention.

[0041] This embodiment provides a method for forming a semiconductor device, which can be applied to semiconductor process equipment. Refer to Figure 2 the flowchart of the method for forming a semiconductor device shown, and this method mainly includes the following steps:

[0042] Step S202, depositing a gate oxide layer with a high dielectric constant on a preset substrate;

[0043] Refer to Figures 3a to 3e the flowchart of manufacturing a semiconductor device shown, as Figure 3aAs shown, the preset substrate includes a substrate 100, an interface layer 102 above the active region 101 of the substrate, and an interlayer dielectric layer 104 at a position where the interface layer is not formed. The height of the interface layer 102 is less than that of the interlayer dielectric layer 104 to form a trench; a gate oxide layer 301 with a high dielectric constant is deposited, and the gate oxide layer 301 covers the interlayer dielectric layer 104 and the bottom and sidewalls of the trench.

[0044] Step S204: Form a decomposable thin film sidewall layer on the sidewalls of the trench;

[0045] As Figure 3a shown, a decomposable thin film sidewall layer 302' is formed on the sidewalls of the trench, and the decomposable thin film sidewall layer 302' adheres to the gate oxide layer 301 on the sidewalls of the trench.

[0046] The material of the decomposable thin film sidewall layer 302' can be a degradable sacrificial material that decomposes within a suitable temperature range, such as a UV (ultraviolet light) decomposable thin film.

[0047] Step S206: Deposit a metal gate electrode material to form a metal gate electrode in the trench, and remove the gate oxide layer above the interlayer dielectric layer;

[0048] As Figure 3b shown, deposit a metal gate electrode material, and remove the metal gate electrode material and the gate oxide layer above the interlayer dielectric layer 104 to expose the interlayer dielectric layer 104 except, and form a metal gate electrode 303 in the trench. The material of the metal gate electrode can be materials such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), molybdenum (Mo), and ruthenium (Ru).

[0049] Step S208: Deposit a porous thin film layer, etch the gate oxide layer on both sidewalls of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and fill with metal to form a contact hole in contact with the source / drain active region;

[0050] As Figure 3c shown, deposit a porous thin film layer 304. The porous thin film layer 304 can be a thin film layer containing a porous structure so that the gas generated when the decomposable thin film sidewall layer 302' decomposes can volatilize through the porous thin film layer 304. In a specific embodiment, in order to facilitate the volatilization of the gas, the porous thin film layer 304 can be a silica-based porous thin film layer.

[0051] As Figure 3d shown, etch the gate oxide layer on both sidewalls of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and fill with metal to form a contact hole electrode 305 in contact with the source / drain active region.

[0052] In step S210, an annealing process is performed to decompose the sidewall layer of the decomposable film and volatilize it through the porous film layer, so as to form an air layer between the contact hole and the metal gate electrode in the sidewall layer of the decomposable film.

[0053] As Figure 3e shown, an annealing process is performed to decompose the sidewall layer 302' of the decomposable film on the inner sidewall of the trench, and the decomposed gas is volatilized through the upper porous film layer 304, so as to form an air layer 302" in the sidewall layer 302' of the decomposable film between the contact hole and the metal gate electrode. Since the dielectric constant of the air layer 302" is 1, the parasitic capacitance between the metal gate electrode 303 and the source-drain contact hole electrode 305 of the semiconductor device can be minimized, thereby reducing the RC delay.

[0054] In the method for forming the semiconductor device provided in this embodiment, by forming a sidewall layer of a decomposable film on the sidewall of the trench and performing an annealing process after forming the metal gate electrode and the contact hole, the sidewall layer of the decomposable film is decomposed and volatilized through the porous film layer to form an air layer, and the high-dielectric-constant gate oxide layer between the contact hole and the metal gate electrode can be replaced with an air layer with a low dielectric constant, so that the parasitic capacitance between the metal gate electrode and the source-drain contact hole electrode of the semiconductor device can be minimized, thereby reducing the RC delay.

[0055] The method for forming the semiconductor device provided in this embodiment is applicable not only to the High-K Metal Gate (HKMG) process of planar transistors, but also to the HKMG processes of Fin Field-Effect Transistors (FinFETs) and Gate-All-Around (GAA) transistors.

[0056] In one embodiment, this embodiment provides a specific implementation for forming a sidewall layer of a decomposable film on the sidewall of the trench: depositing a decomposable film layer above the gate oxide layer; performing anisotropic etching on the decomposable film layer to form a sidewall layer of the decomposable film attached to the sidewall of the trench.

[0057] Refer to as Figure 4 shown in the schematic diagram of depositing the decomposable film layer. A decomposable film layer 302 is deposited above the gate oxide layer 301. The gate oxide layer 301 and the decomposable film layer 302 cover the bottom, sidewall and outside of the trench. Anisotropic etching is performed on the decomposable film layer 302 to etch away the decomposable film layer above the interlayer dielectric layer 104 and at the bottom of the trench until the high-dielectric-constant gate oxide layer 301 is exposed, forming a sidewall layer 302' of the decomposable film attached to the sidewall of the trench as Figure 3a shown.

[0058] In one embodiment, this embodiment provides a specific implementation manner of depositing a metal gate electrode material in a trench to form a metal gate electrode and removing the gate oxide layer above the interlayer dielectric layer:

[0059] Deposit a metal gate electrode material, and perform chemical mechanical polishing on the metal gate electrode material and the gate oxide layer until the interlayer dielectric layer is exposed to form a metal gate electrode.

[0060] After depositing the metal gate electrode material, the metal gate electrode material will fill the trench, and the deposited metal gate electrode material will also cover the gate oxide layer above the interlayer dielectric layer. Perform chemical mechanical polishing on the metal gate electrode material and the gate oxide layer to remove the metal gate electrode material and the gate oxide layer above the interlayer dielectric layer to expose the interlayer dielectric layer, and make the metal gate electrode in the trench flush with the surface of the interlayer dielectric layer.

[0061] In one embodiment, before the above step S202, the method provided in this embodiment further includes:

[0062] Successively form an interface layer and a replacement gate layer at the active region position of the substrate;

[0063] Deposit an interlayer dielectric layer at the position on the substrate surface where the interface layer and the replacement gate layer are not formed;

[0064] Remove the replacement gate layer buried in the interlayer dielectric layer to form a trench, and obtain a preset substrate.

[0065] As Figures 1a to 1c shown, an interface layer 102 and a replacement gate layer 103 are successively formed at the active region 101 position of the substrate 100. On the surface of the semiconductor substrate 100, an interlayer dielectric layer 104 is deposited at the position where the interface layer 102 and the replacement gate layer 103 are not formed, and the replacement gate 103 is removed from the buried interlayer dielectric layer 104 to form a trench.

[0066] In a specific implementation manner, the above interface layer can be a silicon oxide layer or a silicon oxynitride layer.

[0067] In a specific implementation manner, the material of the above replacement gate layer can be an amorphous silicon gate.

[0068] In a specific implementation manner, the above interlayer dielectric layer can be a silicon oxide layer.

[0069] In the method for forming the semiconductor device provided in this embodiment, by forming air layers on both sides of the metal gate electrode, the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrodes of the semiconductor device can be minimized, signal delay can be reduced, enabling the circuit to operate at a higher speed and frequency; dynamic power consumption can also be reduced. Since dynamic power consumption is proportional to capacitance, a decrease in capacitance indicates that at the same switching frequency, the energy consumed by the circuit is reduced, thereby reducing the overall power consumption; signal distortion and crosstalk can also be reduced, signal integrity can be improved, heat dissipation performance can be enhanced, noise coupling can be reduced, and the noise performance of the circuit can be improved.

[0070] Based on the foregoing embodiment, this embodiment provides an example of applying the method for forming the semiconductor device to reduce the parasitic capacitance between the metal gate electrode and the contact hole electrode of the semiconductor device. Refer to Figures 5a to 5i the flowchart for forming another conductor device as shown in

[0071] Step 501: Sequentially form an interface layer 102 and a replacement gate layer 103 at the active region 101 of the substrate 100.

[0072] Step 502: Deposit an interlayer dielectric layer 104 on the surface of the semiconductor substrate 100 at positions where the interface layer 102 and the replacement gate layer 103 are not formed.

[0073] Step 503: Remove the replacement gate 103 from the buried interlayer dielectric layer 104 to form a trench.

[0074] Step 504: Sequentially deposit a gate oxide layer 301 with a high dielectric constant and a decomposable thin film layer 302.

[0075] Step 505: Anisotropically etch the decomposable thin film layer 302 until the gate oxide layer 301 with a high dielectric constant is exposed, forming a decomposable thin film sidewall layer 302' attached to the sidewalls of the trench.

[0076] Step 506: Deposit a metal gate electrode material, and perform chemical mechanical polishing on the metal gate electrode material and the gate oxide layer until the interlayer dielectric layer 104 is exposed, forming a metal gate electrode 303.

[0077] Step 507: Deposit a silicon dioxide-based porous thin film layer 304.

[0078] Step 508: Etch the gate oxide layer with a high dielectric constant located on the sidewalls of the trench and the interlayer dielectric layer in contact therewith, and fill with metal to form a contact hole electrode 305 in contact with the active region.

[0079] Step 509: Perform an annealing process to decompose the decomposable thin film sidewall layer 302' in the trench, volatilize it through the silicon dioxide-based porous thin film layer 304 thereon, and form an air layer 302" on the sidewalls of the metal gate electrode 303.

[0080] In this embodiment, by pre-depositing a decomposable thin film sidewall layer on both sidewalls of the trench and forming an air layer through annealing treatment for decomposition and volatilization, since the dielectric constant of the air layer is 1, the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrode of the semiconductor device can be minimized, reducing the parasitic capacitance and thus reducing the RC delay.

[0081] Corresponding to the method for forming a semiconductor device provided in the above embodiment, an embodiment of the present invention provides a semiconductor device, which is manufactured by the method for forming a semiconductor device provided in the above embodiment.

[0082] As Figure 3e shown, the semiconductor device includes a substrate 100, a porous thin film layer 304, an interface layer 102, a gate oxide layer 301 distributed above the interface layer, a metal gate electrode 303, and contact hole electrodes 305 distributed on both sides of the metal gate electrode 303. An air layer 302" is provided between the metal gate electrode 303 and the contact hole electrodes 305.

[0083] For the semiconductor device provided in this embodiment, its implementation principle and the technical effects produced are the same as those of the foregoing embodiment. For the sake of brief description, for the parts not mentioned in the semiconductor device embodiment, reference may be made to the corresponding content in the foregoing method embodiment.

[0084] An embodiment of the present invention provides an electronic device, which includes a processor and a memory. A computer program that can run on the processor is stored in the memory. When the processor executes the computer program, the steps of the method provided in the above embodiment are implemented.

[0085] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described system can refer to the corresponding process in the foregoing embodiment, and will not be described in detail here.

[0086] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0087] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0088] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0089] Finally, it should be noted that the above-mentioned embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting them. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the technical field of the present invention can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes, or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, Including: Depositing a gate oxide layer with a high dielectric constant on a preset substrate; wherein, the preset substrate includes a substrate, an interface layer above the active region of the substrate, and an interlayer dielectric layer at a position where the interface layer is not formed, and the height of the interface layer is less than the height of the interlayer dielectric layer to form a trench; Forming a decomposable thin film sidewall layer on the sidewall of the trench; Depositing a metal gate electrode material to form a metal gate electrode in the trench, and removing the gate oxide layer above the interlayer dielectric layer; Depositing a porous thin film layer, etching the gate oxide layer on both sidewalls of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and filling with metal to form a contact hole electrode in contact with the source / drain active region; Performing an annealing process to decompose the decomposable thin film sidewall layer and volatilize it through the porous thin film layer, so as to form an air layer of the decomposable thin film sidewall layer between the contact hole and the metal gate electrode.

2. The method for forming a semiconductor device according to claim 1, wherein, The forming of the decomposable thin film sidewall layer on the sidewall of the trench includes: Depositing a decomposable thin film layer above the gate oxide layer; Performing anisotropic etching on the decomposable thin film layer to form the decomposable thin film sidewall layer attached to the sidewall of the trench.

3. The method for forming a semiconductor device according to claim 1, wherein, The depositing a metal gate electrode material to form a metal gate electrode in the trench and removing the gate oxide layer above the interlayer dielectric layer includes: Depositing a metal gate electrode material, and performing chemical mechanical polishing on the metal gate electrode material and the gate oxide layer until the interlayer dielectric layer is exposed to form the metal gate electrode.

4. The method for forming a semiconductor device according to claim 1, wherein, Before depositing the gate oxide layer with a high dielectric constant on the preset substrate, it further includes: Sequentially forming the interface layer and the replacement gate layer at the active region of the substrate; Depositing the interlayer dielectric layer at a position on the surface of the substrate where the interface layer and the replacement gate layer are not formed; Removing the replacement gate layer buried in the interlayer dielectric layer to form a trench, and obtaining the preset substrate.

5. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The porous thin film layer is a silica-based porous thin film layer.

6. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the decomposable thin film sidewall layer includes an ultraviolet-light decomposable thin film.

7. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the interface layer includes silicon oxide or silicon oxynitride.

8. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the replacement gate layer includes an amorphous silicon gate.

9. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the interlayer dielectric layer includes silicon oxide.

10. A semiconductor device, characterized in that, The semiconductor device is obtained by the method for forming a semiconductor device according to any one of claims 1-9.

Images