A method of forming a semiconductor device and a semiconductor device

Abstract

This invention provides a method for forming a semiconductor device and the semiconductor device itself. The method includes: depositing a gate oxide layer with a high dielectric constant onto a predetermined substrate; forming a degradable thin film sidewall layer on the sidewalls of a trench; depositing a metal gate electrode material to form a metal gate electrode within the trench; removing the gate oxide layer above the interlayer dielectric layer; depositing a porous thin film layer; etching the gate oxide layer on both sides of the trench and the interlayer dielectric layer in contact with the gate oxide layer; and filling with metal to form contact hole electrodes in contact with the source / drain active regions; and performing an annealing process to decompose the degradable thin film sidewall layer and allow it to volatilize through the porous thin film layer, thereby forming an air layer between the contact hole and the metal gate electrode. This invention replaces the high dielectric constant gate oxide layer between the contact hole and the metal gate electrode with a low dielectric constant air layer, reducing the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrodes, thereby reducing RC delay.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device and the semiconductor device itself. Background Technology

[0002] In semiconductor manufacturing, the delay caused by resistance (R) and capacitance (C) (hereinafter referred to as RC delay) affects chip performance and power consumption. Reducing RC delay can improve chip speed, reduce chip power consumption, improve chip signal integrity, and also increase chip integration density to improve timing margin. To reduce RC delay, it is necessary to reduce the parasitic capacitance between the metal gate electrode and the contact hole electrode of the semiconductor device, thereby achieving the goal of reducing RC delay.

[0003] Related metal gate electrode fabrication techniques typically involve a high-dielectric-constant gate oxide layer and an interlayer dielectric layer between the contact hole and the metal gate electrode. However, the high-dielectric-constant gate oxide layer between the contact hole and the metal gate electrode has an extremely high dielectric constant, which greatly increases the parasitic capacitance between the contact hole and the metal gate electrode, thus increasing the RC delay. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide a method for forming a semiconductor device and a semiconductor device that can minimize the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrode of the semiconductor device, thereby reducing RC delay.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide a method for forming a semiconductor device, comprising:

[0007] A gate oxide layer with a high dielectric constant is deposited on a predetermined substrate; wherein the predetermined substrate includes a substrate, an interface layer located above the active region of the substrate, and an interlayer dielectric layer located at a position where the interface layer is not formed, and the height of the interface layer is less than the height of the interlayer dielectric layer to form a trench.

[0008] A biodegradable thin film sidewall layer is formed on the sidewall of the trench;

[0009] Depositing metal gate electrode material in the trench forms a metal gate electrode, removing the gate oxide layer above the interlayer dielectric layer;

[0010] A porous thin film layer is deposited, the gate oxide layer on both sides of the trench and the interlayer dielectric layer in contact with the gate oxide layer are etched, and metal is filled to form a contact hole electrode in contact with the source and drain active regions.

[0011] An annealing process is performed to decompose the decomposable thin film sidewall layer and allow it to volatilize through the porous thin film layer, thereby forming an air layer between the contact hole and the metal gate electrode.

[0012] Furthermore, embodiments of the present invention provide a first possible implementation of the first aspect, wherein forming a degradable thin film sidewall layer on the trench sidewall includes:

[0013] A degradable thin film layer is deposited over the gate oxide layer;

[0014] The degradable thin film layer is anisotropically etched to form the degradable thin film sidewall layer attached to the trench sidewall.

[0015] Furthermore, the present invention provides a second possible implementation of the first aspect, wherein the deposited metal gate electrode material forms a metal gate electrode within the trench, and the removal of the gate oxide layer above the interlayer dielectric layer includes:

[0016] A metal gate electrode material is deposited, and the metal gate electrode material and the gate oxide layer are chemically and mechanically polished until the interlayer dielectric layer is exposed to form the metal gate electrode.

[0017] Furthermore, the present invention provides a third possible implementation of the first aspect, wherein, before depositing a gate oxide layer with a high dielectric constant onto a predetermined substrate, the method further includes:

[0018] The interface layer and the alternative gate layer are sequentially formed at the active region location of the substrate;

[0019] The interlayer dielectric layer is deposited at a location on the substrate surface where the interface layer and the alternative gate layer are not formed;

[0020] The alternative gate layer buried within the interlayer dielectric layer is removed to form a trench, thereby obtaining the preset substrate.

[0021] Furthermore, the present invention provides a fourth possible implementation of the first aspect, wherein the porous thin film layer is a silicon dioxide-based porous thin film layer.

[0022] Furthermore, the present invention provides a fifth possible implementation of the first aspect, wherein the material of the degradable thin film sidewall layer includes an ultraviolet-degradable thin film.

[0023] Furthermore, this embodiment of the invention provides a sixth possible implementation of the first aspect, wherein the material of the interface layer includes silicon oxide or silicon oxynitride.

[0024] Furthermore, this embodiment of the invention provides a seventh possible implementation of the first aspect, wherein the material of the alternative gate layer includes an amorphous silicon gate.

[0025] Furthermore, this embodiment of the invention provides an eighth possible implementation of the first aspect, wherein the material of the interlayer dielectric layer includes silicon oxide.

[0026] Secondly, embodiments of the present invention also provide a semiconductor device, which is fabricated by the semiconductor device forming method described in any one of the first aspects.

[0027] This invention provides a method for forming a semiconductor device and a semiconductor device. The method includes: depositing a gate oxide layer with a high dielectric constant onto a predetermined substrate; wherein the predetermined substrate includes a substrate, an interface layer located above an active region of the substrate, and an interlayer dielectric layer located at a position where the interface layer is not formed, the height of the interface layer being less than the height of the interlayer dielectric layer to form a trench; forming a decomposable thin film sidewall layer on the sidewalls of the trench; depositing a metal gate electrode material to form a metal gate electrode in the trench, and removing the gate oxide layer above the interlayer dielectric layer; depositing a porous thin film layer, etching the gate oxide layer on both sidewalls of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and filling with metal to form a contact hole electrode in contact with the source / drain active regions; performing an annealing process to decompose the decomposable thin film sidewall layer and volatilize it through the porous thin film layer, so that an air layer is formed between the contact hole and the metal gate electrode due to the decomposable thin film sidewall layer. This invention forms a decomposable thin film sidewall layer on the trench sidewall and performs an annealing process after forming the metal gate electrode and contact hole. This causes the decomposable thin film sidewall layer to decompose and volatilize through the porous thin film layer to form an air layer. This air layer replaces the high-dielectric-constant gate oxide layer between the contact hole and the metal gate electrode with a low-dielectric-constant air layer, thereby reducing the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrode of the semiconductor device and thus reducing RC delay.

[0028] Other features and advantages of the embodiments of the present invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above in the embodiments of the present invention.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0030] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figures 1a-1e A flowchart illustrating the fabrication process of the relevant metal gate electrode is shown.

[0032] Figure 2 A flowchart illustrating a method for forming a semiconductor device according to an embodiment of the present invention is shown;

[0033] Figures 3a-3e A flowchart illustrating the fabrication process of a semiconductor device according to an embodiment of the present invention is shown;

[0034] Figure 4 This diagram illustrates a deposition of a decomposable thin film layer provided by an embodiment of the present invention;

[0035] Figures 5a to 5i A flowchart illustrating the formation process of another conductor device provided by an embodiment of the present invention is shown. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0037] Currently, RC delay directly impacts chip performance, power consumption, reliability, and cost. For example, reducing RC delay can increase the speed at which signals reach their destination, allowing chips to operate at higher frequencies and improving processing speed. Lower RC delay means circuits can complete operations in a shorter time, reducing power consumption. It also reduces signal attenuation and distortion, improving signal integrity and ensuring reliable data transmission. Furthermore, it allows for the integration of more circuitry within a smaller chip area, increasing chip integration density. Finally, it enables circuit designs with higher fault tolerance and makes it easier to meet timing requirements. Therefore, reducing RC delay is one of the core objectives of semiconductor process improvement.

[0038] For related metal gate electrode fabrication techniques, see, for example... Figures 1a-1e The flowchart shown illustrates the fabrication process of the related metal gate electrode, in which an interface layer 102 and an amorphous silicon dummy gate 103 are sequentially formed on the active region 101 of the semiconductor substrate 100. Figure 1bAs shown, on the surface of the semiconductor substrate 100, an interlayer dielectric layer (ILD) 104 is deposited at the location where the interface layer 102 and the amorphous silicon dummy gate 103 are not formed. The height of the interlayer dielectric layer 104 is flush with that of the amorphous silicon dummy gate 103. Figure 1c As shown, an amorphous silicon dummy gate 103 is removed from the buried interlayer dielectric layer 104 to form a trench. Figure 1d As shown, a gate oxide layer with a high dielectric constant and a metal gate electrode material are deposited. During deposition, the gate oxide layer with a high dielectric constant also covers the surface of the interlayer dielectric layer 104. The metal gate electrode material covers the surface of the gate oxide layer with a high dielectric constant. The metal gate electrode material and the gate oxide layer with a high dielectric constant are sequentially polished by chemical mechanical polishing (CMP) until the interlayer dielectric layer 104 is exposed, forming a gate oxide layer 105 with a high dielectric constant and a metal gate electrode 106. Figure 1e As shown, above the active regions 101 on both sides of the metal gate electrode 106, the interlayer dielectric layer 104 is etched to form source / drain contact hole electrodes 107.

[0039] from Figure 1e As can be seen, there is a high-dielectric-constant gate oxide layer 105 and an interlayer dielectric layer 104 between the contact hole 107 and the metal gate electrode 106. The high-dielectric-constant gate oxide layer 105 has an extremely high dielectric constant, which greatly increases the parasitic capacitance between the contact hole 107 and the metal gate electrode 106, increases RC delay, and causes the formed semiconductor device to be prone to a series of problems such as signal delay, increased dynamic power consumption, signal distortion and crosstalk, severe heat generation, and severe noise coupling.

[0040] To address the aforementioned issues, this invention provides a method for forming a semiconductor device and a semiconductor device in general. The following provides a detailed description of the embodiments of this invention.

[0041] This embodiment provides a method for forming a semiconductor device. This method can be applied to semiconductor process equipment. See [link to documentation]. Figure 2 The flowchart shown illustrates a method for forming a semiconductor device, which mainly includes the following steps:

[0042] Step S202: Deposit a gate oxide layer with a high dielectric constant onto a preset substrate;

[0043] See also Figures 3a-3e The diagram shown is a flowchart of a semiconductor device fabrication process, such as... Figure 3aAs shown, the preset substrate includes a substrate 100, an interface layer 102 located above the active region 101 of the substrate, and an interlayer dielectric layer 104 located at the position where the interface layer is not formed. The height of the interface layer 102 is less than the height of the interlayer dielectric layer 104 to form a trench. A gate oxide layer 301 with a high dielectric constant is deposited, and the gate oxide layer 301 covers the interlayer dielectric layer 104 and the bottom and sidewalls of the trench.

[0044] Step S204: A biodegradable thin film sidewall layer is formed on the trench sidewall;

[0045] like Figure 3a As shown, a degradable thin film sidewall layer 302' is formed on the trench sidewall, and the degradable thin film sidewall layer 302' is attached to the gate oxide layer 301 on the trench sidewall.

[0046] The material of the biodegradable film sidewall layer 302' can be a biodegradable sacrificial material that decomposes within a suitable temperature range, such as an ultraviolet (UV) biodegradable film.

[0047] Step S206: Deposit metal gate electrode material to form a metal gate electrode in the trench and remove the gate oxide layer above the interlayer dielectric layer;

[0048] like Figure 3b As shown, a metal gate electrode material is deposited, and the metal gate electrode material and gate oxide layer above the interlayer dielectric layer 104 are removed to expose the interlayer dielectric layer 104, forming a metal gate electrode 303 in the trench. The material of the metal gate electrode can be titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), molybdenum (Mo), ruthenium (Ru), etc.

[0049] Step S208: Deposit a porous thin film layer, etch the gate oxide layer on both sides of the trench and the interlayer dielectric layer in contact with the gate oxide layer, and fill with metal to form contact holes in contact with the source and drain active regions.

[0050] like Figure 3c As shown, a porous thin film layer 304 is deposited. This porous thin film layer 304 can be a thin film layer with a porous structure so that the gas generated during the decomposition of the decomposable thin film sidewall layer 302' can evaporate through the porous thin film layer 304. In a specific embodiment, to facilitate gas evaporation, the porous thin film layer 304 can be a silica-based porous thin film layer.

[0051] like Figure 3d As shown, the gate oxide layer on both sides of the trench and the interlayer dielectric layer in contact with the gate oxide layer are etched and filled with metal to form a contact hole electrode 305 that contacts the source and drain active regions.

[0052] Step S210: An annealing process is performed to decompose the decomposable thin film sidewall layer and volatilize it through the porous thin film layer, so that an air layer is formed between the contact hole and the metal gate electrode by the decomposable thin film sidewall layer.

[0053] like Figure 3e As shown, an annealing process is performed to decompose the decomposable thin film sidewall layer 302' on the inner sidewall of the trench, and the decomposed gas is volatilized through the porous thin film layer 304 above, so that an air layer 302" is formed between the decomposable thin film sidewall layer 302' between the contact hole and the metal gate electrode. Since the dielectric constant of the air layer 302" is 1, the parasitic capacitance between the metal gate electrode 303 and the source / drain contact hole electrode 305 of the semiconductor device can be minimized, thereby reducing RC delay.

[0054] The semiconductor device formation method provided in this embodiment forms a decomposable thin film sidewall layer on the trench sidewall and performs an annealing process after forming the metal gate electrode and contact hole. This causes the decomposable thin film sidewall layer to decompose and evaporate through the porous thin film layer to form an air layer. This can replace the high-dielectric-constant gate oxide layer between the contact hole and the metal gate electrode with a low-dielectric-constant air layer, thereby minimizing the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrode of the semiconductor device and reducing RC delay.

[0055] The semiconductor device formation method provided in this embodiment is applicable not only to the high-K metal gate (HKMG) process of planar transistors, but also to the HKMG process of FinFET and Gate-All-Around (GAA) transistors.

[0056] In one embodiment, this embodiment provides a specific implementation of forming a biodegradable thin film sidewall layer on the trench sidewall: depositing a biodegradable thin film layer over a gate oxide layer; and anisotropically etching the biodegradable thin film layer to form a biodegradable thin film sidewall layer attached to the trench sidewall.

[0057] Participate as Figure 4 The schematic diagram shown illustrates the deposition of a degradable thin film layer. A degradable thin film layer 302 is deposited above the gate oxide layer 301. The gate oxide layer 301 and the degradable thin film layer 302 cover the bottom, sidewalls, and exterior of the trench. Anisotropic etching is performed on the degradable thin film layer 302 to remove the degradable thin film layer above the interlayer dielectric layer 104 and at the bottom of the trench until the high-dielectric-constant gate oxide layer 301 is exposed, forming a layer as shown in the diagram. Figure 3a The biodegradable thin film sidewall layer 302' attached to the trench sidewall is shown.

[0058] In one embodiment, this embodiment provides a specific implementation method for depositing metal gate electrode material to form a metal gate electrode in a trench, thereby removing the gate oxide layer above the interlayer dielectric layer:

[0059] A metal gate electrode material is deposited, and the metal gate electrode material and the gate oxide layer are chemically and mechanically polished until the interlayer dielectric layer is exposed to form a metal gate electrode.

[0060] After depositing the metal gate electrode material, the metal gate electrode material will fill the trench. The deposited metal gate electrode material will also cover the gate oxide layer on the interlayer dielectric layer. The metal gate electrode material and the gate oxide layer are chemically and mechanically polished to remove the metal gate electrode material and the gate oxide layer on the interlayer dielectric layer, exposing the interlayer dielectric layer, and making the metal gate electrode in the trench flush with the surface of the interlayer dielectric layer.

[0061] In one embodiment, prior to step S202 above, the method provided in this embodiment further includes:

[0062] An interface layer and a replacement gate layer are sequentially formed at the active region of the substrate;

[0063] An interlayer dielectric layer is deposited at a location on the substrate surface where no interface layer or alternative gate layer has been formed;

[0064] The replacement gate layer buried in the interlayer dielectric layer is removed to form a trench, thus obtaining the predetermined substrate.

[0065] like Figures 1a-1c As shown, an interface layer 102 and a substitute gate layer 103 are sequentially formed at the active region 101 of the substrate 100. On the surface of the semiconductor substrate 100, an interlayer dielectric layer 104 is deposited at a location where the interface layer 102 and the substitute gate layer 103 are not formed. The substitute gate 103 is removed from the buried interlayer dielectric layer 104 to form a trench.

[0066] In one specific embodiment, the interface layer can be a silicon oxide layer or a silicon oxynitride layer.

[0067] In one specific embodiment, the material of the aforementioned alternative gate layer can be an amorphous silicon gate.

[0068] In one specific embodiment, the interlayer dielectric layer can be a silicon oxide layer.

[0069] The semiconductor device formation method provided in this embodiment can minimize the parasitic capacitance between the metal gate electrode and the source / drain contact electrode by forming an air layer on both sides of the metal gate electrode. This reduces signal delay, enabling the circuit to operate at higher speeds and frequencies. It also reduces dynamic power consumption, as dynamic power consumption is proportional to capacitance. A smaller capacitance indicates less energy consumed by the circuit at the same switching frequency, thus reducing overall power consumption. Furthermore, it reduces signal distortion and crosstalk, improves signal integrity, enhances heat dissipation performance, reduces noise coupling, and improves the noise performance of the circuit.

[0070] Based on the foregoing embodiments, this embodiment provides an example of using the aforementioned semiconductor device formation method to reduce the parasitic capacitance between the metal gate electrode and the contact hole electrode of the semiconductor device, as shown in the example below. Figures 5a to 5i The flowchart for the formation of another conductor device is shown below. The specific steps are as follows:

[0071] Step 501: An interface layer 102 and a substitute gate layer 103 are sequentially formed at the active region 101 of the substrate 100.

[0072] Step 502: On the surface of the semiconductor substrate 100, at the location where the interface layer 102 and the alternative gate layer 103 are not formed, an interlayer dielectric layer 104 is deposited.

[0073] Step 503: Remove the replacement gate 103 from the buried interlayer dielectric layer 104 to form a trench;

[0074] Step 504: Sequentially deposit a gate oxide layer 301 with a high dielectric constant and a degradable thin film layer 302;

[0075] Step 505: Anisotropic etching is performed on the decomposable thin film layer 302 until the gate oxide layer 301 with a high dielectric constant is exposed, forming a decomposable thin film sidewall layer 302' attached to the trench sidewall.

[0076] Step 506: Deposit metal gate electrode material, and perform chemical mechanical polishing on the metal gate electrode material and the gate oxide layer until the interlayer dielectric layer 104 is exposed to form metal gate electrode 303;

[0077] Step 507: Deposit a silica-based porous thin film layer 304;

[0078] Step 508: Etch the gate oxide layer with a high dielectric constant located on the trench sidewall and the interlayer dielectric layer in contact with it, and fill the metal to form a contact hole electrode 305 in contact with the active region.

[0079] Step 509: An annealing process is performed to decompose the decomposable thin film sidewall layer 302' in the trench, and volatilize it through the silica-based porous thin film layer 304 on it, so that an air layer 302 is formed on the sidewall of the metal gate electrode 303.

[0080] In this embodiment, a decomposable thin film sidewall layer is pre-deposited on both sides of the trench and then decomposed and volatilized through annealing to form an air layer. Since the dielectric constant of the air layer is 1, the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrode of the semiconductor device can be minimized, thereby reducing the RC delay.

[0081] Corresponding to the semiconductor device formation method provided in the above embodiments, this embodiment of the invention provides a semiconductor device, which is obtained by the semiconductor device formation method provided in the above embodiments.

[0082] like Figure 3e As shown, the semiconductor device includes a substrate 100, a porous thin film layer 304, an interface layer 102, a gate oxide layer 301 distributed above the interface layer, a metal gate electrode 303, and contact hole electrodes 305 distributed on both sides of the metal gate electrode 303, with an air layer 302 between the metal gate electrode 303 and the contact hole electrode 305.

[0083] The semiconductor device provided in this embodiment has the same implementation principle and technical effect as the aforementioned embodiments. For the sake of brevity, any parts not mentioned in the semiconductor device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0084] This invention provides an electronic device, which includes a processor and a memory. The memory stores a computer program that can run on the processor. When the processor executes the computer program, it implements the steps of the method provided in the above embodiments.

[0085] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system described above can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0086] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0087] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0089] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A gate oxide layer with a high dielectric constant is deposited on a predetermined substrate; wherein the predetermined substrate includes a substrate, an interface layer located above the active region of the substrate, and an interlayer dielectric layer located at a position where the interface layer is not formed, and the height of the interface layer is less than the height of the interlayer dielectric layer to form a trench. A biodegradable thin film sidewall layer is formed on the sidewall of the trench; Depositing metal gate electrode material in the trench forms a metal gate electrode, removing the gate oxide layer above the interlayer dielectric layer; A porous thin film layer is deposited, the gate oxide layer on both sides of the trench and the interlayer dielectric layer in contact with the gate oxide layer are etched, and metal is filled to form a contact hole electrode in contact with the source and drain active regions. An annealing process is performed to decompose the decomposable thin film sidewall layer and allow it to volatilize through the porous thin film layer, thereby forming an air layer between the contact hole and the metal gate electrode.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The process of forming a biodegradable thin film sidewall layer on the trench sidewall includes: A degradable thin film layer is deposited over the gate oxide layer; The degradable thin film layer is anisotropically etched to form the degradable thin film sidewall layer attached to the trench sidewall.

3. The method for forming a semiconductor device according to claim 1, characterized in that, The deposited metal gate electrode material forms a metal gate electrode within the trench, removing the gate oxide layer above the interlayer dielectric layer, including: A metal gate electrode material is deposited, and the metal gate electrode material and the gate oxide layer are chemically and mechanically polished until the interlayer dielectric layer is exposed to form the metal gate electrode.

4. The method for forming a semiconductor device according to claim 1, characterized in that, Before depositing a gate oxide layer with a high dielectric constant onto a predetermined substrate, the method further includes: The interface layer and the alternative gate layer are sequentially formed at the active region location of the substrate; The interlayer dielectric layer is deposited at a location on the substrate surface where the interface layer and the alternative gate layer are not formed; The alternative gate layer buried within the interlayer dielectric layer is removed to form a trench, thereby obtaining the preset substrate.

5. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The porous thin film layer is a silicon dioxide-based porous thin film layer.

6. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the biodegradable film sidewall layer includes a UV-biodegradable film.

7. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the interface layer includes silicon oxide or silicon oxynitride.

8. The method for forming a semiconductor device according to claim 4, characterized in that, The material of the alternative gate layer includes an amorphous silicon gate.

9. The method for forming a semiconductor device according to any one of claims 1-4, characterized in that, The material of the interlayer dielectric layer includes silicon oxide.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured by the semiconductor device forming method according to any one of claims 1-9.

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