Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, the semiconductor device comprises a semiconductor body, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body comprises a well region and a first region, and the first region is located on the first surface; the well region is located at one side of the first region away from the first surface; the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the first epitaxial layer is located at the bottom of the gate trench; the first insulating layer is positioned on the side wall of the gate trench and one side, close to the first surface, of the first epitaxial layer; a gate located in the gate trench and located at one side of the first insulating layer away from the semiconductor body; the source electrode is positioned on the first surface; and a drain electrode located on the second surface. According to the invention, high electric fields at the bottom and the groove angle of the gate groove can be effectively shielded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] The trench metal oxide semiconductor field effect transistor (MOSFET) semiconductor device has the advantages of large current density and small cell size. However, the high electric fields at the bottom and the corners of the gate trench result in a very high electric field on the gate oxide layer, which in turn causes the gate oxide layer to be extremely vulnerable to breakdown.

[0003] To better protect the gate oxide layer, one solution is that the trench MOSFET semiconductor device adopts a double trench structure, that is, source double trenches are constructed on both sides of the gate trench to shield the electric field at the bottom of the gate trench. However, the double trench structure requires additional fabrication of source trenches, and the process is complex. Another solution is that the trench MOSFET semiconductor device adopts an asymmetric gate trench structure, and the electric field at the bottom of the gate trench is weakened by embedding a P+ doped region or an N+ doped region at the bottom of the gate trench. However, the asymmetric structure sacrifices half of the conductive trenches, thereby reducing the on-state current. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle to solve the problem that the gate oxide layer of the trench MOSFET semiconductor device is extremely vulnerable to breakdown.

[0005] In a first aspect, the present invention provides a semiconductor device, which includes:

[0006] A semiconductor body of a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other. The semiconductor body includes a well region of a second conductivity type and a first region of a first conductivity type. The first region is located on the first surface, and the well region is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body;

[0007] A first epitaxial layer of a second conductivity type, located at the bottom of the gate trench;

[0008] A first insulating layer, located on the sidewall of the gate trench and on a side of the first epitaxial layer close to the first surface;

[0009] A gate located in the gate trench and on a side of the first insulating layer away from the semiconductor body;

[0010] A source located on the first surface;

[0011] The drain located on the second surface.

[0012] Optionally, the doping concentration of the first epitaxial layer is greater than that of the well region.

[0013] Optionally, the thickness of the first insulating layer on the side of the first epitaxial layer close to the first surface is greater than the thickness of the first insulating layer on the sidewall of the gate trench.

[0014] Optionally, the semiconductor device further includes a second insulating layer on the side of the gate away from the semiconductor body, and the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface;

[0015] The source is located on the first surface of the semiconductor body, the source is connected to the first region, and the vertical projection of the source on the first surface covers the vertical projection of the second insulating layer on the first surface.

[0016] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, and the manufacturing method includes:

[0017] Providing a semiconductor body of a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body includes a well region arranged as a second conductivity type and a first region arranged as a first conductivity type, the first region is located on the first surface, and the well region is located on the side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body;

[0018] Forming a first epitaxial layer of a second conductivity type at the bottom of the gate trench;

[0019] Forming a first insulating layer on the sidewall of the gate trench and on the side of the first epitaxial layer close to the first surface;

[0020] Forming a gate in the gate trench and on the side of the first insulating layer away from the semiconductor body;

[0021] Forming a source on the first surface;

[0022] Forming a drain on the second surface.

[0023] Optionally, forming a first epitaxial layer at the bottom of the gate trench includes:

[0024] Epitaxially growing a first epitaxial layer at the bottom and sidewall of the gate trench and on the first surface;

[0025] Forming a mask layer on the side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body;

[0026] Using the mask layer as a mask, remove the first epitaxial layer located on the first surface and at least partially on the sidewalls of the gate trenches;

[0027] Remove the mask layer.

[0028] Optionally, form a mask layer on the side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body, including:

[0029] Form a silicon dioxide mask layer on the side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0030] Optionally, form a first insulating layer on the sidewalls of the gate trenches and on the side of the first epitaxial layer close to the first surface, including:

[0031] Perform a thermal oxidation process on the first epitaxial layer at the bottom of the gate trench and perform a thermal oxidation process on the semiconductor body on the sidewalls of the gate trenches to form the first insulating layer; the oxidation rate of the first epitaxial layer is greater than the oxidation rate of the semiconductor body.

[0032] In a third aspect, the present invention provides a power module, which includes a substrate and at least one semiconductor device provided as in the first aspect above, and the substrate is used to carry the semiconductor device.

[0033] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0034] The power conversion circuit includes a circuit board and at least one semiconductor device provided as in the first aspect above, and the semiconductor device is electrically connected to the circuit board.

[0035] In a fifth aspect, the present invention provides a vehicle, which includes a load and a power conversion circuit provided as in the fourth aspect above. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0036] In the technical solution of the embodiment of the present invention, a first epitaxial layer is provided at the bottom and the corners of the gate trench. The first epitaxial layer can serve as an electric field shielding layer, which can effectively shield the high electric field at the bottom and the corners of the gate trench, and reduce the electric field strength at the bottom and the corners of the gate trench. The semiconductor device provided by the embodiment of the present invention does not need to be provided with a source trench. By providing the first epitaxial layer, the high electric field at the bottom and the corners of the gate trench can be effectively shielded, and the electric field strength at the bottom and the corners of the gate trench can be reduced. Therefore, the embodiment of the present invention effectively simplifies the manufacturing process of the semiconductor device, increases the contact area between the second region and the source, and reduces the contact resistance between the source and the second region. Moreover, the embodiment of the present invention does not need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric gate trench structure sacrifices half of the conductive trenches, resulting in a reduction in the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and the corners of the gate trench leads to a very high electric field on the gate oxide layer, and further leads to the easy breakdown of the gate oxide layer, effectively improving the reliability of the semiconductor device.

[0037] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0040] Figure 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0041] Figures 3 - 8 is a structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 9 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0043] Figures 10 - 12 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0044] Figure 13It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 14 It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0046] Figures 15 - 17 It is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Detailed implementation manners

[0047] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0049] In order to solve the problem that the high electric field at the bottom and corners of the gate trench of a trench MOSFET semiconductor device causes a very high electric field on the gate oxide layer, which in turn easily breaks down the gate oxide layer, and to improve the reliability of the trench MOSFET semiconductor device, the embodiments of the present invention provide the following technical solutions:

[0050] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, as Figure 1As shown, the semiconductor device includes: a semiconductor body 1 of a first conductivity type, the semiconductor body 1 includes a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 1 includes a well region 13 of a second conductivity type and a first region 14 of a first conductivity type, the first region 14 is located on the first surface 101, and the well region 13 is located on a side of the first region 14 away from the first surface 101. A gate trench is provided on the first surface 101, and the gate trench extends from the first surface 101 into the semiconductor body 1. A first epitaxial layer 16 of a second conductivity type is located at the bottom of the gate trench. A first insulating layer 17 is located on the sidewalls of the gate trench and on a side of the first epitaxial layer 16 close to the first surface 101. A gate 2 is located in the gate trench and on a side of the first insulating layer 17 away from the semiconductor body 1. A source 4 is located on the first surface 101. A drain 5 is located on the second surface 102.

[0051] Optionally, as Figure 1 shown, the semiconductor body 1 may further include a second region 15, and the doping concentration of the second region 15 is greater than that of the well region 13, and a good ohmic contact can be formed with the source 4.

[0052] It should be noted that the MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N+ doped region, the second region 15 is a P+ doped region, and the first epitaxial layer 16 is a P+ epitaxial layer. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P+ doped region, the second region 15 is an N+ doped region, and the first epitaxial layer 16 is an N+ epitaxial layer.

[0053] Exemplarily, as Figure 1As shown, the semiconductor body 1 may further include a substrate 11 and a second epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the second epitaxial layer 12 includes an N- epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the second epitaxial layer 12 includes a P- epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may also only include the second epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may further include a substrate 11 and a semiconductor layer formed by other processes. Among them, the second epitaxial layer 12 is a semiconductor layer formed on the basis of the substrate 11 through a single epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE). The conduction types of the first epitaxial layer 16 and the second epitaxial layer 12 may be different.

[0054] The semiconductor device may further include a first insulating layer 17. The first insulating layer 17 is located on the sidewalls of the gate trench and on the side of the first epitaxial layer 16 close to the first surface 101, and may also extend to the first surface 101. The first insulating layer 17 may include a gate oxide layer.

[0055] The first epitaxial layer 16 may be a semiconductor layer formed at the bottom of the gate trench through a single epitaxial process. The first epitaxial layer 16 has the advantages of controllable thickness and controllable doping region, and has a neat demarcation line with the second epitaxial layer 12. The bottom and corners of the gate trench are provided with the first epitaxial layer 16, and the first epitaxial layer 16 can be used as an electric field shielding layer, which can effectively shield the high electric field at the bottom and corners of the gate trench and reduce the electric field intensity at the bottom and corners of the gate trench.

[0056] In the technical solution of the embodiment of the present invention, the first epitaxial layer 16 is provided at the bottom and corners of the gate trench. The first epitaxial layer 16 can be used as an electric field shielding layer, which can effectively shield the high electric field at the bottom and corners of the gate trench and reduce the electric field intensity at the bottom and corners of the gate trench. The semiconductor device provided by the embodiment of the present invention does not need to be provided with a source trench. By providing the first epitaxial layer 16, the high electric field at the bottom and corners of the gate trench can be effectively shielded, and the electric field intensity at the bottom and corners of the gate trench can be reduced. Therefore, the embodiment of the present invention effectively simplifies the manufacturing process of the semiconductor device, increases the contact area between the second region 15 and the source 4, and reduces the contact resistance between the source 4 and the second region 15. Moreover, the embodiment of the present invention does not need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric gate trench structure sacrifices half of the conductive trench, resulting in a reduction in the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the electric field at the bottom and corners of the gate trench is strong, resulting in a very high electric field on the gate oxide layer, and thus the gate oxide layer is extremely easy to break down, effectively improving the reliability of the semiconductor device.

[0057] Optionally, based on the above embodiments, continue to refer to Figure 1 , the thickness of the first insulating layer 17 on the side of the first epitaxial layer 16 close to the first surface 101 is greater than the thickness of the first insulating layer 17 on the sidewall of the gate trench.

[0058] Specifically, at the bottom of the gate trench and on the side of the first epitaxial layer 16 close to the first surface 101, the thickness of the first insulating layer 17 is relatively thick, and the thickness of the first insulating layer 17 on the sidewall of the gate trench is relatively thin. By setting the thickness of the first insulating layer 17 on the side of the first epitaxial layer 16 close to the first surface 101 to be relatively thick, the breakdown voltage capability of the semiconductor device can be effectively improved, and further solves the problem that the high electric field at the bottom and the corner of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the first insulating layer 17, resulting in the first insulating layer 17 being extremely easy to break down.

[0059] Optionally, based on the above embodiments, continue to refer to Figure 1 , the doping concentration of the first epitaxial layer 16 is greater than the doping concentration of the well region 13.

[0060] Specifically, the first insulating layer 17 can be formed by thermally oxidizing the first epitaxial layer 16 at the bottom of the gate trench, the second epitaxial layer 12, the well region 13, and the first region 14 on the sidewall of the gate trench. The doping concentration of the first epitaxial layer 16 is greater than the doping concentration of the well region 13, and is also greater than the doping concentration of the second epitaxial layer 12, and can also be greater than the doping concentration of the first region 14, so that the oxidation rate of the first epitaxial layer 16 is greater than the oxidation rates of the second epitaxial layer 12, the well region 13, and the first region 14. Therefore, the thickness of the first insulating layer 17 formed by thermally oxidizing the first epitaxial layer 16 at the bottom of the gate trench is relatively thick, while the thickness of the first insulating layer 17 formed by thermally oxidizing the second epitaxial layer 12, the well region 13, and the first region 14 on the sidewall of the gate trench is relatively thin, realizing that the thickness of the first insulating layer 17 on the side of the first epitaxial layer 16 close to the first surface 101 at the bottom of the gate trench is greater than the thickness of the first insulating layer 17 on the sidewall of the gate trench.

[0061] By providing the first epitaxial layer 16 at the bottom of the gate trench, compared with thermally oxidizing the second epitaxial layer 12 at the bottom of the gate trench to form the first insulating layer 17, the thickness of the first insulating layer 17 formed by thermally oxidizing the first epitaxial layer 16 at the bottom of the gate trench is thicker. Such a setting can effectively improve the breakdown voltage capability of the semiconductor device, and further solves the problem that the high electric field at the bottom and the corner of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the first insulating layer 17, resulting in the first insulating layer 17 being extremely easy to break down.

[0062] Optionally, based on the above embodiments, continue to refer to Figure 1, the semiconductor device further includes a second insulating layer 3 located on the side of the gate 2 away from the semiconductor body 1, and the vertical projection of the second insulating layer 3 on the first surface 101 covers the vertical projection of the gate 2 on the first surface 101. The source electrode 4 is located on the first surface 101 of the semiconductor body 1, the source electrode 4 is connected to the first region 14, and the vertical projection of the source electrode 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101.

[0063] Specifically, for a single-groove MOSFET semiconductor device, its source structure is a planar source structure, that is, there is no need to set a source trench. The vertical projection of the first insulating layer 17 on the first surface 101 may coincide with the vertical projection of the second insulating layer 3 on the first surface 101. The second insulating layer 3 may include an interlayer dielectric layer, and the second insulating layer 3 is used for insulating and isolating the gate 2 and the source electrode 4. The source electrode 4 is located on the first surface 101 of the semiconductor body 1, and the material of the source electrode 4 may be metal. The source electrode 4 is electrically connected to the first region 14. The manufacturing process of the single-groove MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost. At the same time, the embodiment of the present invention increases the contact area between the second region 15 and the source electrode 4 and reduces the contact resistance between the source electrode 4 and the second region 15.

[0064] Figure 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 3 - 8 is a structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 2 shown, the manufacturing method includes:

[0065] S100: Provide a semiconductor body of a first conductivity type. The semiconductor body includes a first surface and a second surface arranged opposite to each other. The semiconductor body includes a well region of a second conductivity type and a first region of a first conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0066] Specifically, as Figure 3 shown, first provide the semiconductor body 1. The semiconductor body 1 may include a substrate 11 and a second epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also only include the second epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. Among them, the second epitaxial layer 12 is a semiconductor layer formed on the basis of the substrate 11 through a single epitaxial process. The epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0067] The semiconductor body 1 may further include a well region 13, a first region 14, and a second region 15. The well region 13, the first region 14, and the second region 15 are formed on the side of the second epitaxial layer 12 away from the substrate 11 through processes such as doping, and then the doped impurities are activated through an annealing process. A gate trench 20 is formed on the first surface 101 through processes such as photolithography and etching. The gate trench 20 can penetrate through the well region 13 and the first region 14 and extend into the second epitaxial layer 12.

[0068] The MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conduction type is N-type and the second conduction type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N+-doped region, the second region 15 is a P+-doped region, the substrate 11 is an N+ substrate, and the second epitaxial layer 12 is an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the first conduction type is P-type and the second conduction type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P+-doped region, the second region 15 is an N+-doped region, the substrate 11 is a P+ substrate, and the second epitaxial layer 12 is a P-epitaxial layer.

[0069] S110: Form a first epitaxial layer at the bottom of the gate trench, and the first epitaxial layer is set to the second conduction type.

[0070] Specifically, as Figure 4 shown, the conduction types of the first epitaxial layer 16 and the second epitaxial layer 12 may be different. For an N-channel MOSFET semiconductor device, the first epitaxial layer 16 may be a P+ epitaxial layer. For a P-channel MOSFET semiconductor device, the first epitaxial layer 16 may be an N+ epitaxial layer.

[0071] The first epitaxial layer 16 may be a semiconductor layer formed at the bottom of the gate trench through a single epitaxial process. The first epitaxial layer 16 has the advantages of controllable thickness and controllable doping region, and it has a neat demarcation line with the second epitaxial layer 12. The bottom and the corners of the gate trench are provided with the first epitaxial layer 16, and the first epitaxial layer 16 can be used as an electric field shielding layer, which can effectively shield the high electric field at the bottom and the corners of the gate trench and reduce the electric field intensity at the bottom and the corners of the gate trench.

[0072] S120: Form a first insulating layer on the sidewall of the gate trench and on the side of the first epitaxial layer close to the first surface.

[0073] Specifically, as Figure 5As shown, the semiconductor device may further include a first insulating layer 17. The first insulating layer 17 is located on the sidewalls of the gate trench and on the side of the first epitaxial layer 16 close to the first surface 101, and may also extend to the first surface 101. The first insulating layer 17 may include a gate oxide layer.

[0074] S130: Form a gate in the gate trench and on the side of the first insulating layer away from the semiconductor body.

[0075] Specifically, as Figure 6 shown, a gate 2 is formed in the gate trench and on the side of the first insulating layer 17 away from the semiconductor body 1. Exemplarily, the first insulating layer 17 may include a silicon dioxide insulating layer, and the gate 2 may include a doped polysilicon gate.

[0076] Specifically, as Figure 7 shown, after the gate 2 is formed, a second insulating layer 3 may be formed on the side of the gate 2 away from the semiconductor body 1. The vertical projection of the second insulating layer 3 on the first surface 101 may coincide with the vertical projection of the first insulating layer 17 on the first surface 101, and the vertical projection of the second insulating layer 3 on the first surface 101 should cover the vertical projection of the gate 2 on the first surface 101, so as to effectively insulate the source and the gate 2. The second insulating layer 3 may include an interlayer dielectric layer.

[0077] S140: Form a source on the first surface.

[0078] Specifically, as Figure 8 shown, the source structure is a planar source structure, that is, no source trench needs to be provided. The source 4 is located on the first surface 101 of the semiconductor body 1. Exemplarily, a metal is deposited on the first surface 101 to form the source 4. The source 4 is electrically connected to the first region 14, and the vertical projection of the source 4 on the first surface 101 may cover the vertical projection of the second insulating layer 3 on the first surface 101.

[0079] S150: Form a drain on the second surface.

[0080] Specifically, as Figure 1 shown, a drain 5 is formed on the second surface 102. Exemplarily, the drain 5 is formed by depositing a metal on the second surface 102.

[0081] In the technical solution of the embodiment of the present invention, a first epitaxial layer 16 is formed at the bottom and the groove corners of the gate trench through a single epitaxial process. The first epitaxial layer 16 can be used as an electric field shielding layer, which can effectively shield the high electric fields at the bottom and the groove corners of the gate trench, and reduce the electric field strength at the bottom and the groove corners of the gate trench. The semiconductor device provided by the embodiment of the present invention does not need to be provided with source trenches. By providing the first epitaxial layer 16, the high electric fields at the bottom and the groove corners of the gate trench can be effectively shielded, and the electric field strength at the bottom and the groove corners of the gate trench can be reduced. Therefore, the embodiment of the present invention effectively simplifies the manufacturing process of the semiconductor device, increases the contact area between the second region 15 and the source 4, and reduces the contact resistance between the source 4 and the second region 15. Moreover, the embodiment of the present invention does not need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric gate trench structure sacrifices half of the conductive trenches, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the electric fields at the bottom and the groove corners of the gate trench are relatively strong, resulting in a very high electric field on the gate oxide layer, and further causing the gate oxide layer to be easily broken down, effectively improving the reliability of the semiconductor device.

[0082] Optionally, on the basis of the above embodiments, Figure 9 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 10 - 12 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention, as Figure 9 shown. The manufacturing method includes:

[0083] S200: Provide a semiconductor body of a first conductivity type. The semiconductor body includes a first surface and a second surface arranged opposite to each other. The semiconductor body includes a well region of a second conductivity type and a first region of a first conductivity type. The first region is located on the first surface, and the well region is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0084] S210: Epitaxially grow a first epitaxial layer on the bottom and sidewalls of the gate trench and on the first surface.

[0085] Specifically, as Figure 10 shown, a first epitaxial layer 16 is epitaxially grown on the bottom and sidewalls of the gate trench 20 and on the first surface 101. The doping concentration of the first epitaxial layer 16 can be greater than the doping concentration of the well region 13.

[0086] S220: Form a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0087] Specifically, as Figure 11As shown, a mask layer 7 is formed on the side of the first epitaxial layer 16 away from the semiconductor body 1 at the bottom of the gate trench 20. Exemplarily, the mask layer 7 can be formed on the entire surface of the side of the first epitaxial layer 16 away from the semiconductor body 1, and then through a full-surface etch-back process, a small amount of the mask layer 7 remains on the side of the first epitaxial layer 16 away from the semiconductor body 1 at the bottom of the gate trench 20.

[0088] S230: Using the mask layer as a mask, remove the first epitaxial layer located on the first surface and at least partially on the sidewalls of the gate trench.

[0089] Specifically, as Figure 12 shown, using the mask layer 7 as a mask, remove the first epitaxial layer 16 located on the first surface 101 and at least partially on the sidewalls of the gate trench 20, and retain the first epitaxial layer 16 at the bottom of the gate trench 20.

[0090] S240: Remove the mask layer.

[0091] Specifically, as Figure 4 shown, remove the mask layer through processes such as wet etching.

[0092] S250: Form a first insulating layer on the sidewalls of the gate trench and on the side of the first epitaxial layer close to the first surface.

[0093] S260: Form a gate inside the gate trench and on the side of the first insulating layer away from the semiconductor body.

[0094] S270: Form a second insulating layer on the side of the gate away from the semiconductor body, and the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface.

[0095] S280: Form a source electrode on the first surface.

[0096] S290: Form a drain electrode on the second surface.

[0097] Optionally, on the basis of the above embodiments, Figure 13 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 13 shown, the manufacturing method includes:

[0098] S300: Provide a semiconductor body of a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body includes a well region of a second conductivity type and a first region of a first conductivity type, the first region is located on the first surface, and the well region is located on the side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0099] S310: Epitaxially grow a first epitaxial layer on the bottom and sidewalls of the gate trench and on the first surface.

[0100] S320: Form a silicon dioxide mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0101] Specifically, as Figure 11 shown, form a mask layer 7 on a side of the first epitaxial layer 16 at the bottom of the gate trench 20 away from the semiconductor body 1. Exemplarily, the mask layer 7 can be a silicon dioxide mask layer.

[0102] S330: Using the silicon dioxide mask layer as a mask, remove the first epitaxial layer located on the first surface and at least partially on the sidewalls of the gate trench.

[0103] S340: Remove the silicon dioxide mask layer.

[0104] S350: Form a first insulating layer on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface.

[0105] S360: Form a gate inside the gate trench and on a side of the first insulating layer away from the semiconductor body.

[0106] S370: Form a second insulating layer on a side of the gate away from the semiconductor body, and the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface.

[0107] S380: Form a source electrode on the first surface.

[0108] S390: Form a drain electrode on the second surface.

[0109] Optionally, based on the above embodiments, Figure 14 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 15 - 17 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 14 shown, the manufacturing method includes:

[0110] S400: Provide a semiconductor body of a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body includes a well region of a second conductivity type and a first region of a first conductivity type, the first region is located on the first surface, and the well region is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0111] S410: Epitaxially grow a first epitaxial layer on the bottom and sidewalls of the gate trench and on the first surface.

[0112] S420: Form a mask layer on the side of the first epitaxial layer away from the semiconductor body at the bottom of the gate trench.

[0113] S430: Using the mask layer as a mask, remove the first epitaxial layer located on the first surface and at least partially on the sidewall of the gate trench.

[0114] S440: Remove the mask layer.

[0115] S450: Perform thermal oxidation on the first epitaxial layer at the bottom of the gate trench and perform thermal oxidation on the semiconductor body on the sidewall of the gate trench to form a first insulating layer, and the oxidation rate of the first epitaxial layer is greater than the oxidation rate of the semiconductor body.

[0116] Specifically, as Figure 15 shown, thermal oxidation can be performed on the first epitaxial layer 16 at the bottom of the gate trench 20, and thermal oxidation can be performed on the second epitaxial layer 12, the well region 13, and the first region 14 on the sidewall of the gate trench 20, and thermal oxidation can be performed on the first region 14 and the second region 15 on the first surface to form the first insulating layer 17.

[0117] The doping concentration of the first epitaxial layer 16 is greater than the doping concentration of the well region 13, greater than the doping concentration of the second epitaxial layer 12, and can also be greater than the doping concentration of the first region 14, so that the oxidation rate of the first epitaxial layer 16 is greater than the oxidation rates of the second epitaxial layer 12, the well region 13, and the first region 14. Therefore, the thickness of the first insulating layer 17 formed by thermal oxidation of the first epitaxial layer 16 at the bottom of the gate trench is relatively thick, while the thickness of the first insulating layer 17 formed by thermal oxidation of the second epitaxial layer 12, the well region 13, and the first region 14 on the sidewall of the gate trench is relatively thin, realizing that the thickness of the first insulating layer 17 on the side of the first epitaxial layer 16 close to the first surface 101 at the bottom of the gate trench is greater than the thickness of the first insulating layer 17 on the sidewall of the gate trench.

[0118] By providing the first epitaxial layer 16 at the bottom of the gate trench, compared with forming the first insulating layer 17 by thermal oxidation of the second epitaxial layer 12 at the bottom of the gate trench, the thickness of the first insulating layer 17 formed by thermal oxidation of the first epitaxial layer 16 at the bottom of the gate trench is thicker. Such a setting can effectively improve the breakdown voltage capability of the semiconductor device, and further solve the problem that the high electric field at the bottom and the trench corners of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the first insulating layer 17, resulting in the first insulating layer 17 being extremely prone to breakdown.

[0119] S460: Form a gate in the gate trench and on the side of the first insulating layer away from the semiconductor body.

[0120] Specifically, as Figure 16As shown, a gate 2 is formed in the gate trench and on the side of the first insulating layer 17 away from the semiconductor body 1. Exemplarily, the gate 2 may include a polysilicon gate. First, doped polysilicon may be deposited over the entire surface in the gate trench and on the side of the first insulating layer 17 away from the first surface 101, and then etched back over the entire surface to form the gate 2 in the gate trench.

[0121] S470: A second insulating layer is formed on the side of the gate away from the semiconductor body, and the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface.

[0122] Specifically, as Figure 17 shown, a second insulating layer 3 may be formed on the side of the gate 2 away from the semiconductor body 1 and on the side of the first insulating layer 17 of the first surface 101 away from the first surface 101.

[0123] As Figure 7 shown, a part of the second insulating layer 3 on the first surface 101 and a part of the first insulating layer 17 on the first surface 101 are removed. The width of the second insulating layer 3 is greater than the width of the gate trench, and the first region 14 needs to be exposed.

[0124] S480: A source electrode is formed on the first surface.

[0125] S490: A drain electrode is formed on the second surface.

[0126] An embodiment of the present invention provides a power module. Among them, the power module includes a substrate and at least one semiconductor device provided in any of the above embodiments of the present invention, and the substrate is used to carry at least one semiconductor device provided in any of the above embodiments of the present invention.

[0127] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0128] An embodiment of the present invention provides a power conversion circuit. Among them, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0129] The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the above embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0130] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0131] An embodiment of the present invention provides a vehicle, wherein the vehicle includes a load and the power conversion circuit provided in any of the above embodiments of the present invention. The power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input it to the load.

[0132] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention. The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention. Therefore, the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0133] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0134] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body of a first conductivity type, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body including a well region of a second conductivity type and a first region of a first conductivity type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; A first epitaxial layer of the second conductivity type, located at the bottom of the gate trench; A first insulating layer, located on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface; A gate located within the gate trench and on a side of the first insulating layer away from the semiconductor body; A source located on the first surface; A drain located on the second surface.

2. The semiconductor device according to claim 1, wherein The doping concentration of the first epitaxial layer is greater than the doping concentration of the well region.

3. The semiconductor device according to claim 1, wherein The thickness of the first insulating layer on a side of the first epitaxial layer close to the first surface is greater than the thickness of the first insulating layer on the sidewalls of the gate trench.

4. The semiconductor device according to claim 1, characterized in that, Further included is a second insulating layer on a side of the gate away from the semiconductor body, and a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; The source is located on the first surface of the semiconductor body, the source is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

5. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor body of a first conductivity type, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body including a well region of a second conductivity type and a first region of a first conductivity type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; Forming a first epitaxial layer of the second conductivity type at the bottom of the gate trench; Forming a first insulating layer on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface; Forming a gate within the gate trench and on a side of the first insulating layer away from the semiconductor body; Forming a source on the first surface; Forming a drain on the second surface.

6. The manufacturing method of the semiconductor device according to claim 5, characterized in that, Forming a first epitaxial layer at the bottom of the gate trench, including: Epitaxially growing the first epitaxial layer on the bottom and sidewalls of the gate trench and on the first surface; Forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body; Using the mask layer as a mask to remove the first epitaxial layer located on the first surface and at least partially on the sidewalls of the gate trench; Removing the mask layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, Forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body, including: A silicon dioxide mask layer is formed on a side of the first epitaxial layer away from the semiconductor body at the bottom of the gate trench.

8. The method for manufacturing a semiconductor device according to claim 5, characterized in that, A first insulating layer is formed on a sidewall of the gate trench and on a side of the first epitaxial layer close to the first surface, including: Performing thermal oxidation treatment on the first epitaxial layer at the bottom of the gate trench and performing thermal oxidation treatment on the semiconductor body at the sidewall of the gate trench to form the first insulating layer, wherein an oxidation rate of the first epitaxial layer is greater than an oxidation rate of the semiconductor body.

9. A power module, characterized in that, Comprising a substrate and at least one semiconductor device as claimed in any one of claims 1-4, the substrate being configured to carry the semiconductor device.

10. A power conversion circuit, characterized in that, The power conversion circuit is configured for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as claimed in any one of claims 1-4, the semiconductor device being electrically connected to the circuit board.

11. A vehicle, characterized in that, Comprising a load and a power conversion circuit as claimed in claim 10, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted current to the load.

Images