Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and the semiconductor device comprises a semiconductor body which is provided with a first groove; the semiconductor device further comprises a first region, a second region, a first well region and a second well region. The grid electrode is located in the first groove, and the insulating layer wraps the surface of the grid electrode; the source electrode is located on the first surface, and at least part of the source electrode covers the first groove and covers the second area of the bottom wall; according to the semiconductor device, the number of conducting channels is increased, the overall channel density of the device is improved, the specific on-resistance of the semiconductor device is further reduced, the quality factor of the semiconductor device is improved, and the dynamic characteristic of the semiconductor device is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Silicon carbide (SiC) has excellent physical and electrical properties. Currently, semiconductor devices prepared using SiC materials have advantages such as a large current density and a small cell pitch, and are widely used.

[0003] For planar SiC semiconductor devices, it is necessary to reduce the width of the JFET region to protect the gate oxide in the forward blocking state. However, this will narrow the current path when the device is conducting, increase the on-resistance of the semiconductor device, and thus affect the conduction characteristics of the device. For trench-type SiC semiconductor devices, their feedback capacitance and gate-drain charge are relatively large, which will also lead to a decline in the switching performance of the device. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, which can increase the number of conductive channels, improve the overall channel density of the device, thereby reducing the specific on-resistance of the semiconductor device, and improving the figure of merit of the semiconductor device and the dynamic characteristics of the semiconductor device.

[0005] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0006] A semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a first trench, and the first trench extends from the first surface into the semiconductor body; the semiconductor body further includes a first region, a second region, a first well region, and a second well region; the first region is set to a first conduction type and is arranged on the first surface on one side of the first trench; the first well region is set to a second conduction type and is arranged on the side of the first region away from the first surface; the second region is set to a first conduction type and is arranged on the bottom wall of the first trench; the second well region is set to a second conduction type and is arranged on the side of the second region away from the bottom wall, and on the side of the second well region close to the first well region, at least a part of the second well region extends to the bottom wall; the first conduction type is different from the second conduction type;

[0007] A gate, located in the first trench, the vertical projection of the gate on the bottom wall at least covers the vertical projection of the second well region on the bottom wall; the vertical projection of the gate on the side wall of the first trench at least covers the vertical projection of the first well region on the side wall;

[0008] An insulating layer, covering the surface of the gate;

[0009] A source electrode, located on the first surface, and at least part of the source electrode covers the first trench, and covers the second region and the third region of the bottom wall;

[0010] A drain electrode, located on the second surface.

[0011] Optionally, there is a preset spacing distance between the orthographic projection of the first well region on the second surface and the orthographic projection of the second well region on the second surface.

[0012] Optionally, the semiconductor body further includes a third region, which is set to the second conductivity type, is disposed between the second well region and the bottom wall, and is adjacent to the second region; wherein, the ion concentration of the third region is greater than or equal to the ion concentration of the second well region.

[0013] Optionally, the first trench is a stepped trench, and the side wall of the first trench close to the first well region includes a first side wall and a second side wall extending along the first direction, and a third side wall extending along the second direction; the second direction is parallel to the first surface, and the first direction intersects with the second direction;

[0014] The first side wall is adjacent to the first well region;

[0015] The second side wall is located on the side of the first side wall away from the first surface, and the distance between the first side wall and the first well region in the second direction is less than the distance between the second side wall and the first well region in the second direction;

[0016] The third side wall is located between the first side wall and the second side wall; the first side wall and the third side wall are connected to form a first corner; the second side wall and the third side wall are connected to form a second corner; the second side wall and the bottom wall are connected to form a third corner.

[0017] Optionally, the semiconductor body further includes: a fourth region, which is set to the second conductivity type and is located on the side of the third side wall away from the first surface.

[0018] Optionally, the orthographic projection of the fourth region on the second surface does not overlap with the orthographic projection of the first well region on the second surface; the orthographic projection of the fourth region in the second direction does not overlap with the second well region.

[0019] Optionally, a sidewall of the first trench adjacent to the first well region includes a fourth sidewall extending in a first direction and a fifth sidewall extending in a third direction; wherein the first direction intersects a second direction, and the second direction is parallel to the first surface; the third direction intersects both the first direction and the second direction;

[0020] The fourth sidewall is adjacent to the first well region;

[0021] The fourth sidewall and the fifth sidewall are connected to form a fourth corner; the fifth sidewall and the bottom wall are connected to form a fifth corner; both the fourth corner and the fifth corner are greater than 90°; wherein the gate has the same shape as the first trench.

[0022] Optionally, the thickness of the insulating layer adjacent to the first well region and adjacent to the second well region is less than the thickness of the insulating layer at the remaining positions.

[0023] In a second aspect, an embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device as described in any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0024] In a third aspect, an embodiment of the present invention provides a power conversion circuit, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0025] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0026] In a fourth aspect, an embodiment of the present invention provides a vehicle, including a load and a power conversion circuit as described in any embodiment of the present invention, and the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0027] In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:

[0028] A semiconductor body is provided. The semiconductor body includes a first surface and a second surface which are oppositely arranged. The first surface is provided with a first trench that extends from the first surface into the semiconductor body. The semiconductor body further includes a first region, a second region, a first well region, and a second well region. The first region is of a first conductivity type and is disposed on the first surface on one side of the first trench. The first well region is of a second conductivity type and is disposed on the side of the first region away from the first surface. The second region is of a first conductivity type and is disposed on the bottom wall of the first trench. The second well region is of a second conductivity type and is disposed on the side of the second region away from the bottom wall. On the side of the second well region close to the first well region, at least part of the second well region extends to the bottom wall. The first conductivity type is different from the second conductivity type.

[0029] A gate is formed in the first trench. The vertical projection of the gate on the bottom wall at least covers the vertical projection of the second well region on the bottom wall. The vertical projection of the gate on the side wall of the first trench at least covers the vertical projection of the first well region on the side wall.

[0030] An insulating layer is formed on the surface of the gate.

[0031] A source electrode is formed on the first surface, and at least part of the source electrode covers the first trench, and at least part of the source electrode covers the second region on the bottom wall.

[0032] A drain electrode is formed on the second surface.

[0033] Optionally, providing the semiconductor body includes:

[0034] An epitaxial layer is grown on one side of a substrate.

[0035] The side of the epitaxial layer away from the substrate is used as the first surface. The first trench is formed on the first surface, and the first trench extends from the first surface into the epitaxial layer.

[0036] The first well region is formed on one side of the first surface. The second well region is formed on one side of the bottom wall of the first trench.

[0037] The first region is formed on the first surface on one side of the first trench, and the first region extends into the first well region. The second region is formed on the side of the bottom wall of the first trench away from the first surface, and the second region extends into the second well region. The first region is of a first conductivity type, and the first well region is of a second conductivity type. The second region is of a first conductivity type, and the second well region is of a second conductivity type. The first conductivity type is different from the second conductivity type.

[0038] Optionally, the first trench is a stepped trench; the sidewalls of the first trench include a first sidewall and a second sidewall extending in a first direction, and a third sidewall extending in a second direction; wherein, the first direction intersects the second direction, and the second direction is parallel to the first surface;

[0039] Forming the first trench in the first surface includes:

[0040] Forming a first sub-trench in the first surface, the first sub-trench extending from the first surface into the epitaxial layer;

[0041] Forming a second sub-trench in the bottom wall of the first sub-trench, the distance between the sidewall of the first sub-trench close to the first well region and the first well region in the second direction being less than the distance between the sidewall of the second sub-trench close to the first well region and the first well region in the second direction; the first sub-trench and the second sub-trench constitute the first trench; the sidewall of the first sub-trench close to the first well region serves as the first sidewall, the sidewall of the second sub-trench close to the first well region serves as the second sidewall, and a part of the bottom wall of the first sub-trench between the sidewall of the first sub-trench close to the first well region and the sidewall of the second sub-trench close to the first well region serves as the third sidewall; the first sidewall and the third sidewall are connected to form a first corner; the second sidewall and the third sidewall are connected to form a second corner; the second sidewall and the bottom wall are connected to form a third corner.

[0042] Optionally, the sidewalls of the first trench include a fourth sidewall extending in a first direction, and a fifth sidewall extending in a third direction; wherein, the first direction intersects the second direction, and the second direction is parallel to the first surface; the third direction intersects both the first direction and the second direction;

[0043] Forming the first trench in the first surface includes:

[0044] Forming a third sub-trench in the first surface, the third sub-trench extending from the first surface into the epitaxial layer;

[0045] Forming a fourth sub-trench in the bottom wall of the third sub-trench, the opening diameter of the third sub-trench being larger than the opening diameter of the fourth sub-trench;

[0046] Remove the corner between the bottom wall of the third sub-groove and the side wall of the fourth sub-groove close to the first well region; the third sub-groove and the fourth sub-groove constitute the first groove; the side wall of the third sub-groove close to the first well region serves as the fourth side wall, and the side wall corresponding to the removed corner serves as the fifth side wall; the fourth side wall and the fifth side wall are connected to form a fourth corner; the fifth side wall and the bottom wall of the fourth sub-groove are connected to form a fifth corner; both the fourth corner and the fifth corner are greater than 90°; wherein, the gate has the same shape as the first groove.

[0047] Optionally, forming an insulating layer on the surface of the gate includes:

[0048] Before forming the gate in the first groove, form a first sub-insulating layer on the side wall and the bottom wall of the first groove;

[0049] Thicken part of the thickness of the first sub-insulating layer so that the thickness of the first sub-insulating layer not adjacent to the first well region and the second well region is greater than the thickness of the first sub-insulating layer adjacent to the first well region and the second well region;

[0050] After forming the gate in the first groove, form a second sub-insulating layer on the side of the gate away from the semiconductor body; the first sub-insulating layer and the second sub-insulating layer constitute the insulating layer; wherein, the thickness of the second sub-insulating layer is greater than the thickness of the first sub-insulating layer.

[0051] Optionally, while thickening part of the thickness of the first sub-insulating layer, deposit a high-k material to form the composite first sub-insulating layer.

[0052] The semiconductor device provided by the embodiment of the present invention introduces a first groove in the semiconductor body, sets the second well region on the side of the second region away from the bottom wall, and at least part of the second well region on the side of the second well region close to the first well region extends to the bottom wall; then set the first region on the first surface on one side of the first groove, and set the first well region on the side of the first region away from the first surface. The gate in the first groove can control the conductive channels of the second region and the second well region, as well as the conductive channels of the first region and the first well region, thereby realizing a trench MOS device introduced on a planar MOS device, which can additionally increase the number of conductive channels, improve the overall channel density of the device, and further reduce the specific on-resistance of the semiconductor device. The gate in the first groove is a split gate, and the first well region and the second well region can serve as a suppression structure between the gate and the drain, suppressing the coupling between the gate and the drain, thereby reducing the feedback capacitance Crss between the gate and the drain and the gate-drain charge Qgd, which is beneficial to improving the figure of merit of the semiconductor device and improving the dynamic characteristics of the semiconductor device. Description of the Drawings

[0053] Figure 1 Schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0054] Figure 2 Schematic cross-sectional structure diagram of a first trench provided by an embodiment of the present invention;

[0055] Figure 3 Schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0056] Figure 4 Schematic cross-sectional structure diagram of another first trench provided by an embodiment of the present invention;

[0057] Figure 5 Schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0058] Figure 6 Flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 7 Flowchart of a method for manufacturing a semiconductor body provided by an embodiment of the present invention;

[0060] Figure 8 Schematic structural diagram of a semiconductor body provided by an embodiment of the present invention;

[0061] Figure 9 Flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0062] Figures 10-11 Schematic diagram of an intermediate structure in the manufacturing process provided by an embodiment of the present invention;

[0063] Figure 12 Flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0064] Figure 13 Schematic diagram of an intermediate structure in the manufacturing process provided by an embodiment of the present invention. Detailed implementation manners

[0065] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0066] Figure 1A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention is shown in Figure 1 , including:

[0067] A semiconductor body 100, the semiconductor body 100 includes a first surface and a second surface arranged opposite to each other. A first trench 10 is provided on the first surface, and the first trench 10 extends from the first surface into the semiconductor body 100; the semiconductor body 100 further includes a first region 20, a second region 30, a first well region 50 and a second well region 60; the first region 20 is set to a first conduction type and is arranged on the first surface on one side of the first trench 10; the first well region 50 is set to a second conduction type and is arranged on the side of the first region 20 away from the first surface; the second region 30 is set to the first conduction type and is arranged on the bottom wall of the first trench 10; the second well region 60 is set to the second conduction type and is arranged on the side of the second region 30 away from the bottom wall. On the side of the second well region 60 close to the first well region 50, at least part of the second well region 60 extends to the bottom wall; the first conduction type is different from the second conduction type;

[0068] A gate 110, located in the first trench 10, and the vertical projection of the gate 110 on the bottom wall at least covers the vertical projection of the second well region 60 on the bottom wall; the vertical projection of the gate 110 on the side wall of the first trench 10 at least covers the vertical projection of the first well region 50 on the side wall;

[0069] An insulating layer 120, covering the surface of the gate 110;

[0070] A source electrode 130, located on the first surface, and at least part of the source electrode 130 covers the first trench 10, and at least part of the source electrode 130 covers the second region 30 on the bottom wall;

[0071] A drain electrode 140, located on the second surface.

[0072] Specifically, the semiconductor body 100 may include a substrate 70 and an epitaxial layer 80. The epitaxial layer 80 is located on one side of the substrate 70. The materials of the substrate 70 and the epitaxial layer 80 may be silicon or silicon carbide. Exemplarily, the epitaxial layer 80 may be formed on the surface of the substrate 70 by epitaxial growth. In the embodiment of the present invention, the epitaxial layer 80 may further include a drift region 81 and a current diffusion region 82. The drift region 81 is adjacent to the substrate 70, and the current diffusion region 82 is located on the side of the drift region 81 away from the substrate 70. Taking the surface of the epitaxial layer 80 away from the substrate 70 as the first surface, at least one first trench 10 is formed on the first surface by an etching process. Among them, when the semiconductor body 100 is provided with one first trench 10, the semiconductor body 100 may form a shape similar to an "L", and when the semiconductor body 100 is provided with two first trenches 10, the semiconductor body 100 may form a shape similar to a "convex" character. Figure 1An exemplary illustration in the figure shows that the semiconductor body 100 is provided with two first trenches 10. A first region 20 is provided on the first surface between adjacent first trenches 10. A first well region 50 is provided on the side of the first region 20 away from the first surface. The first well region 50 and the first region 20 can form a conductive channel of a semiconductor device. Among them, the first region 20 is of the first conduction type, and the first well region 50 is of the second conduction type. A third region 40 can also be provided in the first region 20 between adjacent first trenches 10. The third region 40 is of the second conduction type. The first region 20 is isolated into two parts of the first region 20 through the third region 40, so that a conductive channel can be formed by the first well region 50 and the first region 20 on one side of each first trench 10. A second region 30 is provided on the bottom wall of the first trench 10 and extends to the current diffusion region 82 in the epitaxial layer 80. A second well region 60 is provided on the side of the second region 30 away from the bottom wall of the first trench 10. The second well region 60 and the second region 30 can form a conductive channel of a semiconductor device. Among them, the second region 30 is of the first conduction type, and the second well region 60 is of the second conduction type.

[0073] It should be noted that the first conduction type in the embodiments of the present invention can be an N-type conduction type, and the second conduction type can be a P-type conduction type, or the first conduction type can be a P-type conduction type, and the second conduction type can be an N-type conduction type. P+ and N+ shown in the drawings indicate that the ion conduction concentration in this region is high, and P- and N- indicate that the ion conduction concentration in this region is low. Among them, the N-type conduction type can be obtained by doping P (phosphorus) or N (nitrogen) ions, and the P-type conduction type can be obtained by doping Al (aluminum) ions or B (boron) ions. Exemplarily, taking the first conduction type as an N-type conduction type and the second conduction type as a P-type conduction type in the embodiments of the present invention, when the semiconductor device is an N-type device, the substrate 70 can be an N+-type silicon carbide substrate 70; the epitaxial layer 80 is an N--type silicon carbide epitaxial layer 80; when the semiconductor device is a P-type device, the substrate 70 is a P+-type silicon carbide substrate 70, and the epitaxial layer 80 is a P--type silicon carbide epitaxial layer 80.

[0074] The gate 110 is located in the first trench 10. In order to improve the control ability of the gate 110 over the first well region 50 and the second well region 60, the gate 110 can be provided on the side wall of the first trench 10 close to the first well region 50. The surface of the gate 110 is coated with an insulating layer 120. Exemplarily, before forming the gate 110, a first sub-insulating layer can be formed in the first trench 10 through a dry oxidation process. After forming the gate 110 through processes such as deposition and etching, a second sub-insulating layer is generated on the surface of the gate 110 through a wet oxidation process, and finally the insulating layer 120 covering the gate 110 is formed.

[0075] The vertical projection of the gate 110 on the bottom wall at least covers the vertical projection of the second well region 60 on the bottom wall. That is to say, the gate 110 can control the conductive channels of the second region 30 and the second well region 60. The second region 30, the second well region 60, and the gate 110 can form a planar MOS device. The vertical projection of the gate 110 on the sidewall of the first trench 10 at least covers the vertical projection of the first well region 50 on the sidewall. That is to say, the gate 110 can control the conductive channels of the first region 20 and the first well region 50. The first region 20, the first well region 50, and the gate 110 can form a trench-type MOS device. By introducing a trench-type MOS device on the planar MOS device, the number of conductive channels is additionally increased, the overall channel density of the device is improved, and thus the specific on-resistance of the semiconductor device is reduced. Further, since the gate 110 in each first trench 10 is a split gate, the coupling between the gate 110 and the drain can be suppressed by the collective effect of the first well region 50 and the second well region 60, thereby reducing the feedback capacitance Crss between the gate and the drain 140 and the gate-drain 140 charge Qgd, which is beneficial to improving the figure of merit of the semiconductor device and improving the dynamic characteristics of the semiconductor device.

[0076] In the semiconductor device provided by the embodiment of the present invention, by introducing the first trench 10 into the semiconductor body 100, the second well region 60 is disposed on the side of the second region 30 away from the bottom wall, and at least a part of the second well region 60 on the side of the second well region 60 close to the first well region 50 extends to the bottom wall; then the first region 20 is disposed on the first surface on one side of the first trench 10, and the first well region 50 is disposed on the side of the first region 20 away from the first surface. The gate 110 in the first trench 10 can control the conductive channels of the second region 30 and the second well region 60, and the conductive channels of the first region 20 and the first well region 50, so as to realize the introduction of a trench-type MOS device on the planar MOS device, which can additionally increase the number of conductive channels, improve the overall channel density of the device, and thus reduce the specific on-resistance of the semiconductor device. Further, since the gate 110 in the first trench 10 is a split gate, and the first well region 50 and the second well region 60 can be used as a suppression structure between the gate 110 and the drain 140 to suppress the coupling between the gate 110 and the drain 140, thereby reducing the feedback capacitance Crss between the gate and the drain 140 and the gate-drain 140 charge Qgd, which is beneficial to improving the figure of merit of the semiconductor device and improving the dynamic characteristics of the semiconductor device.

[0077] Continue to refer to Figure 1 , optionally, there is a preset interval distance between the positive projection of the first well region 50 on the second surface and the positive projection of the second well region 60 on the second surface.

[0078] Specifically, the first well region 50 is located on the first surface on one side of the first trench 10, and the second well region 60 is located on the bottom wall of the first trench 10. When there is a preset interval distance between the orthographic projections of the first well region 50 and the second well region 60 on the second surface, it indicates that there is also a certain interval distance between the conductive channels of the first well region 50 and the second well region 60. The conductive channel of the first well region 50 is offset in the second direction X compared to the conductive channel of the second well region 60. The second direction X is parallel to the first surface. Therefore, when the conductive channel of the first well region 50 is turned on, the current can be fully expanded in the current expansion region of the epitaxial layer 80, avoiding excessive current density in the JFET region caused by the simultaneous conduction of the conductive channels of the first well region 50 and the second well region 60, which may lead to local overheating and affect the on-resistance of the device. Exemplarily, in order to satisfy the offset of the conductive channel of the first well region 50 in the second direction X compared to the conductive channel of the second well region 60, the formation position of the second well region 60 can be controlled. For example, the second well region 60 is arranged on the bottom wall of the first trench 10 at a certain distance away from the first well region 50 in the opposite direction of the second direction X. The offset effect between the first well region 50 and the second well region 60 can also be achieved by changing the sidewall topography of the first trench 10.

[0079] Continuing to refer to Figure 1 Optionally, the semiconductor body 100 further includes a third region 40, which is set to the second conductivity type, is disposed between the second well region 60 and the bottom wall, and is adjacent to the second region 30; wherein, the ion concentration of the third region 40 is greater than or equal to the ion concentration of the second well region 60.

[0080] Specifically, the third region 40 is disposed on the side adjacent to the second region 30. The third region 40 can have the same ion concentration as that of the second well region 60 doped, or the ion concentration of the third region 40 doped is greater than the ion concentration of the second well region 60 doped. Exemplarily, when there are multiple adjacent Figure 1 shown cross-sectional structures in the second direction X, the third region 40 can be used as an isolation structure to isolate the conductive channels of the second well region 60 and the second region 30 in adjacent first trenches 10.

[0081] Based on the above embodiments, Figure 2 is a schematic cross-sectional structure diagram of a first trench provided by an embodiment of the present invention. Combining Figure 1 and referring to Figure 2 , the first trench 10 is a stepped trench. The sidewall of the first trench 10 adjacent to the first well region 50 includes a first sidewall 11 and a second sidewall 12 extending along the first direction Y, and a third sidewall 13 extending along the second direction X; the second direction X is parallel to the first surface, and the first direction Y intersects with the second direction X;

[0082] The first sidewall 11 is adjacent to the first well region 50;

[0083] The second sidewall 12 is located on the side of the first sidewall 11 away from the first surface. The distance between the first sidewall 11 and the first well region 50 in the second direction X is less than the distance between the second sidewall 12 and the first well region 50 in the second direction X;

[0084] The third sidewall 13 is located between the first sidewall 11 and the second sidewall 12; the first sidewall 11 and the third sidewall 13 are connected to form a first corner; the second sidewall 12 and the third sidewall 13 are connected to form a second corner; the second sidewall 12 and the bottom wall are connected to form a third corner.

[0085] Specifically, the first trench 10 adopts a stepped trench. The sidewall of the first trench 10 close to the first well region 50 has a stepped bend. Among them, the first sidewall 11 and the second sidewall 12 are sidewalls extending in the first direction Y, and the third sidewall 13 is a sidewall extending in the second direction X. Here, the first direction Y can be the direction perpendicular to the first surface, and the second direction X is the direction parallel to the first surface. The first sidewall 11 has an offset closer to the first well region 50 than the second sidewall 12 in the second direction X. Therefore, the first trench 10 can be a reverse stepped trench. The first sidewall 11 is adjacent to the first well region 50, and the bottom wall of the first trench 10 is adjacent to the second well region 60. Due to the shape of the stepped trench, the conduction channel of the first well region 50 can have an offset effect compared to the conduction channel of the second well region 60 in the second direction X. When forming the insulating layer 120 and the gate 110 in the first trench 10, the insulating layer 120 and the gate 110 can follow the sidewall morphology of the first trench 10 to form a stepped shape, so as to meet the control of the gate 110 over the conduction channel. Moreover, the first well region 50 is close to the first corner between the first sidewall 11 and the third sidewall 13, and the second well region 60 is close to the third corner between the second sidewall 12 and the bottom wall. The first well region 50 and the second well region 60 can jointly play a good role in protecting the corner of the insulating layer 120 at the step by electric field shielding.

[0086] Figure 3 It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. Refer to Figure 3 , including: The semiconductor body 100 further includes: a fourth region 90, which is set to the second conduction type and is located on the side of the third sidewall 13 away from the first surface.

[0087] Specifically, the difference between the embodiment of the present invention and the Figure 1 embodiment is that a fourth region 90 is provided at the second corner formed by the connection of the second sidewall 12 and the third sidewall 13. Exemplarily, the fourth region 90 is of P-type conduction type, so as to utilize the fourth region 90 to perform electric field shielding protection on the insulating layer 120 at the stepped second corner.

[0088] Optionally, the orthographic projection of the fourth region 90 on the second surface does not overlap with the orthographic projection of the first well region 50 on the second surface; the orthographic projection of the fourth region 90 in the second direction does not overlap with the second well region. That is to say, the fourth region 90 is located within the second corner, and the extension dimensions of the fourth region 90 in the first direction Y and in the second direction X do not exceed the second sidewall and the third sidewall, thereby avoiding the influence of the fourth region on the current path of the adjacent channel.

[0089] Figure 4 Schematic cross-sectional structure diagram of another first trench provided by an embodiment of the present invention Figure 5 Schematic structure diagram of another semiconductor device provided by an embodiment of the present invention, see Figure 5 , see Figures 4-5 , one sidewall of the first trench 10 close to the first well region 50 includes a fourth sidewall 14 extending along the first direction Y and a fifth sidewall 15 extending along the third direction; wherein, the first direction Y intersects with the second direction X, and the second direction X is parallel to the first surface; the third direction intersects with both the first direction Y and the second direction X;

[0090] The fourth sidewall 14 is adjacent to the first well region 50;

[0091] The fourth sidewall 14 and the fifth sidewall 15 are connected to form a fourth corner; the fifth sidewall 15 and the bottom wall are connected to form a fifth corner; both the fourth corner and the fifth corner are greater than 90°; wherein, the gate 110 has the same shape as the first trench 10.

[0092] Specifically, the difference between the embodiment of the present invention and the embodiment in Figure 1 is that the sidewall of the first trench 10 close to the first well region 50 has a sidewall inclined in the third direction. Here, the third direction intersects with both the first direction Y and the second direction X and has a certain included angle. The fourth sidewall 14 is the sidewall extending in the first direction Y, and the fourth sidewall 14 is connected to the bottom wall of the first trench 10 through the fifth sidewall 15, and both the fourth corner and the fifth corner are greater than 90°, that is to say, compared with the stepped trench in Figure 1 , the second corner and the second sidewall 12 are removed to obtain the fifth sidewall 15. Figure 4 The exemplary fifth sidewall 15 in is a straight sidewall, and in other embodiments, the fifth sidewall 15 can also be a curved arc sidewall.

[0093] The fourth sidewall 14 is adjacent to the first well region 50, and the bottom wall of the first trench 10 is adjacent to the second well region 60. Due to the inclination of the fifth sidewall 15, the conduction channel of the first well region 50 can also be offset in the second direction X compared to the conduction channel of the second well region 60. When forming the insulating layer 120 and the gate 110 in the first trench 10, the insulating layer 120 and the gate 110 can follow the sidewall morphology of the first trench 10, which can meet the control of the gate 110 over the conduction channel. The inclined fifth sidewall 15 can also slow down the corner degree at this position to reduce the electric field strength at the corner of the insulating layer 120 and prevent the phenomenon of electric field concentration.

[0094] Based on the above embodiments, optionally, the thickness of the insulating layer 120 adjacent to the first well region 50 and the second well region 60 is less than the thickness of the insulating layer 120 at the remaining positions. Taking Figure 2 as an example, the thickness of the insulating layer 120 on one side of the first sidewall 11 and the thickness of the insulating layer 120 on one side of the bottom wall of the first trench 10 are less than the thickness of the insulating layer 120 on one side of the other sidewalls, so as to ensure the control ability of the gate 110 over the first well region 50 and the second well region 60, and the shielding and protection effects can be improved by thickening the thickness of the insulating layer 120 on one side of the other sidewalls.

[0095] Based on the above embodiments, an embodiment of the present invention provides a power module, including a substrate and the semiconductor device of any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0096] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0097] Based on the above embodiments, an embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0098] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0099] Based on the above embodiments, an embodiment of the present invention provides a vehicle, including a load and a power conversion circuit as in any embodiment of the present invention, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it to the load.

[0100] Based on the above embodiments, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 6The following is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. With reference to Figure 1 、 Figure 3 and Figure 5 , the manufacturing method includes: Figure 6

[0101] S110. Provide a semiconductor body 100. The semiconductor body 100 includes a first surface and a second surface that are oppositely arranged. A first trench 10 is formed on the first surface, and the first trench 10 extends from the first surface into the semiconductor body 100. The semiconductor body 100 further includes a first region 20, a second region 30, a first well region 50, and a second well region 60. The first region 20 is of a first conduction type and is disposed on the first surface on one side of the first trench 10. The first well region 50 is of a second conduction type and is disposed on the side of the first region 20 away from the first surface. The second region 30 is of a first conduction type and is disposed on the bottom wall of the first trench 10. The second well region 60 is of a second conduction type and is disposed on the side of the second region 30 away from the bottom wall. On the side of the second well region 60 close to the first well region 50, at least a part of the second well region 60 extends to the bottom wall. The first conduction type is different from the second conduction type.

[0102] Specifically, the semiconductor body 100 may include a substrate 70 and an epitaxial layer 80. The epitaxial layer 80 is located on one side of the substrate 70. The materials of the substrate 70 and the epitaxial layer 80 may be silicon or silicon carbide. Exemplarily, the epitaxial layer 80 may be formed on the surface of the substrate 70 by epitaxial growth. In the embodiment of the present invention, the epitaxial layer 80 may further include a drift region 81 and a current diffusion region 82. The drift region 81 is adjacent to the substrate 70, and the current diffusion region 82 is located on the side of the drift region 81 away from the substrate 70. The surface of the epitaxial layer 80 away from the substrate 70 is used as the first surface, and at least one first trench 10 is formed on the first surface by an etching process. Wherein, when the semiconductor body 100 is provided with one first trench 10, the semiconductor body 100 may form a shape similar to an "L", and when the semiconductor body 100 is provided with two first trenches 10, the semiconductor body 100 may form a shape similar to a "convex" character. Figure 1 ​An exemplary illustration in the present invention is that a semiconductor body 100 is provided with two first trenches 10. A first region 20 is provided on a first surface between adjacent first trenches 10. A first well region 50 is provided on a side of the first region 20 away from the first surface. The first well region 50 and the first region 20 can form a conductive channel of a semiconductor device. Among them, the first region 20 is of a first conduction type, and the first well region 50 is of a second conduction type. A third region 40 can also be provided in the first region 20 between adjacent first trenches 10. The third region 40 is of the second conduction type. The first region 20 is isolated into two parts of the first region 20 through the third region 40, so that a conductive channel can be formed by the first well region 50 and the first region 20 on each side of each first trench 10. A second region 30 is provided on a bottom wall of the first trench 10 and extends to a current diffusion region 82 in an epitaxial layer 80. A second well region 60 is provided on a side of the second region 30 away from the bottom wall of the first trench 10. The second well region 60 and the second region 30 can form a conductive channel of a semiconductor device. Among them, the second region 30 is of the first conduction type, and the second well region 60 is of the second conduction type.

[0103] It should be noted that the first conduction type in the embodiments of the present invention can be an N-type conduction type, and the second conduction type can be a P-type conduction type, or the first conduction type can be a P-type conduction type, and the second conduction type can be an N-type conduction type. P+ and N+ shown in the drawings indicate that the ion conduction concentration in this region is high, and P- and N- indicate that the ion conduction concentration in this region is low. Among them, the N-type conduction type can be obtained by doping with P (phosphorus) or N (nitrogen) ions, and the P-type conduction type can be obtained by doping with Al (aluminum) ions or B (boron) ions. Exemplarily, in the embodiments of the present invention, taking the first conduction type as the N-type conduction type and the second conduction type as the P-type conduction type as an example, when the semiconductor device is an N-type device, the substrate 70 can be an N+-type conductive silicon carbide substrate 70; the epitaxial layer 80 is an N--type conductive silicon carbide epitaxial layer 80; when the semiconductor device is a P-type device, the substrate 70 is a P+-type conductive silicon carbide substrate 70, and the epitaxial layer 80 is a P--type conductive silicon carbide epitaxial layer 80.

[0104] S120. Form a gate 110 in the first trench 10. The vertical projection of the gate 110 on the bottom wall at least covers the vertical projection of the second well region 60 on the bottom wall; the vertical projection of the gate 110 on the side wall of the first trench 10 at least covers the vertical projection of the first well region 50 on the side wall;

[0105] Specifically, the gate 110 is located in the first trench 10. The gate 110 can be made of polysilicon material and is formed in the first trench 10 through a deposition process. In order to improve the control ability of the gate 110 over the first well region 50 and the second well region 60, the gate 110 can be provided on a side wall of the first trench 10 close to the first well region 50.

[0106] The vertical projection of the gate 110 on the bottom wall at least covers the vertical projection of the second well region 60 on the bottom wall. That is to say, the gate 110 can control the conductive channels of the second region 30 and the second well region 60. The second region 30, the second well region 60, and the gate 110 can form a planar MOS device. The vertical projection of the gate 110 on the side wall of the first trench 10 at least covers the vertical projection of the first well region 50 on the side wall. That is to say, the gate 110 can control the conductive channels of the first region 20 and the first well region 50. The first region 20, the first well region 50, and the gate 110 can form a trench MOS device. By introducing a trench MOS device on the planar MOS device, the number of conductive channels is additionally increased, the overall channel density of the device is improved, and further the specific on-resistance of the semiconductor device is reduced. Further, since the gate 110 in each first trench 10 is a split gate, the coupling between the gate 110 and the drain 140 can be suppressed by the collective effect of the first well region 50 and the second well region 60, thereby reducing the feedback capacitance Crss between the gate and the drain 140 and the gate-drain charge Qgd, which is beneficial to improving the figure of merit of the semiconductor device and improving the dynamic characteristics of the semiconductor device.

[0107] S130. Form an insulating layer 120 on the surface of the gate 110;

[0108] Specifically, the surface of the gate 110 is coated with an insulating layer 120. Exemplarily, before forming the gate 110, a first sub-insulating layer 120 can be formed in the first trench 10 by a dry oxidation process. After forming the gate 110 by processes such as deposition and etching, a second sub-insulating layer is generated on the surface of the gate 110 by a wet oxidation process, and finally the insulating layer 120 covering the gate 110 is formed.

[0109] S140. Form a source 130 on the first surface, and at least part of the source 130 covers the first trench 10 and the second region 30 covering the bottom wall;

[0110] Specifically, the source 130 can be formed on the first surface by means such as sputter coating. Exemplarily, the material of the source 130 can be titanium (Ti), nickel (Ni), or silver (Ag).

[0111] S150. Form a drain 140 on the second surface.

[0112] Specifically, first thin the surface of the substrate 70 away from the epitaxial layer 80, and then form the drain 140 by means such as sputter coating. Exemplarily, the material of the drain 140 can be titanium (Ti), nickel (Ni), or silver (Ag).

[0113] The manufacturing method of the semiconductor device provided by the embodiment of the present invention includes introducing a first trench 10 into the semiconductor body 100, disposing a second well region 60 on one side of the second region 30 away from the bottom wall, and extending at least a part of the second well region 60 on the side of the second well region 60 close to the first well region 50 to the bottom wall; then disposing the first region 20 on the first surface on one side of the first trench 10, and disposing the first well region 50 on the side of the first region 20 away from the first surface. The gate 110 in the first trench 10 can control the conductive channels of the second region 30 and the second well region 60, as well as the conductive channels of the first region 20 and the first well region 50, thereby realizing the introduction of a trench-type MOS device on a planar MOS device, which can additionally increase the number of conductive channels, improve the overall channel density of the device, and further reduce the specific on-resistance of the semiconductor device. Further, since the gate 110 in each first trench 10 is a split gate, and the first well region 50 and the second well region 60 can serve as a suppression structure between the gate 110 and the drain 140, suppressing the coupling between the gate 110 and the drain 140, thereby reducing the feedback capacitance Crss between the gate and the drain 140 and the gate-drain 140 charge Qgd, which is beneficial to improving the figure of merit of the semiconductor device and improving the dynamic characteristics of the semiconductor device.

[0114] As an alternative embodiment, Figure 7 is a flowchart of a manufacturing method of a semiconductor body provided by the embodiment of the present invention, Figure 8 is a schematic structural diagram of a semiconductor body provided by the embodiment of the present invention, in combination with Figure 1 , with reference to Figure 7 and Figure 8 , the manufacturing method includes:

[0115] S210. Grow an epitaxial layer 80 on one side of the substrate 70;

[0116] Specifically, the semiconductor body 100 may include a substrate 70 and an epitaxial layer 80. The epitaxial layer 80 is located on one side of the substrate 70. The materials of the substrate 70 and the epitaxial layer 80 may be silicon or silicon carbide. Exemplarily, the epitaxial layer 80 may be formed on the surface of the substrate 70 by epitaxial growth. In the embodiment of the present invention, the epitaxial layer 80 may further include a drift region 81 and a current diffusion region 82. The drift region 81 is adjacent to the substrate 70, and the current diffusion region 82 is located on the side of the drift region 81 away from the substrate 70.

[0117] S220. Take the side of the epitaxial layer 80 away from the substrate 70 as the first surface; form a first trench 10 on the first surface, and the first trench 10 extends from the first surface into the epitaxial layer 80;

[0118] Specifically, at least one first trench 10 is formed on the first surface through an etching process. When there is one first trench 10 in the semiconductor body 100, the semiconductor body 100 can form a shape similar to an "L". When there are two first trenches 10 in the semiconductor body 100, the semiconductor body 100 can form a shape similar to a "convex" character. Figure 1 The exemplary illustration in [reference] shows that there are two first trenches 10 in the semiconductor body 100.

[0119] S230. Form a first well region 50 on one side of the first surface; form a second well region 60 on one side of the bottom wall; the first well region 50 and the second well region 60 are of the second conductivity type;

[0120] Specifically, the first well region 50 and the second well region 60 have the same conductivity type, and the first well region 50 and the second well region 60 can be formed by means such as epitaxial growth, ion implantation, or vapor deposition. In the embodiments of the present invention, the first well region 50 and the second well region 60 can be formed by ion implantation. Exemplarily, the first well region 50 and the second well region 60 can be formed simultaneously through an ion implantation process. The first well region 50 is formed in the current diffusion region 82 on one side of the first surface between adjacent first trenches 10. The second well region 60 is formed in the current diffusion region 82 on one side of the bottom wall of the first trench 10. In some embodiments, the first well region 50 and the second well region 60 can also be formed separately through an ion implantation process, and no specific limitation is made here.

[0121] S240. Form a first region 20 on the first surface on one side of the first trench 10, and the first region 20 is located between the first well region 50 and the first surface; form a second region 30 on the side of the bottom wall of the first trench 10 away from the first surface, and the second region 30 is located between the second well region 60 and the bottom wall of the first trench 10; the first region 20 and the second region 30 are of the first conductivity type.

[0122] Specifically, the first region 20 and the second region 30 can be formed simultaneously through an ion implantation process. The first region 20 is formed on the first surface between adjacent first trenches 10 and extends from the first surface to be adjacent to the first well region 50. The second region 30 is formed on the bottom wall of the first trench 10 and extends from the bottom wall of the first trench 10 to be adjacent to the second well region 60. In some embodiments, the first region 20 and the second region 30 can also be formed separately through an ion implantation process, and no specific limitation is made here.

[0123] S250. Form a third region 40 on the side of the bottom wall of the first trench 10 away from the first surface, and the third region 40 is located between the second well region 60 and the bottom wall of the first trench 10 and is adjacent to the second region 30; the third region 40 is of the second conductivity type; the first conductivity type is different from the second conductivity type.

[0124] Specifically, in some embodiments, a third region 40 may be further provided in the first region 20 between adjacent first trenches 10. The third region 40 is of a second conductivity type. The first region 20 is separated into two parts by the third region 40, so that a conductive channel can be formed in the first well region 50 and the first region 20 on one side of each first trench 10. The third region 40 is formed on one side adjacent to the second region 30. The third region 40 may have the same ion doping concentration as that of the second well region 60, or the ion doping concentration of the third region 40 is greater than that of the second well region 60. Exemplarily, when there are multiple adjacent Figure 1 cross-sectional structures as shown, the third region 40 may serve as an isolation structure to isolate the conductive channels of the second well region 60 and the second region 30 in adjacent first trenches 10. Its structure is as Figure 8 shown.

[0125] An embodiment of the present invention takes the Figure 1 semiconductor device structure as an example to introduce a method for manufacturing a semiconductor device. Among them, the first trench 10 is a stepped trench; the sidewall of the first trench 10 includes a first sidewall 11 and a second sidewall 12 extending along the first direction Y, and a third sidewall 13 extending along the second direction X; wherein, the first direction Y intersects the second direction X, and the second direction X is parallel to the first surface.

[0126] Figure 9 FIG. is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figure 10 and Figure 11 FIG. is a schematic diagram of an intermediate structure in the manufacturing process provided by an embodiment of the present invention. The manufacturing method includes:

[0127] S310. Form an epitaxial layer 80 on one side of the substrate 70;

[0128] S320. Form a first sub-trench 16 on the first surface. The first sub-trench 16 extends from the first surface into the epitaxial layer 80; wherein, the first sub-trench 16 is etched on the first surface along the first direction Y by an etching process. Its structure is as Figure 10 shown.

[0129] S330. Form a second sub-trench 17 on the bottom wall of the first sub-trench 16. The distance between the sidewall of the first sub-trench 16 close to the first well region 50 and the first well region 50 in the second direction X is less than the distance between the sidewall of the second sub-trench 17 close to the first well region 50 and the first well region 50 in the second direction X;

[0130] Among them, the first sub-groove 16 and the second sub-groove 17 constitute the first groove 10; the side wall of the first sub-groove 16 close to the first well region 50 serves as the first side wall 11, the side wall of the second sub-groove 17 close to the first well region 50 serves as the second side wall 12, and a part of the bottom wall of the first sub-groove 16 between the side wall of the first sub-groove 16 close to the first well region 50 and the side wall of the second sub-groove 17 close to the first well region 50 serves as the third side wall 13; the first side wall 11 is connected to the third side wall 13 to form a first corner; the second side wall 12 is connected to the third side wall 13 to form a second corner; the second side wall 12 is connected to the bottom wall to form a third corner.

[0131] Specifically, the second sub-groove 17 is etched along the first direction Y on the bottom wall of the first sub-groove 16 through an etching process again. Among them, the side wall of the first sub-groove 16 close to the first well region 50 has an offset in the second direction X relative to the side wall of the second sub-groove 17 close to the first well region 50. Therefore, the first sub-groove 16 and the second sub-groove 17 can form the first groove 10 with a reverse stepped shape. Through two etching processes, each time a stepped groove is formed by removing a large amount of the epitaxial layer 80 and retaining the top epitaxial layer 80 above the JFET region. Each time the etching area of the groove is large, and the etching accuracy requirement is low. Compared with the conventional trench-type semiconductor device that digs a trench downward from the silicon carbide surface, the etching difficulty is reduced. Its structure is as Figure 11 shown.

[0132] S340. Form a first well region 50 on one side of the first surface; form a second well region 60 on one side of the bottom wall; the first well region 50 and the second well region 60 are of the second conductivity type;

[0133] S350. Form a first region 20 on the first surface on one side of the first groove 10. The first region 20 is located between the first well region 50 and the first surface; form a second region 30 on the side of the bottom wall of the first groove 10 away from the first surface. The second region 30 is located between the second well region 60 and the bottom wall of the first groove 10; the first region 20 and the second region 30 are of the first conductivity type.

[0134] S360. Form a third region 40 on the side of the bottom wall of the first groove 10 away from the first surface. The third region 40 is located between the second well region 60 and the bottom wall of the first groove 10 and is adjacent to the second region 30; the third region 40 is of the second conductivity type; the first conductivity type is different from the second conductivity type.

[0135] S370. Form a first sub-insulating layer 120 on the side wall and the bottom wall of the first groove 10;

[0136] Specifically, the first sub-insulating layer 120 is formed in the first groove 10 through a dry oxidation process. The first sub-insulating layer 120 can follow the shape of the side wall of the first groove 10.

[0137] S380. Form a gate 110 in the first trench 10. The vertical projection of the gate 110 on the bottom wall covers at least the vertical projection of the second well region 60 on the bottom wall; the vertical projection of the gate 110 on the side wall of the first trench 10 covers at least the vertical projection of the first well region 50 on the side wall.

[0138] S390. Form a second sub-insulating layer 120 on the side of the gate 110 away from the semiconductor body 100; the first sub-insulating layer 120 and the second sub-insulating layer 120 constitute the insulating layer 120.

[0139] Specifically, the second sub-insulating layer is generated on the surface of the gate 110 through a wet oxidation process, and finally an insulating layer 120 covering the gate 110 is formed. Among them, the thickness of the first sub-insulating layer 120 is less than the thickness of the second sub-insulating layer 120, which can ensure the control ability of the gate 110 over the first well region 50 and the second well region 60, and can also increase the thickness of the insulating layer 120 on the other side to improve the shielding and protection effects.

[0140] S400. Form a source electrode 130 on the first surface, and at least part of the source electrode 130 covers the first trench 10, as well as the second region 30 and the third region 40 covering the bottom wall.

[0141] S410. Form a drain electrode 140 on the second surface.

[0142] Optionally, the semiconductor body 100 further includes:

[0143] A fourth region 90, set to the second conduction type, is located on the side of the third side wall 13 away from the first surface.

[0144] Before forming the gate 110 in the first trench 10, a fourth region 90 is formed at the second corner formed by the connection of the second side wall 12 and the third side wall 13. Exemplarily, the fourth region 90 is of P-type conduction type, so as to use the fourth region 90 to perform an electric field shielding and protection function on the insulating layer 120 at the stepped second corner. Optionally, the positive projection of the fourth region 90 on the second surface does not overlap with the positive projection of the first well region 50 on the second surface; the positive projection of the fourth region 90 in the second direction does not overlap with the second well region. That is to say, the fourth region 90 is located within the second corner, and the extension dimensions of the fourth region 90 in the first direction Y and in the second direction X do not exceed the second side wall and the third side wall, so as to avoid the influence of the fourth region on the current path of the adjacent channel.

[0145] The embodiment of the present invention uses Figure 5Taking the semiconductor device structure as an example, a method for manufacturing a semiconductor device is introduced. Among them, the sidewall of the first trench 10 includes a fourth sidewall 14 extending along the first direction Y and a fifth sidewall 15 extending along the third direction. Among them, the first direction Y intersects with the second direction X, the second direction X is parallel to the first surface, and the third direction intersects with both the first direction Y and the second direction X.

[0146] Figure 12 FIG. 4 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 13 FIG. 5 is a schematic diagram of an intermediate structure in the manufacturing process provided by an embodiment of the present invention. The manufacturing method includes:

[0147] S510. Form an epitaxial layer 80 on one side of the substrate 70.

[0148] S520. Form a third sub-trench 18 on the first surface. The third sub-trench extends from the first surface into the epitaxial layer 80.

[0149] Specifically, a third sub-trench 18 is formed on the first surface. The third sub-trench 18 extends from the first surface into the epitaxial layer 80. Among them, the third sub-trench 18 is formed by etching along the first direction Y on the first surface. Its structure is as Figure 10 shown.

[0150] S530. Form a fourth sub-trench 19 on the bottom wall of the third sub-trench 18. The distance between the sidewall of the third sub-trench 18 close to the first well region 50 and the first well region 50 in the second direction X is less than the distance between the sidewall of the fourth sub-trench 19 close to the first well region 50 and the first well region 50 in the second direction X.

[0151] Specifically, the fourth sub-trench 19 is formed by etching along the first direction Y on the bottom wall of the third sub-trench 18 again. Among them, the sidewall of the third sub-trench 18 close to the first well region 50 has an offset relative to the sidewall of the fourth sub-trench 19 close to the first well region 50 in the second direction X. Through two etching processes, each time a stepped trench is formed by removing a large amount of the epitaxial layer 80 and retaining the top epitaxial layer 80 above the JFET region. The etching area of each trench is large, and the etching accuracy requirement is low. Compared with the conventional trench-type semiconductor device that digs a trench downward from the silicon carbide surface, the etching difficulty is reduced. Its structure is as Figure 11 shown.

[0152] S540. Remove the corner between the bottom wall of the third sub-trench 18 and the sidewall of the fourth sub-trench 19 close to the first well region 50, so that the sidewall of the third sub-trench 18 close to the first well region 50 is connected to the sidewall of the fourth sub-trench 19 close to the first well region 50 through the fifth sidewall 15.

[0153] Among them, the corresponding sidewall after removing the corner serves as the fifth sidewall 15; the third sub-groove 18 and the fourth sub-groove 19 form the first groove 10; the sidewall of the third sub-groove 18 close to the first well region 50 serves as the fourth sidewall 14, and the fourth sidewall 14 is connected to the fifth sidewall 15 to form a fourth corner; the fifth sidewall 15 is connected to the bottom wall of the fourth sub-groove 19 to form a fifth corner; the gate 110 has the same shape as the first groove 10.

[0154] Specifically, due to the inclination of the fifth sidewall 15, the conductive channel of the first well region 50 can also be offset in the second direction X compared to the conductive channel of the second well region 60. When forming the insulating layer 120 and the gate 110 in the first groove 10, the insulating layer 120 and the gate 110 can follow the sidewall morphology of the first groove 10, which can meet the control of the gate 110 over the conductive channel. The inclined fifth sidewall 15 can also slow down the corner degree at this position to reduce the electric field intensity at the corner of the insulating layer 120 and prevent the phenomenon of electric field concentration. Its structure is as Figure 13 shown. The fifth sidewall 15 exemplified in the figure is a straight sidewall. In other embodiments, the fifth sidewall 15 can also be a curved arc sidewall.

[0155] S550. Form a first well region 50 on one side of the first surface; form a second well region 60 on one side of the bottom wall; the first well region 50 and the second well region 60 are of the second conductivity type;

[0156] S560. Form a first region 20 on the first surface on one side of the first groove 10, and the first region 20 is located between the first well region 50 and the first surface; form a second region 30 on the side of the bottom wall of the first groove 10 away from the first surface, and the second region 30 is located between the second well region 60 and the bottom wall of the first groove 10; the first region 20 and the second region 30 are of the first conductivity type.

[0157] S570. Form a third region 40 on the side of the bottom wall of the first groove 10 away from the first surface, and the third region 40 is located between the second well region 60 and the bottom wall of the first groove 10 and is adjacent to the second region 30; the third region 40 is of the second conductivity type; the first conductivity type is different from the second conductivity type.

[0158] S580. Form a first sub-insulating layer 120 on the sidewall and the bottom wall of the first groove 10;

[0159] S590. Form a gate 110 in the first groove 10, and the vertical projection of the gate 110 on the bottom wall at least covers the vertical projection of the second well region 60 on the bottom wall; the vertical projection of the gate 110 on the sidewall of the first groove 10 at least covers the vertical projection of the first well region 50 on the sidewall;

[0160] S600. A second sub-insulating layer 120 is formed on the side of the gate 110 away from the semiconductor body 100; the first sub-insulating layer 120 and the second sub-insulating layer 120 constitute the insulating layer 120;

[0161] S610. A source electrode 130 is formed on the first surface, and at least a part of the source electrode 130 covers the first trench 10, as well as the second region 30 and the third region 40 covering the bottom wall;

[0162] S620. A drain electrode 140 is formed on the second surface.

[0163] Based on the above embodiments, optionally, after the first sub-insulating layer 120 is formed on the sidewall and the bottom wall of the first trench 10, the thickness of a part of the first sub-insulating layer 120 is increased so that the thickness of the first sub-insulating layer 120 not adjacent to the first well region 50 and the second well region 60 is greater than the thickness of the first sub-insulating layer 120 adjacent to the first well region 50 and the second well region 60.

[0164] Specifically, before forming the gate 110, the first sub-insulating layer 120 can be formed in the first trench 10 by a dry oxidation process, and the first sub-insulating layer 120 can follow the sidewall morphology of the first trench 10. Then, the thickness of the first sub-insulating layer 120 not adjacent to the first well region 50 and the second well region 60 is increased, and the shielding ability is improved by increasing the thickness of the first sub-insulating layer 120. Optionally, a high-k material can be deposited while increasing the thickness of a part of the first sub-insulating layer 120 to form a composite first sub-insulating layer 120. By using the composite first sub-insulating layer 120 with a high-k material, the electron mobility at the interface of the gate 110 can be improved, and the on-resistance of the device can be reduced. After the gate 110 is formed by processes such as deposition and etching, a second sub-insulating layer is generated on the surface of the gate 110 by a wet oxidation process, and finally the insulating layer 120 covering the gate 110 is formed. Among them, the thickness of the second sub-insulating layer 120 is greater than the thickness of the first sub-insulating layer 120, that is to say, the thickness of the insulating layer 120 adjacent to the first well region 50 and the second well region 60 is the thinnest region compared with the entire insulating layer 120, so as to ensure the control ability of the gate 110 over the first well region 50 and the second well region 60, and the shielding and protection effects can be improved by increasing the thickness of the insulating layer 120 on the other sidewall.

[0165] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body, the semiconductor body includes a first surface and a second surface disposed opposite to each other, the first surface is provided with a first trench, and the first trench extends from the first surface into the semiconductor body; the semiconductor body further includes a first region, a second region, a first well region, and a second well region; the first region is set to a first conduction type and is disposed on the first surface on one side of the first trench; the first well region is set to a second conduction type and is disposed on the side of the first region away from the first surface; the second region is set to the first conduction type and is disposed on the bottom wall of the first trench; the second well region is set to the second conduction type and is disposed on the side of the second region away from the bottom wall, and at least part of the second well region extends to the bottom wall on the side of the second well region close to the first well region; the first conduction type is different from the second conduction type; A gate, located in the first trench, and the vertical projection of the gate on the bottom wall at least covers the vertical projection of the second well region on the bottom wall; The vertical projection of the gate on the side wall of the first trench at least covers the vertical projection of the first well region on the side wall; An insulating layer, covering the surface of the gate; A source electrode, located on the first surface, and at least part of the source electrode covers the first trench, and at least part of the source electrode covers the second region on the bottom wall; A drain electrode, located on the second surface.

2. The semiconductor device according to claim 1, wherein There is a preset interval distance between the positive projection of the first well region on the second surface and the positive projection of the second well region on the second surface.

3. The semiconductor device according to claim 2, wherein, The semiconductor body further includes a third region, the third region is set to the second conduction type, is disposed between the second well region and the bottom wall, and is adjacent to the second region; wherein, the ion concentration of the third region is greater than or equal to the ion concentration of the second well region.

4. The semiconductor device according to claim 2, wherein The first trench is a stepped trench, and the side wall of the first trench close to the first well region includes a first side wall and a second side wall extending along a first direction, and a third side wall extending along a second direction; the second direction is parallel to the first surface, and the first direction intersects with the second direction; The first side wall is adjacent to the first well region; The second side wall is located on the side of the first side wall away from the first surface, and the distance between the first side wall and the first well region in the second direction is less than the distance between the second side wall and the first well region in the second direction; The third side wall is located between the first side wall and the second side wall; the first side wall and the third side wall are connected to form a first corner; the second side wall and the third side wall are connected to form a second corner; the second side wall and the bottom wall are connected to form a third corner.

5. The semiconductor device according to claim 4, wherein The semiconductor body further includes: a fourth region, set to the second conduction type, located on the side of the third side wall away from the first surface.

6. The semiconductor device according to claim 5, wherein, The positive projection of the fourth region on the second surface does not overlap with the positive projection of the first well region on the second surface; the positive projection of the fourth region in the second direction does not overlap with the second well region.

7. The semiconductor device according to claim 2, wherein The side wall of the first trench adjacent to the first well region includes a fourth side wall extending in a first direction and a fifth side wall extending in a third direction; wherein the first direction intersects the second direction, the second direction is parallel to the first surface; the third direction intersects both the first direction and the second direction; The fourth side wall is adjacent to the first well region; The fourth side wall and the fifth side wall are connected to form a fourth corner; the fifth side wall and the bottom wall are connected to form a fifth corner; both the fourth corner and the fifth corner are greater than 90°; wherein the gate has the same shape as the first trench.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The thickness of the insulating layer adjacent to the first well region and adjacent to the second well region is less than the thickness of the insulating layer at the remaining positions.

9. A power module, characterized in that, Comprising a substrate and at least one semiconductor device as described in any one of claims 1-8, the substrate being used to carry the semiconductor device.

10. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-8, the semiconductor device being electrically connected to the circuit board.

11. A vehicle, characterized in that, Comprising a load and a power conversion circuit as described in claim 10, the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a first trench, the first trench extends from the first surface into the semiconductor body; the semiconductor body further includes a first region, a second region, a first well region and a second well region; the first region is set to a first conduction type and is arranged on the first surface on one side of the first trench; the first well region is set to a second conduction type and is arranged on the side of the first region away from the first surface; the second region is set to a first conduction type and is arranged on the bottom wall of the first trench; the second well region is set to a second conduction type and is arranged on the side of the second region away from the bottom wall, on the side of the second well region close to the first well region, at least part of the second well region extends to the bottom wall; the first conduction type is different from the second conduction type; Forming a gate in the first trench, the vertical projection of the gate on the bottom wall at least covers the vertical projection of the second well region on the bottom wall; the vertical projection of the gate on the side wall of the first trench at least covers the vertical projection of the first well region on the side wall; Forming an insulating layer on the surface of the gate; Forming a source electrode on the first surface, and at least part of the source electrode covers the first trench, and at least part of the source electrode covers the second region of the bottom wall; Form a drain on the second surface.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, Provide a semiconductor body including: Grow an epitaxial layer on one side of the substrate; Use the side of the epitaxial layer away from the substrate as the first surface; form the first trench on the first surface, and the first trench extends from the first surface into the epitaxial layer; Form the first well region on one side of the first surface; form the second well region on one side of the bottom wall of the first trench; Form the first region on the first surface on one side of the first trench, and the first region extends into the first well region; form the second region on the side of the bottom wall of the first trench away from the first surface, and the second region extends into the second well region; the first region is of a first conduction type, and the first well region is of a second conduction type; the second region is of the first conduction type, and the second well region is of the second conduction type; the first conduction type is different from the second conduction type.

14. The method for manufacturing a semiconductor device according to claim 13, wherein, The first trench is a stepped trench; the side walls of the first trench include a first side wall and a second side wall extending in a first direction, and a third side wall extending in a second direction; wherein, the first direction intersects with the second direction, and the second direction is parallel to the first surface; Forming the first trench on the first surface includes: Form a first sub-trench on the first surface, and the first sub-trench extends from the first surface into the epitaxial layer; Form a second sub-trench on the bottom wall of the first sub-trench, and the distance between the side wall of the first sub-trench close to the first well region and the first well region in the second direction is less than the distance between the side wall of the second sub-trench close to the first well region and the first well region in the second direction; the first sub-trench and the second sub-trench constitute the first trench; the side wall of the first sub-trench close to the first well region serves as the first side wall, the side wall of the second sub-trench close to the first well region serves as the second side wall, and a part of the bottom wall of the first sub-trench between the side wall of the first sub-trench close to the first well region and the side wall of the second sub-trench close to the first well region serves as the third side wall; the first side wall and the third side wall are connected to form a first corner; the second side wall and the third side wall are connected to form a second corner; the second side wall and the bottom wall are connected to form a third corner.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The side walls of the first trench include a fourth side wall extending in a first direction, and a fifth side wall extending in a third direction; wherein, the first direction intersects with the second direction, and the second direction is parallel to the first surface; the third direction intersects with both the first direction and the second direction; Forming the first trench on the first surface includes: Form a third sub-trench on the first surface, and the third sub-trench extends from the first surface into the epitaxial layer; Form a fourth sub-trench on the bottom wall of the third sub-trench, and the opening diameter of the third sub-trench is larger than the opening diameter of the fourth sub-trench; Remove the corner between the bottom wall of the third sub-groove and the side wall of the fourth sub-groove close to the first well region; the third sub-groove and the fourth sub-groove constitute the first groove; the side wall of the third sub-groove close to the first well region serves as the fourth side wall, and the side wall corresponding to the removed corner serves as the fifth side wall; the fourth side wall and the fifth side wall are connected to form a fourth corner; the fifth side wall and the bottom wall of the fourth sub-groove are connected to form a fifth corner; both the fourth corner and the fifth corner are greater than 90°; wherein, the gate has the same shape as the first groove.

16. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming an insulating layer on the surface of the gate includes: Before forming the gate in the first groove, forming a first sub-insulating layer on the side walls and the bottom wall of the first groove; Thickening the thickness of part of the first sub-insulating layer so that the thickness of the first sub-insulating layer not adjacent to the first well region and the second well region is greater than the thickness of the first sub-insulating layer adjacent to the first well region and the second well region; After forming the gate in the first groove, forming a second sub-insulating layer on the side of the gate away from the semiconductor body; the first sub-insulating layer and the second sub-insulating layer constitute the insulating layer; wherein, the thickness of the second sub-insulating layer is greater than the thickness of the first sub-insulating layer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein, While thickening the thickness of part of the first sub-insulating layer, depositing a high-k material to form the composite first sub-insulating layer.

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