Semiconductor devices comprising multilayer titanium nitride

Abstract

The semiconductor device includes a silicon surface (1402), a titanium silicide layer (1404) in contact with the silicon surface, a first titanium nitride layer (1406) over the titanium silicide layer, a titanium oxynitride layer (1512) in contact with the first titanium nitride layer, a second titanium nitride layer (1516) in contact with the titanium oxynitride layer, and a metal fill layer (84B) over the second titanium nitride layer.

Description

[0001] This application is a divisional application of Chinese Patent Application (Application No.: 201780003018.9, filing date: November 17, 2017, invention title: Semiconductor device including a multi-layer titanium nitride diffusion barrier and method for manufacturing the same).

[0002] Related Applications

[0003] This application claims the priority of U.S. Provisional Patent Application No. 62 / 463,291, filed on February 24, 2017, and U.S. Non - Provisional Application No. 15 / 617,499, filed on June 8, 2017, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure generally relates to the field of semiconductor devices, and in particular, to three - dimensional memory devices including multi - layer titanium nitride diffusion barriers and methods for manufacturing the same. Background Art

[0005] Three - dimensional vertical NAND strings having one bit per cell are disclosed in the article entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell" by T. Endoh et al. in IEDM Proc. (2001) 33 - 36. Summary of the Invention

[0006] According to an aspect of the present disclosure, a semiconductor device includes a silicon surface, a titanium silicide layer in contact with the silicon surface, a first titanium nitride layer located above the titanium silicide layer, a titanium oxynitride layer in contact with the first titanium nitride layer, a second titanium nitride layer in contact with the titanium oxynitride layer, and a metal fill layer located above the second titanium nitride layer.

[0007] According to an aspect of the present disclosure, a method for manufacturing a semiconductor device includes forming a titanium silicide layer in contact with a silicon surface, forming a first titanium nitride layer located above the titanium silicide layer, performing a titanium silicide crystallization annealing to crystallize the titanium silicide layer, forming a second titanium nitride layer above the first titanium nitride layer after the step of performing the titanium silicide crystallization annealing, and forming a metal fill layer above the second titanium nitride layer.

[0008] According to aspects of the present disclosure, a three-dimensional memory device is provided, which includes: a semiconductor device located on a substrate; an alternating stack of insulating layers and conductive layers located above the substrate; a memory stack structure extending through the alternating stack, wherein each of the memory stack structures includes a memory film, a vertical semiconductor channel contacting an inner sidewall of the memory film, and a dielectric core contacting an inner sidewall of the vertical semiconductor channel; a dielectric material portion above the semiconductor device and including a top surface located at or above a horizontal plane including a top surface of the memory stack structure; and a contact via structure extending through the dielectric material portion and contacting the semiconductor device, and including a metal pad stack and a metal fill material portion, wherein the metal pad stack includes: a first titanium nitride layer, a titanium oxynitride layer contacting the first titanium nitride layer, and a second titanium nitride layer contacting the titanium oxynitride layer.

[0009] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. The method includes the steps of: forming a semiconductor device on a substrate; forming an alternating stack of insulating layers and spacer material layers above the substrate, wherein the spacer material layer is formed as a conductive layer or replaced by a conductive layer; forming a memory stack structure extending through the alternating stack, wherein each of the memory stack structures includes a memory film, a vertical semiconductor channel contacting an inner sidewall of the memory film, and a dielectric core contacting an inner sidewall of the vertical semiconductor channel; forming a dielectric material portion above the semiconductor device, wherein the dielectric material portion includes a top surface located at or above a horizontal plane including a top surface of the memory stack structure; forming a contact via cavity through the dielectric material portion to a top surface of the semiconductor device; and forming a contact via structure in the contact via cavity by the following steps: forming a first titanium nitride layer on a surface of the semiconductor device; annealing the first titanium nitride layer to provide gaps between grains of the first titanium nitride layer; forming a titanium oxynitride layer in the gaps of the first titanium nitride layer and on a top surface of the first titanium nitride layer; and forming a second titanium nitride layer on the titanium oxynitride layer. Description of the Drawings

[0010] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming at least one peripheral device, a semiconductor material layer, and a gate dielectric layer.

[0011] Figure 2 is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming an alternating stack of insulating layers and a sacrificial material layer.

[0012] Figure 3Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming a stepped pedestal and a retrograde stepped dielectric material portion.

[0013] Figure 4A Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming a memory opening and a support opening.

[0014] Figure 4B Is Figure 4A A top view of an exemplary structure of. The vertical plane A-A' is Figure 4A The plane of the cross-section of.

[0015] Figures 5A - 5H Is a sequential schematic vertical cross-sectional view of a memory opening within an exemplary structure of process steps according to an embodiment of the present disclosure up to the deposition of a second semiconductor channel layer.

[0016] Figure 6 Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming a memory stack structure and a support pillar structure.

[0017] Figure 7A Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming a backside trench.

[0018] Figure 7B Is Figure 7A A partial perspective top view of an exemplary structure of. The vertical plane A-A' is Figure 7A The plane of the schematic vertical cross-sectional view of.

[0019] Figure 8 Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming a backside recess.

[0020] Figures 9A - 9D Is a sequential vertical cross-sectional view of a region of an exemplary structure according to an embodiment of the present disclosure during the formation of a conductive layer.

[0021] Figure 10 Is an exemplary structure at Figure 9D The process step of.

[0022] Figure 11 Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after removing the deposited conductive material from within the backside trench.

[0023] Figure 12A Is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming an insulating spacer and a backside contact structure.

[0024] Figure 12B is Figure 12A an enlarged view of a region of an exemplary structure of

[0025] Figure 13A is a schematic vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure after forming an additional contact via structure.

[0026] Figure 13B is Figure 13A a top view of an exemplary structure of Figure 13A The vertical plane A-A’ is the plane of the schematic vertical cross-sectional view of

[0027] Figure 13C is Figure 13A and Figure 13B another schematic vertical cross-sectional view of an exemplary structure of

[0028] Figure 14A and Figure 14B illustrate two conventional process flows for forming a metal liner stack.

[0029] Figure 15 illustrates a sequence of process steps for forming a metal liner stack of the present disclosure.

[0030] Figure 16 is a schematic view of a portion of a metal liner stack according to an embodiment. DETAILED DESCRIPTION

[0031] As described above, the present disclosure relates to a three-dimensional memory device including a vertical stack of multi-level memory arrays and a method of manufacturing the same, and aspects thereof are described below. Embodiments of the present disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional monolithic memory array devices including a plurality of NAND memory strings.

[0032] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is shown, unless explicitly described or clearly indicated as having no element duplication. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be different in the description and claims of the present disclosure. Identical reference numerals refer to identical or similar elements. Unless otherwise specified, elements having the same reference numeral are assumed to have the same composition. As used herein, a first element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is “directly” located “on” a second element if there is physical contact between the surface of the first element and the surface of the second element.

[0033] As used herein, a "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a smaller extent than the underlying or overlying structure. Additionally, a layer can be a region of a homogeneous or non-homogeneous continuous structure, and the thickness of the layer is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes that are between the top and bottom surfaces of the continuous structure or at the top and bottom surfaces of the continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, above it, and / or below it.

[0034] A monolithic three-dimensional memory array is an array in which multiple memory levels are formed above a single substrate such as a semiconductor wafer without intervening substrates. The term "monolithic" means that the layers of each level in the array are directly deposited on the layers of each underlying level in the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in the U.S. Patent titled "Three-dimensional Structure Memory" with patent number 5,915,167, a non-monolithic stacked memory has been constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrates can be thinned or removed from the memory levels before bonding, but since the memory levels were initially formed on separate substrates, such a memory is not a truly monolithic three-dimensional memory array. The various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein.

[0035] Reference Figure 1 , shows an exemplary structure according to an embodiment of the present disclosure, which can be used, for example, to fabricate a device structure containing a vertical NAND memory device. The exemplary structure includes a substrate (9, 10), which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer 9 and an optional semiconductor material layer 10. The substrate semiconductor layer 9 can be a semiconductor wafer or a semiconductor material layer and can include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a main surface 7, which can be, for example, the topmost surface of the substrate semiconductor layer 9. The main surface 7 can be a semiconductor surface. In one embodiment, the main surface 7 can be a single crystal semiconductor surface, such as a single crystal semiconductor surface.

[0036] As used herein, "semiconductor material" refers to a material having from 1.0×10-6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm and once properly doped with electrical dopants can produce conductivity ranging from 1.0 S / cm to 1.0×10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, a "heavily doped semiconductor material" refers to a material doped with an electrical dopant at a sufficiently high atomic concentration to become conductive (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material containing a doped semiconductor material having a conductivity of from 1.0×10 -6 S / cm to 1.0×10 5 S / cm) in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Therefore, a semiconductor material can be semiconductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Depending on the atomic concentration of the electrical dopant therein, a doped semiconductor material can be semiconductive or conductive. As used herein, a "metallic material" refers to a conductive material containing at least one metal element therein. All measurements of conductivity are performed under standard conditions.

[0037] At least one semiconductor device 700 (not shown) for a peripheral circuit can be formed on a portion of the semiconductor material layer 9. The at least one semiconductor device can include, for example, a field effect transistor. For example, at least one shallow trench isolation structure 120 can be formed by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer 9 and can subsequently be patterned to form at least one gate structure (150, 152, 154, 158), each of which can include a gate dielectric 150, a gate electrode (152, 154), and a gate cap dielectric 158. The gate electrode (152, 154) can include a stack of a first gate electrode portion 152 and a second gate electrode portion 154. At least one gate spacer 156 can be formed around the at least one gate structure (150, 152, 154, 158) by depositing and anisotropically etching a dielectric liner. The active region 130 can be formed in an upper portion of the substrate semiconductor layer 9, for example, by introducing an electrical dopant using at least one gate structure (150, 152, 154, 158) as a mask structure. Additional masks can be employed as needed. The active region 130 can include source and drain regions of a field effect transistor. Optionally, a first dielectric liner 161 and a second dielectric liner 162 can be formed. Each of the first and second dielectric liners (161, 162) can include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide and non-stoichiometric silicon oxides, which have more or fewer than two oxygen atoms per silicon atom. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 161 can be a silicon oxide layer and the second dielectric liner 162 can be a silicon nitride layer. At least one semiconductor device of the peripheral circuit can contain a driver circuit for a memory device to be subsequently formed, and the memory device can include at least one NAND device.

[0038] A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device and can subsequently be planarized to form a planarized dielectric layer 170. In one embodiment, a planarized top surface of the planarized dielectric layer 170 can be coplanar with a top surface of the dielectric liners (161, 162). Subsequently, the planarized dielectric layer 170 and the dielectric liners (161, 162) can be removed from the region to physically expose the top surface of the substrate semiconductor layer 9. As used herein, a surface is "physically exposed" if it is in physical contact with a vacuum or a gaseous material such as air.

[0039] If an optional semiconductor material layer 10 is present, it can be formed on the top surface of the substrate semiconductor layer 9 by depositing a single-crystal semiconductor material by selective epitaxy, either before or after forming at least one semiconductor device 700. The deposited semiconductor material can be the same as or different from the semiconductor material of the substrate semiconductor layer 9. The deposited semiconductor material can be any material that can be used for the semiconductor substrate layer 9 as described above. The single-crystal semiconductor material of the semiconductor material layer 10 can be epitaxially aligned with the single-crystal structure of the substrate semiconductor layer 9. The portion of the deposited semiconductor material located above the top surface of the planarized dielectric layer 170 can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer 10 can have a top surface coplanar with the top surface of the planarized dielectric layer 170.

[0040] The region (i.e., area) of at least one semiconductor device 700 is referred to herein as the peripheral device region 200. The region where the memory array is subsequently formed is referred to herein as the memory array region 100. A contact region 300 for subsequently forming a stepped terrace for a conductive layer can be provided between the memory array region 100 and the peripheral device region 200. Optionally, a gate dielectric layer 12 can be formed over the semiconductor material layer 10 and the planarized dielectric layer 170. The gate dielectric layer 12 can be, for example, a silicon oxide layer. The thickness of the gate dielectric layer 12 can be in the range from 3 nm to 30 nm, although smaller and larger thicknesses can also be employed.

[0041] Reference Figure 2 , a stack of alternating multiple first material layers (which can be insulating layers 32) and second material layers (which can be sacrificial material layers 42) is formed on the top surface of the substrate, which can be, for example, on the top surface of the gate dielectric layer 12. As used herein, a "material layer" refers to a layer that contains a material throughout its entirety. As used herein, alternating multiple first elements and second elements refer to a structure in which instances of the first element and instances of the second element alternate. Each instance of the first element that is not an end element of the alternating multiple elements is adjacent on both sides by two instances of the second element, and each instance of the second element that is not an end element of the alternating multiple elements is adjacent at both ends by two instances of the first element. The first elements can have the same thickness among them, or can have different thicknesses. The second elements can have the same thickness among them, or can have different thicknesses. The alternating multiple first material layers and second material layers can start with an instance of the first material layer or an instance of the second material layer, and can terminate with an instance of the first material layer or an instance of the second material layer. In one embodiment, instances of the first element and instances of the second element can form units that are periodically repeated within the alternating multiple elements.

[0042] Each first material layer contains a first material, and each second material layer contains a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer. In this case, the stack may include a plurality of alternating insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of the insulating layer 32 and the sacrificial material layer 42. As used herein, a "prototype" structure or a "structure in process" refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0043] A stack of alternating multi-components is referred to herein as an alternating stack (32, 42). In one embodiment, the alternating stack (32, 42) may include an insulating layer 32 made of a first material and a sacrificial material layer 42 made of a second material different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. In this regard, each insulating layer 32 may be a layer of insulating material. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxides (including doped and undoped silicate glasses), silicon nitrides, silicon oxynitrides, organosilicate glasses (OSG), spin-on dielectric materials, dielectric metal oxides generally referred to as high dielectric constant (high-k) dielectric oxides (such as aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0044] The second material of the sacrificial material layer 42 is a sacrificial material that can be selectively removed with respect to the first material of the insulating layer 32. As used herein, if a removal process removes the first material at a rate at least twice that of the removal of the second material, the removal of the first material is "selective" with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material.

[0045] The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may subsequently be replaced with a conductive electrode, which may, for example, function as a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride or a semiconductor material containing at least one of silicon and germanium.

[0046] In one embodiment, the insulating layer 32 can comprise silicon oxide, and the sacrificial material layer can comprise a silicon nitride sacrificial material layer. The first material of the insulating layer 32 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) can be used as the precursor material for the CVD process. The second material of the sacrificial material layer 42 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0047] The sacrificial material layer 42 can be appropriately patterned such that the conductive material portion subsequently formed by replacement through the sacrificial material layer 42 can function as a conductive electrode, such as a control gate electrode of a subsequently formed monolithic three-dimensional NAND string memory device. The sacrificial material layer 42 can include portions having stripes extending substantially parallel to the main surface 7 of the substrate.

[0048] The thicknesses of the insulating layer 32 and the sacrificial material layer 42 can be in the range from 20 nm to 50 nm, although smaller or larger thicknesses can also be employed for each insulating layer 32 and for each sacrificial material layer 42. The number of repetitions of the pairs of the insulating layer 32 and the sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 can be in the range from 2 to 1024, and typically from 8 to 256, although a larger number of repetitions can also be employed. The top and bottom gate electrodes in the stack can function as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer 42.

[0049] Although embodiments using the sacrificial material layer 42 in which a spacer material layer is subsequently replaced by a conductive layer are described for this disclosure, embodiments in which the sacrificial material layer is formed as the conductive layer are explicitly covered herein. In such a case, the step of replacing the spacer material layer with a conductive layer can be omitted.

[0050] Optionally, an insulating capping layer 70 can be formed over the alternating stack (32, 42). The insulating capping layer 70 comprises a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 can comprise a dielectric material that can be used for the insulating layer 32 as described above. The insulating capping layer 70 can have a greater thickness than each of the insulating layers 32. The insulating capping layer 70 can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating capping layer 70 can be a silicon oxide layer.

[0051] Reference Figure 3, a stepped cavity can be formed within the contact region 300, which is located between the device region 100 and the peripheral region 200 of at least one semiconductor device containing peripheral circuits. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes gradually as a function of the vertical distance from the top surface of the substrate 10. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of process steps. The set of process steps can include, for example, a first type of etching process and a second type of etching process. The first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally expands the area that will be vertically etched in a subsequent first type of etching process. As used herein, a "level" of a structure comprising an alternating multi-component structure is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0052] After the stepped cavity is formed, the peripheral portion of the alternating stack (32, 42) can have a stepped surface after the stepped cavity is formed. As used herein, a "stepped surface" refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface that extends upward from a first edge of the horizontal surface and is adjacent to a second vertical surface that extends downward from a second edge of the horizontal surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0053] The stepped region is formed by patterning the alternating stack (32, 42). Each sacrificial material layer 42 within the alternating stack (32, 42) except for the topmost sacrificial material layer 42 extends laterally farther than any of the sacrificial material layers 42 above it within the alternating stack (32, 42). The stepped region includes the stepped surface of the alternating stack (32, 42), which continuously extends from the bottommost layer within the alternating stack (32, 42) to the topmost layer within the alternating stack (32, 42).

[0054] A retrograde stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed from above the top surface of the insulating capping layer 70 by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material that fills the stepped cavity constitutes the retrograde stepped dielectric material portion 65. As used herein, a "retrograde stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the top surface of the substrate on which the element is located. If silicon oxide is used for the retrograde stepped dielectric material portion 65, the silicon oxide of the retrograde stepped dielectric material portion 65 can be doped or can be undoped with dopants such as B, P, and / or F.

[0055] Optionally, a drain select level isolation structure 72 can be formed through the insulating capping layer 70 and a subset of the sacrificial material layer 42 located at the drain select level. The drain select level isolation structure 72 can be formed by forming a drain select level isolation trench and filling the drain select level isolation trench with a dielectric material such as silicon oxide. The excess portion of the dielectric material can be removed from above the top surface of the insulating capping layer 70.

[0056] Reference Figure 4A and Figure 4B , a lithographic material stack (not shown) at least including a photoresist layer can be formed over the insulating capping layer 70 and the retrograde stepped dielectric material portion 65, and can be lithographically patterned to form openings therein. The openings include a first subset of openings formed over the memory array region 100 and a second subset of openings formed over the contact region 300. The pattern in the lithographic material stack can be transferred through the insulating capping layer 70 or the retrograde stepped dielectric material portion 65 and through the alternating stack (32, 42) by at least one anisotropic etch using the patterned lithographic material stack as an etch mask. The portion of the alternating stack (32, 42) below the openings in the patterned lithographic material stack is etched to form memory openings 49 and support openings 19. As used herein, a "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, a "support opening" refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings 49 are formed through the entire insulating capping layer 70 and the alternating stack (32, 42) in the memory array region 100. The support openings 19 are formed through the retrograde stepped dielectric material portion 65 in the contact region 300 and the portion of the alternating stack (32, 42) below the stepped surface.

[0057] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemical process of the anisotropic etching process for etching through the materials of the alternating stack (32, 42) can be alternated to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etches. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical or can be tapered. The patterned photoresist material stack can be removed, for example, by ashing.

[0058] The memory opening 49 and the support opening 19 can be formed through the gate dielectric layer 12 such that the memory opening 49 and the support opening 19 extend from the top surface of the alternating stack (32, 42) to at least the horizontal plane containing the topmost surface of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, an over-etch into the semiconductor material layer 10 can be optionally performed. The over-etch can be performed before or after removing the photoresist material stack. In other words, the recessed surface of the semiconductor material layer 10 can be vertically offset from the non-recessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth can be, for example, in the range from 1 nm to 50 nm, although smaller and larger recess depths can also be employed. The over-etch is optional and can be omitted. If the over-etch is not performed, the bottom surfaces of the memory opening 49 and the support opening 19 can be coplanar with the topmost surface of the semiconductor material layer 10.

[0059] Each of the memory opening 49 and the support opening 19 can include sidewalls (or a sidewall) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 can be formed in the memory array region 100. A two-dimensional array of support openings 19 can be formed in the contact region 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute the substrate (9, 10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer 10 can be omitted, and the memory opening 49 and the support opening 19 can extend to the top surface of the substrate semiconductor layer 9.

[0060] Figures 5A - 5H A structural change in the memory opening 49 is shown, which is Figure 4A and Figure 4B one of the memory openings 49 in the exemplary structure. The same structural change occurs simultaneously in each of the other memory openings 49 and in each support opening 19.

[0061] Referring to Figure 5A it is shown Figure 4A andFigure 4B Memory opening 49 in the exemplary device structure. The memory opening 49 extends through the insulating capping layer 70, the alternating stack (32, 42), the gate dielectric layer 12, and optionally into the upper portion of the semiconductor material layer 10. In this process step, each support opening 19 can extend through the recessed stepped dielectric material portion 65, a subset of the layers in the alternating stack (32, 42), the gate dielectric layer 12, and optionally through the upper portion of the semiconductor material layer 10. The recessed depth of the bottom surface of each memory opening relative to the top surface of the semiconductor material layer 10 can be in the range from 0 nm to 30 nm, although larger recessed depths can also be employed. Optionally, the sacrificial material layer 42 can be partially laterally recessed, for example, by isotropic etching, to form a lateral recess (not shown).

[0062] Reference Figure 5B , an optional epitaxial channel portion (e.g., epitaxial pedestal) 11 can be formed, for example, by selective epitaxy at the bottom portion of each memory opening 49 and each support opening 19. Each epitaxial channel portion 11 includes single-crystalline semiconductor material that is epitaxially aligned with the single-crystalline semiconductor material of the semiconductor material layer 10. In one embodiment, the epitaxial channel portion 11 can be doped with an electrical dopant of the same conductivity type as the semiconductor material layer 10. In one embodiment, the top surface of each epitaxial channel portion 11 can be formed above the horizontal plane including the top surface of the sacrificial material layer 42. In this case, at least one source select gate electrode can be subsequently formed by replacing each sacrificial material layer 42 located below the horizontal plane including the top surface of the epitaxial channel portion 11 with a corresponding conductive material layer. The epitaxial channel portion 11 can be part of a transistor channel that extends between a source region to be subsequently formed in the substrate (9, 10) and a drain region to be subsequently formed in the upper portion of the memory opening 49. A memory cavity 49' exists in the unfilled portion of the memory opening 49 above the epitaxial channel portion 11. In one embodiment, the epitaxial channel portion 11 can include single-crystalline silicon. In one embodiment, the epitaxial channel portion 11 can have a doping of a first conductivity type that is the same as the conductivity type of the semiconductor material layer 10 in contact with the epitaxial channel portion. If the semiconductor material layer 10 does not exist, the epitaxial channel portion 11 can be directly formed on the substrate semiconductor layer 9, and the substrate semiconductor layer 9 can have a doping of a first conductivity type.

[0063] Reference Figure 5C , a stack of layers including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional first semiconductor channel layer 601 can be subsequently deposited in the memory opening 49.

[0064] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material containing at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride).

[0065] Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, their alloys, and their stacks. The dielectric metal oxide layer may be deposited by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source aerosol chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer may range from 1 nm to 20 nm, although smaller and larger thicknesses may also be employed. The dielectric metal oxide layer may then function as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include multiple dielectric metal oxide layers having different material compositions.

[0066] Alternatively or additionally, the blocking dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. In this case, the blocking dielectric layer 52 of the dielectric semiconductor compound may be formed by a conformal deposition method, such as low-pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound may range from 1 nm to 20 nm, although smaller and larger thicknesses may also be employed. Alternatively, the blocking dielectric layer 52 may be omitted, and a backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be subsequently formed.

[0067] Subsequently, a charge storage layer 54 can be formed. In one embodiment, the charge storage layer 54 can be a continuous layer or patterned discrete portions of a charge trapping material, and the charge trapping material can include a dielectric charge trapping material such as silicon nitride. Alternatively, the charge storage layer 54 can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metal material that are patterned into a plurality of electrically isolated portions (e.g., floating gates) by being formed, for example, within a lateral recess into a sacrificial material layer 42. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 can have vertically coincident sidewalls, and the charge storage layer 54 can be formed as a single continuous layer.

[0068] In another embodiment, the sacrificial material layer 42 can be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and an anisotropic etching process can be employed to form the charge storage layer 54 into a plurality of vertically spaced-apart memory material portions. Although embodiments in which the charge storage layer 54 is a single continuous layer are used to describe the present disclosure, embodiments in which the charge storage layer 54 is replaced by a plurality of vertically spaced-apart memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions) are expressly covered herein.

[0069] The charge storage layer 54 can be formed as a single charge storage layer of a homogeneous composition, or can include a stack of multiple charge storage layers. The multiple charge storage layers (if employed) can include multiple spaced-apart floating gate material layers that contain a conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and their alloys, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and / or a semiconductor material (e.g., a polycrystalline or amorphous semiconductor material that includes at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the charge storage layer 54 can include an insulating charge trapping material such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 can include conductive nanoparticles (such as metal nanoparticles), which can be, for example, ruthenium nanoparticles. The charge storage layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage layer 54 can be in the range from 2 nm to 30 nm, although smaller and larger thicknesses can also be employed.

[0070] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can occur under appropriate electrical biasing conditions. Charge tunneling can be effected by hot carrier injection or charge transfer induced by Fowler-Nordheim tunneling, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can comprise a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the tunneling dielectric layer 56 can range from 2 nm to 20 nm, although smaller and larger thicknesses can also be employed.

[0071] The optional first semiconductor channel layer 601 comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 comprises amorphous silicon or polysilicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can range from 2 nm to 10 nm, although smaller and larger thicknesses can also be employed. A memory cavity 49' is formed in the volume of the unfilled deposited material layers (52, 54, 56, 601) of each memory opening 49.

[0072] Reference Figure 5D, at least one anisotropic etching process is adopted to anisotropically etch, in sequence, an optional first semiconductor channel layer 601, a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52. The portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 that are located above the top surface of the insulating cap layer 70 can be removed through at least one anisotropic etching process. Additionally, the horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form openings in their remaining portions. Each of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can be etched through a corresponding anisotropic etching process that employs a corresponding etching chemistry, and the etching chemistry can be the same or different for various material layers.

[0073] Each remaining portion of the first semiconductor channel layer 601 can have a tubular configuration. The charge storage layer 54 can include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 can include a vertical stack of charge storage regions that store charge upon being programmed. In one embodiment, the charge storage layer 54 can be a charge storage layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0074] The surface of the epitaxial channel portion 11 (or the surface of the semiconductor material layer 10 in the case where the epitaxial channel portion 11 is not employed) can be physically exposed under the opening by passing through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the semiconductor surface physically exposed at the bottom of each memory cavity 49' can be vertically recessed such that the semiconductor surface recessed under the memory cavity 49' is vertically offset by a recess distance from the topmost surface of the epitaxial channel portion 11 (or the semiconductor substrate layer 10 in the case where the epitaxial channel portion 11 is not employed). The tunneling dielectric layer 56 is located above the charge storage layer 54. The assembly of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 in the memory opening 49 constitutes a memory film 50 that includes a plurality of charge storage regions (such as those implemented as the charge storage layer 54), and the plurality of charge storage regions are insulated from the surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can have vertically coincident sidewalls.

[0075] Reference Figure 5E, it is possible to directly deposit the second semiconductor channel layer 602 on the semiconductor surface of the epitaxial channel portion 11 (or directly on the semiconductor surface of the semiconductor substrate layer 10 if the epitaxial channel portion 11 is omitted), and directly on the first semiconductor channel layer 601. The second semiconductor channel layer 602 comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 comprises amorphous silicon or polycrystalline silicon. The second semiconductor channel layer 602 can be formed by a conformal deposition method, such as low-pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602 can be in the range from 2 nm to 10 nm, although smaller and larger thicknesses can also be employed. The second semiconductor channel layer 602 can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0076] The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. In other words, the semiconductor channel material is the collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

[0077] Reference Figure 5F , in the case where the memory cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method, such as low-pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process, such as spin coating.

[0078] Reference Figure 5G , the horizontal portion of the dielectric core layer 62L can be removed, for example, by recess etching from above the top surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62. Additionally, the horizontal portion of the second semiconductor channel layer 602 located above the top surface of the insulating cap layer 70 can be removed by a planarization process, which can employ recess etching or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 can be entirely located within the memory opening 49 or entirely located within the support opening 19.

[0079] Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent set of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 collectively constitutes a memory film 50 capable of storing charge with a macroscopic retention time. In some embodiments, at this step, the blocking dielectric layer 52 may not be present in the memory film 50 and may be subsequently formed after forming the backside recess. As used herein, macroscopic retention time refers to the retention time suitable for the operation of a memory device for a permanent memory device, such as a retention time exceeding 24 hours.

[0080] Reference Figure 5H , for example, by recess etching to a depth between the top surface and the bottom surface of the insulating cap layer 70, the top surface of each dielectric core 62 is further recessed within each memory opening. A drain region 63 can be formed by depositing a doped semiconductor material within each recessed region above the dielectric core 62. The drain region 63 can be doped with a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain region 63 can be in the range from 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 , although smaller and larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. The excess of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or recess etching, to form the drain region 63.

[0081] Each combination of the memory film 50 within the memory opening 49 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, multiple memory elements (such as a portion implemented as the charge storage layer 54), and an optional blocking dielectric layer 52. Each combination of the epitaxial channel portion 11 (if present) within the memory opening 49, the memory stack structure 55, the dielectric core 62, and the drain region 63 is referred to herein as a memory opening fill structure (11, 55, 62, 63). Each combination of the epitaxial channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure 20. Refer to Figure 6 。

[0082] Reference Figure 6 , which shows an exemplary structure after the memory opening fill structure (11, 55, 62, 63) and the support pillar structure 20 are respectively formed within the memory opening 49 and the support opening 19. In Figure 4A and Figure 4B an instance of the memory opening fill structure (11, 55, 62, 63) can be formed within each memory opening 49 of the structure. In Figure 4A and Figure 4B an instance of the support pillar structure 20 can be formed within each support opening 19 of the structure.

[0083] Each memory stack structure 55 includes a vertical semiconductor channel 60 and a memory film 50. The vertical semiconductor channel 60 may include multiple semiconductor channel layers (601, 602). The memory film 50 may include a tunneling dielectric layer 56 that laterally surrounds the vertical semiconductor channel 60, and a vertical stack of a charge storage region (such as a memory material layer 54) that laterally surrounds the tunneling dielectric layer 56 and an optional blocking dielectric layer 52. Although the present disclosure is described using the configuration shown for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures, and the alternative stack structures include different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0084] Reference Figure 7A and Figure 7B, a contact-level dielectric layer 73 may be formed over an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42, and over the memory stack structure 55 and the support pillar structure 20. The contact-level dielectric layer 73 comprises a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact-level dielectric layer 73 may comprise silicon oxide. The contact-level dielectric layer 73 may have a thickness in the range from 50 nm to 500 nm, although smaller and larger thicknesses may also be employed.

[0085] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 73 and may be lithographically patterned to form openings in the regions between clusters of the memory stack structure 55. Anisotropic etching may be employed to transfer the pattern in the photoresist layer through the contact-level dielectric layer 73, the alternating stack (32, 42), and / or the retrograde stepped dielectric material portion 65 to form a backside trench 79 that extends at least vertically from the top surface of the contact-level dielectric layer 73 to the top surface of the substrate (9, 10) and extends laterally across the memory array region 100 and the contact region 300. In one embodiment, the backside trench 79 may comprise a source contact opening in which a source contact via structure may be subsequently formed. The photoresist layer may be removed, for example, by ashing.

[0086] Reference Figure 8 and Figure 9A , an etchant that selectively etches the second material of the sacrificial material layer 42 with respect to the first material of the insulating layer 32 may be introduced into the backside trench 79, for example, by an etching process. Figure 9A shows Figure 8 a region of an exemplary structure. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 may be selective with respect to the first material of the insulating layer 32, the material of the retrograde stepped dielectric material portion 65, the semiconductor material of the semiconductor material layer 10, and the material of the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32 and the retrograde stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxides.

[0087] The etching process for selectively removing the second material from the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or it can be a gas-phase (dry) etching process, in which the etchant is introduced into the backside trench 79 in the gas phase. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching bath containing phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the retrograde stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the backside recess 43 is present in the volume previously occupied by the sacrificial material layer 42.

[0088] Each backside recess 43 can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as a front-side opening or a front-side cavity as compared to the backside recess 43. In one embodiment, the memory array region 100 includes an array of a plurality of device-level monolithic three-dimensional NAND strings disposed above a substrate (9, 10). In such a case, each backside recess 43 can define a space for receiving a corresponding word line of the array of monolithic three-dimensional NAND strings.

[0089] Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the substrate (9, 10). The backside recess 43 can be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each backside recess 43 can have a uniform height throughout.

[0090] The physical exposed surface portions of the optional epitaxial channel portions 11 and the semiconductor material layer 10 can be converted into dielectric material portions by thermally converting and / or plasma converting the semiconductor material into a dielectric material. For example, thermal conversion and / or plasma conversion can be used to convert the surface portions of each epitaxial channel portion 11 into tubular dielectric spacers 116, and to convert each physically exposed surface portion of the semiconductor material layer 10 into a flat dielectric portion 616. In one embodiment, each tubular dielectric spacer 116 can be homeomorphic to a torus topology, i.e., generally annular. As used herein, an element is homeomorphic to a torus topology if the shape of the element can be continuously stretched into the shape of a torus without breaking holes or forming new holes. The dielectric spacer 116 comprises a dielectric material, the dielectric material comprising the same semiconductor elements as the epitaxial channel portion 11, and additionally comprising at least one non-metallic element such as oxygen and / or nitrogen, such that the material of the tubular dielectric spacer 116 is a dielectric material. In one embodiment, the tubular dielectric spacer 116 can comprise a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of the epitaxial channel portion 11. Similarly, each flat dielectric portion 616 comprises a dielectric material, the dielectric material comprising the same semiconductor elements as the semiconductor material layer, and additionally comprising at least one non-metallic element such as oxygen and / or nitrogen, such that the material of the flat dielectric portion 616 is a dielectric material. In one embodiment, the flat dielectric portion 616 can comprise a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of the semiconductor material layer 10.

[0091] Reference Figure 9B , a backside blocking dielectric layer 44 can optionally be formed. The backside blocking dielectric layer 44 (if present) comprises a dielectric material that functions as a control gate dielectric for a control gate subsequently formed in the backside recess 43. The backside blocking dielectric layer 44 is optional in the case where a blocking dielectric layer 52 is present within each memory opening. The backside blocking dielectric layer 44 is present in the case where the blocking dielectric layer 52 is omitted.

[0092] The dorsal blocking dielectric layer 44 may be formed in the dorsal recess 43 and on the sidewalls of the dorsal trench 79. The dorsal blocking dielectric layer 44 may be directly formed on the horizontal surface of the insulating layer 32 within the dorsal recess 43 and on the sidewalls of the memory stack structure 55. If the dorsal blocking dielectric layer 44 is formed, it is optional to form the tubular dielectric spacer 116 and the planar dielectric portion 616 before forming the dorsal blocking dielectric layer 44. In one embodiment, the dorsal blocking dielectric layer 44 may be formed by a conformal deposition process such as atomic layer deposition (ALD). The dorsal blocking dielectric layer 44 may be substantially composed of aluminum oxide. The thickness of the dorsal blocking dielectric layer 44 may range from 1 nm to 15 nm, such as from 2 to 6 nm, although smaller and larger thicknesses may also be employed.

[0093] The dielectric material of the dorsal blocking dielectric layer 44 may be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, or a dielectric oxide of a combination of aluminum, at least one transition metal element, and / or at least one lanthanide element. Alternatively or additionally, the dorsal blocking dielectric layer 44 may include a silicon oxide layer. The dorsal blocking dielectric layer 44 may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The dorsal blocking dielectric layer 44 is formed on the sidewalls of the dorsal trench 79, the horizontal surface and sidewalls of the insulating layer 32, the portions of the sidewall surfaces of the memory stack structure 55 that are physically exposed to the dorsal recess 43, and the top surface of the planar dielectric portion 616. A dorsal cavity 79' exists within the portion of each dorsal trench 79 that is not filled with the dorsal blocking dielectric layer 44.

[0094] Reference Figure 9C , a metal barrier layer 46A may be deposited in the dorsal recess 43. The metal barrier layer 46A includes a conductive metal material that may act as a diffusion barrier layer and / or an adhesion promotion layer for the metal fill material to be subsequently deposited. The metal barrier layer 46A may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition. The thickness of the metal barrier layer 46A may range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although smaller and larger thicknesses may also be employed. In one embodiment, the metal barrier layer 46A may be substantially composed of a conductive metal nitride such as TiN.

[0095] Reference Figure 9D and Figure 10, a metal fill material is deposited in the plurality of backside recesses 43, on the sidewalls of at least one backside trench 79, and on top of the contact-level dielectric layer 73 to form a metal fill material layer 46B. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer 46B can consist essentially of at least one elemental metal. At least one elemental metal of the metal fill material layer 46B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer 46B can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 can be used to deposit the metal fill material layer 46B. In one embodiment, the metal fill material layer 46B can be a tungsten layer that contains a residual level of fluorine atoms as an impurity. The metal fill material layer 46B is spaced from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer 46A, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0096] A plurality of conductive layers 46 can be formed in the plurality of backside recesses 43, and a continuous metal material layer 46L can be formed on the sidewalls of each backside trench 79 and on top of the contact-level dielectric layer 73. Each conductive layer 46 includes a portion of the metal barrier layer 46A and a portion of the metal fill material layer 46B, and the portion of the metal barrier layer 46A and the portion of the metal fill material layer 46B are located between vertically adjacent pairs of dielectric material layers, which can be pairs of the insulating layer 32, pairs of the bottommost insulating layer and the gate dielectric layer 12, or pairs of the topmost insulating layer and the insulating cap layer 70. The continuous metal material layer 46L includes a continuous portion of the metal barrier layer 46A and a continuous portion of the metal fill material layer 46B, and the continuous portion of the metal barrier layer 46A and the continuous portion of the metal fill material layer 46B are located in the backside trench 79 or above the contact-level dielectric layer 73.

[0097] Each sacrificial material layer 42 can be replaced with a conductive layer 46. A backside cavity 79' exists in the unfilled backside blocking dielectric layer 44 of each backside trench 79 and in a portion of the continuous metal material layer 46L. The tubular dielectric spacer 116 laterally surrounds the epitaxial channel portion 11. Once the conductive layer 46 is formed, the bottommost conductive layer 46 laterally surrounds each tubular dielectric spacer 116.

[0098] Reference Figure 11, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof, etch back the deposited metal material of the continuous conductive material layer 46L from each backside trench 79 and from above the contact-level dielectric layer 73. Each remaining portion of the deposited metal material in the backside recess 43 constitutes the conductive layer 46. Each conductive layer 46 can be a conductive wire structure. Thus, the sacrificial material layer 42 can be replaced with the conductive layer 46.

[0099] Each conductive layer 46 can function as a combination of a plurality of control gate electrodes located at the same level and a word line that electrically interconnects (i.e., electrically shorts) the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are the control gate electrodes of the vertical memory device including the memory stack structure 55. In other words, each conductive layer 46 can be a word line that functions as a common control gate electrode for a plurality of vertical memory devices.

[0100] In one embodiment, the removal of the continuous conductive material layer 46L can be selective with respect to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 can be present at the bottom of each backside trench 79. The gate dielectric layer 12 can be spaced from the backside trench 79 by the horizontal portion of the backside blocking dielectric layer 44.

[0101] In another embodiment, the removal of the continuous conductive material layer 46L can be non-selective with respect to the material of the backside blocking dielectric layer 44, or the backside blocking dielectric layer 44 can be not used. In this case, depending on whether the gate dielectric layer 12 is not removed or is partially removed during the removal of the continuous conductive material layer 46L, the top surface and / or sidewall surface of the gate dielectric layer 12 can be physically exposed at the bottom of the backside trench 79. A backside cavity 79' is present within each backside trench 79.

[0102] Reference Figure 12A and Figure 12B , through a conformal deposition process, an insulating material layer can be formed in at least one backside trench 79 and above the contact-level dielectric layer 73. Exemplary conformal deposition processes include but are not limited to chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, nitrogen oxide, dielectric metal oxide, organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in the range from 1.5 nm to 60 nm, although smaller and larger thicknesses can also be used.

[0103] If a dorsal blocking dielectric layer 44 is present, the insulating material layer can be formed directly on the surface of the dorsal blocking dielectric layer 44 and directly on the sidewalls of the conductive layer 46. If the dorsal blocking dielectric layer 44 is not employed, the insulating material layer can be formed directly on the sidewalls of the insulating layer 32 and directly on the sidewalls of the conductive layer 46.

[0104] An anisotropic etch is performed to remove the horizontal portions of the insulating material layer above the contact-level dielectric layer 73 and at the bottom of each dorsal trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A dorsal cavity 79' exists within the volume surrounded by each dorsal trench 74.

[0105] The anisotropic etch process can continue with or without a change in the etch chemistry to remove the optional dorsal blocking dielectric layer 44 and portions of the planar dielectric section 616 that are below the openings through the insulating spacers 74. Openings are formed through the planar dielectric section 616 below each dorsal cavity 79' to vertically extend the dorsal cavities 79'. The top surface of the semiconductor material layer 10 can be physically exposed at the bottom of each dorsal trench 79. The remaining portion of each planar dielectric section 616 is referred to herein as a ring dielectric section 616', which can include a dielectric oxide of the semiconductor material of the semiconductor material layer 10, having a uniform thickness, and an opening therethrough.

[0106] Source regions 61 can be formed at the surface portions of the semiconductor material layer 10 below each dorsal cavity 79' by implanting an electrical dopant into the physically exposed surface portions of the semiconductor material layer 10. Each source region 61 is formed in the surface portion of the substrate (9, 10) below the respective opening through the insulating spacer 74. Due to the straggle of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during a subsequent activation annealing process, each source region 61 can have a lateral extent greater than the lateral extent of the opening through the insulating spacer 74.

[0107] The upper portion of the semiconductor material layer 10 extending between the source region 61 and the plurality of epitaxial channel portions 11 constitutes the horizontal semiconductor channels 59 of the plurality of field effect transistors. The horizontal semiconductor channels 59 are connected to the plurality of vertical semiconductor channels 60 through the respective epitaxial channel portions 11. The horizontal semiconductor channels 59 are in contact with the source region 61 and the plurality of epitaxial channel portions 11. The lowermost conductive layer 46 provided by forming the conductive layer 46 in the alternating stack (32, 46) may include the select gate electrode of the field effect transistor. Each source region 61 is formed in the upper portion of the semiconductor substrate (9, 10). The semiconductor channels (59, 11, 60) extend between the respective sets of each source region 61 and the drain region 63. The semiconductor channels (59, 11, 60) include the vertical semiconductor channels 60 of the memory stack structure 55.

[0108] The backside contact via structure 76 may be formed in each backside cavity 79'. Each contact via structure 76 may fill the respective cavity 79'. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of the backside trench 79 (i.e., the backside cavity 79'). For example, the at least one conductive material may include a conductive liner 76A and a conductive fill material portion 76B. The conductive liner 76A may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or a stack thereof. The thickness of the conductive liner 76A may range from 3 nm to 30 nm, although smaller and larger thicknesses may also be employed. The conductive fill material portion 76B may include a metal or a metal alloy. For example, the conductive fill material portion 76B may include W, Cu, Al, Co, Ru, Ni, their alloys, or a stack thereof.

[0109] The contact-level dielectric layer 73 over the alternating stack (32, 46) may be used as a stop layer to planarize the at least one conductive material. If a chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 73 may be used as the CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes the backside contact via structure 76.

[0110] The backside contact via structure 76 extends through the alternating stack (32, 46) and contacts the top surface of the source region 61. If a backside barrier dielectric layer 44 is employed, the backside contact via structure 76 may contact the sidewalls of the backside barrier dielectric layer 44.

[0111] Reference Figures 13A - 13C, can pass through the contact-level dielectric layer 73 and optionally through the retrograde stepped dielectric material portion 65 to form additional contact via structures (88, 86, 8P). For example, a drain contact via structure 88 can be formed through the contact-level dielectric layer 73 over each drain region 63. A word line contact via structure 86 can be formed on the conductive layer 46 by passing through the contact-level dielectric layer 73 and through the retrograde stepped dielectric material portion 65. A peripheral device contact via structure 84 can be formed directly on the corresponding node of the peripheral device by passing through the retrograde stepped dielectric material portion 65.

[0112] The peripheral device contact via structure 84 (and optionally, the drain contact via structure 88 and the word line contact via structure 86) can include a metal liner stack 84A and a metal fill material portion (e.g., a tungsten fill layer) 84B.

[0113] Typically, after tungsten is deposited, the TiSi x material is subjected to high-temperature annealing. This means that the TiSi x material undergoes a phase change from the monosilicide / Ti3Si5 phase to the C49 phase, or from the C49 phase to the C54 phase during high-temperature annealing. The TiSi x material can move around at the (multiple) phase change temperatures to diffuse through the grain boundaries of the overlying TiN layer and / or cause the grain boundaries of the overlying TiN layer to spread. During high-temperature annealing, silicon, fluorine, boron, phosphorus, and other elements in the silicon substrate can also diffuse through the titanium silicide layer and the titanium nitride layer into the tungsten material, thereby forming voids in the silicon substrate and degrading the electrical contact.

[0114] Figure 14A and Figure 14B shows a prior art method of a metal liner stack for forming a contact via structure. Figure 14A The first conventional process flow shown in forms a first prior art metal liner stack 84A, where a titanium silicide layer 1404 (e.g., containing the C49 phase of TiSi x or TiSi2) is formed directly on the silicon substrate 1402. A TiN layer 1406 is then deposited on the TiSi x or TiSi2 layer. A tungsten fill layer 84B can be deposited directly on the TiN layer as the metal fill material. The inventors have recognized that during high-temperature crystallization annealing, the TiSi xThe or TiSi2 material is transformed into a single C54 phase or a mixed-phase TiSi2 material containing the C49 phase and the C54 phase. Silicon and / or other atoms from the silicon surface diffuse through the grain boundaries 1410 in the TiN layer 1406 and into the tungsten fill layer 84B, thereby forming voids in the upper portion of the silicon substrate 1402 and degrading the electrical contact between the silicon substrate 1402 and the contact via structure including the TiSi2 layer 1404, the TiN layer 1406, and the tungsten fill layer 84B.

[0115] The inventors recognized that, as shown in the second conventional process flow in Figure 14B , performing a crystallization anneal before depositing the tungsten fill layer 84B did not significantly alleviate the problem because the grain boundaries 1410 between the TiN 1406 grains still spread during the crystallization anneal. Thus, during subsequent high-temperature process steps, silicon and other atoms can still diffuse out of the substrate 1402 through the spreading TiN grain boundaries 1410 into the overlying tungsten fill layer 84B.

[0116] Referring to Figure 15 , a method of forming the metal pad stack 84A of the present disclosure is shown. In this method, after the titanium silicide crystallization anneal 1404 crystallization anneal, at least one additional (e.g., second) TiN barrier layer 1516 is deposited over the overlying (e.g., first) TiN barrier layer 1406. The second TiN barrier layer 1516 has grain boundaries 1510 that are offset from the grain boundaries 1410 of the underlying first TiN barrier layer 1406 to reduce or prevent silicon or other atoms from diffusing from the underlying silicon substrate surface 1402 into the subsequently formed tungsten fill layer 84B.

[0117] As Figure 15 shown, a titanium silicide layer 1404 such as TiSi x or TiSi2 containing the C49 phase is directly formed on the silicon substrate surface 1402 (such as the doped source or drain region of a transistor in a silicon layer in or on the silicon substrate 1402). The titanium silicide layer 1404 can be formed by depositing a titanium layer in contact with the silicon surface 1402 and then performing a silicidation anneal. These steps can be performed before forming the overlying dielectric material layer or after forming the dielectric material layer and the via cavity extending through the dielectric material layer.

[0118] The first TiN layer 1406 can be formed by physical vapor deposition or chemical vapor deposition or by nitriding the deposited titanium layer during the silicidation anneal. The thickness of the first TiN layer 1406 can be in the range from 1 nm to 10 nm, such as from 2 to 3 nm, although smaller and larger thicknesses can also be employed.

[0119] Crystallization annealing is performed to convert the titanium silicide layer 1404 into a stable single C54 phase or a mixed-phase titanium silicide (TiSi2) layer 1404 that includes a mixture of C49 and C54 phases. Grain boundaries 1410 in the first TiN layer 1406 can physically spread apart to form cracks.

[0120] According to aspects of the present disclosure, after titanium silicide crystallization annealing, a second TiN layer 1516 is deposited to fill cracks at the grain boundaries 1410. By offsetting the grain boundaries 1410 from the grain boundaries in the first TiN layer 1406 and / or by filling the spreading grain boundaries 1410 in the first TiN layer 1406, the second TiN layer 1516 reduces the negative impact of the physical separation of the grain boundaries 1410 of the first TiN layer 1406 caused by crack formation during the crystallization annealing process.

[0121] In one embodiment, prior to depositing the second TiN layer 1516, the surface of the first TiN layer 1406 (the surface that includes cracks at the grain boundaries 1410) can be physically exposed to an oxygen-containing environment (such as an atmospheric environment (e.g., air at atmospheric pressure) or an oxidizing environment that includes water vapor or oxygen at a partial pressure greater than 1 Torr). The duration of exposure to the oxygen-containing environment can be temperature-dependent. Typically, a duration of exposure to ambient air at atmospheric pressure for more than 10 seconds at 20 degrees Celsius may be sufficient. A titanium oxynitride layer 1512 is formed on the surface of the first TiN layer 1406. The titanium oxynitride layer 1512 can extend vertically along the cracks of the grain structure 1410 of the first TiN layer 1406 and can fill the cracks of the first TiN layer 1406. By more effectively stopping the migration of silicon, oxygen, fluorine, boron, phosphorus, and other atoms, forming a titanium oxynitride layer 1512 between the first TiN layer 1406 and the second TiN layer 1516 can improve the diffusion barrier performance of the first and second TiN layers 1406, 1516. The thickness of the titanium oxynitride layer 1512 (as measured in the horizontal portion) can range from 0.5 nm to 6 nm, although smaller and larger thicknesses can also be employed.

[0122] According to one embodiment of the present disclosure, a titanium layer can be deposited by chemical vapor deposition to form the metal pad stack 84A of the present disclosure. The deposited titanium material can be silicided with the underlying silicon surface 1402 (e.g., source or drain region) to form the TiSi x layer 1404. A nitridation process can be performed to convert the TiSi xThe top portion of layer 1404 is converted into a first TiN layer 1406. In other words, forming the first titanium nitride layer 1406 includes: forming a titanium layer on the silicon surface, annealing the titanium layer in a nitrogen-containing environment so that the bottom portion of the titanium layer reacts with the silicon surface to form a titanium silicide layer, and nitriding the top portion of the titanium layer to form the first titanium nitride layer. A subsequent crystallization annealing (which is also referred to as TiSi x phase control annealing) can be performed to convert the formed silicide 1404 (e.g., a mixed titanium monosilicide / Ti3Si5 phase or another phase) into a C54 phase or a C49 / C54 mixed phase. After optionally forming a titanium oxynitride layer 1512, a second TiN layer 1516 can be deposited on the titanium oxynitride layer 1512 by chemical vapor deposition to a sufficient thickness to act as a diffusion barrier, and the second TiN layer 1516 can be in the range from 5 nm to 100 nm. A tungsten fill layer can be deposited on or above the second TiN layer 1516 to form a metal fill material portion 84B to complete the contact via structure 84.

[0123] According to another embodiment of the present disclosure, a metal pad stack 84A of the present disclosure can be formed by depositing titanium by chemical vapor deposition. A TiSi x layer 1404 can be formed by siliciding the titanium layer deposited on the silicon surface 1402. For example, a first TiN layer 1406 can be deposited on the TiSi x layer 1404 to a thickness in the range from 1 nm to 10 nm (such as from 2 nm to 3 nm) by chemical vapor deposition, although smaller or larger thicknesses can also be employed. A crystallization annealing (which is also referred to as TiSi x phase control annealing) can be performed to convert the formed silicide into a C54 phase or a C49 / C54 mixed phase. After optionally forming a titanium oxynitride layer 1512, a second TiN layer 1516 can be deposited on the titanium oxynitride layer 1512 by chemical vapor deposition to a sufficient barrier thickness, which can be in the range from 5 nm to 100 nm. Tungsten fill 84B can be deposited on the second TiN layer 1516 to form a metal fill material portion 84B to complete the contact via structure 84.

[0124] According to yet another embodiment of the present disclosure, the titanium layer and / or the TiN layers 1406, 1516 can be deposited by physical vapor deposition (e.g., sputtering) instead of by CVD. The thickness of the titanium layer can be in the range from 5 nm to 50 nm. Then the process continues as described above.

[0125] According to yet another embodiment of the present disclosure, the first TiN layer 1406 can be replaced by a multi-layer stack 1602, such as Figure 16The TiN / Ti / TiN stack shown therein. In other words, the third TiN layer 1620 is formed on the titanium silicide layer 1404, the Ti layer 1618 is formed on the third TiN layer 1620, and then the first TiN layer 1406 is formed on the Ti layer 1618. After depositing the multi-layer stack, crystallization annealing is performed, and then titanium oxynitride 1512 is optionally formed by oxidizing the top of the first TiN layer 1406 in the stack 1602, and then the second TiN layer 1506 is deposited after the crystallization annealing.

[0126] Exemplary structures can include three-dimensional memory devices. In one embodiment, the three-dimensional memory device includes a vertical NAND memory device. The conductive layer 46 can include or can be electrically connected to corresponding word lines of a monolithic three-dimensional NAND memory device. The substrate (9, 10) can include a silicon substrate. The vertical NAND memory device can include an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell (such as a portion at the level of the conductive layer 46 implemented as a charge storage layer 54) in a first device level of the array of monolithic three-dimensional NAND strings can be located above another memory cell (such as another portion at the level of another conductive layer 46 implemented as a charge storage layer 54) in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit, and the integrated circuit includes a driver circuit of a memory device located on the silicon substrate. The conductive layer 46 can include a plurality of control gate electrodes having a bar shape extending substantially parallel to the top surface of the substrate (9, 10) (e.g., between pairs of backside trenches 79). The plurality of control gate electrodes at least includes a first control gate electrode located in the first device level and a second control gate electrode located in the second device level. The array of monolithic three-dimensional NAND strings can include: a plurality of semiconductor channels (59, 11, 60), wherein at least one end portion 60 of each of the plurality of semiconductor channels (59, 11, 60) extends substantially perpendicular to the top surface of the substrate (9, 10); and a plurality of charge storage elements (such as implemented as charge trapping material portions). Each charge storage element can be located adjacent to a corresponding one of the plurality of semiconductor channels (59, 11, 60).

[0127] Although a multi-layer barrier containing at least two TiN layers 1406, 1516 and an optional titanium oxynitride layer 1512 is described as being formed in a three-dimensional memory device, the barrier can be formed in any suitable device, such as in any transistor (e.g., as part of a source or drain electrode of a transistor) located in any memory or logic device. The metal fill layer can include a tungsten source or drain electrode of a transistor located above the multi-layer barrier.

[0128] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Various modifications may be made to the disclosed embodiments by those of ordinary skill in the art, and such modifications are intended to be within the scope of the present disclosure. Where embodiments employing a specific structure and / or configuration are shown in the present disclosure, it should be understood that the present disclosure may be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A semiconductor device, comprising: A silicon surface; A titanium silicide layer contacting the silicon surface; A first titanium nitride layer located above the titanium silicide layer; A titanium oxynitride layer contacting the first titanium nitride layer; A second titanium nitride layer contacting the titanium oxynitride layer; And A metal fill layer located above the second titanium nitride layer.

2. The device according to claim 1, wherein the semiconductor device comprises a transistor, the silicon surface comprises a source region or a drain region of the transistor, and the metal fill layer comprises a tungsten source electrode or a drain electrode.

3. A three-dimensional memory device, comprising: The semiconductor device according to claim 1, the semiconductor device being located on a substrate; An alternating stack of an insulating layer and a conductive layer, the alternating stack being located above the substrate; A memory stack structure extending through the alternating stack, wherein each of the memory stack structures comprises a memory film, a vertical semiconductor channel contacting an inner sidewall of the memory film, and a dielectric core contacting an inner sidewall of the vertical semiconductor channel; A dielectric material portion above the semiconductor device and having a top surface located at a horizontal plane including a top surface of the memory stack structure or above a horizontal plane including the top surface of the memory stack structure; And A contact via structure extending through the dielectric material portion and contacting the semiconductor device, and comprising a metal pad stack and the metal fill layer, the metal pad stack comprising the first titanium nitride layer, the titanium oxynitride layer, and the second titanium nitride layer.

4. The device according to claim 1, further comprising a titanium layer and a third titanium nitride layer located between the titanium silicide layer and the titanium oxynitride layer, wherein the titanium layer is located between the first titanium nitride layer and the third titanium nitride layer.

5. The device according to claim 1, wherein the titanium oxynitride layer is located in a crack in a grain boundary of the first titanium nitride layer.

6. The device according to claim 1, wherein a thickness of the first titanium nitride layer is 1 to 10 nm.

7. The device according to claim 6, wherein the thickness of the first titanium nitride layer is 2 to 3 nm, and the thickness of the second titanium nitride layer is 5 to 100 nm.

8. The device according to claim 1, wherein the titanium silicide layer comprises a C54-phase titanium silicide layer.

9. The device according to claim 1, wherein the titanium silicide layer comprises a mixed C54-phase and C49-phase titanium silicide layer.

10. A method of manufacturing a semiconductor device, comprising: Forming a titanium silicide layer contacting a silicon surface; Forming a first titanium nitride layer above the titanium silicide layer; Performing titanium silicide crystallization annealing to crystallize the titanium silicide layer; After the step of performing titanium silicide crystallization annealing, forming a second titanium nitride layer above the first titanium nitride layer; And Forming a metal fill layer above the second titanium nitride layer.

11. The method according to claim 10, wherein the semiconductor device includes a transistor, the silicon surface includes a source region or a drain region of the transistor, and the metal fill layer includes a tungsten source electrode or a drain electrode.

12. The method according to claim 10, further comprising forming a titanium oxynitride layer contacting the first titanium nitride layer after the step of performing the titanium silicide crystallization annealing.

13. The method according to claim 12, wherein the step of forming the second titanium nitride layer includes forming the second titanium nitride layer directly on the titanium oxynitride layer.

14. The method according to claim 13, wherein: Performing the crystallization annealing causes the grain boundaries of the first titanium nitride layer to spread to form cracks; and Forming the titanium oxynitride layer includes oxidizing the top surface of the first titanium nitride layer and the cracks in the grain boundaries in the first titanium nitride layer.

15. The method according to claim 10, further comprising: Forming a semiconductor device on the silicon surface of the substrate; Forming an alternating stack of an insulating layer and a spacer material layer on the substrate, wherein the spacer material layer is formed as a conductive layer or replaced by a conductive layer; Forming a memory stack structure that extends through the alternating stack, wherein each of the memory stack structures includes a memory film, a vertical semiconductor channel in contact with the inner sidewalls of the memory film, and a dielectric core in contact with the inner sidewalls of the vertical semiconductor channel; Forming a dielectric material portion on the semiconductor device, wherein the dielectric material portion includes a top surface at or above a horizontal plane including the top surface of the memory stack structure; And Forming a contact via cavity through the dielectric material portion to the top surface of the semiconductor device.

16. The method according to claim 15, wherein the first titanium nitride layer, the second titanium nitride layer, and the metal fill layer are formed in the contact via cavity to form a contact via structure.

17. The method according to claim 10, wherein forming the first titanium nitride layer includes depositing the first titanium nitride layer on the titanium silicide layer.

18. The method according to claim 10, wherein forming the first titanium nitride layer includes forming a titanium layer on the silicon surface, annealing the titanium layer in an environment containing nitrogen to react the bottom portion of the titanium layer with the silicon surface to form the titanium silicide layer and nitride the top portion of the titanium layer to form the first titanium nitride layer.

19. The method according to claim 10, wherein forming the second titanium nitride layer fills the gaps between the grains of the first titanium nitride layer formed during the titanium silicide crystallization annealing.

20. The method according to claim 10, further comprising forming a third titanium nitride layer and a titanium layer on the titanium silicide layer before forming the first titanium nitride layer, wherein the titanium layer is located between the first titanium nitride layer and the third titanium nitride layer.

Images