Semiconductor devices and power equipment

Abstract

The semiconductor device and power equipment disclosed herein include a driving circuit having an N-type field-effect transistor and a P-type field-effect transistor. The N-type field-effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer on its carbon side, a first gate located on the first 3C-SiC layer away from the 4H-SiC substrate, and first and second electrodes. The P-type field-effect transistor includes a 4H-SiC substrate, a second 3C-SiC layer on its silicon side, a second gate located on the second 3C-SiC layer away from the 4H-SiC substrate, and third and fourth electrodes. Interconnect pillars penetrate the 4H-SiC substrate and are insulated from the first and second 3C-SiC layers and the 4H-SiC substrate. The interconnect pillars include a first, second, and third interconnect pillar. The first interconnect pillar connects to the first and second gates, the second interconnect pillar connects to the first and third electrodes, and the third interconnect pillar connects the fourth electrode to one end of a constant voltage source. The other end of the constant voltage source and the second electrode are grounded.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and power equipment. Background Technology

[0002] Power devices require driving circuits (also known as driving buffers) to drive them. Related technologies integrate the driving circuits on one side of the substrate, resulting in dense layout of the driving circuits and greater process difficulty. Summary of the Invention

[0003] This disclosure provides a semiconductor device and power equipment to solve the technical problems of dense layout and difficult manufacturing process of drive circuits.

[0004] The semiconductor devices and power equipment provided in this disclosure are specifically designed as follows:

[0005] On one hand, embodiments of this disclosure provide a semiconductor device, including:

[0006] A driving circuit includes N-type field-effect transistors and P-type field-effect transistors spaced apart. The N-type field-effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer located on the carbon side of the 4H-SiC substrate, and a first gate, a first electrode, and a second electrode located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The P-type field-effect transistor includes the 4H-SiC substrate, a second 3C-SiC layer located on the silicon side of the 4H-SiC substrate, and a second gate, a third electrode, and a fourth electrode located on the side of the second 3C-SiC layer away from the 4H-SiC substrate.

[0007] An interconnect pillar penetrates the 4H-SiC substrate. The interconnect pillar is insulated from the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer. The interconnect pillar includes a first interconnect pillar, a second interconnect pillar, and a third interconnect pillar. The first interconnect pillar connects the first gate and the second gate. The second interconnect pillar connects the first electrode and the third electrode. The third interconnect pillar connects the fourth electrode to one end of a constant voltage source. The other end of the constant voltage source and the second electrode are both grounded.

[0008] In some embodiments, the semiconductor device provided in this disclosure further includes a first isolation structure and a second isolation structure;

[0009] The first 3C-SiC layer is also located in the region where the P-type field-effect transistor is located, and the first isolation structure penetrates the first 3C-SiC layer in the region where the P-type field-effect transistor is located and extends into the 4H-SiC substrate;

[0010] The second 3C-SiC layer is also located in the region where the N-type field-effect transistor is located. The second isolation structure penetrates the second 3C-SiC layer in the region where the N-type field-effect transistor is located and extends into the 4H-SiC substrate.

[0011] In some embodiments, in the semiconductor device provided in the present disclosure, the first isolation structure is a groove structure or a P-type doped structure, and the second isolation structure is a groove structure or an N-type doped structure.

[0012] In some embodiments, in the semiconductor device provided in the present disclosure, the interconnect pillar specifically penetrates the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer.

[0013] In some embodiments, the semiconductor device provided in the present disclosure further includes: a seed layer, a barrier layer, and a dielectric layer penetrating the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer, wherein the seed layer is in contact with the interconnect pillar, the dielectric layer is in contact with the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer, and the barrier layer is located between the seed layer and the dielectric layer.

[0014] In some embodiments, in the semiconductor device provided in the present disclosure, one of the first electrode and the second electrode is the source and the other is the drain, and one of the third electrode and the fourth electrode is the source and the other is the drain.

[0015] In some embodiments, in the semiconductor device provided in the present disclosure, the thickness of the first 3C-SiC layer and the second 3C-SiC layer is 25nm~30nm.

[0016] In some embodiments, in the semiconductor device provided in the present disclosure, the driving circuit includes a first-stage driving circuit, which includes the N-type field-effect transistor and the P-type field-effect transistor, wherein the first gate is a pulse gate signal input terminal and the first electrode is a driving signal output terminal.

[0017] In some embodiments, in the semiconductor device provided in the present disclosure, the driving circuit includes a first-stage driving circuit and a second-stage driving circuit, wherein the first-stage driving circuit and the second-stage driving circuit respectively include the N-type field-effect transistor and the P-type field-effect transistor;

[0018] The first gate of the first-stage driving circuit is a pulse gate signal input terminal, the first gate of the second-stage driving circuit is electrically connected to the first electrode of the first-stage driving circuit, and the first electrode of the second-stage driving circuit is a driving signal output terminal.

[0019] In some embodiments, the semiconductor device provided in this disclosure further includes a power device spaced apart from the driving circuit. The power device includes the 4H-SiC substrate, the first 3C-SiC layer, the second 3C-SiC layer, and a gate, a source, and a drain located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The gate of the power device is electrically connected to the driving signal output terminal, the source of the power device is grounded, and the drain of the power device is electrically connected to the load.

[0020] In some embodiments, the semiconductor device provided in the present disclosure further includes a third isolation structure located between the region where the power device is located and the region where the driving circuit is located. The third isolation structure penetrates the first 3C-SiC layer and extends into the 4H-SiC substrate.

[0021] In some embodiments, in the semiconductor device provided in the present disclosure, the third isolation structure is a groove structure or a P-type doped structure.

[0022] On the other hand, embodiments of this disclosure provide a power device including the semiconductor device described above.

[0023] The beneficial effects of this disclosure are as follows:

[0024] The semiconductor device and power device provided in this disclosure include: a driving circuit, which includes N-type field-effect transistors and P-type field-effect transistors spaced apart. The N-type field-effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer located on the carbon side of the 4H-SiC substrate, and a first gate, a first electrode, and a second electrode located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The P-type field-effect transistor includes a 4H-SiC substrate and a second 3C-SiC layer located on the silicon side of the 4H-SiC substrate. The second 3C-SiC layer includes a second gate, a third electrode, and a fourth electrode located on the side of the second 3C-SiC layer away from the 4H-SiC substrate; interconnect pillars penetrating the 4H-SiC substrate, insulated from the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer; the interconnect pillars include a first interconnect pillar, a second interconnect pillar, and a third interconnect pillar; the first interconnect pillar connects the first gate and the second gate; the second interconnect pillar connects the first electrode and the third electrode; the third interconnect pillar connects the fourth electrode to one end of a constant voltage source; the other end of the constant voltage source and the second electrode are both grounded. This disclosure distributes the components of the driving circuit on both sides of the 4H-SiC substrate and utilizes interconnect pillars to achieve electrical connection between the components on both sides, simplifying the single-sided layout of the 4H-SiC substrate and reducing the process difficulty. Attached Figure Description

[0025] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0026] Figure 2 This is another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0027] Figure 3 A SPICE current simulation diagram including a single-stage drive circuit is provided for embodiments of this disclosure;

[0028] Figure 4 for Figure 3 The curves showing the change of the square wave voltage pulse signal input to the V2 signal generator and the output voltage waveform of the drive circuit over time;

[0029] Figure 5 for Figure 3 A schematic diagram of a dual-pulse test simulation;

[0030] Figure 6 for Figure 3 Turn-off curves of power devices in the medium at times t ~ 40 μs;

[0031] Figure 7 A SPICE current simulation diagram including a two-stage drive circuit is provided for embodiments of this disclosure;

[0032] Figure 8 for Figure 7 A schematic diagram of a dual-pulse test simulation;

[0033] Figure 9 for Figure 7 Turn-off curves of power devices in the medium at times t ~ 40 μs;

[0034] Figure 10 for Figure 2 The diagram shows a structural schematic of a semiconductor device during its fabrication process.

[0035] Figure 11 for Figure 2 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0036] Figure 12 for Figure 2 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the embodiments described in this disclosure should not be construed as limited to the specific shape of the region shown in this disclosure, but rather include shape deviations caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0038] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0039] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0040] Figure 1 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure is given. For example... Figure 1 As shown, the semiconductor device provided in this embodiment may include:

[0041] The driving circuit DB includes N-type field-effect transistors (NFETs) and P-type field-effect transistors (PFETs) spaced apart. The NFETs include a 4H-SiC substrate 101 and a carbon surface located on the 4H-SiC substrate 101. The first 3C-SiC layer 102 on the side where the silicon surface (0001) of the 4H-SiC substrate 101 is located, and the first gate G1, the first electrode S1 and the second electrode D1 on the side of the first 3C-SiC layer 102 away from the 4H-SiC substrate 101, due to the spontaneous polarization of the 4H-SiC substrate 101, can induce a two-dimensional electron gas (2DEG) at the interface between the first 3C-SiC layer 102 and the 4H-SiC substrate 101; the P-type field-effect transistor PFET includes a 4H-SiC substrate 101, a second 3C-SiC layer 103 on the side where the silicon surface (0001) of the 4H-SiC substrate 101 is located, and the second gate G2, the third electrode S2 and the fourth electrode D2 on the side of the second 3C-SiC layer 103 away from the 4H-SiC substrate 101, due to the spontaneous polarization of the 4H-SiC substrate 101, can induce a two-dimensional hole gas (2DHG) at the interface between the second 3C-SiC layer 103 and the 4H-SiC substrate 101.

[0042] In some embodiments, the first 3C-SiC layer 102 may be lightly doped with N-type (doping concentration <10). 15 cm -3 The second 3C-SiC layer 103 can be a lightly doped p-type layer (doping concentration <10). 15 cm -3The first 3C-SiC layer 102 and the second 3C-SiC layer 103 can both have a thickness of 25nm~30nm, such as 26nm, 27nm, 28nm, 29nm, etc., to facilitate gate control. One of the first electrode S1 and the second electrode D1 is the source and the other is the drain, and one of the third electrode S2 and the fourth electrode D2 is the source and the other is the drain; for example, the first electrode S1 is the source, the second electrode D1 is the drain, the third electrode S2 is the source, and the fourth electrode D2 is the drain; or, the first electrode S1 is the source, the second electrode D1 is the drain, the third electrode S2 is the drain, and the fourth electrode D2 is the source; or, the first electrode S1 is the drain, the second electrode D1 is the source, the third electrode S2 is the source, and the fourth electrode D2 is the drain; or, the first electrode S1 is the drain, the second electrode D1 is the source, the third electrode S2 is the drain, and the fourth electrode D2 is the source.

[0043] Interconnect post 104 penetrates through 4H-SiC substrate 101. Interconnect post 104 is insulated from the first 3C-SiC layer 102, the 4H-SiC substrate 101 and the second 3C-SiC layer 103. Interconnect post 104 includes a first interconnect post 1041, a second interconnect post 1042 and a third interconnect post 1043. The first interconnect post 1041 connects the first gate G1 and the second gate G2. The second interconnect post 1042 connects the first electrode S1 and the third electrode S2. The third interconnect post 1043 connects the fourth electrode D2 and one end of the constant voltage source V1. The other end of the constant voltage source V1 and the second electrode D1 are both grounded.

[0044] As can be seen from the above, this disclosure places the N-type field-effect transistor (NFET) and the P-type field-effect transistor (PFET) of the driving circuit DB on the carbon surface and silicon surface of the 4H-SiC substrate 101 respectively, and uses the interconnect pillars 104 to realize the electrical connection between the NFET and the PFET. This simplifies the single-sided layout of the 4H-SiC substrate 101 and reduces the process difficulty.

[0045] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1As shown, the first 3C-SiC layer 102 can be located in both the region where the N-type field-effect transistor (FET) is located and the region where the P-type field-effect transistor (PFET) is located. Similarly, the second 3C-SiC layer 103 can be located in both the region where the N-type FET is located and the region where the PFET is located. This allows the first 3C-SiC layer 102 and the second 3C-SiC layer 103 to be fabricated using epitaxial technology, eliminating the need to remove the first 3C-SiC layer 102 in the region where the PFET is located and the second 3C-SiC layer 103 in the region where the N-type FET is located through etching. This simplifies the fabrication process of the first 3C-SiC layer 102 and the second 3C-SiC layer 103. In this case, a first isolation structure 105 and a second isolation structure 106 can be provided. The first isolation structure 105 penetrates the first 3C-SiC layer 102 in the region where the P-type field-effect transistor (PFET) is located and extends into the 4H-SiC substrate 101, thereby cutting off the two-dimensional electron gas (2DEG) interconnection between the region where the P-type field-effect transistor (PFET) is located and the region where the N-type field-effect transistor (NFET) is located. The second isolation structure 106 penetrates the second 3C-SiC layer 103 in the region where the N-type field-effect transistor (NFET) is located and extends into the 4H-SiC substrate 101, thereby cutting off the two-dimensional hole gas (2DHG) interconnection between the region where the P-type field-effect transistor (PFET) is located and the region where the N-type field-effect transistor (NFET) is located, ensuring that the P-type field-effect transistor (PFET) and the N-type field-effect transistor (NFET) do not interfere with each other.

[0046] In some embodiments, in the semiconductor device provided in this disclosure, the first isolation structure 105 and the second isolation structure 106 can be fabricated by ion implantation or etching processes. Specifically, P-type dopant atoms can be implanted to form the first isolation structure 105, and N-type dopant atoms can be implanted to form the second isolation structure 106. In other words, the first isolation structure 105 is a P-type doped structure, and the second isolation structure 106 is an N-type doped structure. When the first isolation structure 105 and the second isolation structure 106 are fabricated using an etching process, both the first isolation structure 105 and the second isolation structure 106 are groove structures.

[0047] In some embodiments, when the first 3C-SiC layer 102 and the second 3C-SiC layer 103 are fabricated using an epitaxial process in the semiconductor device provided in this disclosure, the first 3C-SiC layer 102 and the second 3C-SiC layer 103 will exist in the region where the interconnect pillar 104 is located, such as... Figure 1 As shown, in order to effectively conduct the P-type field-effect transistor (PFET) and the N-type field-effect transistor (NFET), the interconnect pillar 104 needs to penetrate the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103.

[0048] In some embodiments, the semiconductor device provided in this disclosure may further include a seed layer, a barrier layer, and a dielectric layer penetrating the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103. The seed layer is in contact with the interconnect pillar 104, the dielectric layer is in contact with the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103, and the barrier layer is located between the seed layer and the dielectric layer. The dielectric layer provides insulation between the interconnect pillar 104 and the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103. The barrier layer prevents the metal from the seed layer from diffusing into the first 3C-SiC layer 102, the 4H-SiC substrate 101, and the second 3C-SiC layer 103. The seed layer may be copper. The seed layer acts as a conductor during the electroplating filling process of the interconnect pillar 104 and also provides a crystal nucleus (e.g., a copper nucleus) to achieve more uniform crystallization.

[0049] In some embodiments, Figure 2 A schematic diagram of yet another structure of the semiconductor device provided in this disclosure is shown. For example... Figure 2 As shown, the semiconductor device disclosed herein may further include a power device PD disposed at a distance from the driving circuit DB. The power device PD includes a 4H-SiC substrate 101, a first 3C-SiC layer 102, a second 3C-SiC layer 103, and a gate G3, a source S3, and a drain D3 located on the side of the first 3C-SiC layer 102 away from the 4H-SiC substrate 101. The gate G3 of the power device PD is electrically connected to the driving signal output terminal (e.g., the first electrode S1 of an N-type field-effect transistor NFET). The source S3 of the power device PD may be grounded, and the drain D3 of the power device PD may be connected to a load (e.g., a load). Figure 3 The L1 inductor shown is electrically connected.

[0050] In new energy vehicle main drive modules, the drive circuit DB and power device PD are spatially separated. A long connecting line is required to electrically connect them, resulting in a large parasitic inductance in the gate-source loop formed by the DB and PD. This high parasitic inductance can cause significant gate drive oscillations. This disclosure monolithically integrates the drive circuit DB and power device PD, effectively reducing the parasitic inductance of the gate-source loop and improving drive performance.

[0051] In some embodiments, in the semiconductor device provided in this disclosure, the first 3C-SiC layer 102 and the second 3C-SiC layer 103 can be fabricated using an epitaxial process to isolate the two-dimensional electron gas (2DEG) interconnect between the region where the power device PD is located and the region where the driving circuit DB is located, such as... Figure 2 As shown, the semiconductor device of this disclosure may further include a third isolation structure 107 located between the region where the power device PD is located and the region where the driving circuit DB is located. The third isolation structure 107 penetrates the first 3C-SiC layer 102 and extends into the 4H-SiC substrate 101. The third isolation structure 107 may be a groove structure prepared by an etching process, or a P-type doped structure formed by implanting P-type doped atoms by an ion implantation process.

[0052] In some embodiments, Figure 3 A SPICE current simulation diagram of the single-stage drive circuit provided in the embodiments of this disclosure is shown, as follows: Figure 3 As shown, the driving circuit DB of this disclosure includes a first-stage driving circuit DB1, which includes an N-type field-effect transistor (NFET) and a P-type field-effect transistor (PFET). The first gate of the NFET is a pulse gate signal input terminal electrically connected to the V2 signal generator, and the first electrode of the NFET is a driving signal output terminal electrically connected to the gate G3 of the power device PD.

[0053] It should be noted that, in order to facilitate verification of the driving performance of the driving circuit DB of this disclosure, the P-type field-effect transistor PFET, N-type field-effect transistor NFET and power device PD of this disclosure are... Figure 3 Commercial pipes can be used as alternatives in both cases. Figure 3 The system contains one P-type field-effect transistor (PFET) and 50 N-type field-effect transistors (NFETs) connected in parallel to match the rated currents of the PFETs and NFETs. The PFET is model 2N5018 with a rated current of 30mA and a threshold voltage of +4.15V, while the NFET is model 2N4119A with a rated current of 600μA and a threshold voltage of -4.5V. Figure 3 The circuit on the right is a typical dual-pulse test circuit. The power device PD is a silicon carbide power JFET device (normally open type, threshold voltage of -10V) from UnitedSiC, and the upper transistor U is a silicon carbide diode device from UnitedSiC.

[0054] Figure 4The time-voltage curve with the triangle symbol represents the change of the square wave voltage pulse signal input to the V2 signal generator over time, while the time-voltage curve with the square symbol represents the change of the gate voltage of the power device PD after the square wave voltage pulse signal passes through the first-stage drive circuit DB1 over time. It can be seen that in this disclosure, the gate voltage input to the power device PD through the first-stage drive circuit DB1 remains in phase with the square wave voltage pulse signal.

[0055] Figure 5 for Figure 3 The test results of the dual-pulse test circuit on the right side are shown. The time-voltage curve with square symbols represents the change in the gate voltage of the power device PD as a function of time, where the square wave voltage pulse signal input from the V2 signal generator is passed through the first-stage drive circuit DB1. The time-current curve with dots represents the change in the current of inductor L1 in the dual-pulse test circuit as a function of time. It can be seen that when the gate voltage is approximately 0V, the power device PD is turned on, and the current I of inductor L1 increases, indicating a charging state. When the gate voltage is approximately -20V, the power device PD is turned off, and inductor L1 freewheels through the upper transistor U, at which point the internal current of inductor L1 remains approximately constant.

[0056] Figure 6 This is the turn-off curve of the power device PD at approximately 40 μs. The time-voltage curve with triangles represents the change of the gate voltage of the power device PD over time, and the time-current curve with squares represents the change of the gate current of the power device PD over time. At approximately 40 μs, the gate voltage of the power device PD drops from -0.63V to approximately -12.3V, entering the Miller plateau, and the gate current of the power device PD is approximately -613mA. Afterward, the gate voltage of the power device PD reaches -19.3V, and the power device PD is completely turned off. The maximum peak value of the gate current of the power device PD is approximately -664mA, after which it decreases to the Miller plateau, and the gate current is approximately -613mA. The duration of the gate current pulse is 0.3 μs.

[0057] In some embodiments, Figure 7 A SPICE current simulation diagram of the two-stage drive circuit provided in the embodiments of this disclosure is shown, as follows: Figure 7As shown, the driving circuit DB may include a first-stage driving circuit DB1 and a second-stage driving circuit DB2. The first-stage driving circuit DB1 and the second-stage driving circuit DB2 respectively include an N-type field-effect transistor (NFET) and a P-type field-effect transistor (PFET). Specifically, the first gate of the NFET in the first-stage driving circuit DB1 is the pulse gate signal input terminal electrically connected to the V2 signal generator. The first gate of the NFET in the second-stage driving circuit DB2 is electrically connected to the first electrode of the NFET in the first-stage driving circuit DB1. The first electrode of the NFET in the second-stage driving circuit DB2 is the driving signal output terminal electrically connected to the gate G3 of the power device PD.

[0058] It should be noted that, in order to facilitate verification of the driving performance of the driving circuit DB of this disclosure, the P-type field-effect transistor PFET, N-type field-effect transistor NFET and power device PD of this disclosure are... Figure 7 Commercial pipes can be used as alternatives in both cases. Figure 7 The first-stage driver circuit DB1 consists of one P-type field-effect transistor (PFET) and 50 N-type field-effect transistors (NFETs) connected in parallel. The second-stage driver circuit DB2 consists of three P-type PFETs connected in parallel and 150 NFETs connected in parallel, the purpose of which is to match the rated current of the PFETs and NFETs. The PFET is model 2N5018, rated current 30mA, threshold voltage +4.15V, and the NFET is model 2N4119A, rated current 600μA, threshold voltage -4.5V. The rated current of the first-stage driver circuit DB1 is 30mA, and the rated current of the second-stage driver circuit DB2 is 90mA.

[0059] By adjusting the number of parallel connections in the second-stage drive circuit DB2, such as... Figure 7 As shown, by adding parallel devices to a quantity three times greater, the switching time of the power device PD can be adjusted to increase by approximately three times (this can only be achieved using a two-stage drive circuit). Figure 7 The triple switching time effect in the illustrated embodiment is achieved by simply increasing the number of parallel connections in the first-stage drive circuit DB1 without changing the magnitude and duration of the gate drive pulse for the power device PD. Since the gate drive charge is constant, the embodiment using a two-stage drive circuit can reduce the drive current of the power device PD to approximately one-third of that in the single-stage drive circuit embodiment, thereby reducing the peak value of the switching current at the PD's gate. The design using a two-stage drive circuit allows for active modulation of the PD's peak gate current, protecting the PD's gate.

[0060] Figure 8 for Figure 7 The illustrated embodiment is a schematic diagram of a dual-pulse test simulation. The time-current curve with a triangle symbol represents the change of current in inductor L1 over time; the time-voltage curve with a square symbol represents the change of gate voltage of power device PD over time; and the time-current curve with a dot symbol represents the change of gate current of power device PD over time.

[0061] Figure 9 This is the turn-off curve of the power device PD at approximately 40 μs. The time-voltage curve with triangles represents the change of the gate voltage of the power device PD over time, and the time-current curve with squares represents the change of the gate current of the power device PD over time. At approximately 40 μs, the gate voltage of the power device PD drops from -1.26V to approximately -9.7V, entering the Miller plateau, and the gate current of the power device PD is -87mA. Afterwards, the gate voltage of the power device PD reaches -18.6V, and the power device PD is completely turned off. The maximum peak value of the gate current of the power device PD is approximately -143mA, after which it decreases to the Miller plateau, and the gate current is approximately -87mA. The duration of the gate drive current pulse is 1.14 μs.

[0062] Verification was performed using SPICE simulation. Figure 7 In the driving circuit DB of the illustrated embodiment, the source and drain of one P-type field-effect transistor (PFET) in the first-stage driving circuit DB1 are swapped, and / or the source and drain of 50 N-type field-effect transistors (NFETs) in the first-stage driving circuit DB1 are swapped; the source and drain of three P-type field-effect transistors (PFETs) in the second-stage driving circuit DB2 are swapped, and / or the source and drain of 150 N-type field-effect transistors (NFETs) in the second-stage driving circuit DB2 are swapped, to achieve the same function.

[0063] In some embodiments, this disclosure also addresses Figure 2 The fabrication process of the semiconductor device shown is explained in detail below:

[0064] Step 1: Epitaxially grow a first 3C-SiC layer 102 and a second 3C-SiC layer 103 with target thicknesses of 25nm~30nm on the carbon and silicon surfaces of a 4H-SiC substrate 101, respectively. Specifically, a lightly doped n-type layer (doping concentration <10) is epitaxially grown on the carbon surface of the 4H-SiC substrate 101. 15 cm -3 Or intrinsic 3C-SiC, epitaxially p-type lightly doped (doping concentration <10) on the silicon surface of a 4H-SiC substrate 101. 15 cm -3Or intrinsic 3C-SiC. A spontaneously polarized induced two-dimensional electron gas (2DEG) is formed at the interface between the first 3C-SiC layer 102 and the 4H-SiC substrate 101, and a spontaneously polarized induced two-dimensional hole gas (2DHG) is formed at the interface between the second 3C-SiC layer 103 and the 4H-SiC substrate 101, such as... Figure 10 As shown.

[0065] Step 2: Fabricate through-silicon vias (TSVs) in designated areas of the epitaxial wafer, such as... Figure 11 As shown. For example, by dry etching, the bias power is 1kW, the ICP power is 4kW, the flow rate of etching gases such as SF6 / O2 / Ar is 6sccm / 6sccm / 8sccm, the reaction chamber pressure is 15mTorr, and the ambient temperature is 20℃.

[0066] Step 3: Deposit a dielectric layer to isolate the filler metal of the interconnect pillar 104 from the 4H-SiC substrate 101, the first 3C-SiC layer 102, and the second 3C-SiC layer 103. The dielectric layer material on the inner wall of the via TSV can include silicon oxide, silicon nitride, and polymers, and the deposition process can be PECVD, SACVD, ALD, or thermal oxidation.

[0067] Step 4: Deposit a barrier layer. The barrier layer material may include metals or metal compounds such as Ta, TaN / Ta, and TiN.

[0068] Step 5: Deposit a seed layer. After the barrier layer, grow another Cu seed layer to conduct electricity in the subsequent electroplating filling process, and at the same time provide Cu crystal nuclei to obtain more uniform crystallization.

[0069] Step 6: Electrochemical plating (ECP) is used to fill the conductive material inside the through-hole (TSV). Conductive materials that can be filled by ECP include Cu, W, and polycrystalline silicon. This disclosure uses Cu metal for electroplating and then annealing the wafer after filling to make the conductive metal filler grains more uniform.

[0070] Step 7: After Cu electroplating, a Cu metal layer of uneven thickness is deposited on the wafer surface. Chemical mechanical polishing (CMP) is used to remove the excess Cu metal, planarizing the surface and retaining only the Cu metal within the vias (TSVs) as interconnect pillars 104 (including first interconnect pillar 1041, second interconnect pillar 1042, and third interconnect pillar 1043). This step simultaneously removes the dielectric layer, barrier layer, and seed layer from the surface of the 4H-SiC substrate 101, retaining only the dielectric layer, barrier layer, and seed layer within the vias (TSVs). The final wafer cross-section is shown below. Figure 12 As shown, Figure 12 The dielectric layer, barrier layer, and seed layer are not shown.

[0071] Step 8: By depositing ohmic metal on the surface and dry etching, the first electrode S1, the second electrode D1, the source electrode S3 and D3 on the surface of the first 3C-SiC layer 102, and the third electrode S2 and the fourth electrode D2 on the surface of the second 3C-SiC layer 103 are realized. Further, Schottky metal is deposited on the surface and etched to realize the first gate electrode G1 and the gate electrode G3 on the surface of the first 3C-SiC layer 102, and the second gate electrode G2 on the surface of the second 3C-SiC layer 103.

[0072] Step 9: In the region between the first interconnect pillar 1041 and the second interconnect pillar 1042, and in the region between the first interconnect pillar 1041 and the power device PD, P-type dopant atoms are implanted from the carbon side of the 4H-SiC substrate 101 to form a first isolation structure 105 that penetrates the first 3C-SiC layer 102 and extends into the 4H-SiC substrate 101 in the region between the first interconnect pillar 1041 and the second interconnect pillar 1042, and a third isolation structure 107 that penetrates the first 3C-SiC layer 102 and extends into the 4H-SiC substrate 101 in the region between the first interconnect pillar 1041 and the power device PD. Alternatively, N-type dopant atoms can be implanted from the silicon side of the 4H-SiC substrate 101 in the region between the second interconnect pillar 1042 and the third interconnect pillar 1043 to obtain a second isolation structure 106 that penetrates the second 3C-SiC layer 103 and extends into the 4H-SiC substrate 101.

[0073] Step 10: Dielectric layer deposition, via opening, and metallization interconnection are performed on the first 3C-SiC layer 102 and the second 3C-SiC layer 103 to achieve... Figure 2 The electrical connections between the various parts of the device are shown.

[0074] Based on the same inventive concept, this disclosure provides a power device including the semiconductor device described above. Since the principle by which this power device solves the problem is similar to that of the semiconductor device described above, the implementation of the power device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be repeated.

[0075] In some embodiments, the power devices provided in this disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances. Of course, the power devices provided in this disclosure may include other structures besides semiconductor devices. For example, when the power device is a radar, it may also include structures such as transmitters, antennas, and receivers; when the power device is a mixer, it may also include structures such as input ports and output ports.

[0076] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0077] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A driving circuit includes N-type field-effect transistors and P-type field-effect transistors spaced apart. The N-type field-effect transistor includes a 4H-SiC substrate, a first 3C-SiC layer located on the carbon side of the 4H-SiC substrate, and a first gate, a first electrode, and a second electrode located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The P-type field-effect transistor includes the 4H-SiC substrate, a second 3C-SiC layer located on the silicon side of the 4H-SiC substrate, and a second gate, a third electrode, and a fourth electrode located on the side of the second 3C-SiC layer away from the 4H-SiC substrate. An interconnect pillar penetrates the 4H-SiC substrate. The interconnect pillar is insulated from the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer. The interconnect pillar includes a first interconnect pillar, a second interconnect pillar, and a third interconnect pillar. The first interconnect pillar connects the first gate and the second gate. The second interconnect pillar connects the first electrode and the third electrode. The third interconnect pillar connects the fourth electrode to one end of a constant voltage source. The other end of the constant voltage source and the second electrode are both grounded. The first electrode is the source, the second electrode is the drain, the third electrode is the source, and the fourth electrode is the drain; or, the first electrode is the source, the second electrode is the drain, the third electrode is the drain, and the fourth electrode is the source; or, the first electrode is the drain, the second electrode is the source, the third electrode is the source, and the fourth electrode is the drain; or, the first electrode is the drain, the second electrode is the source, the third electrode is the drain, and the fourth electrode is the source.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a first isolation structure and a second isolation structure; The first 3C-SiC layer is also located in the region where the P-type field-effect transistor is located, and the first isolation structure penetrates the first 3C-SiC layer in the region where the P-type field-effect transistor is located and extends into the 4H-SiC substrate; The second 3C-SiC layer is also located in the region where the N-type field-effect transistor is located. The second isolation structure penetrates the second 3C-SiC layer in the region where the N-type field-effect transistor is located and extends into the 4H-SiC substrate.

3. The semiconductor device as described in claim 2, characterized in that, The first isolation structure is a groove structure or a P-type doped structure, and the second isolation structure is a groove structure or an N-type doped structure.

4. The semiconductor device as described in claim 2, characterized in that, The interconnect pillars specifically penetrate the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer.

5. The semiconductor device as claimed in claim 4, characterized in that, Also includes: A seed layer, a barrier layer, and a dielectric layer are provided that penetrate the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer, wherein the seed layer is in contact with the interconnect pillar, the dielectric layer is in contact with the first 3C-SiC layer, the 4H-SiC substrate, and the second 3C-SiC layer, and the barrier layer is located between the seed layer and the dielectric layer.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The thickness of both the first 3C-SiC layer and the second 3C-SiC layer is 25nm~30nm.

7. The semiconductor device as claimed in claim 1, characterized in that, The driving circuit includes a first-stage driving circuit, which includes the N-type field-effect transistor and the P-type field-effect transistor. The first gate is a pulse gate signal input terminal, and the first electrode is a driving signal output terminal.

8. The semiconductor device as claimed in claim 1, characterized in that, The driving circuit includes a first-stage driving circuit and a second-stage driving circuit, wherein the first-stage driving circuit and the second-stage driving circuit respectively include the N-type field-effect transistor and the P-type field-effect transistor; The first gate of the first-stage driving circuit is a pulse gate signal input terminal, the first gate of the second-stage driving circuit is electrically connected to the first electrode of the first-stage driving circuit, and the first electrode of the second-stage driving circuit is a driving signal output terminal.

9. The semiconductor device as claimed in claim 7 or 8, characterized in that, It also includes a power device spaced apart from the driving circuit. The power device includes the 4H-SiC substrate, the first 3C-SiC layer, the second 3C-SiC layer, and a gate, a source, and a drain located on the side of the first 3C-SiC layer away from the 4H-SiC substrate. The gate of the power device is electrically connected to the driving signal output terminal, the source of the power device is grounded, and the drain of the power device is electrically connected to the load.

10. The semiconductor device as claimed in claim 9, characterized in that, It also includes a third isolation structure located between the region where the power device is located and the region where the driving circuit is located, the third isolation structure penetrating the first 3C-SiC layer and extending into the 4H-SiC substrate.

11. The semiconductor device as claimed in claim 10, characterized in that, The third isolation structure is a groove structure or a P-type doped structure.

12. A power device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 11.

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