Etching method for manufacturing back incidence micro lens and manufacturing method of detector chip

Abstract

The invention relates to an etching method for manufacturing a back incidence micro lens and a manufacturing method for a detector chip. The etching method for manufacturing the back incidence micro lens comprises the following steps: thinning and polishing the back surface of a wafer subjected to a front surface process; manufacturing a photoresist lens pattern of which the morphology meets the target requirement on the back surface of the thinned wafer; photoresist is spin-coated on the front surface of the wafer and baked, so that a front surface protection layer is formed on the surface of the front surface process; coating vacuum silicone grease on the surface of the front protective layer; and performing dry etching on a mask layer by using the photoresist lens pattern on the back surface of the wafer as the mask layer. According to the method, the back surface of the wafer is thinned and polished, so that the technical problems of photoresist burning, non-uniform etching and the like caused by heat accumulation can be effectively avoided; meanwhile, the vacuum silicone grease can avoid performance degradation and photoresist burning caused by overheating of the chip in the subsequent dry etching process, enables the chip to be kept at a stable position, and prevents wafer displacement from affecting the etching precision.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor photodetectors, and particularly to an etching method for fabricating a back-illuminated microlens and a method for fabricating a detector chip. Background Art

[0002] With the rapid development of optical communication technology towards high speed, large capacity, and miniaturization, stringent requirements are imposed on the performance and integration of optoelectronic devices. As a new generation of optical transmission standard, the optical communication system urgently needs to adapt high-performance microlenses to optimize the optical signal transmission and coupling efficiency.

[0003] InP (indium phosphide) material has become an ideal semiconductor substrate material for manufacturing high-speed optoelectronic devices due to its high electron mobility, direct bandgap characteristics, and good optical properties. In the field of microlenses, it can achieve precise control of light and meet the requirements for fine processing such as light focusing and collimation during high-speed signal transmission.

[0004] In related technologies, when the traditional microlens manufacturing process is applied to the back-illuminated scenario, many drawbacks are exposed. For example, in the high-precision photoresist forming and ICP etching processes, problems such as photoresist burning, low etching accuracy, rough etching surface, unbalanced etching selectivity, and slow etching rate often occur, and it is impossible to stably produce products that meet the stringent design specifications of microlenses (such as bottom diameter 60 - 130μm, arch height 2 - 30μm).

[0005] Therefore, it is necessary to design a new etching method for fabricating a back-illuminated microlens to overcome the above problems. Summary of the Invention

[0006] The present application provides an etching method for fabricating a back-illuminated microlens and a method for fabricating a detector chip, which can solve the technical problems of photoresist burning and low etching accuracy in the etching process in related technologies.

[0007] In a first aspect, an embodiment of the present application provides an etching method for fabricating a back-illuminated microlens, which includes the following steps:

[0008] Thin and polish the back surface of the wafer after the front process is completed;

[0009] Fabricate a photoresist lens pattern with a morphology meeting the target requirements on the back surface of the thinned wafer;

[0010] Spin-coat and bake photoresist on the front surface of the wafer to form a front protective layer on the surface of the front process;

[0011] Coat vacuum silicone grease on the surface of the front protective layer;

[0012] Use the photoresist lens pattern on the back surface of the wafer as a mask layer and perform dry etching on the mask layer.

[0013] In combination with the first aspect, in one embodiment, applying vacuum silicone grease on the surface of the front protective layer includes:

[0014] Evenly apply the vacuum silicone grease to the front protective layer with a cotton swab.

[0015] In combination with the first aspect, in one embodiment, when dry-etching the mask layer, the etching gas used includes Hbr and N2, and the proportion of Hbr in the etching gas is 40% - 80%, the proportion of N2 is 30% - 60%, and the etching chamber pressure is 2 - 8 mTorr.

[0016] In combination with the first aspect, in one embodiment, the dry-etching of the mask layer includes:

[0017] Place the side of the wafer coated with vacuum silicone grease flat on the wafer chuck, and blow the center of the wafer with an N2 gun to make the wafer tightly adhere to the wafer chuck due to the force;

[0018] Then place the wafer chuck together with the wafer in an ICP etching equipment for etching; wherein, the ICP etching power is 350 - 800 W, the RF etching power is 50 - 250 W, the etching time is 20 - 90 min, and the etching temperature is 0 - 20 °C.

[0019] In combination with the first aspect, in one embodiment, when baking to form the front protective layer, the baking temperature is 95 - 115 °C, and the baking time is 60 - 120 s.

[0020] In combination with the first aspect, in one embodiment, after dry-etching the mask layer by using the photoresist lens pattern on the back of the wafer as the mask layer, it further includes:

[0021] Immerse the etched wafer in the stripping solution until the front protective layer falls off together with the vacuum silicone grease and is removed.

[0022] In combination with the first aspect, in one embodiment, fabricating the photoresist lens pattern with a morphology meeting the target requirements on the back of the thinned wafer includes:

[0023] Spin-coat photoresist on the back of the thinned wafer to fabricate the photoresist lens pattern;

[0024] Perform a curing process on the photoresist lens pattern to make the morphology of the photoresist lens pattern meet the target requirements.

[0025] In combination with the first aspect, in one embodiment, the type of photoresist for fabricating the photoresist lens pattern is AZP4620 or P4903, and the spin-coating thickness is 6 - 30 um.

[0026] In combination with the first aspect, in one embodiment, spin-coating a photoresist on the back surface of the thinned wafer and fabricating a photoresist lens pattern includes:

[0027] Spin-coating a photoresist on the back surface of the thinned wafer, and then baking the photoresist;

[0028] Exposing the baked photoresist using an exposure device, and then developing it; wherein, the baking temperature is 90 - 130 °C, the baking time is 1 - 5 min, the exposure time is 20 - 150 S, and the development time is 3 - 12 min.

[0029] In a second aspect, an embodiment of the present application provides a method for fabricating a semiconductor detector chip, which includes the following steps:

[0030] Fabricating a wafer with an epitaxial layer grown on its surface and having completed front-side processes;

[0031] Fabricating a back-illuminated microlens on the wafer according to the above-described etching method for fabricating a back-illuminated microlens to form a semiconductor detector chip.

[0032] The beneficial effects brought by the technical solution provided by the embodiment of the present application include:

[0033] By thinning and polishing the back surface of the wafer, it is possible to effectively avoid process problems such as burned photoresist and uneven etching caused by heat accumulation in subsequent photolithography and etching processes of the microlens, thereby improving the product yield; at the same time, the vacuum silicone grease coated on the surface of the front-side protective layer can conduct the heat generated by the chip during subsequent dry etching, preventing the chip from deteriorating in performance and burning the photoresist due to overheating, and the vacuum silicone grease can keep the chip in a stable position during etching, preventing the wafer from shifting and affecting the etching accuracy, thus solving the technical problems of burned photoresist and low etching accuracy in the etching process in the related art. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0035] Figure 1 It is a flowchart of an etching method for fabricating a back-illuminated microlens provided by an embodiment of the present application;

[0036] Figure 2 It is a flowchart of another etching method for fabricating a back-illuminated microlens provided by an embodiment of the present application;

[0037] Figure 3 An example cross-sectional view of the back-illuminated microlens provided by the embodiment of the present application;

[0038] Figure 4 A schematic diagram of the back structure of the back-illuminated microlens provided by the embodiment of the present application;

[0039] Figure 5 A schematic diagram of the front structure of the back-illuminated microlens provided by the embodiment of the present application. Specific embodiments

[0040] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0041] The embodiment of the present application provides an etching method for manufacturing a back-illuminated microlens and a manufacturing method for a detector chip, which can solve the technical problems of photoresist burning and low etching accuracy in the etching process in the related art.

[0042] See Figure 1 As shown, an etching method for manufacturing a back-illuminated microlens provided by the embodiment of the present application may include the following steps:

[0043] S1: Thinning and polishing the back surface of the wafer after the front process is completed.

[0044] S2: Making a photoresist lens pattern with a topography meeting the target requirements on the back surface of the thinned wafer.

[0045] S3: Spin-coating and baking photoresist on the front surface of the wafer to form a front protective layer on the surface of the front process.

[0046] S4: Coating vacuum silicone grease on the surface of the front protective layer.

[0047] S5: Using the photoresist lens pattern on the back surface of the wafer as a mask layer to perform dry etching on the mask layer.

[0048] Before step S1, a wafer with an epitaxial layer grown on the surface and the front process completed is provided first. Among them, in this embodiment, the structure of the epitaxial layer includes a substrate layer InP, an absorption layer InGaAs, a buffer layer InGaAsP, a charge layer InGaAs, a multiplication layer INP, and a contact layer InGaAsP grown in sequence. The finally obtained back-illuminated microlens is a lens pattern made of InP material. See Figure 4and Figure 5 As shown Figure 4 is a schematic diagram of the back structure of the finally obtained back-illuminated microlens, Figure 5 and is a schematic diagram of the front structure of the finally obtained back-illuminated microlens.

[0049] In step S1, the thickness range of the back thinning is 100 - 200 um. In this embodiment, the thinned thickness is relatively thin, and a thinner structure is conducive to the rapid dissipation of heat, helps to reduce the propagation path of light inside the material, reduces light loss, enables the microlens to have a more accurate focusing and collimating effect on light, can better meet the requirements of the optical communication system for the fine control of optical signals, improves the optical signal coupling efficiency, and ensures high-quality data transmission; in subsequent processes such as photolithography and etching in the production of microlenses, it can effectively avoid process problems such as the burning of photoresist and uneven etching caused by heat accumulation, and improve the product yield. Preferably, the back thinning thickness of the wafer is 100 um.

[0050] In this embodiment, by thinning and polishing the back of the wafer, process problems such as the burning of photoresist and uneven etching caused by heat accumulation can be effectively avoided in subsequent photolithography and etching processes of the microlens, improving the product yield; at the same time, the vacuum silicone grease coated on the surface of the front protective layer can conduct the heat generated by the chip during the subsequent dry etching process, avoiding the performance degradation and burning of the photoresist due to overheating of the chip, and the viscous property of the vacuum silicone grease can keep the chip in a stable position during etching, preventing the displacement of the wafer from affecting the etching accuracy, further ensuring the product yield and performance of the chip in the entire process, and solving the technical problems of the burning of photoresist and low etching accuracy in the etching process in the related art.

[0051] Further, in one embodiment, referring to Figure 2 as shown, in step S2, fabricating a photoresist lens pattern with a morphology meeting the target requirements on the back of the thinned wafer may include:

[0052] S21: Spin-coat photoresist on the back of the thinned wafer to fabricate a photoresist lens pattern.

[0053] S22: Perform a curing process on the photoresist lens pattern to make the morphology of the photoresist lens pattern meet the target requirements.

[0054] In this embodiment, first spin-coat photoresist on the back of the thinned wafer to initially fabricate a photoresist lens pattern. At this time, it is not yet cured, and the photoresist lens pattern can still be fine-tuned, and then cured, so that the shape of the photoresist lens pattern is fixed to fabricate a photoresist lens pattern with a morphology meeting the target requirements.

[0055] Further, in some preferred embodiments, in step S21, the photoresist type for fabricating the photoresist lens pattern is AZ P4620 or P4903, and the spin coating thickness is 6 - 30 um. In this embodiment, the thickness of the photoresist for fabricating the photoresist lens pattern is 14 um. The two selected photoresists, AZ P4620 or P4903, in this embodiment can meet the process requirements of the lens arch height, and can reduce the requirements for the etching selectivity ratio, reducing the difficulty of the etching process; the spin coating thickness can be determined according to the final height of the lens.

[0056] Further, in one embodiment, in step S21, spin - coating a photoresist on the back surface of the thinned wafer to fabricate a photoresist lens pattern may include the following steps:

[0057] S211: Spin - coat a photoresist on the back surface of the thinned wafer, and then bake the photoresist.

[0058] S212: Use an exposure device to expose the baked photoresist, and then develop it; wherein, the baking temperature is 90 - 130 °C, the baking time is 1 - 5 min, the exposure time is 20 - 150 S, and the development time is 3 - 12 min.

[0059] In this embodiment, the wafer is first baked, then exposed using a MA6 manual exposure device, and then developed; wherein, the baking temperature is 90 - 130 °C, the baking time is 1 - 5 min, the MA6 exposure time is 20 - 150 S, and the development time is 3 - 12 min. Preferably, the baking temperature is 110 °C, the baking time is 2.5 min, the exposure time is 110 S, and the development time is 11 min. In this embodiment, the lithography process can easily adjust the values of the above - mentioned parameters within the above - mentioned broad parameter range according to the bottom diameter, arch height, etc., with little limitation, and a good lens pattern can be obtained.

[0060] In the above - mentioned embodiment, step S22 is also crucial. First, it is necessary to accurately measure the thickness of the photoresist of the obtained photoresist lens pattern, and this data will provide a key basis for subsequent operations. Then, determine the required arch height of the photoresist according to the final target to be achieved, and then carry out the thermal melting treatment. The thermal melting treatment can be achieved by means of various devices, such as a curing furnace, an annealing furnace, an oven or a hot plate. These devices have their own characteristics, but they can all meet the basic thermal melting requirements. During the thermal melting treatment, the temperature should be controlled in the range of 150 - 200 °C, and the time should be kept within the range of 3 - 10 min. Such settings are obtained through repeated experiments and debugging, which can ensure that the photoresist reaches an ideal forming effect during the thermal melting process. It will neither be insufficiently thermally melted due to too low temperature and too short time, affecting the final optical performance of the lens, nor will it be overly deformed or damaged due to too high temperature and too long time, destroying the stability of the entire process.

[0061] Preferably, the hot melting device is selected as a hot plate, the hot melting temperature is 180 °C, and the hot melting time is 5 min. The reason for such selection is that, compared with other devices, the hot plate performs better in controlling temperature uniformity, enabling the photoresist to be heated more evenly, making the lens arch height after hot melting more accurately meet the expectations, and having a shorter process time, thus enabling rapid mass production. Refer to Figure 3 As shown, it is a cross-sectional view of an example of a back-illuminated microlens fabricated in this embodiment. In the figure, D2 is the lens arch height, and the lens arch height obtained in this embodiment is 23.86 um.

[0062] Further, in one embodiment, in step S3, the type of the photoresist for forming the front protective layer is AZ5214, and the spin coating thickness is 1 - 3 um. In this embodiment, the function of the front protective layer is to protect the front pattern of the wafer. Selecting the photoresist type AZ5214 and a spin coating thickness of 1 - 3 um can achieve better results in protecting the front pattern. It not only ensures sufficient protection thickness but also avoids difficulties in subsequent processing due to excessive thickness. At the same time, appropriate baking temperature and time help the photoresist to cure better, enhancing its protection performance, providing a more reliable basis for subsequent operations related to vacuum grease, and ensuring the stability of the chip throughout the process. In this embodiment, when baking to form the front protective layer, the baking temperature is 95 - 115 °C, and the baking time is 60 - 120 s. Preferably, the spin coating thickness of the photoresist is 3 um, the baking temperature is 110 °C, and the baking time is 90 s.

[0063] Further, in one embodiment, in step S4, the application of vacuum grease on the surface of the front protective layer may include: evenly applying the vacuum grease to the front protective layer with a cotton swab. In this embodiment, the vacuum grease is evenly applied to the surface of the above-mentioned front protective layer with a cotton swab, which is used for heat dissipation protection and position fixation during the etching process. Preferably, the DOW CORNING340 model of vacuum grease is selected. This model of vacuum grease has good heat dissipation performance and can effectively conduct the heat generated by the chip during the etching process, avoiding problems such as performance degradation of the chip due to overheating. At the same time, its viscous property can keep the chip in a stable position during etching, preventing the wafer from shifting and affecting the etching accuracy, and further ensuring the yield and performance of the chip throughout the process. Of course, in other embodiments, other methods can also be used to apply the vacuum grease on the surface of the front protective layer, which is not limited herein.

[0064] Further, in some alternative embodiments, in step S5, when dry etching the mask layer, the etching gas used includes Hbr and N2, and the proportion of Hbr in the etching gas is 40% to 80%, and the proportion of N2 is 30% to 60%, and the etching chamber pressure is 2 to 8 mTorr. In this embodiment, by controlling the proportions of Hbr and N2 in the etching gas for dry etching the mask layer, the selectivity between the photoresist and InP and the lithography pattern can be better controlled. At the same time, according to the size of the photoresist lens pattern and the thickness of the photoresist, the etching conditions are adjusted, and the final ideal etching rate and selectivity can be obtained.

[0065] In the above embodiments, the etching gases HBr and N2 have the following advantages: Reducing material damage: Compared with commonly used Ar gas, etc., N2 has lower ion energy, and the physical bombardment effect during etching is relatively weak, which can effectively reduce the damage to InP material, help maintain the integrity and performance of the material, and is very important for fabricating high-performance InP-based optoelectronic devices, etc., and can reduce problems such as device performance degradation caused by etching damage. As a bromine-based gas, HBr reacts relatively mildly with InP. In a plasma environment, the bromine element radicals released by its decomposition react chemically with InP, and will not cause excessive etching or violent reaction to the material like some strongly corrosive gases, thus reducing the impact on the internal structure and performance of the material. High etching rate: HBr can generate sufficient active bromine atoms in the plasma, react chemically with In and P elements in InP to form volatile products, thereby achieving a relatively fast etching rate, improving the etching efficiency, and shortening the process time. Small surface roughness: The combined etching of HBr and N2 can obtain an etching effect with a small surface roughness, making the surface of the InP material smoother. This is very important for InP-based optoelectronic devices because a smooth surface can reduce light scattering and electron scattering, and improve the optical and electrical performance of the device. For example, it can reduce the threshold current of the laser and improve the responsivity of the detector, etc. High selectivity to mask materials: When etching InP, the combination of HBr and N2 has good selectivity to some commonly used mask materials, such as photoresist. This means that during the etching process, it can preferentially remove the InP material, and the etching amount of the mask material is relatively small, thus ensuring the integrity and effectiveness of the mask, accurately defining the etching area, and improving the accuracy and controllability of the etching. Selectivity to different InP layers: For InP-based multi-layer structures, such as InP / InGaAsP, etc., HBr and N2 etching can achieve selective etching of different material layers. By adjusting the etching process parameters, such as gas flow rate, plasma power, etc., the etching process can be made to preferentially target a specific InP layer, with less impact on other layers, which is beneficial for fabricating InP-based devices with complex structures, such as photodetectors. No harmful residues: During the etching process of HBr and N2, the reaction products are usually volatile indium bromide (InBrx) and phosphorus bromide (PBrx), etc., as well as N2 itself. These products can be easily discharged from the reaction chamber through a vacuum system, etc. after etching, and will not leave harmful residues on the material surface or in the chamber, reducing environmental pollution and the impact on subsequent processes. Relatively safe: N2 is an inert gas with stable chemical properties and will not undergo violent chemical reactions during the etching process, reducing the safety risks during the process. At the same time, although HBr has certain corrosiveness, compared with some other strongly corrosive gases, its use safety is relatively high under reasonable operation and protection conditions.

[0066] Further, in one embodiment, in step S5, the dry etching of the mask layer may include: flatly attaching the side of the wafer coated with vacuum silicone grease to the wafer chuck, and purging the center of the wafer with an N2 gun to make the wafer tightly attached to the wafer chuck by force; then placing the wafer chuck together with the wafer in an ICP etching equipment for etching; wherein, the ICP etching power is 350-800 W, the RF etching power is 50-250 W, the etching time is 20-90 min, and the etching temperature is 0-20 °C.

[0067] In this embodiment, when dry etching the mask layer, the wafer with the side coated with vacuum silicone grease is flatly attached to the wafer chuck, and the center is purged with an N2 gun to make it tightly attached to the wafer chuck by force, so that it can dissipate heat evenly. Then it is placed in an ICP etching equipment. The etching gas used includes Hbr and N2, and the proportion of Hbr in the etching gas is 40%-80%, and the proportion of N2 is 30%-60%. The etching chamber pressure is 2-8 mTorr, the ICP etching power is 350-800 W, the RF etching power is 50-250 W, the etching time is 20-90 min, and the etching temperature is 0-20 °C. In this embodiment, by controlling the proportion of Hbr and N2 in the etching gas for dry etching of the mask layer, the selectivity ratio between the photoresist and InP and the photolithographic pattern can be better controlled. At the same time, according to the size of the photoresist lens pattern and the thickness of the photoresist, the etching conditions are adjusted, and the final ideal etching rate and selectivity ratio can be obtained. Preferably, in step S5, the proportion of the etching gas used for dry etching is Hbr:N2 = 15:20, the etching chamber pressure is 6 mTorr, the RF (Radio Frequency Source) etching power is 130 W, the ICP etching power is 800 W, and the etching temperature is 20 °C.

[0068] In the above embodiments, different process parameters are matched according to products with different etching areas or etching depths. For example, the chamber pressure is set to 2 - 4 mtorr. A low chamber pressure can reduce physical damage, lower ion energy, and reduce the bombardment damage to the photoresist, especially suitable for thin photoresist layers. The chamber pressure can also be set to 5 - 8 mtorr. A high chamber pressure can provide a high etching rate: increase the concentration of neutral radicals, promote the chemical etching reaction, and is suitable for scenarios where materials need to be quickly removed and appearance improvement. Uniformity optimization: By adjusting the gas pressure, the plasma distribution uniformity can be improved, and the thermal stress on the photoresist caused by ion bombardment can be reduced, which is particularly prominent in large-area wafer etching. When the ICP etching power is 300 - 500 W, it can protect the photoresist: avoid the decomposition or carbonization of the photoresist caused by high-energy ions; Selectivity optimization: The etching rate ratio of the photoresist to the material to be etched is higher at low power. When the ICP etching power is 500 - 800 W, it can quickly remove the photoresist: suitable for dry ashing of thick photoresist layers, but the time needs to be strictly controlled to avoid overheating. When the RF etching power is 50 - 100 w, it can minimize ion energy: reduce the physical damage to the photoresist; and prevent pattern deformation: at low power, ion bombardment is milder, avoiding the collapse of the photoresist edge due to excessive energy. When the RF etching power is 150 - 250 W, it can enhance anisotropy: suitable for high aspect ratio structures, but low temperature needs to be combined to suppress the thermal effect. The etching temperature is set to 0 - 20 °C, so that the photoresist is prone to softening or decomposition at high temperatures, and low temperature can maintain its mechanical strength and pattern fidelity.

[0069] In the related art, when the traditional micro-lens manufacturing process is applied to the back-illumination scenario, in the high-precision photoresist forming and ICP etching processes, problems such as photoresist burning, rough etching surface, unbalanced etching selectivity, and too slow etching rate often occur, and products that meet the strict design specifications of micro-lenses (such as bottom diameter 60 - 130 μm, arch height 2 - 30 μm) cannot be stably produced. Through the above etching steps, this embodiment optimizes the etching process, adjusts key parameters, and coordinates with the resist stripping process, greatly reducing the process problems of rework such as photoresist burning and rough etching surface, promoting mass production, and precisely controlling the process to produce micro-lenses that meet strict specifications (bottom diameter 60 - 130 μm, arch height 2 - 30 μm), ensuring the light manipulation ability, improving the optical signal coupling efficiency, and helping the optical communication system to operate stably; solving the problems that in the high-precision photoresist forming and ICP etching processes, problems such as photoresist burning, rough etching surface, unbalanced etching selectivity, and too slow etching rate often occur, and products that meet the strict design specifications of micro-lenses cannot be stably produced. See Figure 3 As can be seen from the cross-sectional view of the back-illumination micro-lens produced in this embodiment shown in

[0070] Further, in one embodiment, after using the photoresist lens pattern on the back side of the wafer as a mask layer and performing dry etching on the mask layer, the following steps may further be included:

[0071] S6: Immerse the etched wafer in a stripping solution until the front protective layer falls off together with the vacuum grease; after removal, a back-illuminated microlens is obtained.

[0072] The specific operation steps of this embodiment may be as follows: First, use a U-shaped spatula to gently push the wafer (i.e., the above-mentioned wafer) off the silicon wafer tray, and then place the thin sheet with the vacuum grease and the front protective layer in an inclined basket, where the side with the vacuum grease and the front protective layer faces down. Then, completely immerse the inclined basket in the NMP solution (in other embodiments, other types of stripping solutions may also be selected, which are not limited herein). The solution temperature is 50-180°C, the solution volume is 300-600 ml, and the soaking time is 5-20 min. Observe until the front protective layer falls off together with the vacuum grease. Finally, replace the flat-bottom basket with the front side up for flushing treatment. Preferably, the method for removing the front protective layer is as follows: First, soak in 350 ml of NMP at 130°C for 10 min, then replace it with 350 ml of clean NMP and soak at 130°C for 5 min to dissolve the residue completely. Finally, replace the soaked wafer with a clean flat-bottom basket, flush with water for 5 min, and then dry.

[0073] In the above embodiment, during the first 10-minute soaking, the high temperature enables the NMP molecules to fully contact the residual substances, quickly dissolving most of the substances. During the second soaking with fresh NMP for 5 minutes, the inhibition of the high-concentration impurities in the solution after the first soaking is eliminated, allowing the residual insoluble substances to dissolve further, enhancing the dissolution efficiency and achieving a more thorough cleaning. For a single long soaking, the increase in impurity concentration will cause the dissolved substances to precipitate or hinder dissolution. By replacing the NMP with fresh NMP for two soakings, the high dissolution power of NMP can be maintained, preventing impurity accumulation and reducing impurity residues. Each soaking time is short, which can reduce the damage of high temperature and NMP to the object being processed, prevent deformation or performance changes, and is beneficial for protection. At the same time, the NMP impurities are single after each soaking, which is convenient for classification and recycling, and the object being processed is also easier to clean, facilitating subsequent processing and use.

[0074] When the traditional micro-lens manufacturing process is applied to the back-illumination scenario, many drawbacks are exposed. For example, in the process of thinning and then processing the back micro-lens after the subsequent complex front process, there is a lack of a reliable thin-film handling solution, making it difficult to ensure the safe and efficient separation of the thin film from the silicon wafer and prone to causing contamination of the front chip appearance during the back process manufacturing. In this embodiment, by fabricating a photoresist lens pattern on the back of the thinned wafer and performing etching, photoresist removal and other treatments, a clean back-illumination micro-lens can be obtained. At the same time, the front protective layer formed on the wafer surface before etching can prevent the front chip appearance from being contaminated during etching. After etching, immersing the wafer in the photoresist removal solution can efficiently and safely remove the residual photoresist on the wafer surface, which can solve the technical problems in the related art, such as the lack of a reliable thin-film handling solution, the difficulty in ensuring the safe and efficient separation of the thin film from the silicon wafer, and the tendency to cause contamination of the front chip appearance during the back process manufacturing, improve the product quality, overcome the problem of thin-film separation, avoid contamination of the front chip, ensure excellent appearance and high quality of the micro-lens and the chip, and meet the appearance requirements of high-end devices.

[0075] Preferably, in step S6, the solution volume of the photoresist removal solution is 300 - 600 ml, and the immersion time of the wafer is 5 - 20 min. In this embodiment, selecting 300 - 600 ml of the photoresist removal solution and immersing for 5 - 20 min has the following effects: Efficient photoresist removal: A sufficient amount of the photoresist removal solution (300 - 600 ml) can fully cover the wafer surface, ensuring sufficient contact between the photoresist and the photoresist removal solution. The immersion time of 5 - 20 min provides a suitable duration for the chemical substances in the photoresist removal solution to react with the photoresist, effectively decomposing and dissolving the photoresist, achieving the purpose of efficiently removing the photoresist, and ensuring that the subsequent processing of the wafer is not interfered by photoresist residues. Cost control: If the amount of the photoresist removal solution used is too small, it may not be able to fully cover the wafer or it may be difficult to completely remove the photoresist, requiring multiple repeated operations, increasing the total amount of the photoresist removal solution and time costs. If it is too much, it will cause waste. 300 - 600 ml balances the usage amount of the photoresist removal solution while ensuring the photoresist removal effect, controlling costs. If the immersion time is too short, the photoresist removal is incomplete; if it is too long, it will increase the time cost. 5 - 20 min is a more economical and efficient time range. Protecting the wafer: The appropriate amount of the photoresist removal solution and immersion time can, while effectively removing the photoresist, minimize the damage to the wafer's own material and surface micro-structure to the greatest extent. Avoiding excessive corrosion and etching of the wafer surface due to too high a concentration, too large an amount or too long an immersion time of the photoresist removal solution, which affects the key characteristics such as the electrical and optical properties of the wafer. Process stability: This range of the photoresist removal solution amount and immersion time provides a relatively stable parameter range for the process operation. In mass production, wafers of different batches can obtain relatively consistent photoresist removal effects under this process condition, ensuring the stability and consistency of the product quality, reducing the risk of product quality fluctuations, and improving production efficiency and the yield rate.

[0076] Preferably, in step S6, the solution temperature of the photoresist stripping solution is 50 to 180 °C. In this embodiment, within the temperature range of 50 to 180 °C, the following effects are achieved: Accelerate the photoresist stripping reaction: Raising the temperature provides energy for the photoresist stripping reaction, increases molecular activity and collision frequency, accelerates the decomposition and dissolution of the photoresist, improves the photoresist stripping efficiency, shortens the photoresist stripping time, and can also act uniformly on the wafer to avoid uneven photoresist stripping locally. Improve the photoresist stripping effect: High temperature softens stubborn photoresist, facilitating the penetration and peeling of the photoresist stripping solution, ensuring complete removal of the photoresist, and guaranteeing the cleanliness of the wafer surface. Adapt to different materials and processes: Different wafers and photoresist materials have different temperature tolerances and reactivities. This temperature range can be flexibly adjusted to adapt to various material combinations and process requirements, such as different lithography and chip manufacturing processes. Improve production efficiency: Raising the temperature accelerates photoresist stripping, shortens the photoresist stripping time for a single wafer, increases the output per unit time, reduces costs, and can also reduce the residence time of the wafer in the equipment, improving equipment utilization. Reduce the influence of thermal stress: Compared with too high temperatures, this range can control thermal stress, reduce the impact on the microscopic structure of the wafer, and reduce microscopic structure deformation and damage, ensuring the performance and reliability of the chip.

[0077] This application optimizes the lens etching process and the photoresist stripping process. On the one hand, it ensures the safe and efficient separation of the thin film and the silicon wafer, and at the same time solves the problem of contamination of the front-side chip during the back-side process. On the other hand, it also solves the problems that often occur in the high-precision photoresist forming and ICP etching processes, such as photoresist burning, rough etching surface, unbalanced etching selectivity, and too slow etching rate, which cannot stably produce products that meet the strict design specifications of the micro-lens.

[0078] The embodiment of this application also provides a method for manufacturing a semiconductor detector chip, which may include the following steps: manufacturing a wafer with an epitaxial layer grown on the surface and having completed the front-side process; manufacturing a back-illuminated micro-lens on the wafer according to the etching method for manufacturing a back-illuminated micro-lens as described above to form a semiconductor detector chip.

[0079] In this embodiment, when manufacturing a semiconductor detector chip, first manufacture a substrate layer InP, an absorption layer InGaAs, a buffer layer InGaAsP, a charge layer InGaAs, a multiplication layer INP, and its contact layer InGaAsP to form an epitaxial layer structure; then perform subsequent processes such as Zn diffusion, contact ring preparation, passivation growth, metal electrode deposition, thinning, polishing, etc.; finally, use the above-described photoresist stripping method for manufacturing a back-illuminated micro-lens to manufacture a back-illuminated micro-lens, that is, to form a semiconductor detector chip.

[0080] After the semiconductor detector chip is manufactured, performance testing is carried out, and the long-term reliability result is qualified, and each performance parameter is qualified.

[0081] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. Unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0082] It should be noted that in the present application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0083] The above are only specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. An etching method for fabricating a back-illuminated microlens, characterized in that It includes the following steps: Thin and polish the back surface of the wafer after the front process is completed; Fabricate a photoresist lens pattern with a topography meeting the target requirements on the back surface of the thinned wafer; Spin-coat and bake photoresist on the front surface of the wafer to form a front protective layer on the surface of the front process; Apply vacuum grease on the surface of the front protective layer; Use the photoresist lens pattern on the back surface of the wafer as a mask layer and perform dry etching on the mask layer.

2. The etching method for fabricating a back-illuminated microlens according to claim 1, characterized in that, The applying vacuum grease on the surface of the front protective layer includes: Evenly apply the vacuum grease to the front protective layer with a cotton swab.

3. The etching method for fabricating a back-illuminated microlens according to claim 1, wherein When performing dry etching on the mask layer, the etching gas used includes Hbr and N2, and the proportion of Hbr in the etching gas is 40% - 80%, the proportion of N2 is 30% - 60%, and the etching chamber pressure is 2 - 8 mTorr.

4. The etching method for fabricating a back-illuminated microlens according to claim 3, wherein, The performing dry etching on the mask layer includes: Flatly attach the side of the wafer coated with vacuum grease to the wafer chuck, and use an N2 gun to blow the center of the wafer to make the wafer tightly attached to the wafer chuck by force; Then place the wafer chuck together with the wafer in an ICP etching equipment for etching; wherein, the ICP etching power is 350 - 800 W, the RF etching power is 50 - 250 W, the etching time is 20 - 90 min, and the etching temperature is 0 - 20 °C.

5. The etching method for fabricating a back-illuminated microlens according to claim 1, wherein When baking to form the front protective layer, the baking temperature is 95 - 115 °C, and the baking time is 60 - 120 s.

6. The etching method for fabricating a back-illuminated microlens according to claim 1, characterized in that, After performing dry etching on the mask layer using the photoresist lens pattern on the back surface of the wafer as a mask layer, it further includes: Immerse the etched wafer in a stripping solution until the front protective layer falls off together with the vacuum grease.

7. The etching method for fabricating a back-illuminated microlens according to claim 1, wherein The fabricating a photoresist lens pattern with a topography meeting the target requirements on the back surface of the thinned wafer includes: Spin-coat photoresist on the back surface of the thinned wafer to fabricate a photoresist lens pattern; Perform a curing process on the photoresist lens pattern to make the topography of the photoresist lens pattern meet the target requirements.

8. The etching method for fabricating a back-illuminated microlens according to claim 7, wherein The type of photoresist for fabricating the photoresist lens pattern is AZ P4620 or P4903, and the spin-coating thickness is 6 - 30 um.

9. The etching method for fabricating a back-illuminated microlens according to claim 7, characterized in that, The spin-coating photoresist on the back surface of the thinned wafer to fabricate a photoresist lens pattern includes: Spin-coat photoresist on the back surface of the thinned wafer, and then bake the photoresist; Use an exposure device to expose the baked photoresist, and then develop it; wherein, the baking temperature is 90 - 130 °C, the baking time is 1 - 5 min, the exposure time is 20 - 150 S, and the development time is 3 - 12 min.

10. A method for fabricating a semiconductor detector chip, characterized in that, It includes the following steps: Fabricate a wafer with an epitaxial layer grown on its surface and the front process completed; Fabricate a back-illuminated microlens on the wafer according to the etching method for fabricating a back-illuminated microlens described in any one of claims 1 - 9 to form a semiconductor detector chip.

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