Micro-LED chip with equal-height electrodes, preparation method of Micro-LED chip and display panel
By designing contour electrode structures and optimizing electrode hole shapes and materials, the bonding defects and manufacturing complexity of traditional Micro-LED chips are solved, the chip yield and life are improved, and the preparation process is simplified.
Patent Information
- Application Number
- CN202510387183.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-04
AI Technical Summary
There is a height difference between the p and n electrodes of traditional Micro-LED chips, which leads to bonding defects, affects the chip yield and luminous performance, and is complex in manufacturing process and reduces production efficiency.
Design a contour electrode structure, n-electrode and p-electrode at the same height, optimize the bottom cross-section and depth of the electrode hole, increase the contact area, adopt multi-layer protective layers and optimize electrode materials, and simplify the preparation process.
It improves contact performance and current uniformity during bonding, improves chip yield and service life, and simplifies the manufacturing process.
Smart Images
Figure CN120264964A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor LED chips, and particularly to a Micro-LED chip with equal-height electrodes, a preparation method thereof, and a display panel. Background Art
[0002] Micro-LED display technology is a new type of self-luminous display technology obtained by miniaturizing and matrixing light-emitting diodes (LEDs). It is known as the "next-generation display technology" because of its advantages such as high brightness, high contrast, high resolution, fast response, and low energy consumption. Micro-LED combines the advantages of LCD and OLED. At the same time, since it belongs to inorganic light-emitting diodes, there are no restrictions on the lifespan of OLED organic materials and the "burn-in problem", and it is expected to become the "ultimate display technology" that subverts the industry.
[0003] However, there is a height difference between the p and n electrodes of GaN-based flip-chip Micro-LED chips manufactured by traditional methods, which inevitably leads to bonding defects during the chip bonding process, thereby affecting the yield and luminous performance of chip manufacturing. The thickness of the chip also affects the development prospect of Micro-LED. How to manufacture GaN-based Micro-LED chips with a lower thickness has become a major difficulty in the future full-colorization of Micro-LED. At the same time, multi-step lithography in the manufacturing process will also reduce the production efficiency of Micro-LED chips. These problems seriously restrict the industrial development of Micro-LED. Summary of the Invention
[0004] In view of the deficiencies of the prior art, the present invention provides a Micro-LED chip with equal-height electrodes, including an epitaxial structure formed on a substrate and an electrode structure; The epitaxial structure includes a bonding layer, an n-type material layer, a multi-quantum well active layer, an electron blocking layer, a p-type material layer, and a transparent conductive layer from bottom to top. An n electrode hole reaching the n-type material layer and a p electrode hole reaching the p-type material layer are provided in the epitaxial structure. The bottom cross-section of the n electrode hole is a circle with a diameter larger than the depth of the n electrode hole; The electrode structure includes an n electrode and a p electrode respectively disposed in the n electrode hole and the p electrode hole. The n electrode includes a first connection end and a first bonding end, and the p electrode includes a second connection end and a second bonding end. The first bonding end and the second bonding end have the same height.
[0005] Further, the bottom cross-section of the p electrode hole is a circle with a diameter larger than that of the n electrode hole.
[0006] The n-electrode and the p-electrode are respectively grown in the n-electrode hole and the p-electrode hole. If the bottom cross-section of the n-electrode hole and the p-electrode hole is too small, the contact area between the n-electrode and the n-type material layer, and between the p-electrode and the p-type material layer will be reduced, resulting in an increase in contact resistance. At the same time, the insufficient contact area leads to uneven current distribution, causing local overheating and affecting the device life. In addition, too small diameters of the n-electrode and the p-electrode will reduce the mechanical strength, increase the difficulty of the bonding process, may cause poor connection, and affect the electrical characteristics of the chip. Considering these characteristics, the present invention optimizes the contact area between the electrode and the semiconductor material and sets the electrodes at the same height.
[0007] Further, a protective layer and a DBR layer are sequentially provided on the top of the transparent conductive layer and on the side wall of the n-electrode hole; The thickness of the protective layer is 0.5 - 1 μm; The thickness of the DBR layer is 0.5 - 1 μm.
[0008] Further, a first passivation layer is also provided on the DBR layer; The thickness of the first passivation layer is 0.5 - 1 μm.
[0009] Further, a superlattice stress buffer layer is also provided between the n-type material layer and the multi-quantum well active layer.
[0010] Further, the thickness of the epitaxial structure is 5.0 - 5.5 μm.
[0011] Further, an oxide layer and a second passivation layer are sequentially provided on the side of the epitaxial structure.
[0012] It should be noted that in the present invention, the types and compositions of the substrate and the epitaxial structure do not need to be strictly limited and can be selected according to the conventional understanding in the art. Exemplarily, the epitaxial structure is a GaN-based material. Among them, the bonding layer is composed of undoped u-GaN and n-AlGaN, and the n-AlGaN can block the upward extension of dislocations; the superlattice stress buffer layer is composed of an alternating stack of 10 periods of 2-nm InGaN and 5-nm GaN, and the In component in the InGaN layer is 5%, which can significantly improve the crystal quality of the multi-quantum well active layer; the n-type material layer and the p-type material layer are selected according to the color display requirements, and the structure of the multi-quantum well active layer is adjusted according to the light-emitting performance.
[0013] The present invention also provides a method for manufacturing the Micro-LED chip with the above-mentioned electrodes of equal height, including, Growing epitaxial materials on the substrate and performing etching to obtain an epitaxial structure on the substrate; Growing electrode materials in the n-electrode hole and the p-electrode hole of the epitaxial structure to obtain the n-electrode and the p-electrode.
[0014] Furthermore, the electrode material includes at least one of Cr, Al, Ti, Pt, Ti, Ni, and Au; The total thickness of the electrode material is 1.5 - 2 μm.
[0015] The present invention also provides a display panel with the above-mentioned Micro-LED chip having equal-height electrodes.
[0016] Compared with the prior art, the present invention has the following beneficial effects: The Micro-LED chip of the present invention has equal-height p and n electrodes, which can maintain good contact performance and electrical performance during the bonding process and can improve the uniformity of the current near the electrodes. The present invention optimizes the bottom cross-section and depth of the electrode holes, enhancing the contact between the electrodes and the semiconductor material layer, and can improve the yield and service life of the Micro-LED chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0018] Figure 1 Shows a schematic structural diagram of an epitaxial wafer in an embodiment; Figure 2 Shows a transmission electron microscope image of the n-AlGaN layer in an embodiment; Figure 3 Shows a schematic structural diagram of the product obtained in Step 2 of the embodiment; Figure 4 Shows a schematic structural diagram of the product obtained in Step 3 of the embodiment; Figure 5 Shows a schematic structural diagram of the product obtained in Step 4 of the embodiment; Figure 6 Shows a schematic structural diagram of the product obtained in Step 5 of the embodiment; Figure 7 Shows a schematic structural diagram of the product obtained in Step 6 of the embodiment; Figure 8 Shows a schematic structural diagram of the product obtained in Step 7 of the embodiment; Figure 9 Shows a schematic structural diagram of the product obtained in Step 8 of the embodiment; Figure 10 Shows a schematic structural diagram of the product obtained in Step 9 of the embodiment; Figure 11 The structural schematic diagram of the product obtained in Step Ten of the embodiment is shown; Figure 12 The structural schematic diagram of the product obtained in Step Eleven of the embodiment is shown; Figure 13 The structural schematic diagram of the product obtained in Step Twelve of the embodiment is shown; Figure 14 The structural schematic diagram of the Micro-LED chip with an isometric electrode prepared in the embodiment is shown; Figure 15 The structural schematic diagram of the existing blue / green Micro-LED chip is shown; Explanation of the reference numerals: 1. Sapphire substrate; 2. Undoped u-GaN layer; 3. n-AlGaN layer; 4. n-GaN layer; 5. Superlattice stress buffer layer; 6. Multi-quantum well active layer; 7. First electron blocking layer; 8. Second electron blocking layer; 9. p-GaN layer; 10. ITO layer; 11. Positive photoresist; 12. n-electrode hole; 13. Hard template; 14. Negative photoresist; 15. DBR layer; 16. Oxide layer; 17. First passivation layer; 18. Second passivation layer; 19. p-electrode hole; 20. n-electrode; 201. First connection end; 202. First bonding end; 21. p-electrode; 211. Second connection end; 212. Second bonding end. Detailed implementation manners
[0019] In the ranges disclosed in the present invention, the endpoints and any values are not limited to the exact ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values, they can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in the present invention.
[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the specific embodiments of the present invention and the accompanying drawings of the specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0021] Embodiment A preparation method of a Micro-LED chip with an isometric electrode includes the following steps, Step One: Epitaxial materials are sequentially grown on the sapphire substrate 1 to obtain as Figure 1The epitaxial wafer shown includes, from bottom to top, a sapphire substrate 1, an undoped u-GaN layer 2, an n-AlGaN layer 3, an n-GaN layer 4, a superlattice stress buffer layer 5, a multi-quantum well active layer 6, a first electron blocking layer 7, a second electron blocking layer 8, and a p-GaN layer 9; wherein the thicknesses are 200-300 μm, 3 μm, 30-100 nm, 1.8 μm, 70 nm, 91 nm, 5 nm, 106 nm, and 132 nm in sequence; the superlattice stress buffer layer 5 is composed of 10 periods of alternating stacked layers of 2 nm InGaN and 5 nm GaN, and the In component in the InGaN layer is 5%; in the multi-quantum well active layer 6, the thickness of the InGaN quantum well is 3 nm, the thickness of the GaN barrier is 10 nm, and there are 7 periods in total. By adjusting the In component, the emission of blue light and green light can be achieved; the materials of the first electron blocking layer 7 and the second electron blocking layer 8 are p-AlGaN, and the Al components are 30% and 15% respectively. As Figure 2 shown, the n-AlGaN layer 3 is located between the undoped u-GaN layer 2 and the n-GaN layer 4, and has a lower thickness.
[0022] Step two: As Figure 3 shown, indium tin oxide (ITO) with a thickness of 140 nm is evaporated on the top of the epitaxial wafer to form an ITO layer 10. Figure 3 In, the structures of the undoped u-GaN layer 2, the n-AlGaN layer 3, the superlattice stress buffer layer 5, the first electron blocking layer 7, and the second electron blocking layer 8 are simplified, and the subsequent Figures 4 - 14 is the same.
[0023] Step three: As Figure 4 shown, a positive photoresist 11 is spin-coated on the ITO layer 10 and the n-electrode region is exposed.
[0024] Step four: As Figure 5 shown, the ITO layer 10 in the exposed n-electrode region is etched using an ITO etchant, and the positive photoresist 11 is removed. Among them, the ITO etchant is an aqueous solution of hydrochloric acid and nitric acid; acetone is used to remove the residual positive photoresist 11.
[0025] Step five: As Figure 6 shown, mesa etching is performed, etching the p-GaN layer 9, the second electron blocking layer 8, the first electron blocking layer 7, the multi-quantum well active layer 6, and the superlattice stress buffer layer 5 in sequence until the n-GaN layer 4 is exposed, forming an n-electrode hole 12. The cross-section of the n-electrode hole 12 is similar to a frustum of a cone, and the bottom cross-section of the n-electrode hole 12 is a circle with a diameter larger than the depth of the n-electrode hole 12.
[0026] Step six: As Figure 7As shown, deposit SiO2 on the upper surface of the product obtained in Step Five as the hard mask 13 for subsequent ISO etching, and spin-coat a negative photoresist 14 on the SiO2 as the soft mask for ISO etching.
[0027] Step Seven: As Figure 8 shown, remove the structures not protected by the negative photoresist 14 through ISO etching and remove the negative photoresist 14; and remove the hard mask 13 with BOE solution.
[0028] Step Eight: As Figure 9 shown, deposit SiO2 with a thickness of 0.5 μm again on the upper surface of the product obtained in Step Seven as the protective layer, and deposit 7 layers of Ti3O5 / SiO2 material on the protective layer using ALD technology to form the DBR layer 15. The thickness of each layer of Ti3O5 / SiO2 material in the DBR layer 15 is determined by the chip emission wavelength, and the total thickness of the DBR layer 15 is 800 nm.
[0029] Step Nine: As Figure 10 shown, place the product obtained in Step Eight in an oxidation furnace and deposit an oxide layer 16 on the side by wet oxidation.
[0030] Step Ten: As Figure 11 shown, deposit 700 nm of Al2O3 material on the upper surface and side of the product obtained in Step Nine, and form the first passivation layer 17 and the second passivation layer 18 on the DBR layer 15 and the oxide layer 16 on the side respectively.
[0031] Step Eleven: As Figure 12 shown, spin-coat a positive photoresist on the first passivation layer to expose the n-electrode region and the p-electrode region, and through PV etching, expose the p-GaN layer 9 to obtain an epitaxial structure. The epitaxial structure has an n-electrode hole 12 reaching the n-GaN layer 4 and a p-electrode hole 19 reaching the p-GaN layer 9. Among them, the bottom cross-section of the p-electrode hole 19 is a circle with a diameter larger than that of the n-electrode hole 12, and the diameters of the bottom cross-sections of the n-electrode hole 12 and the p-electrode hole 19 are 5 μm and 10 μm respectively.
[0032] Step Twelve: As Figure 13 shown, remove the residual positive photoresist and etch the n-electrode hole 12 with BOE solution to remove the SiO2 and DBR material at the bottom of the n-electrode hole 12, exposing the n-GaN layer 4.
[0033] Step 13: Evaporate Cr / Al / Ti / Pt / Ti / Pt / Ti / Ni / Au with thicknesses of 5 / 120 / 100 / 50 / 100 / 50 / 100 / 1000 / 200 nm at evaporation rates of 0.1 / 1 / 2 / 2 / 2 / 2 / 2 / 5 / 5 Å / s in the p-electrode hole 19 and the n-electrode hole 12 respectively, to obtain the p-electrode 21 and the n-electrode 20 in the p-electrode hole 19 and the n-electrode hole 12 respectively, and obtain the Micro-LED chip with the isometric electrodes as shown in Figure 14 The n-electrode 20 includes a first connection end 201 connected to the n-GaN layer 4 and a first bonding end 202 located on the first passivation layer 17; the p-electrode 21 includes a second connection end 211 connected to the p-GaN layer 9 and a second bonding end 212 located on the first passivation layer 17, and the first bonding end 202 and the second bonding end 212 are at the same height.
[0034] In this embodiment, the total thickness of the epitaxial structure is about 5.27 μm, and the total thickness of the finally obtained Micro-LED chip is about 9 μm. Combining the evaporation of the p-electrode and the n-electrode into one step, the total number of photolithography steps is only 4 steps, specifically including MESA lithography, ISO lithography, PV lithography and pad lithography, reducing the complexity of the manufacturing process and improving the efficiency of Micro-LED chip manufacturing.
[0035] In this embodiment, the n-electrode and the p-electrode are respectively grown in the n-electrode hole and the p-electrode hole. The bottom cross-section of the n-electrode hole is a circle with a diameter larger than the depth of the n-electrode hole, and the diameter of the bottom cross-section of the p-electrode hole is larger than that of the n-electrode hole. Such a setting not only simplifies the preparation process of the electrodes, making the n-electrode and the p-electrode isometric, but also ensures that the n-electrode and the n-type material layer, and the p-electrode and the p-type material layer have a large contact area, which can reduce the difficulty of the bonding process, improve the uniformity of the current near the electrodes, optimize heat dissipation, and improve the service life of the Micro-LED chip.
[0036] Comparative Example 1 The existing blue and green Micro-LED chips, as shown in the figure, have a stepped epitaxial structure. The materials of each layer are basically the same as those in the embodiment. The total thickness of the epitaxial structure is about 5.27 μm. The n-electrode structure and the p-electrode structure are composed of electrodes and pads. The electrode material is Cr / Al / Ti / Pt / Ti / Pt / Au / Pt / Ti, and the thicknesses are 5 / 120 / 100 / 50 / 100 / 50 / 930 / 220 / 50 nm respectively; the pad material is Al / Ti / Pt / Ti / Ni / Au, and the thicknesses are 1600 / 100 / 200 / 50 / 1000 / 200 nm respectively. The total thickness of the chip is about 10.5 μm. The n-electrode structure and the p-electrode structure of this kind of Micro-LED chip will cause insecure welding, resulting in poor welding. In addition, the height difference causes poor contact between the chip and the substrate, affecting heat dissipation, which may cause local overheating and shorten the LED lifespan.
[0037] Comparative Example 2 It is basically the same as Example 1, and the difference is that: the bottom cross-section of the n-electrode hole is a circle with a diameter smaller than the depth of the n-electrode hole. The results show that too small an n-electrode diameter during chip preparation will reduce the contact area with the n-GaN layer, resulting in an increase in contact resistance; at the same time, insufficient contact area leads to uneven current distribution, causing local overheating and affecting the device lifespan; finally, too small an electrode diameter will reduce the mechanical strength and increase the difficulty of the bonding process, which may lead to poor connection and affect the electrical characteristics of the chip.
[0038] Finally, it should be noted that: the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A Micro-LED chip with an isometric electrode, characterized in that, It includes an epitaxial structure formed on a substrate and an electrode structure; The epitaxial structure includes, from bottom to top, a bonding layer, an n-type material layer, a multi-quantum well active layer, an electron blocking layer, a p-type material layer, and a transparent conductive layer. An n-electrode hole reaching the n-type material layer and a p-electrode hole reaching the p-type material layer are provided in the epitaxial structure. The bottom cross-section of the n-electrode hole is a circle with a diameter larger than the depth of the n-electrode hole; The electrode structure includes an n-electrode and a p-electrode respectively disposed in the n-electrode hole and the p-electrode hole. Among them, the n-electrode includes a first connection end and a first bonding end, and the p-electrode includes a second connection end and a second bonding end. The first bonding end and the second bonding end have the same height.
2. The Micro-LED chip with an isometric electrode according to claim 1, wherein The bottom cross-section of the p-electrode hole is a circle with a diameter larger than that of the n-electrode hole.
3. The Micro-LED chip with an isometric electrode according to claim 1, wherein, On the top of the transparent conductive layer and on the side wall of the n-electrode hole, a protective layer and a DBR layer are sequentially provided; The thickness of the protective layer is 0.4 - 0.6 μm; The thickness of the DBR layer is 0.7 - 1 μm.
4. The Micro-LED chip with an isometric electrode according to claim 3, characterized in that, A first passivation layer is further provided on the DBR layer; The thickness of the first passivation layer is 0.5 - 1 μm.
5. The Micro-LED chip with an isometric electrode according to claim 1, characterized in that, A superlattice stress buffer layer is further provided between the n-type material layer and the multi-quantum well active layer.
6. The Micro-LED chip with an isometric electrode according to claim 5, wherein, The thickness of the epitaxial structure is 5.0 - 5.5 μm.
7. The Micro-LED chip with an isometric electrode according to any one of claims 1-6, characterized in that, An oxide layer and a second passivation layer are sequentially provided on the side of the epitaxial structure.
8. A method for preparing a Micro-LED chip with an isometric electrode as described in any one of claims 1-7, characterized in that, including, Growing epitaxial material on the substrate and etching to obtain an epitaxial structure on the substrate; Growing electrode material in the n-electrode hole and the p-electrode hole of the epitaxial structure to obtain the n-electrode and the p-electrode.
9. The method for manufacturing a Micro-LED chip with an isometric electrode according to claim 8, wherein the electrode material includes at least one of Cr, Al, Ti, Pt, Ti, Ni, Au; The total thickness of the electrode material is 1.5 - 2 μm.
10. A display panel, characterized in that, A Micro-LED chip with an isometric electrode according to any one of claims 1 - 7.