Micro LED chip and pixel-level optical shaping coating method thereof

Abstract

The invention provides a Micro LED chip and a pixel-level optical shaping coating method thereof, and relates to the technical field of coating. The coating method comprises the following steps: forming a coating substrate, wherein the coating substrate comprises a light-emitting mesa array, a side wall dielectric layer located on the peripheral side of a light-emitting mesa, and a first top conductive layer covering the side wall dielectric layer and the light-emitting mesa; and the film coating substrate is plated with a film layer through inductively coupled plasma until a target film layer is formed on the film coating substrate. According to the pixel-level optical shaping coating method provided by the invention, internal holes of the micro LED chip surface film layer can be reduced or even eliminated, and after the micro lens on the micro LED chip surface is processed on the target film layer in the subsequent process, the appearance uniformity and brightness of the micro lens can be improved, the color difference abnormal phenomenon can be reduced, and the lens effect and brightness can be improved.

Description

Technical Field

[0001] The present application relates to the field of coating technology, and particularly to a Micro LED chip and its pixel-level optical shaping coating method. Background Art

[0002] Micro Light Emitting Diode, also known as MicroLED, is a display array technology composed of tiny LED light-emitting units. MicroLED pixel-level optics are widely used in devices such as display screens and smart products.

[0003] When coating a MicroLED pixel-level optical Micro LED chip conventionally, the plasma-enhanced chemical vapor deposition (PECVD) process is usually utilized. Specifically, the coating operation is completed by a PECVD machine tool, and this coating operation includes depositing a film layer on the pixel points of the Micro LED chip.

[0004] However, for the film layer formed by the above coating process, its surface is prone to be uneven, and voids are likely to appear inside the film layer, resulting in abnormal device appearance and poor coverage of pixel points, causing brightness loss. Summary of the Invention

[0005] The present application provides a Micro LED chip and its pixel-level optical shaping coating method, where the surface of the formed film layer is flatter, internal voids can be reduced, which is beneficial to enhancing the coating integrity of pixel points and improving display brightness.

[0006] In a first aspect, the present application provides a Micro LED chip, including: a light-emitting mesa array including a plurality of light-emitting mesas arranged in an array; a sidewall dielectric layer covering at least the sidewalls of each of the light-emitting mesas, with at least part of the area on top of the light-emitting mesa exposed; a first top conductive layer covering the sidewall dielectric layer and the exposed area on top of the light-emitting mesa; a microlens array including a plurality of microlenses covering the first top conductive layer, wherein there are no pores inside each of the microlenses.

[0007] In some embodiments, the internal material of the microlens is continuous.

[0008] In some embodiments, the microlens array further includes a spacer layer covering the first top conductive layer; the microlenses are located on part of the spacer layer.

[0009] In some embodiments, the microlens and the spacer layer are of an integral structure.

[0010] In some embodiments, there are no pores inside the spacer layer below the microlens.

[0011] In some embodiments, the diameter of the microlens is not greater than 20 microns, and the width of the light-emitting mesa is not greater than 20 microns.

[0012] In some embodiments, the first top conductive layer between the light-emitting mesas is continuous; the sidewall dielectric layer between the light-emitting mesas is continuous.

[0013] In some embodiments, a pixel driving layer and a conductive contact structure located on the pixel driving layer are further provided at the bottom of the light-emitting mesa; the bottom of the light-emitting mesa is electrically connected to the conductive contact structure.

[0014] In some embodiments, each light-emitting mesa in the light-emitting mesa array can be independently controlled; each light-emitting mesa includes, from bottom to top in sequence: a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer; the conductive types of the first-type semiconductor layer and the second-type semiconductor layer are different, the light-emitting layer includes a plurality of stacked layers; a second top conductive layer is further provided between the top of the second-type semiconductor layer and the first top conductive layer; a bottom conductive layer is further provided between the bottom of the first-type semiconductor layer and the conductive contact structure.

[0015] In a second aspect, the present application provides a pixel-level optical shaping coating method for a Micro LED chip, which is used to prepare the above-mentioned Micro LED chip, and includes the following steps:

[0016] Form a coating substrate, the coating substrate includes: a light-emitting mesa array, a sidewall dielectric layer located on the periphery of the light-emitting mesa, and a first top conductive layer covering the sidewall dielectric layer and the light-emitting mesa;

[0017] Use inductively coupled plasma to coat a film layer on the coating substrate until a target film layer is formed on the coating substrate.

[0018] In some embodiments, the coating method further includes: etching the film layer using inductively coupled plasma.

[0019] In some embodiments, the coating method further includes: alternately performing coating a film layer on the coating substrate using inductively coupled plasma and etching the film layer using inductively coupled plasma until the target film layer is formed.

[0020] In a possible implementation manner, the coating a film layer on the coating substrate using inductively coupled plasma includes: filling a reaction gas into the coating chamber, the reaction gas includes SiH4, N20 or NH3; applying a high-frequency magnetic field to the reaction gas through an induction electrode to generate coating plasma.

[0021] In a possible implementation, etching the film layer using inductively coupled plasma includes: evacuating the reaction gas in the coating chamber; filling the coating chamber with a first etching gas; and applying a high-frequency magnetic field to the first etching gas through an induction electrode to generate etching plasma.

[0022] In some embodiments, the material of the first etching gas includes CF4.

[0023] In a possible implementation, depositing a film layer on a coating substrate using inductively coupled plasma further includes: filling the coating chamber with a second etching gas, and the volume flow rate of the second etching gas is less than that of the reaction gas; generating etching plasma by acting on the second etching gas through an induction electrode, so that the coating plasma and the etching plasma act on the coating substrate synchronously.

[0024] In some embodiments, the material of the second etching gas includes noble gases.

[0025] In a possible implementation, the first etching gas and the second etching gas are of different types.

[0026] In a possible implementation, when depositing a film layer on a coating substrate using inductively coupled plasma, the temperature in the coating chamber is 240°C - 300°C; and / or,

[0027] the deposition rate of the film layer is 6 Å / s - 9 Å / s; and / or,

[0028] the deposition time of the film layer is 1000 s - 2000 s; and / or,

[0029] the etching acceleration power is 80 W - 120 W; and / or,

[0030] the ionization power is 100 W - 500 W.

[0031] In a possible implementation, when etching the film layer using inductively coupled plasma, the temperature in the coating chamber is 240°C - 300°C; and / or,

[0032] the etching rate of the film layer is 8 Å / s - 9 Å / s; and / or,

[0033] the etching time of the film layer is 500 s - 800 s.

[0034] In a possible implementation, the process of depositing a film layer on a coating substrate using inductively coupled plasma is performed at least twice. Among the at least two times, when performing the process of depositing a film layer on the coating substrate using inductively coupled plasma for the second time, the etching acceleration power is greater than that when performing the process of depositing a film layer on the coating substrate using inductively coupled plasma for the first time.

[0035] In a possible implementation, the process of depositing a film layer on a coating substrate using inductively coupled plasma is performed at least twice. Among the at least two times, when performing the process of depositing a film layer on the coating substrate using inductively coupled plasma for the second time, the etching amount is greater than that when performing the process of depositing a film layer on the coating substrate using inductively coupled plasma for the first time.

[0036] The Micro LED chip and its pixel-level optical shaping coating method provided by this application effectively solve the problems of voids and uneven film layer surfaces that are prone to occur in the traditional PECVD process through the ICPCVD process, improve the film layer quality. After processing the target film layer in subsequent processes to form microlenses on the surface of the Micro LED chip, the uniformity and brightness of the appearance of the microlenses can be improved, the abnormal color difference of the microlenses can be reduced, and the lens effect and brightness can be enhanced. In addition, this design also makes the film layer deposition and etching processes more uniform and controllable, thereby improving the overall quality of the film layer, obtaining a more flat coating interface, and reducing abnormalities such as glue dropping in subsequent processes. Moreover, depositing and etching are alternately performed in the ICPCVD equipment, avoiding the waste of time and cost that may be brought about by multiple transfers of the coating substrate, improving production efficiency. This method can also flexibly adjust the coating and etching parameters according to the pixel-level optical display requirements of different MicroLED chips, and thus achieve customized production. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0038] Figure 1 Schematic diagram of the steps for forming a substrate in the pixel-level optical shaping coating method of the embodiment of this application;

[0039] Figure 2 Schematic diagram of the steps for forming a light-emitting mesa in the pixel-level optical shaping coating method of the embodiment of this application;

[0040] Figure 3 Schematic diagram of the steps for forming a sidewall dielectric layer in the pixel-level optical shaping coating method of the embodiment of this application;

[0041] Figure 4 Schematic diagram of the steps for forming a second top conductive layer in the pixel-level optical shaping coating method of the embodiment of this application;

[0042] Figure 5 Schematic diagram of the step of forming the first top conductive layer in the pixel-level optical shaping coating method according to the embodiment of the present application;

[0043] Figure 6 Schematic diagram of the step of depositing the target film layer by using an inductively coupled plasma process in the pixel-level optical shaping coating method according to the embodiment of the present application;

[0044] Figure 7 Schematic diagram of the structure of the Micro LED chip according to some embodiments provided by the present application;

[0045] Figure 8 Schematic diagram of the structure of the Micro LED chip according to some other embodiments provided by the present application;

[0046] Figure 9 Schematic diagram of the process flow of the pixel-level optical shaping coating method provided by the present application;

[0047] Figure 10 Schematic diagram of the target film layer formed when coating by using the PECVD process in the prior art.

[0048] Reference numerals:

[0049] 100 - coating substrate; 1 - substrate;

[0050] 10 - first bonding wafer; 20 - second bonding wafer;

[0051] 101 - first substrate; 102 - bottom conductive layer; 103 - epitaxial layer; 1031 - light-emitting mesa;

[0052] 1032 - first type semiconductor layer; 1033 - light-emitting layer; 1034 - second type semiconductor layer;

[0053] 104 - first bonding layer;

[0054] 201 - pixel driving layer; 202 - second bonding layer;

[0055] 30 - conductive contact structure; 40 - sidewall dielectric layer; 50 - first top conductive layer;

[0056] 60 - second top conductive layer;

[0057] 200 - target film layer; 210 - microlens; 220 - spacer layer.

[0058] Through the above-mentioned accompanying drawings, specific embodiments of the present application have been shown, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by reference to specific embodiments. Detailed Description of the Invention

[0059] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0060] A micro light-emitting diode, also known as a Micro LED, is a display array technology composed of tiny LED light-emitting units.

[0061] The Micro LED chip includes a pixel structure. Each sub-pixel in the pixel structure of the Micro LED is individually controlled. The color Micro LED is composed of red, green, and blue sub-pixels. In this way, the Micro LED can precisely control the display brightness, color, and contrast. Since the pixel pitch of the Micro LED is small, a high resolution can be achieved, thereby presenting a delicate and clear image.

[0062] In addition, the Micro LED chip has the characteristics of high brightness, high contrast, and high color saturation. Its brightness can reach 10 times that of OLEDs, making it suitable for high-brightness environments such as outdoors. Moreover, each pixel point can emit light independently, enabling a high contrast and showing a good display effect. The Micro LED chip of the present application can be applied to devices such as display screens and smart products, and can also be applied to fields such as medical treatment and communication.

[0063] It can be understood that coating the Micro LED chip can further improve its display effect, enhance its durability and stability, and optimize its optical performance.

[0064] The plasma-enhanced chemical vapor deposition (PECVD, hereinafter simply referred to as PECVD) process is widely used in the filling of insulating dielectrics in various microelectronic device processes. Therefore, when coating the Micro LED chip conventionally, the PECVD process is usually used. Specifically, the coating operation is completed through a PECVD machine tool, and this coating operation includes depositing a film layer on the pixel points of the Micro LED chip.

[0065] However, during the process of depositing the film layer, referring to Figure 10As shown, during the film coating process and after the target film layer is formed, voids are likely to appear in the bottom region of the film layer, and the surface of the film layer is uneven, resulting in abnormal appearance of the device, poor coverage of pixel points, and brightness loss.

[0066] In view of this, the present application provides a Micro LED chip and its pixel-level optical shaping film coating method. Through the Inductively Coupled Plasma Chemical Vapor Deposition (ICPCVD) process, the problem of voids that are likely to appear in the traditional PECVD process is effectively solved. A flatter film coating interface can be obtained, the film layer quality is improved, the uniformity and brightness of the appearance of the Micro LED chip are enhanced, the abnormal color difference phenomenon is reduced, and the lens effect and brightness are also enhanced.

[0067] The following combines Figures 1 - 10 to describe the Micro LED chip according to the first aspect embodiment of the present application.

[0068] Referring to Figure 7 and Figure 8 , the Micro LED chip of this embodiment may include: a light-emitting mesa array, a sidewall dielectric layer 40, a first top conductive layer 50, and a microlens array.

[0069] Specifically, the light-emitting mesa array may include a plurality of light-emitting mesas 1031 for emitting light. The light-emitting mesa 1031 may be a frustum structure, a square platform structure, a cylindrical structure, or other shapes. Each light-emitting mesa 1031 constitutes a MicroLED structure, that is, the light-emitting mesa 1031 constitutes the smallest light-emitting structure on the Micro LED chip. Exemplarily, the plurality of light-emitting mesas 1031 may be arranged in a square array, a circular array, a ring array, or other arrays. The present application does not limit this, and the array manner of the plurality of light-emitting mesas 1031 can be flexibly set according to actual needs.

[0070] The sidewall dielectric layer 40 covers at least the sidewalls of each light-emitting mesa 1031, and at least part of the region on the top of the light-emitting mesa 1031 is exposed. That is to say, the sidewall dielectric layer 40 may only cover the sidewalls of the light-emitting mesa 1031 to completely expose the top wall of the light-emitting mesa 1031; or, in addition to covering the sidewalls of the light-emitting mesa 1031, the sidewall dielectric layer 40 also covers a part of the top wall of the light-emitting mesa 1031 and exposes another part of the top wall.

[0071] In this way, the exposed portion at the top of the light-emitting mesa 1031 can be used for power connection to achieve light emission. Understandably, the sidewall dielectric layer 40 can play a role in protecting the light-emitting mesa 1031 and improving its working stability and reliability. In addition, the sidewall dielectric layer 40 can guide light to emit from the exposed area at the top of the light-emitting mesa 1031 to further improve the light-emitting brightness.

[0072] The first top conductive layer 50 covers the sidewall dielectric layer 40 and the exposed area at the top of the light-emitting mesa 1031. In this way, the first top conductive layer 50 can be in conductive contact with the light-emitting mesa 1031, thereby supplying power for the light emission of the light-emitting mesa 1031. Optionally, the first top conductive layer 50 can be a transparent metal layer. For example, the first transparent conductive layer can be ITO (indium tin oxide), fluorine-doped tin oxide (FTO), zinc oxide (ZnO), etc., to improve the conductive performance and light extraction effect. Of course, the present application is not limited thereto, and the first top conductive layer 50 can also be made of other suitable materials.

[0073] The microlens array can include a plurality of microlenses 210. The plurality of microlenses 210 can cover the first top conductive layer 50, that is, the microlens array is located on the top of the first top conductive layer 50, and the microlens array can form the surface layer structure of the Micro LED chip to ensure the light-emitting effect. Among them, there are no pores inside each microlens 210. Here, the pores refer to structures such as cavities and cracks (as Figure 9 shown), that is, the inside of the microlens 210 is a continuous and dense structure. The microlens 210 can guide light for the light-emitting mesa 1031 and improve the light-emitting effect of the light-emitting mesa 1031. There are no voids inside the microlens 210, which is beneficial to improving the light-emitting brightness, thereby improving the display brightness of the Micro LED chip. The microlens array can be formed by etching the film layer on the surface of the Micro LED chip, and the surface film layer can be formed by coating and etching using inductively coupled plasma in the following embodiments.

[0074] In the Micro LED chip according to the embodiment of the present application, by covering the microlens array on the first top conductive layer 50 and there are no pores inside the microlens 210, the display effect of the Micro LED chip can be improved.

[0075] Combined with Figure 7 、 Figure 8 and Figure 10, in some embodiments, the internal material of the microlens 210 is continuous. For example, when forming the film layer for fabricating the microlens 210, by making the film layer have good internal continuity, density, and surface flatness, in this way, when etching the film layer to form the microlens 210, voids and cracks inside the microlens 210 can be reduced or even eliminated, so that the color inside the microlens 210 is uniform, and the luminous brightness and display effect are improved.

[0076] Combined with Figures 6 - 8 , in some embodiments, the microlens array may further include a spacer layer 220. The spacer layer 220 can cover the first top conductive layer 50, and the microlens 210 is located on a part of the spacer layer 220. For example, the microlens 210 can be formed by removing a part of the redundant material of the spacer layer 220, and the removal method can be etching.

[0077] Combined with Figures 6 - 8 , in some embodiments, the microlens 210 and the spacer layer 220 are an integral structure. That is to say, the microlens 210 can be formed by etching the spacer layer 220. Here, the spacer layer 220 is the film layer on the surface of the above-mentioned MicroLED chip. For example, a part of the structure of the spacer layer 220 along the thickness direction can be etched to form the microlens 210, and the other part can cover the first top conductive layer 50, so as to isolate external water vapor for the first top conductive layer 50, and play an anti-corrosion and insulation role. By setting the microlens 210 and the spacer layer 220 as an integral structure, that is, the microlens 210 and the spacer layer 220 are the same structural layer, compared with fabricating the microlens 210 and the spacer layer 220 separately, it is beneficial to simplify the overall preparation process of the Micro LED chip, and is beneficial to shortening the light conduction path, thereby improving the light transmittance and the luminous brightness.

[0078] In some embodiments, combined with Figures 6 - 8 and Figure 10 , there are no pores inside the spacer layer 220 under the microlens 210. Here, the pores refer to structures such as voids and cracks (such as Figure 10 the voids in), that is, the inside of the spacer layer 220 is a continuous and dense structure. Optionally, inductively coupled plasma can be used for coating and etching to form the spacer layer 220. In this way, there can be no pores inside the spacer layer 220, which is beneficial to improving the light transmittance of the spacer layer 220, thereby improving its luminous brightness.

[0079] In some embodiments, the diameter of the microlens 210 is not greater than 20 microns. Thus, the diameter of a single microlens 210 is small, occupying a small area. When the surface area of the Micro LED chip is fixed, more microlenses 210 can be arranged, so that the overall light emission brightness of the Micro LED chip is relatively uniform, which is beneficial to improving the display effect.

[0080] In some embodiments, the width of the light-emitting mesa 1031 is not greater than 20 microns. It should be noted that the width of the light-emitting mesa 1031 refers to the size of the top wall of the light-emitting mesa 1031. When the top wall of the light-emitting mesa 1031 is a square structure, the width of the light-emitting mesa 1031 refers to the side length of the square; or, when the light-emitting mesa 1031 is a frustum structure or a cylindrical structure, the width of the light-emitting mesa 1031 refers to the diameter of the top wall of the light-emitting mesa 1031. Thus, when the surface area of the Micro LED chip is fixed, more light-emitting mesas 1031 can be arranged, so that the overall light emission brightness of the Micro LED chip is relatively uniform, which is beneficial to improving the display effect.

[0081] Optionally, the width of the light-emitting mesa 1031 can be the same as the diameter of the microlens 210; or, the width of the light-emitting mesa 1031 can be slightly larger than the diameter of the microlens 210; or, the width of the light-emitting mesa 1031 can be slightly smaller than the diameter of the microlens 210. The width of the light-emitting mesa 1031 and the diameter of the microlens 210 are close, so that the microlens 210 can be arranged opposite to the exposed area at the top of the light-emitting mesa 1031, and the microlens 210 and the light-emitting mesa 1031 can be arranged in one-to-one correspondence.

[0082] In some embodiments, the first top conductive layer 50 between the light-emitting mesas 1031 is continuous. Thus, the first top conductive layer 50 can be used to conduct electricity for the multiple light-emitting mesas 1031 of the light-emitting mesa array.

[0083] In some embodiments, the sidewall dielectric layer 40 between the light-emitting mesas 1031 is continuous. Thus, the sidewall dielectric layer 40 can better protect the periphery of the light-emitting mesa 1031 and guide the light to emit from the exposed area at the top.

[0084] In some embodiments, in combination with Figures 1 - 7, a pixel driving layer 201 and a conductive contact structure 30 located on the pixel driving layer 201 are further provided at the bottom of the light-emitting mesa 1031. Among them, the pixel driving layer 201 is the driving backplane, and the driving backplane can be a thin film transistor (TFT) board or an integrated circuit (IC) board. Among them, the pixel driving layer 201 can be electrically connected to the light-emitting mesa 1031. The pixel driving layer 201 can obtain signals such as image data from the outside and control the corresponding light-emitting mesa 1031 to emit light or not. The bottom of the light-emitting mesa 1031 is electrically connected to the conductive contact structure 30, so that the light-emitting mesa 1031 is connected to the pixel driving layer 201 through the conductive contact structure 30. The conductive contact structure 30 can be a bonding metal layer jointly formed after the first bonding layer 104 and the second bonding layer 202 are bonded together.

[0085] In some embodiments, each light-emitting mesa 1031 in the light-emitting mesa array can be independently controlled. For example, the pixel driving layer 201 can be electrically connected to each light-emitting mesa 1031 of the light-emitting mesa array through separate metal interconnections, so as to realize independent control of each light-emitting mesa 1031 to emit light.

[0086] Reference Figure 8 , each light-emitting mesa 1031 includes, from bottom to top in sequence: a first-type semiconductor layer 1032, a light-emitting layer 1033, and a second-type semiconductor layer 1034. The conductive types of the first-type semiconductor layer 1032 and the second-type semiconductor layer 1034 are different. For example, the first-type semiconductor layer 1032 can be an N-type semiconductor layer, and the second-type semiconductor layer 1034 can be a P-type semiconductor layer; or, the first-type semiconductor layer 1032 can be a P-type semiconductor layer, and the second-type semiconductor layer 1034 is an N-type semiconductor layer. Exemplarily, taking the conductive type of the first-type semiconductor layer 1032 as P-type and the conductive type of the second-type semiconductor layer 1034 as N-type as an example, the material of the first-type semiconductor layer 1032 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second-type semiconductor layer 1034 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0087] The light-emitting layer 1033 includes multiple stacked layers. For example, the multiple stacked layers can be multiple quantum well layers; alternatively, the multiple stacked layers can include one or more of the following: a first confinement layer, a quantum well layer, and a second confinement layer; still alternatively, the multiple stacked layers can also include other appropriate layers, such as a sacrificial layer, a buffer layer, etc. The embodiments of the present application do not limit the specific structure of the light-emitting layer 1033.

[0088] Reference Figure 6 , there is also a second top conductive layer 60 between the top of the second-type semiconductor layer 1034 and the first top conductive layer 50. The second top conductive layer 60 has the same conductivity type as the second-type semiconductor layer 1034 to form a good ohmic contact between the second-type semiconductor layer 1034 and the first top conductive layer 50. For example, when the conductivity type of the second-type semiconductor layer 1034 is N-type, the conductivity type of the second top conductive layer 60 is also N-type, and when the conductivity type of the second-type semiconductor layer 1034 is P-type, the conductivity type of the second top conductive layer 60 is also P-type.

[0089] There is also a bottom conductive layer 102 between the bottom of the first-type semiconductor layer 1032 and the conductive contact structure 30. Optionally, the bottom conductive layer 102 can be used to form a good ohmic contact between the first-type semiconductor layer 1032 and the conductive contact structure 30. At this time, the conductivity type of the bottom conductive layer 102 can be the same as the conductivity type of the first-type semiconductor layer 1032. For example, when the conductivity type of the first-type semiconductor layer 1032 is N-type, the conductivity type of the bottom conductive layer 102 is also N-type, and when the conductivity type of the first-type semiconductor layer 1032 is P-type, the conductivity type of the bottom conductive layer 102 is also P-type.

[0090] Optionally, the bottom conductive layer 102 can also include multiple metal layers. In addition to the ohmic contact layer used to make the bottom of the first-type semiconductor layer 1032 and the conductive contact structure 30 form a good ohmic contact, the multiple metal layers can also include a reflective layer, a bonding layer, etc.

[0091] Next, in conjunction with Figures 1 to 9 Describe the pixel-level optical shaping coating method of the Micro LED chip in the second aspect embodiment of the present application. The pixel-level optical shaping coating method of this embodiment can be applied to the coating of the surface film layer of the Micro LED chip in the above embodiment (that is, the film layer where the microlens 210 is located, such as the spacer layer 220, that is, the target film layer 200 below).

[0092] The Micro LED pixel-level optical shaping coating method of the embodiments of the present application can apply the inductively coupled plasma chemical vapor deposition (ICPCVD, hereinafter simply referred to as ICPCVD) process and use an ICPCVD device.

[0093] Reference Figure 6 , the Micro LED pixel-level optical shaping coating method of this embodiment includes the following steps:

[0094] S1. Form a coating substrate 100, and the coating substrate 100 includes: a light-emitting mesa array, a sidewall dielectric layer 40 located on the periphery of the light-emitting mesa 1031, and a first top conductive layer 50 covering the sidewall dielectric layer 40 and the light-emitting mesa 1031;

[0095] S2. Use inductively coupled plasma to coat the coating substrate 100 with a film layer until a target film layer 200 is formed on the coating substrate 100.

[0096] Reference Figure 5 , clean and pre-treat the coating substrate 100 to ensure that the surface is clean and free of impurities, laying a foundation for the subsequent coating process. Subsequently, place the pre-treated coating substrate 100 in the coating chamber of the ICPCVD equipment, and start coating the film layer by adjusting parameters such as the type, flow rate, pressure of the reaction gas, and the power of the inductively coupled plasma. Here, the reaction gas is the raw material gas used to form the film layer, and the type of the reaction gas can be selected according to the function to be achieved by the film layer. It can be understood that the film layer here is the film layer used to form the microlens array in the above embodiment, that is, the spacer layer 220 above. The film layer constitutes the surface film layer of the Micro LED chip, can be used to prepare a microlens array, and plays a role in improving the light-emitting effect of the light-emitting mesa 1031 and enhancing the display brightness of the Micro LED chip.

[0097] It should be noted that during the actual operation process, the reaction temperature, time, coating rate, etc. need to be controlled to ensure the uniformity and density of the film layer.

[0098] The coating method of the embodiment of the present application uses the ICPCVD process and uses inductively coupled plasma to coat the coating substrate 100. Since the density of the plasma generated by the inductively coupled method is relatively high, the density of the film layer formed on the coating substrate 100 is better. Therefore, it is beneficial to reduce or even eliminate the voids inside the film layer and improve the surface flatness of the formed film layer, thereby effectively solving the film layer quality problems that easily occur in the traditional PECVD process. After processing the film layer to form microlenses, the uniformity and brightness of the appearance of the microlenses on the surface of the Micro LED chip can be improved, the abnormal color difference phenomenon is reduced, and the lens effect and brightness are also improved. In addition, this design also makes the deposition and etching processes of the film layer more uniform and controllable, thereby improving the overall quality of the film layer, obtaining a more flat coating interface, and reducing abnormalities such as glue dropping in the subsequent process.

[0099] Further, forming the coated substrate 100, i.e., step S1, may include the following steps:

[0100] S101, forming the substrate 1, the substrate 1 including a pixel driving layer 201, a conductive contact structure 30, a bottom conductive layer 102, and an epitaxial layer 103;

[0101] Reference Figure 1 , after bonding the first surface of the first bonding wafer 10 to the first surface of the second bonding wafer 20, removing the first substrate 101 of the first bonding wafer 10 to obtain the substrate 1,

[0102] Wherein, the first bonding wafer 10 may include one or more of the following from the second surface to the first surface: a first substrate 101, a bottom conductive layer 102, an epitaxial layer 103, and a first bonding layer 104. The second bonding wafer 20 may include one or more of the following from the second surface to the first surface: a second substrate, a second bonding layer 202. The second surface of the first bonding wafer 10 is the side away from the second bonding wafer 20, and the second surface of the second bonding wafer 20 is the side away from the first bonding wafer 10.

[0103] Wherein, after bonding and connecting the first bonding layer 104 and the second bonding layer 202, removing the first substrate 101 of the first bonding wafer 10 to obtain the substrate 1 (which can also be referred to as the intermediate structure of the unfinished substrate 1 at this time), and, exposing the second surface of the epitaxial layer 103. The second surface of the epitaxial layer 103 is the surface of the epitaxial layer 103 away from the first bonding layer 104,

[0104] The epitaxial layer 103 may include one or more of the following: a first confinement layer, a quantum well layer, a second confinement layer. The epitaxial layer 103 may further include other appropriate layers, such as a sacrificial layer, a buffer layer, etc., and the embodiments of the present application do not limit the specific structure of the epitaxial layer 103.

[0105] The bottom conductive layer 102 may be an ITO (indium tin oxide) layer to improve the conductivity and light extraction effect, and may also include other appropriate materials, such as fluorine-doped tin oxide (FTO), zinc oxide (ZnO).

[0106] The first substrate 101 may include, for example, a sapphire substrate, etc., and its composition may include aluminum oxide (AlO), or, the first substrate 101 may include a substrate of other appropriate materials, such as a semiconductor substrate, for example, a silicon substrate, and the material of the semiconductor substrate may also include germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate on which an epitaxial layer 103 (Epitaxy layer, Epi layer) is grown.

[0107] The second substrate may adopt the pixel driving layer 201. For example, the pixel driving layer 201 may be a thin film transistor (TFT) board or an integrated circuit (IC) board. Among them, the pixel driving layer 201 may be electrically connected to the micro LEDs in the pixel array of the micro LEDs. The pixel driving layer 201 can obtain signals such as image data from the outside world and can control the corresponding micro LEDs to emit light or not emit light.

[0108] The material of the first bonding layer 104 and / or the second bonding layer 202 may include: a metal bonding material to improve the bonding material. After the first bonding layer 104 and the second bonding layer 202 are bonded, they together form a conductive contact structure 30.

[0109] S102, etching the epitaxial layer 103 to form a light-emitting mesa 1031;

[0110] Reference Figure 2 , by performing photolithography or etching on the epitaxial layer 103 to form a light-emitting mesa 1031 (i.e., Micro LED).

[0111] S103, forming a sidewall dielectric layer 40 on the periphery of the light-emitting mesa 1031;

[0112] Reference Figure 3 , in the process of forming the sidewall dielectric layer 40, a sidewall dielectric layer material covering the bottom conductive layer 102 and the light-emitting mesa 1031 may be formed first, and then the sidewall dielectric layer material on the top surface of each light-emitting mesa 1031 is removed to form a sidewall dielectric layer 40 covering the area between adjacent light-emitting mesas 1031 and the peripheral wall of the light-emitting mesa 1031. Specifically, the sidewall dielectric layer material can be removed through a photolithography process and an etching process, and other appropriate process steps can also be adopted. The embodiments of the present application do not limit the specific process for removing the redundant sidewall dielectric layer material.

[0113] S104, forming a first top conductive layer 50 covering the light-emitting mesa 1031 on the sidewall dielectric layer 40 to obtain a coated substrate 100;

[0114] Reference Figure 4 , then forming a first top conductive layer 50 on the top of the sidewall dielectric layer 40 and the light-emitting mesa 1031. The first top conductive layer 50 may be an ITO (indium tin oxide) layer to improve the conductivity and light extraction effect, and may also include other appropriate materials, such as fluorine-doped tin oxide (FTO), zinc oxide (ZnO). In this way, the coated substrate 100 required for the coating process can be obtained. The coated substrate 100 can be used as the deposition basis for the target film layer 200.

[0115] Optionally, after the above step S103 and before S104, forming the coated substrate 100 may further include the following steps: forming a second top conductive layer 60 on the exposed area at the top of the light-emitting mesa 1031. The second top conductive layer 60 can be used as an ohmic contact layer. Based on this, performing step S104 can form a good ohmic contact between the first top conductive layer 50 and the light-emitting mesa 1031.

[0116] In some embodiments, the coating method further includes the following step: S3, etching the film layer using inductively coupled plasma.

[0117] After the film layer is deposited in step S2, the etching treatment is directly performed in an ICPCVD device. Specifically, by adjusting parameters such as the type and flow rate of the etching gas and the power of the plasma, the etching and shaping of the film layer formed in step S2 can be realized to remove the uneven parts and voids on the surface of the film layer, so as to achieve the preset film layer morphology and structure.

[0118] In this way, using inductively coupled plasma to etch the film layer formed in the previous step can improve the surface flatness of the formed film layer, reduce or even eliminate the voids inside the film layer, and improve the film layer quality.

[0119] In some embodiments, the coating method further includes the following steps: alternately performing depositing a film layer on the coated substrate 100 using inductively coupled plasma and etching the film layer using inductively coupled plasma until the target film layer 200 is formed.

[0120] Specifically, according to the thickness and structure requirements of the target film layer 200, the above depositing and etching steps are alternately performed, and then finally the target film layer 200 that meets the expectations is formed on the coated substrate 100.

[0121] It should be noted that during the actual operation process, during each alternation process, the coating rate, etching rate, and film layer quality need to be monitored and adjusted in real time to ensure that the finally formed film layer meets the design requirements. It can be understood that during each execution of the etching step, the uneven positions and voids on the film layer formed in the previous step can be removed, thereby providing a good adhesion interface for the film layer deposited in the next coating step.

[0122] Optionally, after the target film layer 200 is formed, the target film layer 200 can be detected, which may include the thickness, uniformity, density, optical properties, and electrical properties of the film layer, etc., to ensure that it meets the usage requirements of the Micro LED chip.

[0123] Combined with Figures 6 - 9, The coating method of the embodiment of the present application adopts the ICPCVD process and uses inductively coupled plasma for alternating coating and etching, which can improve the surface flatness of the formed film layer, reduce or even eliminate the voids inside the film layer, thus effectively solving the film layer quality problems prone to occur in the traditional PECVD process, improving the uniformity and brightness of the appearance of Micro LED chips, reducing the abnormal color difference phenomenon, and also improving the lens effect and brightness. In addition, this design also makes the deposition and etching processes of the film layer more uniform and controllable, thereby improving the overall quality of the film layer, obtaining a more flat coating interface, and reducing abnormalities such as glue dropping in subsequent processes.

[0124] In addition, by alternately performing deposition and etching in the ICPCVD equipment, the time and cost waste that may be brought about by multiple transfers of the coating substrate 100 are avoided, and the production efficiency is improved. This method can also flexibly adjust the coating and etching parameters according to the display quality requirements of different Micro LED chips, and then realize customized production.

[0125] In some actual tests, by adopting the ICPCVD process, the processing temperature is 200 °C and the processing time is 2 hours per piece. When using the traditional PECVD process, the processing temperature needs to reach 260 °C and the processing time is 20 minutes per piece.

[0126] According to the actual test results, compared with the traditional PECVD process, the processing temperature is reduced and the processing time is extended when using the ICPCVD process in this solution. The plasma generated by inductive coupling in ICPCVD has a higher energy density and better energy transfer efficiency. Under the same conditions, the required input power is lower, thus reducing the processing temperature. In addition, the longer processing time of the ICPCVD process ensures the full progress of chemical reactions and the uniform deposition of the film layer, which helps to reduce defects and contaminants in the film layer and improve the performance and stability of the film layer.

[0127] In addition, in some actual tests, combined with Figures 6 to 9 As shown, in the Micro LED pixel-level optical shaping coating method provided by the present application, there are no voids in the film layer during the coating process and after the target film layer 200 is formed, and the filling is good.

[0128] In some examples, combined with Figure 10 , during the coating process of the PECVD process, the film thickness is 2.57 um and the diameter is 4.08 um, and there are voids. After the target film layer 200 is formed, the film thickness is 2.77 um and the diameter is 3.98 um, and the voids still exist.

[0129] While referring to Figures 6 - 8, during the coating process of the pixel-level optical shaping coating method for the Micro LED chip of the present application, the film thickness is 2.72 um, the diameter is 3.91 um, the filling is good, the film layer filling is good. After forming the target film layer 200, the film thickness is 2.76 um, the diameter is 4.32 um, and the film layer is still filled well.

[0130] Through comparative analysis, it is found that the ICPCVD process used in the pixel-level optical shaping coating method of the present application is superior to the traditional PECVD process in terms of film layer density and uniformity, significantly improving the overall performance of the Micro LED chip.

[0131] In some embodiments, an inductively coupled plasma is used to deposit a film layer on the coating substrate 100, including: filling the coating chamber with a reaction gas, where the reaction gas includes SiH4, N20 or NH3; applying a high-frequency magnetic field to the reaction gas through an induction electrode to generate coating plasma.

[0132] Optionally, the power of the induction electrode can be 50 W - 100W. Exemplarily, the power of the induction electrode can be 50W, 70W, 80W, 100W, etc.

[0133] Specifically, an appropriate amount of reaction gas is filled into the coating chamber. The reaction gas can include SiH4 (silane) and N2O (dinitrogen monoxide). These two gases will undergo a chemical reaction in the plasma environment to generate the required film layer. Here, the film layer is a silicon dioxide film. Optionally, when an SiN film layer needs to be generated, N2O can be replaced with NH3 (ammonia).

[0134] It should be noted that during the actual operation process, when filling the gas, it is necessary to control the flow rate and pressure of the gas to ensure the stability and controllability of the coating process.

[0135] Subsequently, a high-frequency magnetic field is applied to the reaction gas through the induction electrode, and the high-frequency magnetic field will excite gas molecules to form plasma.

[0136] Specifically, the high-energy electrons in the plasma will collide with the reaction gas molecules and further react to generate silicon dioxide and deposit on the surface of the coating substrate 100. When the coating reaches the preset thickness or time, the application of the high-frequency magnetic field is stopped and the supply of the reaction gas is closed.

[0137] In this way, through this step, a uniform and dense film layer can be deposited on the coating substrate 100, laying a foundation for the subsequent etching process.

[0138] In some embodiments, inductively coupled plasma is used for etching the film layer, including: evacuating the reaction gas in the coating chamber; filling the coating chamber with a first etching gas; applying a high-frequency magnetic field to the first etching gas through an induction electrode to generate etching plasma.

[0139] Optionally, the power of the induction electrode can be 50 - 100 W. Exemplarily, the power of the induction electrode can be 50 W, 70 W, 80 W, 100 W, etc.

[0140] Specifically, before starting the etching, it is first necessary to completely evacuate the gas in the coating chamber to reach a certain vacuum degree to ensure the purity and controllability of the etching process and avoid the interference of the residual gas in the coating chamber on the etching effect.

[0141] After the vacuuming is completed, an appropriate amount of the first etching gas is filled into the coating chamber. Optionally, the etching gas can be selected according to parameters such as the material of the film layer to be etched, the required etching rate, selectivity, etc., which are not limited here. Exemplarily, the first etching gas can be a fluorine-based gas (such as CF4, SF6, etc.). The fluorine-based gas can chemically react with silicon dioxide to generate volatile fluorides, thereby realizing the etching of the film layer.

[0142] Subsequently, a high-frequency magnetic field is applied to the first etching gas through the induction electrode outside the coating chamber. The high-frequency magnetic field excites gas molecules to form plasma, and the high-energy electrons therein collide with the etching gas molecules, resulting in molecular dissociation and ionization to form the active particles required for etching. When the etching reaches the preset depth or time, the application of the high-frequency magnetic field is stopped and the supply of the etching gas is closed.

[0143] It should be noted that during the actual operation process, parameters such as the temperature, pressure, gas flow rate in the coating chamber, and the power of the induction electrode need to be monitored in real time to ensure the stability and controllability of the etching process.

[0144] In this way, through this step, the etching operation of the film layer is realized, and the preset etching morphology and structure are obtained.

[0145] It can be seen that the coating operation and the film layer etching operation are carried out separately, and the target film layer 200 is finally formed by alternately executing them. This design ensures the precise control of each process step and finally obtains the high-precision target film layer 200. This step-by-step and independent processing method not only ensures the uniformity of the film layer but also improves the etching precision.

[0146] In addition, in some embodiments, when using inductively coupled plasma to deposit a film layer on the coating substrate 100, it further includes: filling the coating chamber with a second etching gas, and the volume flow rate of the second etching gas is less than that of the reaction gas; applying an induction electrode to the second etching gas to generate etching plasma, so that the coating plasma and the etching plasma act on the coating substrate 100 synchronously.

[0147] It can be seen that in another example, the reaction gas and the second etching gas can be simultaneously filled into the coating chamber. Among them, the reaction gas can include SiH4 and N2O, which are used to generate the film layer, and the volume flow rate of the second etching gas is less than that of the reaction gas, ensuring that the film layer forming speed is greater than its etching speed, thereby ensuring the balance and stability of the coating and etching processes.

[0148] Subsequently, a high-frequency magnetic field is simultaneously applied to the reaction gas and the second etching gas through the induction electrode to generate coating plasma and etching plasma. Among them, the high-energy electrons in the coating plasma collide with the reaction gas molecules to generate silicon dioxide and deposit on the surface of the coating substrate 100, and the active particles in the etching plasma slightly etch the deposited film layer to achieve the instant adjustment and optimization of the film layer.

[0149] It should be noted that during the actual operation process, in this synchronous example mode, parameters such as the flow rate, ratio of the reaction gas and the second etching gas, and the power of the induction electrode need to be precisely controlled to ensure the balance and stability of the coating and etching processes.

[0150] Through the process of synchronous coating and etching, the two processes of coating and etching can be overlapped in time, which has the advantages of improving production efficiency, optimizing the quality and performance of the film layer, and simplifying the process flow.

[0151] It can be seen that the above two examples respectively show how to introduce the second etching gas in the inductively coupled plasma coating process to achieve the effects of step-by-step coating and etching or synchronous coating and etching. Both of these two methods can improve the quality, uniformity and performance of the film layer to a certain extent and meet the requirements of the Micro LED chip manufacturing process. The specific choice of which example can depend on factors such as actual process requirements, equipment conditions, and production costs, and is not limited here.

[0152] In some embodiments, the first etching gas and the second etching gas are different types of gases.

[0153] Optionally, the first etching gas and the second etching gas can have different reactivity, selectivity, etching rate, etc.

[0154] As can be seen from the above process steps, in some examples, the first etching gas can be used for the initial etching process, and is selected according to the specific material and process requirements. For example, in some situations, a highly reactive gas may be selected to quickly remove unnecessary material layers. Exemplarily, CF4 can be selected as the first etching gas, which can effectively remove residues and also implement the etching process.

[0155] In other examples, the second etching gas can be introduced after or during the coating process for further fine etching or adjustment. By adjusting the type and flow rate of the second etching gas, fine-tuning of the film structure can be achieved, such as optimizing the sidewall angle, reducing etching damage, etc. For example, the second etching gas can be selected as AR, and argon plasma can be generated during the etching process to effectively refine the film surface and improve flatness.

[0156] In this way, the first etching gas and the second etching gas are used in the etching process, and the two are different types of gases, which can achieve precise control of the coating and etching processes and improve the optical performance of the Micro LED chip.

[0157] In some embodiments, when an inductively coupled plasma is used to coat a film on the coating substrate 100, optionally, the temperature in the coating chamber is 240°C-300°C. Exemplarily, the temperature in the coating chamber may be 240°C, 260°C, 280°C, 300°C, etc. Precise control of temperature helps to ensure uniformity and density of film deposition and further optimize the optical properties of the film.

[0158] Optionally, the deposition rate of the film layer is 6A / s-9A / s. Exemplarily, the deposition rate of the film layer can be 6A / s, 7A / s, 8A / s, 9A / s, etc. By precisely controlling the deposition rate, the thickness and structure of the film layer can be effectively controlled, thereby improving the brightness and color performance of the MicroLED chip.

[0159] Optionally, the deposition time of the film layer is 1000s-2000s. Exemplarily, the deposition time of the film layer can be 1000s, 1200s, 1400s, 1600s, etc. Reasonable selection of deposition time helps to ensure the integrity and stability of the film layer, and further improve the overall performance and durability of the Micro LED chip.

[0160] Optionally, the etching acceleration power is 80W-120W. Exemplarily, the etching acceleration power can be 80W, 90W, 100W, 110W, etc. Precise power control helps to optimize the etching effect, reduce damage, and improve the quality of the film layer.

[0161] Optionally, the ionization power is 100W - 500W. Exemplarily, the ionization power can be 100W, 200W, 300W, 400W, etc. By precisely regulating the ionization power, the activity of the plasma can be effectively enhanced, further optimizing the uniformity and density of the film layer, and ensuring the high performance and stability of the Micro LED chip.

[0162] It should be noted that in some examples of multi-step processes, multiple film layers will be formed. Among the multiple film layers, the deposition rate of the bottom film layer needs to be lower than that of the subsequent film layers, the etching acceleration power needs to be lower, while the pressure and ionization power need to be greater to ensure the density and flatness of the bottom film layer. For example, the deposition rate of the bottom film layer is controlled to be less than 5A / S.

[0163] In some embodiments, when using inductively coupled plasma to etch the film layer, optionally, the temperature in the coating chamber is 240°C - 300°C. Exemplarily, the temperature can be 250°C, 270°C, 290°C, 310°C, etc. Precisely regulating the temperature helps to optimize the etching depth and the smoothness of the film layer surface, further enhancing the clarity and contrast of the Micro LED chip.

[0164] Optionally, the etching rate of the film layer is 8A / s - 9A / s. Exemplarily, the etching rate can be 8A / s, 9A / s, 10A / s, 11A / s, etc. Precisely controlling the etching rate helps to balance film layer removal and structure retention, further optimizing the optical performance and stability of the Micro LED chip.

[0165] Optionally, the etching time of the film layer is 500s - 800s. Exemplarily, the etching time can be 500s, 600s, 700s, 800s, etc. Reasonably selecting the etching time helps to ensure the integrity of the film layer structure and the surface smoothness, further enhancing the image quality and service life of the MicroLED chip.

[0166] In some embodiments, the process of depositing a film layer on the coating substrate 100 using inductively coupled plasma is performed at least twice. Among the at least two times, when performing the second time of depositing a film layer on the coating substrate 100 using inductively coupled plasma, the etching acceleration power is greater than that when performing the first time of depositing a film layer on the coating substrate 100 using inductively coupled plasma.

[0167] It can be understood that the coating method provided by the embodiments of the present application realizes the gradual optimization of the film layer structure by alternately performing the film layer deposition and etching steps, thereby significantly reducing the void ratio and enhancing the film layer density.

[0168] Therefore, in order to ensure that the thickness, uniformity, performance, etc. of the film layer meet the preset requirements, the step of depositing the film layer on the coating substrate 100 by inductively coupled plasma needs to be performed at least twice, that is, before the final target film layer 200 is formed, at least two coating operations will be carried out.

[0169] In addition, during the second coating process, the etching acceleration power is set to be greater than that during the first coating. In this way, by increasing the etching acceleration power, the defects on the surface of the film layer are further removed, and the structure and performance of the film layer are optimized. In addition, increasing the etching acceleration power may also increase the energy level of the plasma, thereby accelerating the deposition rate of the coating material, helping to form a thicker film layer in a shorter time, or improving the density and uniformity of the film layer.

[0170] Furthermore, if there are some deficiencies or defects during the first coating process, by increasing the etching acceleration power of the second coating, these defects can be more effectively removed, providing a better substrate 1 for the deposition of the new layer.

[0171] In some embodiments, the deposition of the film layer on the coating substrate 100 by inductively coupled plasma is performed at least twice. Among the at least two times, the etching amount during the second execution of depositing the film layer on the coating substrate 100 by inductively coupled plasma is greater than the etching amount during the first execution of depositing the film layer on the coating substrate 100 by inductively coupled plasma.

[0172] Similarly, it can be understood that by increasing the amount of the second etching, the defects on the surface of the film layer can be more effectively removed, thereby further improving the quality and performance of the film layer. If the thickness of the film layer formed after the first coating exceeds the expected range, by increasing the amount of the second etching, the final thickness of the film layer can be adjusted to meet the design requirements.

[0173] In addition, in some situations, it may be necessary to form specific structures or patterns in the film layer. By precisely controlling the etching amount, these structures or patterns can be realized in the film layer to ensure the design requirements.

[0174] A specific practical operation example is provided below according to the coating method of the present application.

[0175] The first step is deposition. Among them, the target thickness is 15000 Å, the deposition rate is 6 Å / S - 9 Å / S, the time is 2000 s, the reaction gases are SIH4 (300 sccm - 400 sccm) and N2O (60 sccm - 90 sccm), the etching gas is AR (Argon plasma) (100 sccm), the etching acceleration power is 100 w, the pressure is 0.8 Torr - 1.2 Torr, the ionization power is 100 w - 500 w, and the temperature is 260 °C.

[0176] In this step, by introducing the reaction gas and the etching gas simultaneously, the coating and etching are carried out synchronously. During the deposition of SiO2, slight etching is performed to optimize the surface morphology and the via filling ability of the coating.

[0177] The second step of etching, where the target removal amount is 5000 Å, the etching rate is 8 Å / s - 9 Å / s, the time is 600 s, the etching gas is CF4, and the temperature is 260 °C.

[0178] In this step, CF4 is used as the etching gas to further etch the SiO2 deposited in the first step to remove surface defects and uneven parts.

[0179] The third step of deposition, where the target thickness is 7000 Å, the deposition rate is 6 Å / s - 7 Å / s (lower than that in the first step), the time is 1000 s, the reaction gases are SiH4 (300 sccm - 400 sccm) and N2O (60 sccm - 90 sccm), the etching gas is Ar (100 sccm), the etching acceleration power is 200 w (higher than that in the first step), the pressure is 0.8 Torr - 1.2 Torr, the ionization power is 100 w - 500 w, and the temperature is 260 °C.

[0180] In this step, the deposition rate is lower than that in the first step, the etching acceleration power is higher than that in the first step, and the etching amount also increases accordingly. The deposition is carried out again while increasing the etching acceleration power to increase the etching amount while maintaining the deposition rate and further optimize the surface morphology of the coating.

[0181] The fourth step of etching, where the target removal amount is 5000 Å, the etching rate is 8 Å / s - 9 Å / s, the time is 600 s, the etching gas is CF4, and the temperature is 260 °C.

[0182] This step is similar to the second step, using CF4 to further etch the SiO2 deposited in the third step.

[0183] The fifth step of deposition, where the target thickness is 13000 Å, the deposition rate is 6 Å / s - 7 Å / s, the time is 2000 s, the reaction gases are SiH4 (300 sccm - 400 sccm) and N2O (60 sccm - 90 sccm), the etching gas is Ar (100 sccm), the etching acceleration power is 50 w - 100 w (lower than that in the third step), the pressure is 0.8 Torr - 1.2 Torr, the ionization power is 100 w - 500 w, the temperature is 260 °C, and the total thickness reaches the preset thickness of 25000 Å.

[0184] In this step, the last deposition is performed while reducing the etching acceleration power to ensure that the final preset thickness is reached and a good interface of the target film layer 200 is formed.

[0185] Understandably, for the Micro LED chip of the embodiment of the present application, a microlens array and a spacer layer can be formed by the pixel-level optical shaping coating method of the Micro LED chip in the above embodiment.

[0186] The Micro LED chip is coated by the above coating method. Using the ICPCVD process and combining the alternating deposition and etching methods, it effectively solves the void problem that easily occurs in the traditional PECVD process, improves the filling and coating properties of the film layer, improves the hole filling coverage ability, enhances the uniformity and brightness of the appearance of the Micro LED chip, reduces the abnormal color difference phenomenon, and also enhances the lens effect and brightness. In addition, this design also makes the deposition and etching processes of the film layer more uniform and controllable, thereby improving the overall quality of the film layer, obtaining a flatter coating interface, and reducing abnormalities such as glue dropping in subsequent processes.

[0187] In addition, by alternately performing deposition and etching in the ICPCVD equipment, it avoids the time and cost waste that may be brought by multiple transfers of the coating substrate 100, improves the production efficiency. This method can also flexibly adjust the coating and etching parameters according to different pixel-level optical display requirements of Micro LED chips, and thus realizes customized production.

[0188] The size of the above Micro LED chip of the present application does not exceed 1 cm, preferably does not exceed 20 microns. The Micro LED structure (i.e., the above-mentioned light-emitting mesa 1031) is arranged in an array form in the Micro LED chip, and the resolution is, for example, 720 480, 640 480, 1920 1080, 1280 720, 2K or 4K. The diameter of the Micro LED structure is in the nanometer range, such as 20 nm to 100 nm.

[0189] In the above Micro LED chip of the present application, the Micro LED array (i.e., the above-mentioned light-emitting mesa array) can include a single-layer Micro LED structure, or the Micro LED array can include multiple vertically stacked Micro LED structures.

[0190] In the above-mentioned Micro LED chip of the present application, the Micro LED array may include a blue Micro LED structure. In some embodiments of the present application, the pitch of the Micro LED array, that is, the minimum distance between the centers of adjacent Micro LED structures, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the Micro LED chip may be between several thousand and several million.

[0191] In the above-mentioned Micro LED chip of the present application, the pixel driving layer 201 of the Micro LED chip can be electrically connected to each Micro LED structure in the Micro LED array through separate metal interconnections. In some embodiments, each Micro LED structure can be individually electrically controlled by the pixel driving layer 201. In some embodiments, the pixel driving layer 201 can be electrically connected to the electrodes of the Micro LED chip through metal interconnections. In some embodiments, a dielectric layer can be formed in the gaps between the Micro LED structures. In some embodiments, the dielectric layer can also be formed in the gaps between the interconnections.

[0192] In the above-mentioned Micro LED chip of the present application, it includes a plurality of Micro LED arrays, and each Micro LED array includes a plurality of Micro LED structures. The driving method of the Micro LED structure is, for example, passive matrix (PM) driving, where the cathodes of all Micro LED structures in each array are commonly connected to the cathode line (NL), and the Micro LED structures with the same number in each array are respectively connected to the corresponding anode line (PL). Thus, the on / off and luminous brightness of each light-emitting diode can be individually controlled by controlling the signals on the corresponding cathode line and anode line.

[0193] In the above-mentioned Micro LED chip of the present application, the light-emitting layer (i.e., the epitaxial layer 103) of the Micro LED chip is formed by a plurality of stacked quantum well layers, especially superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In one embodiment of the present application, the quantum well layer is an InGaN / GaN multiple quantum well layer or an InGaN / AlGaN multiple quantum well layer or an InGaAs / AlGaAs multiple quantum well layer. In one embodiment of the present application, the light-emitting layer further includes an electron blocking layer, and the electron blocking layer is disposed on the first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer.

[0194] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A Micro LED chip, characterized in that, Comprising: A light-emitting mesa array including a plurality of light-emitting mesas arranged in an array; A sidewall dielectric layer covering at least the sidewalls of each of the light-emitting mesas, with at least a partial area of the top of the light-emitting mesa exposed; A first top conductive layer covering the sidewall dielectric layer and the exposed area on the top of the light-emitting mesa; A microlens array including a plurality of microlenses covering the first top conductive layer, wherein there are no pores inside each of the microlenses.

2. The Micro LED chip according to claim 1, wherein, The material inside the microlens is continuous.

3. The Micro LED chip according to claim 1, wherein The microlens array further includes a spacer layer covering the first top conductive layer; The microlenses are located on a part of the spacer layer.

4. The Micro LED chip according to claim 3, wherein, The microlenses and the spacer layer are of an integral structure.

5. The Micro LED chip according to claim 3, wherein, There are no pores inside the spacer layer under the microlenses.

6. The Micro LED chip according to claim 4, wherein, The diameter of the microlenses is not greater than 20 microns, and the width of the light-emitting mesas is not greater than 20 microns.

7. The Micro LED chip according to claim 1, wherein, The first top conductive layer between the light-emitting mesas is continuous; The sidewall dielectric layer between the light-emitting mesas is continuous.

8. The Micro LED chip according to claim 1, wherein, A pixel driving layer and a conductive contact structure located on the pixel driving layer are further provided at the bottom of the light-emitting mesa; The bottom of the light-emitting mesa is electrically connected to the conductive contact structure.

9. The Micro LED chip according to claim 8, wherein, Each light-emitting mesa in the light-emitting mesa array can be independently controlled; each light-emitting mesa sequentially includes from bottom to top: a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer; the first-type semiconductor layer and the second-type semiconductor layer have different conductivity types, the light-emitting layer includes multiple stacked layers; there is also a second top conductive layer between the top of the second-type semiconductor layer and the first top conductive layer; there is also a bottom conductive layer between the bottom of the first-type semiconductor layer and the conductive contact structure.

10. A pixel-level optical shaping coating method for Micro LED chips, which is used to prepare the Micro LED chips described in any one of claims 1-9, and is characterized in that, Including the following steps: Forming a coating substrate, the coating substrate including: a light-emitting mesa array, a sidewall dielectric layer located on the periphery of the light-emitting mesa, and a first top conductive layer covering the sidewall dielectric layer and the light-emitting mesa; Coating a film layer on the coating substrate by inductively coupled plasma until a target film layer is formed on the coating substrate.

11. The pixel-level optical shaping coating method for the Micro LED chip according to claim 10, wherein Also including: Etching the film layer by inductively coupled plasma.

12. The pixel-level optical shaping coating method for the Micro LED chip according to claim 11, wherein, Also including: Alternately performing coating a film layer on the coating substrate by inductively coupled plasma and etching the film layer by inductively coupled plasma until the target film layer is formed.

13. The pixel-level optical shaping coating method for a Micro LED chip according to claim 12, wherein The coating of the film layer on the coating substrate by inductively coupled plasma includes: Filling a reaction gas into the coating chamber, the reaction gas including SiH4, N20 or NH3; Applying a high-frequency magnetic field to the reaction gas through an induction electrode to generate coating plasma.

14. The pixel-level optical shaping coating method for the Micro LED chip according to claim 13, wherein The etching of the film layer by inductively coupled plasma includes: Vacuuming the reaction gas in the coating chamber; Filling a first etching gas into the coating chamber; Applying a high-frequency magnetic field to the first etching gas through an induction electrode to generate etching plasma.

15. The pixel-level optical shaping coating method for the Micro LED chip according to claim 14, wherein, The material of the first etching gas includes CF4.

16. The pixel-level optical shaping coating method for a Micro LED chip according to claim 14, characterized in that, The coating of the film layer on the coating substrate by inductively coupled plasma further includes: Introduce a second etching gas into the coating chamber, and the volume flow rate of the second etching gas is less than that of the reaction gas; Act on the second etching gas through an induction electrode to generate etching plasma, so that the coating plasma and the etching plasma act on the coating substrate synchronously.

17. The pixel-level optical shaping coating method for Micro LED chips according to claim 16, wherein The material of the second etching gas includes noble gas.

18. The pixel-level optical shaping coating method for the Micro LED chip according to claim 16, wherein The first etching gas and the second etching gas are different types of gases.

19. The pixel-level optical shaping coating method for the Micro LED chip according to claim 10, wherein, When depositing a film on a coating substrate using inductively coupled plasma, The temperature in the coating chamber is 240°C - 300°C; and / or, The deposition rate of the film is 6 Å / s - 9 Å / s; and / or, The deposition time of the film is 1000 s - 2000 s; and / or, The etching acceleration power is 80 W - 120 W; and / or, The ionization power is 100 W - 500 W.

20. The pixel-level optical shaping coating method for Micro LED chips according to claim 11, wherein, When etching the film using inductively coupled plasma, The temperature in the coating chamber is 240°C - 300°C; and / or, The etching rate of the film is 8 Å / s - 9 Å / s; and / or, The etching time of the film is 500 s - 800 s.

21. The pixel-level optical shaping coating method for a Micro LED chip according to claim 12, wherein, The process of depositing a film on a coating substrate using inductively coupled plasma is performed at least twice, Among the at least two times, the etching acceleration power when performing the process of depositing a film on a coating substrate using inductively coupled plasma for the second time is greater than that when performing it for the first time.

22. The pixel-level optical shaping coating method for a Micro LED chip according to claim 12, characterized in that, The process of depositing a film on a coating substrate using inductively coupled plasma is performed at least twice, Among the at least two times, the etching amount when performing the process of depositing a film on a coating substrate using inductively coupled plasma for the second time is greater than that when performing it for the first time.

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