Packaging substrate and light emitting diode packaging structure

Abstract

The invention provides a packaging substrate and a light emitting diode packaging structure. The packaging substrate comprises an insulating layer and a circuit layer. The circuit layer comprises a first circuit sub-layer, a second circuit sub-layer and a circuit connecting part, the first circuit sub-layer and the second circuit sub-layer are located on the two opposite surfaces of the insulating layer respectively, the insulating layer is provided with a plurality of through holes, and the circuit connecting part penetrates through the through holes to be connected with the first circuit sub-layer and the second circuit sub-layer respectively. The first circuit sub-layer is provided with a closed hollow pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and particularly to a packaging substrate and a light-emitting diode packaging structure. Background Art

[0002] Light Emitting Diodes (LEDs) have advantages such as energy conservation, high brightness, high durability, long lifespan, and light weight, and have been widely used in fields such as lighting and display.

[0003] Related technologies provide a light-emitting diode packaging structure, including: an insulating layer, a circuit layer, a light-emitting diode chip, a white glue layer, and a ball head. The circuit layer is located on the insulating layer, the light-emitting diode chip is located on the circuit layer, the white glue layer is disposed around the light-emitting diode chip, and the ball head covers the circuit layer, the light-emitting diode chip, and the white glue layer.

[0004] However, the circuit layer and the ball head of the light-emitting diode using the above packaging structure are prone to detachment, and the stability is poor. Summary of the Invention

[0005] Embodiments of the present disclosure provide a packaging substrate and a light-emitting diode packaging structure, which reduce the risk of detachment of the circuit layer and the ball head and improve the yield of the light-emitting diode. The technical solutions are as follows:

[0006] On the one hand, a packaging substrate is provided, and the packaging substrate includes:

[0007] an insulating layer and a circuit layer;

[0008] The circuit layer includes a first circuit sub-layer, a second circuit sub-layer, and a circuit connection portion. The first circuit sub-layer and the second circuit sub-layer are respectively located on two opposite surfaces of the insulating layer. The insulating layer has a plurality of through holes, and the circuit connection portion passes through the plurality of through holes and is respectively connected to the first circuit sub-layer and the second circuit sub-layer. The first circuit sub-layer has a closed hollow pattern.

[0009] Optionally, the hollow pattern includes 4 isolated hollow regions.

[0010] Optionally, each hollow region includes a first region, a second region, and a third region; the first region is parallel to one side of the insulating layer, the second region is parallel to another side adjacent to the side, the third region connects the first region and the second region, and the width of the third region is smaller than the widths of the first region and the second region.

[0011] Optionally, the first circuit sub-layer has eight sides, and the insulating layer has four sides; four of the eight sides of the first circuit sub-layer are respectively parallel to the four sides of the insulating layer.

[0012] Optionally, the first circuit sub-layer and the second circuit sub-layer include a negative electrode region and a positive electrode region, and the negative electrode region and the positive electrode region are insulated from each other;

[0013] Two of the hollow areas are located in the negative electrode region, and the other two hollow areas are located in the positive electrode region.

[0014] Optionally, the negative electrode region and the positive electrode region respectively correspond to three through holes, the three through holes are arranged in an isosceles triangle, and the three through holes corresponding to the negative electrode region and the three through holes corresponding to the positive electrode region are symmetrically arranged.

[0015] Optionally, the thickness of the first circuit sub-layer is 60-75 μm.

[0016] Optionally, the distance between the first circuit sub-layer and the edge of the insulating layer is greater than or equal to 0.15 mm.

[0017] On the other hand, a light-emitting diode packaging structure, the light-emitting diode packaging structure includes:

[0018] An insulating layer, a circuit layer, a light-emitting diode chip, a white glue layer, and a ball head;

[0019] The circuit layer includes a first circuit sub-layer, a second circuit sub-layer, and a circuit connection portion. The first circuit sub-layer and the second circuit sub-layer are respectively located on two opposite surfaces of the insulating layer. The insulating layer has a plurality of through holes, and the circuit connection portion passes through the plurality of through holes and is respectively connected to the first circuit sub-layer and the second circuit sub-layer. The first circuit sub-layer has a closed hollow pattern, the light-emitting diode chip is located on the first circuit sub-layer, the hollow pattern is located around the light-emitting diode chip, the white glue layer is bonded to the side wall of the light-emitting diode chip, a part of the insulating layer in the first circuit sub-layer and the hollow pattern, and the ball head covers the first circuit sub-layer, the light-emitting diode chip, the white glue layer, the insulating layer in the hollow pattern, and the insulating layer outside the first circuit sub-layer.

[0020] Optionally, the hollow pattern includes four hollow areas, and the four hollow areas are respectively located at the four corners of the light-emitting diode chip.

[0021] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure are:

[0022] In an embodiment of the present disclosure, the circuit layer includes a first circuit sub-layer, a second circuit sub-layer, and a circuit connection portion. The circuit connection portion passes through a plurality of through holes formed in the insulating layer to connect the first circuit sub-layer and the second circuit sub-layer, making the overall combination of the circuit layer and the insulating layer closer, effectively improving the adhesion between the circuit layer and the insulating layer. Moreover, the circuit connection portion passing through a plurality of through holes makes the current distribution more uniform.

[0023] Among them, the first circuit sub-layer has a hollowed-out pattern, which causes a height difference between the surface of the circuit layer and the surface of the insulating layer. The hollowed-out pattern is located around the light-emitting diode chip. The white glue layer is bonded to the side wall of the light-emitting diode chip, a part of the insulating layer in the first circuit sub-layer, and the hollowed-out pattern. Since the white glue layer flows more slowly on the surface of the insulating layer, the white glue layer stops spreading after flowing a short distance on the insulating layer, which can effectively play a role in isolating the white glue layer. In this way, the ball head can contact more surfaces of the insulating layer, making the ball head fit more closely with the insulating layer. And the ball head covers the first circuit sub-layer, protecting the circuit and avoiding the problem that the circuit layer and the ball head are prone to fall off, improving the stability. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0025] Figure 1 It is a schematic structural diagram of a packaging substrate provided by an embodiment of the present disclosure;

[0026] Figure 2 It is a top view of the front side of a packaging substrate provided by an embodiment of the present disclosure;

[0027] Figure 3 It is a top view of the back side of a packaging substrate provided by an embodiment of the present disclosure;

[0028] Figure 4 It is a schematic diagram of a light-emitting diode packaging structure provided by an embodiment of the present disclosure;

[0029] Figure 5 It is a flowchart of a packaging method for a light-emitting diode packaging structure provided by an embodiment of the present disclosure.

[0030] The reference numerals are as follows:

[0031] 101: insulating layer; 102: circuit layer; 103: light-emitting diode chip; 104: white glue layer; 105: ball head;

[0032] 1021: First circuit sub-layer; 1022: Second circuit sub-layer; 1023: Circuit connection part;

[0033] 201: Through-hole; 202: Hollowed-out pattern;

[0034] 221: Hollowed-out area; 2211: First area; 2212: Second area; 2213: Third area;

[0035] 1: Negative electrode area; 2: Positive electrode area. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0037] Figure 1 The following is a schematic structural diagram of a packaging substrate provided for an embodiment of the present disclosure. Refer to Figure 1 , the packaging substrate includes: an insulating layer 101 and a circuit layer 102;

[0038] Among them, the circuit layer 102 includes a first circuit sub-layer 1021, a second circuit sub-layer 1022 and a circuit connection part 1023. The first circuit sub-layer 1021 and the second circuit sub-layer 1022 are respectively located on two opposite surfaces of the insulating layer 101. The insulating layer 101 has a plurality of through-holes 201, and the circuit connection part 1023 passes through the plurality of through-holes 201 and is respectively connected to the first circuit sub-layer 1021 and the second circuit sub-layer 1022. The first circuit sub-layer 1021 has a closed hollowed-out pattern 202.

[0039] In the embodiment of the present disclosure, the circuit layer includes a first circuit sub-layer, a second circuit sub-layer and a circuit connection part. The circuit connection part passes through a plurality of through-holes opened in the insulating layer to connect the first circuit sub-layer and the second circuit sub-layer, making the overall combination of the circuit layer and the insulating layer closer, effectively improving the adhesion between the circuit layer and the insulating layer; and, the circuit connection part passes through a plurality of through-holes to make the current distribution more uniform;

[0040] Among them, the first circuit sub-layer has a hollowed-out pattern, making a height difference between the surface of the circuit layer and the surface of the insulating layer. The hollowed-out pattern is located around the light-emitting diode chip. The white glue layer is bonded to the side wall of the light-emitting diode chip, a part of the insulating layer in the first circuit sub-layer and the hollowed-out pattern. Since the white glue layer flows more slowly on the surface of the insulating layer, the white glue layer stops spreading after flowing a small distance on the insulating layer, which can effectively play a role in isolating the white glue layer. In this way, the ball head can contact more surfaces of the insulating layer, making the ball head fit more closely with the insulating layer, and the ball head covers the first circuit sub-layer, protecting the circuit and avoiding the problem that the circuit layer and the ball head are easily detached, improving the stability.

[0041] In an embodiment of the present disclosure, the hollowed-out pattern 202 includes 4 isolated hollowed-out areas 221, which can make the subsequent bonding part of the ball head and the insulating layer more uniform, and make the bonding between the ball head and the insulating layer closer.

[0042] In an embodiment of the present disclosure, the hollowed-out pattern 202 includes 4 L-shaped hollows, and the 4 L-shaped hollows are respectively located at the four corners of the light-emitting diode chip 103.

[0043] In an embodiment of the present disclosure, the L-shaped hollowed-out pattern is arranged around the light-emitting diode, which can make the subsequent bonding part of the ball head and the insulating layer more uniform, and make the bonding between the ball head and the insulating layer closer.

[0044] In an embodiment of the present disclosure, each of the hollowed-out areas 221 includes a first area 2211, a second area 2212, and a third area 2213; the first area 2211 is parallel to one side of the insulating layer 101, the second area 2212 is parallel to another side adjacent to the side, the third area 2213 connects the first area 2211 and the second area 2212, and the width of the third area 2213 is smaller than the widths of the first area 2211 and the second area 2212. The hollowed-out area composed of the above three areas has a relatively large area and can form a hollowed-out structure surrounding the chip, which can make the subsequent bonding part of the ball head and the insulating layer more uniform, and make the bonding between the ball head and the insulating layer closer. In other examples, the hollowed-out pattern 202 may include other numbers of L-shaped hollows, or may include hollows of other shapes, such as rectangular or arc-shaped hollows, etc.

[0045] In an embodiment of the present disclosure, the first circuit sub-layer 1021 has eight sides, and the insulating layer 101 has four sides; four of the eight sides of the first circuit sub-layer 1021 are respectively parallel to the four sides of the insulating layer 101. The first circuit sub-layer with the above pattern can expose the insulating layer at the four corners so that the subsequent ball head can completely wrap the first circuit sub-layer, making the bonding between the ball head and the insulating layer closer.

[0046] Figure 2 It is a front top view of a packaging substrate provided by an embodiment of the present disclosure. Figure 2 Shown is a top view of the packaging structure of the light-emitting diode before installing the light-emitting diode chip. Refer to Figure 2 , the first circuit sub-layer 1021 includes a negative electrode area 1 and a positive electrode area 2, and the negative electrode area 1 and the positive electrode area 2 are insulated from each other.

[0047] 2 of the hollowed-out areas 221 are located in the negative electrode area 1, and the other 2 hollowed-out areas 221 are located in the positive electrode area 2.

[0048] Figure 3 It is a back top view of a packaging substrate provided by an embodiment of the present disclosure. Figure 3The top view of the package structure of the light-emitting diode before installing the light-emitting diode is shown. Refer to Figure 3 , the second circuit sub-layer 1022 includes a negative electrode region 1 and a positive electrode region 2, and the negative electrode region 1 and the positive electrode region 2 are arranged insulated from each other.

[0049] In the embodiment of the present disclosure, the negative electrode region 1 and the positive electrode region 2 respectively correspond to 3 through holes 201, and the 3 through holes 201 are arranged in an isosceles triangle, and the 3 through holes 201 corresponding to the negative electrode region 1 and the 3 through holes 201 corresponding to the positive electrode region 2 are symmetrically arranged.

[0050] In the embodiment of the present disclosure, adopting the above distribution method can make the current distribution more uniform and avoid the hidden danger of burning out the circuit layer due to excessive local current.

[0051] In other examples, the negative electrode region 1 and the positive electrode region 2 respectively correspond to 4 through holes 201, and the 4 through holes 201 can be arranged in a rhombus. In the embodiment of the present disclosure, the first circuit sub-layer 1021, the second circuit sub-layer 1022, and the circuit connection portion 1023 can all be made of copper.

[0052] In the embodiment of the present disclosure, copper has good electrical conductivity and can be used as the circuit layer.

[0053] In the embodiment of the present disclosure, the thickness of the first circuit sub-layer 1021 or the second circuit sub-layer 1022 can be 60-75 μm.

[0054] In the embodiment of the present disclosure, adopting the above thickness can form a height difference between the circuit layer and the insulating layer, and the white glue flows between the circuit layer and the insulating layer. When the white glue flows to the insulating layer, since the white glue layer flows more slowly on the surface of the insulating layer, the white glue layer stops spreading after flowing a small distance on the insulating layer, making the white glue layer fit more closely with the circuit layer.

[0055] Exemplarily, the thickness of the first circuit sub-layer 1021 or the second circuit sub-layer 1022 is 60 μm.

[0056] In the embodiment of the present disclosure, the number of the through holes 201 can be 6-8.

[0057] In the embodiment of the present disclosure, adopting the above number of through holes can make the current distribution more uniform and is more conducive to the heat of the light-emitting diode being conducted to the second circuit sub-layer in time.

[0058] Exemplarily, the number of the through holes 201 is 6.

[0059] In the embodiment of the present disclosure, the diameter of the through hole 201 can be 50-200 μm.

[0060] In the embodiments of the present disclosure, by using through-holes with the above diameter, the first circuit sub-layer and the second circuit sub-layer can be more closely connected, and at the same time, it is more conducive to guiding heat to the second circuit sub-layer in a timely manner.

[0061] Exemplarily, the diameter of the through-hole 201 is 150 μm.

[0062] In the embodiments of the present disclosure, the distance between the first circuit sub-layer 1021 and the edge of the insulating layer 101 may be greater than or equal to 0.15 mm.

[0063] In the embodiments of the present disclosure, by using the above distance, the entire circuit layer can be wrapped during subsequent ball head wrapping, avoiding the risk of the ball head falling off.

[0064] Exemplarily, the distance between the first circuit sub-layer 1021 and the edge of the insulating layer 101 is equal to 0.15 mm.

[0065] In the embodiments of the present disclosure, the first circuit sub-layer 1021 may be a regular polygon.

[0066] In the embodiments of the present disclosure, by using a ball head with the above shape, the first circuit sub-layer can be completely covered inside, protecting the circuit and avoiding the possibility of peeling.

[0067] In other embodiments, the first circuit sub-layer 1021 may also be rectangular or circular, and the embodiments of the present disclosure do not limit this.

[0068] In the embodiments of the present disclosure, the insulating layer 101 may be an alumina layer, an aluminum nitride layer, a silicon nitride layer, a silicon carbide layer, a beryllium oxide layer, a Flame Retardant 4 (FR-4) layer, or a Bismaleimide Triazine Layer (BT) layer.

[0069] Exemplarily, the insulating layer 101 is an alumina layer.

[0070] In the embodiments of the present disclosure, the distance between the through-hole 201 and the edge of the insulating layer 101 is 0.4 - 0.8 mm.

[0071] In the embodiments of the present disclosure, by using the above distance, it can be avoided that the through-hole is too close to the edge of the insulating layer, and the risk of the insulating layer cracking caused by too small edge area can be avoided, improving the reliability of the packaging structure.

[0072] Exemplarily, the distance between the through-hole 201 and the edge of the insulating layer 101 is 0.6 mm.

[0073] Figure 4 This is a schematic diagram of a light-emitting diode packaging structure provided by the embodiments of the present disclosure. Refer to Figure 4, the light-emitting diode package structure includes: an insulating layer 101, a circuit layer 102, a light-emitting diode chip 103, a white glue layer 104, and a ball head 105.

[0074] Among them, the circuit layer 102 includes a first circuit sub-layer 1021, a second circuit sub-layer 1022, and a circuit connection portion 1023. The first circuit sub-layer 1021 and the second circuit sub-layer 1022 are respectively located on two opposite surfaces of the insulating layer 101. The insulating layer 101 has a plurality of through holes 201. The circuit connection portion 1023 passes through the plurality of through holes 201 and is respectively connected to the first circuit sub-layer 1021 and the second circuit sub-layer 1022. The first circuit sub-layer 1021 has a closed hollow pattern 202. The light-emitting diode chip 103 is located on the first circuit sub-layer 1021. The hollow pattern 202 is located around the light-emitting diode chip 103. The white glue layer 104 is bonded to the side wall of the light-emitting diode chip 103, a part of the insulating layer 101 in the first circuit sub-layer 1021 and the hollow pattern 202. The ball head 105 covers the first circuit sub-layer 1021, the light-emitting diode chip 103, the white glue layer 104, the insulating layer 101 in the hollow pattern 202, and the insulating layer 101 outside the first circuit sub-layer 1021.

[0075] In the embodiment of the present disclosure, the circuit layer includes a first circuit sub-layer, a second circuit sub-layer, and a circuit connection portion. The circuit connection portion passes through a plurality of through holes opened in the insulating layer to connect the first circuit sub-layer and the second circuit sub-layer, making the overall combination of the circuit layer and the insulating layer closer, effectively improving the adhesion between the circuit layer and the insulating layer; and, the circuit connection portion passes through a plurality of through holes to make the current distribution more uniform;

[0076] Among them, the first circuit sub-layer has a hollow pattern, making a height difference between the surface of the circuit layer and the surface of the insulating layer. The hollow pattern is located around the light-emitting diode chip. The white glue layer is bonded to the side wall of the light-emitting diode chip, the first circuit sub-layer, and a part of the insulating layer in the hollow pattern. Since the white glue layer flows more slowly on the surface of the insulating layer, the white glue layer stops spreading after flowing a small distance on the insulating layer, which can effectively play a role in isolating the white glue layer. In this way, the ball head can contact more surfaces of the insulating layer, making the ball head fit more closely with the insulating layer. And the ball head covers the first circuit sub-layer, protecting the circuit and avoiding the problem that the circuit layer and the ball head are prone to falling off, improving the stability.

[0077] In the embodiment of the present disclosure, the hollow pattern 202 includes 4 hollow areas 221, and the 4 hollow areas 221 are respectively located at the four corners of the light-emitting diode chip 103.

[0078] In the embodiment of the present disclosure, the hollow pattern provided at the four corners of the light-emitting diode can make the subsequent fitting parts of the ball head and the insulating layer more uniform, making the ball head fit more closely with the insulating layer.

[0079] In an embodiment of the present disclosure, the side wall of the white glue layer 104 away from the light-emitting diode chip 103 is in a ramp shape.

[0080] In an embodiment of the present disclosure, the ramp shape can make the white glue layer fit more closely with the circuit layer.

[0081] In a possible implementation manner of the present disclosure, the light-emitting diode chip 103 can be a blue light chip. In other implementation manners, the light-emitting diode chip 103 can also be a chip of other colors.

[0082] In an embodiment of the present disclosure, the white glue layer 104 can be a mixture layer of titanium dioxide and silicone resin.

[0083] In an embodiment of the present disclosure, the thickness of the white glue layer 104 can be greater than 1 / 2 of the thickness of the light-emitting diode chip 103, can also be equal to 1 / 2 of the thickness of the light-emitting diode chip 103, or can also be less than 1 / 2 of the thickness of the light-emitting diode chip 103.

[0084] In one example, the thickness of the white glue layer 104 is less than 1 / 2 of the thickness of the light-emitting diode chip 103, and the thickness of the white glue layer 104 is greater than or equal to 50 microns. This thickness design can ensure the reflection efficiency of the white glue layer 104 on the basis of ensuring the reflection efficiency of the light-emitting diode, and the brightness is improved.

[0085] Exemplarily, the thickness of the light-emitting diode chip 103 is 200 microns, the thickness of the white glue layer 104 is less than 100 microns, and the thickness of the white glue layer 104 is greater than or equal to 50 microns. This thickness design can ensure that the thickness of the white glue layer 104 is less than 1 / 2 of the thickness of the light-emitting diode chip 103, thereby ensuring the reflection efficiency of the light-emitting diode.

[0086] For example, the thickness of the white glue layer 104 is 60 - 80 microns. This thickness design can ensure the reflection efficiency of the light-emitting diode, and the brightness is improved.

[0087] In an embodiment of the present disclosure, the ball head 105 can be a silicone ball head.

[0088] Figure 5 It is a flowchart of a packaging method for a light-emitting diode packaging structure provided by an embodiment of the present disclosure.

[0089] See Figure 5 This method includes the following steps:

[0090] S11. Provide an insulating layer and make a through hole on the insulating layer.

[0091] In an embodiment of the present disclosure, the insulating layer can be an alumina layer, an aluminum nitride layer, a silicon nitride layer, a silicon carbide layer, a beryllium oxide layer, an FR-4 layer, or a BT layer.

[0092] Exemplarily, the insulating layer is an alumina layer.

[0093] In an embodiment of the present disclosure, step S11 may include: fabricating a through hole on the insulating layer by laser drilling technology.

[0094] In an embodiment of the present disclosure, the number of through holes may be 6 to 8.

[0095] In an embodiment of the present disclosure, using the above number of through holes can make the current distribution more uniform and is more conducive to the heat of the light-emitting diode being conducted to the second circuit sub-layer in a timely manner.

[0096] Exemplarily, the number of through holes is 6.

[0097] In an embodiment of the present disclosure, the diameter of the through hole may be 50 to 200 μm.

[0098] In an embodiment of the present disclosure, using the through hole with the above diameter can make the connection between the first circuit sub-layer and the second circuit sub-layer closer and is more conducive to the heat being conducted to the second circuit sub-layer in a timely manner.

[0099] Exemplarily, the diameter of the through hole is 150 μm.

[0100] In an embodiment of the present disclosure, the distance between the through hole and the edge of the insulating layer is 0.4 to 0.8 mm.

[0101] In an embodiment of the present disclosure, using the above distance can prevent the through hole from being too close to the edge of the insulating layer, avoid the risk of the insulating layer cracking due to too small an edge area, and improve the reliability of the packaging structure.

[0102] Exemplarily, the distance between the through hole and the edge of the insulating layer is 0.6 mm.

[0103] S12. Fabricate a circuit layer on the insulating layer. The circuit layer includes a first circuit sub-layer, a second circuit sub-layer, and a circuit connection part. The first circuit sub-layer and the second circuit sub-layer are respectively located on two opposite surfaces of the insulating layer. The circuit connection part passes through a plurality of through holes and is respectively connected to the first circuit sub-layer and the second circuit sub-layer. The first circuit sub-layer has a closed hollow pattern.

[0104] In an embodiment of the present disclosure, the hollow pattern includes 4 isolated hollow areas, which can make the subsequent bonding part of the ball head and the insulating layer more uniform and make the ball head bond more closely to the insulating layer. In an embodiment of the present disclosure, the hollow pattern includes 4 L-shaped hollows, and the 4 L-shaped hollows are respectively located at the four corners of the light-emitting diode chip.

[0105] In an embodiment of the present disclosure, the L-shaped hollow pattern is arranged around the light-emitting diode, which can make the subsequent bonding part of the ball head and the insulating layer more uniform and make the ball head bond more closely to the insulating layer.

[0106] In the embodiments of the present disclosure, two L-shaped hollowings are located in the negative electrode region, and the other two L-shaped hollowings are located in the positive electrode region.

[0107] In the embodiments of the present disclosure, the L-shaped hollowings are respectively located in the negative electrode region and the positive electrode region, so that the insulating layers in the positive electrode region and the negative electrode region can be closely attached to the ball head.

[0108] In the embodiments of the present disclosure, each of the hollowed areas includes a first area, a second area, and a third area; the first area is parallel to one side of the insulating layer, the second area is parallel to the other side adjacent to the side, the third area connects the first area and the second area, and the width of the third area is smaller than the widths of the first area and the second area.

[0109] In other examples, the hollowed-out pattern may include other numbers of L-shaped hollowings, or include hollowings of other shapes, such as rectangular or arc-shaped hollowings, etc.

[0110] In the embodiments of the present disclosure, the first circuit sub-layer includes a negative electrode region and a positive electrode region, and the negative electrode region and the positive electrode region are insulated from each other.

[0111] Two hollowed-out areas are located in the negative electrode region, and the other two hollowed-out areas are located in the positive electrode region.

[0112] In the embodiments of the present disclosure, the negative electrode region and the positive electrode region respectively correspond to three through holes, and the three through holes are arranged in an isosceles triangle, and the three through holes corresponding to the negative electrode region and the three through holes corresponding to the positive electrode region are symmetrically arranged.

[0113] In the embodiments of the present disclosure, adopting the above distribution method can make the current distribution more uniform and avoid the hidden danger of burning out the circuit layer due to excessive local current.

[0114] In other examples, the negative electrode region and the positive electrode region respectively correspond to four through holes, and the four through holes can be arranged in a rhombus.

[0115] In the embodiments of the present disclosure, the first circuit sub-layer, the second circuit sub-layer, and the circuit connection part can all be made of copper.

[0116] In the embodiments of the present disclosure, copper has good electrical conductivity and can be used as the circuit layer.

[0117] In the embodiments of the present disclosure, the thickness of the first circuit sub-layer or the second circuit sub-layer can be 60-75 μm.

[0118] In the embodiments of the present disclosure, adopting the above thickness can form a height difference between the circuit layer and the insulating layer, and the white glue flows between the circuit layer and the insulating layer. When the white glue flows to the insulating layer, since the white glue layer flows more slowly on the surface of the insulating layer, the white glue layer stops spreading after flowing a small distance on the insulating layer, making the white glue layer fit more closely to the circuit layer.

[0119] Exemplarily, the thickness of the first circuit sub-layer or the second circuit sub-layer is 60 μm.

[0120] In the embodiment of the present disclosure, the first circuit sub-layer may be a regular polygon.

[0121] In the embodiment of the present disclosure, by using the above-shaped die top ball head, the first circuit sub-layer can be completely covered inside, which plays a protective role for the circuit and avoids the possibility of peeling.

[0122] In other embodiments, the first circuit sub-layer may also be rectangular or circular, and the embodiment of the present disclosure does not limit this.

[0123] In the embodiment of the present disclosure, the distance between the first circuit sub-layer and the edge of the insulating layer may be greater than or equal to 0.15 mm.

[0124] In the embodiment of the present disclosure, by using the above distance, the entire circuit layer can be wrapped when the subsequent ball head is wrapped, avoiding the ball head from falling off.

[0125] Exemplarily, the distance between the first circuit sub-layer and the edge of the insulating layer is equal to 0.15 mm.

[0126] In the embodiment of the present disclosure, step S12 may include:

[0127] Manufacture the first circuit sub-layer and the second circuit sub-layer on the front and back of the insulating layer respectively, and electroplate and fill the through holes at the through holes to form a circuit connection part to connect the first circuit sub-layer and the second circuit sub-layer.

[0128] S13. Connect the light-emitting diode chip to the first circuit sub-layer, and the hollowed-out pattern is located around the light-emitting diode chip.

[0129] In the embodiment of the present disclosure, a die bonding adhesive (such as solder paste, silver paste or flux, etc.) is used to connect the light-emitting diode chip to the circuit layer.

[0130] In the embodiment of the present disclosure, step S13 may include:

[0131] First step, provide a die bonding adhesive, and the die bonding adhesive is selected from one or more of solder paste, silver paste or flux.

[0132] Second step, coat the die bonding adhesive on the die bonding position of the first circuit sub-layer.

[0133] Third step, place the light-emitting diode chip on the die bonding adhesive.

[0134] Fourth step, place the package structure installed with the light-emitting diode chip in a reflow oven or an eutectic oven, and cure the die bonding adhesive through a high-temperature curing process.

[0135] In the fifth step, through the curing process, the electrodes of the light-emitting diode chip are electrically connected to the first circuit sub-layer, thereby forming an electrical loop.

[0136] In a possible implementation manner of the present disclosure, the light-emitting diode chip can be a blue light chip. In other implementation manners, the light-emitting diode chip can also be a chip of other colors.

[0137] In the embodiments of the present disclosure, each of the hollow areas includes a first area, a second area, and a third area; the first area is parallel to one side of the insulating layer, the second area is parallel to another side adjacent to the side, the third area connects the first area and the second area, and the width of the third area is smaller than the widths of the first area and the second area. The hollow area composed of the above three areas has a relatively large area, and can form a hollow structure surrounding the chip, which can make the bonding part between the subsequent ball head and the insulating layer more uniform, and make the ball head fit more tightly with the insulating layer. In the embodiments of the present disclosure, the first circuit sub-layer has eight sides, and the insulating layer has four sides; four of the eight sides of the first circuit sub-layer are respectively parallel to the four sides of the insulating layer. The first circuit sub-layer with the above shape can expose the insulating layer at the four corners, so that the subsequent ball head can completely wrap the first circuit sub-layer, and make the ball head fit more tightly with the insulating layer. S14. A white glue layer is made around the light-emitting diode chip, and the white glue layer is bonded to the side wall of the light-emitting diode chip, the first circuit sub-layer, and a part of the insulating layer in the hollow pattern.

[0138] In the embodiments of the present disclosure, a piezoelectric valve glue spraying machine is used to spray white glue around the light-emitting diode chip to form a white glue layer. Spraying white glue can effectively prevent the small molecules after die bonding reflow from contacting the ball head silicone, thereby avoiding the problem of blackening of the colloid, and the white glue can extract more side light, improving the brightness of the light-emitting diode chip after encapsulation.

[0139] In the embodiments of the present disclosure, the white glue layer can be a mixture layer of titanium dioxide and silicone resin.

[0140] In the embodiments of the present disclosure, the side wall of the white glue layer away from the light-emitting diode chip is in a slope shape.

[0141] In the embodiments of the present disclosure, the slope shape can make the white glue layer fit more tightly with the circuit layer.

[0142] In the embodiments of the present disclosure, the thickness of the white glue layer can be greater than 1 / 2 of the thickness of the light-emitting diode chip, can also be equal to 1 / 2 of the thickness of the light-emitting diode chip, or can be less than 1 / 2 of the thickness of the light-emitting diode chip.

[0143] In one example, the thickness of the white glue layer is less than 1 / 2 of the thickness of the light-emitting diode chip, and the thickness of the white glue layer is greater than or equal to 50 microns. This thickness design can ensure the reflection efficiency of the white glue layer while ensuring the reflection efficiency of the light-emitting diode and improving the brightness.

[0144] Exemplarily, the thickness of the light-emitting diode chip is 200 microns, the thickness of the white glue layer is less than 100 microns, and the thickness of the white glue layer is greater than or equal to 50 microns. This thickness design can ensure that the thickness of the white glue layer is less than 1 / 2 of the thickness of the light-emitting diode chip, thereby ensuring the reflection efficiency of the light-emitting diode.

[0145] For example, the thickness of the white glue layer is 60 - 80 microns. This thickness design can ensure the reflection efficiency of the light-emitting diode and improve the brightness.

[0146] In the embodiment of the present disclosure, the height difference between the first circuit sub-layer and the insulating layer can be 45 - 75 μm.

[0147] Exemplarily, the height difference between the first circuit sub-layer and the insulating layer is 60 μm.

[0148] S15. Manufacture a ball head, and the ball head covers the insulating layer in the first circuit sub-layer, the light-emitting diode chip, the white glue layer, the hollowed-out pattern, and the insulating layer outside the first circuit sub-layer.

[0149] In the embodiment of the present disclosure, the ball head can be a silicone ball head.

[0150] Exemplarily, use a mold top machine to inject silicone into a mold and bake and cure it to form a ball head by mold topping.

[0151] In the embodiment of the present disclosure, the ball head completely wraps the first circuit sub-layer, which can effectively protect the first circuit sub-layer and prevent the circuit layer from peeling off from the insulating layer.

[0152] After completing the above encapsulation, cut it into single-piece light-emitting diode packaging products according to the scribe lanes.

[0153] In the embodiment of the present disclosure, the circuit layer includes a first circuit sub-layer, a second circuit sub-layer, and a circuit connection part. The circuit connection part passes through a plurality of through holes opened in the insulating layer to connect the first circuit sub-layer and the second circuit sub-layer, making the overall combination of the circuit layer and the insulating layer tighter and effectively improving the adhesion between the circuit layer and the insulating layer; moreover, the circuit connection part passes through a plurality of through holes to make the current distribution more uniform;

[0154] Among them, the first circuit sub-layer has a hollowed-out pattern, so that a height difference is formed between the surface of the circuit layer and the surface of the insulating layer. The hollowed-out pattern is located around the light-emitting diode chip. The white glue layer is bonded to the side wall of the light-emitting diode chip, a part of the insulating layer in the first circuit sub-layer and the hollowed-out pattern. Since the white glue layer flows more slowly on the surface of the insulating layer, the white glue layer stops spreading after flowing a small distance on the insulating layer, which can effectively isolate the white glue layer. In this way, the ball head can contact more surfaces of the insulating layer, making the ball head fit more closely to the insulating layer, and the ball head covers the first circuit sub-layer, protecting the circuit and avoiding the problem that the circuit layer and the ball head are easily detached, thus improving the stability.

[0155] The light-emitting diode packaging structure manufactured in the embodiments of the present disclosure is used to simulate extremely harsh conditions for testing. 22 light-emitting diodes are used to conduct a reliability thermal shock verification experiment. It is powered on for 15 minutes under the condition of -45°C, and then powered on for 15 minutes under the condition of -125°C as one round. The light-emitting diodes of the packaging structure provided by the related technology have surface circuit layer peeling in 150 - 300 rounds, while the light-emitting diode packaging structure provided by the embodiments of the present disclosure has no circuit layer peeling problem in 3000 rounds, effectively solving the problem of LED dead lights caused by circuit layer peeling.

[0156] For the light-emitting diode packaging structure provided by the embodiments of the present disclosure, there are three circuit bridges with a line width of 0.15 - 0.3 mm in a T shape between the die bonding position circuit in the middle of the first circuit sub-layer and the peripheral circuit of the first circuit layer, which disperse the heat and force on the die bonding position circuit of the first circuit layer, thereby enhancing the overall adhesion between the first circuit sub-layer and the insulating layer; the die bonding position is at the center of the entire substrate, the positive and negative electrodes are spaced 0.1 mm apart, and the maximum compatible die bonding chip size is 65 mil. The second circuit sub-layer is thermoelectric integrated, increasing the heat dissipation area of the second circuit sub-layer, and the positive and negative circuit lines are in a triangular shape, which can effectively reduce the solder paste reflow voids during the chip mounting process and enhance the adhesion between the light-emitting diode and the circuit layer.

[0157] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An encapsulation substrate, characterized in that, The encapsulation substrate includes: an insulating layer (101) and a circuit layer (102); The circuit layer (102) includes a first circuit sub-layer (1021), a second circuit sub-layer (1022), and a circuit connection portion (1023). The first circuit sub-layer (1021) and the second circuit sub-layer (1022) are respectively located on two opposite surfaces of the insulating layer (101). The insulating layer (101) has a plurality of through holes (201). The circuit connection portion (1023) passes through the plurality of through holes (201) and is respectively connected to the first circuit sub-layer (1021) and the second circuit sub-layer (1022). The first circuit sub-layer (1021) has a closed hollow pattern (202).

2. The encapsulated substrate according to claim 1, wherein The hollow pattern (202) includes 4 isolated hollow areas (221).

3. The encapsulation substrate according to claim 2, characterized in that, Each hollow area (221) includes a first area (2211), a second area (2212), and a third area (2213). The first area (2211) is parallel to one side of the insulating layer (101). The second area (2212) is parallel to another side adjacent to the side. The third area (2213) connects the first area (2211) and the second area (2212), and the width of the third area (2213) is smaller than the widths of the first area (2211) and the second area (2212).

4. The encapsulated substrate according to claim 1, wherein The first circuit sub-layer (1021) has eight sides, and the insulating layer (101) has four sides. Four of the eight sides of the first circuit sub-layer (1021) are respectively parallel to the four sides of the insulating layer (101).

5. The encapsulation substrate according to claim 2, characterized in that, The first circuit sub-layer (1021) and the second circuit sub-layer (1022) include a negative electrode area (1) and a positive electrode area (2), and the negative electrode area (1) and the positive electrode area (2) are insulated from each other. 2 of the hollow areas (221) are located in the negative electrode area (1), and the other 2 hollow areas (221) are located in the positive electrode area (2).

6. The encapsulated substrate according to claim 5, wherein The negative electrode area (1) and the positive electrode area (2) respectively correspond to 3 of the through holes (201). The 3 through holes (201) are arranged in an isosceles triangle. The 3 through holes (201) corresponding to the negative electrode area (1) and the 3 through holes (201) corresponding to the positive electrode area (2) are symmetrically arranged.

7. The encapsulation substrate according to any one of claims 1 to 6, characterized in that, The thickness of the first circuit sub-layer (1021) is 60 - 75 μm.

8. The encapsulation substrate according to any one of claims 1 to 6, characterized in that, The distance between the first circuit sub-layer (1021) and the edge of the insulating layer (101) is greater than or equal to 0.15 mm.

9. A light-emitting diode packaging structure, characterized in that, The light-emitting diode encapsulation structure includes: an insulating layer (101), a circuit layer (102), a light-emitting diode chip (103), a white glue layer (104), and a ball head (105); The circuit layer (102) includes a first circuit sub-layer (1021), a second circuit sub-layer (1022) and a circuit connection part (1023). The first circuit sub-layer (1021) and the second circuit sub-layer (1022) are respectively located on two opposite surfaces of the insulating layer (101). The insulating layer (101) has a plurality of through holes (201). The circuit connection part (1023) passes through the plurality of through holes (201) and is respectively connected to the first circuit sub-layer (1021) and the second circuit sub-layer (1022). The first circuit sub-layer (1021) has a closed hollowed-out pattern (202). The light-emitting diode chip (103) is located on the first circuit sub-layer (1021). The hollowed-out pattern (202) is located around the light-emitting diode chip (103). The white glue layer (104) is bonded to the side wall of the light-emitting diode chip (103), a part of the insulating layer (101) in the first circuit sub-layer (1021) and the hollowed-out pattern (202). The ball head (105) covers the insulating layer (101) in the first circuit sub-layer (1021), the light-emitting diode chip (103), the white glue layer (104), the hollowed-out pattern (202) and the insulating layer (101) outside the first circuit sub-layer (1021).

10. The light-emitting diode packaging structure according to claim 9, characterized in that, The hollowed-out pattern (202) includes four hollowed-out areas (221), and the four hollowed-out areas (221) are respectively located at the four corners of the light-emitting diode chip (103).

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