Miniature light emitting diode chip and display panel

Abstract

The present invention relates to a micro light emitting diode chip and a display panel, a first micro light emitting diode chip comprising: a micro light emitting diode array comprising a plurality of micro light emitting diodes configured to emit light wherein the micro light emitting diodes comprise a light emitting mesa; the bonding layer is arranged at the bottom of the light-emitting mesa, and the bonding layer comprises a first metal layer, a second metal layer and a third metal layer, and the first metal layer is located below the light-emitting mesa; the second metal layer is located on the bottom layer of the bonding layer, and the outline of the first metal layer is smaller than that of the second metal layer. According to the micro light-emitting diode chip provided by the invention, the bonding layer is provided with the plurality of metal layers, so that the total thickness of the bonding layer can be flexibly controlled by depositing the plurality of metal layers for multiple times in the manufacturing process, the material selection of each metal layer is more flexible, the bonding surface of the light-emitting tabletop can be enlarged, and the bonding strength is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and particularly to a micro light-emitting diode chip and a display panel. Background Art

[0002] Micro Light Emitting Diode (Micro-LED) is an emerging display technology that is becoming increasingly important due to its use in various applications including, for example, self-emissive microdisplays, visible light communication, and optogenetics. Micro-LED technology is a technology that uses micron-scale LEDs as pixel units, thin-films, miniaturizes, and arrays the LED structure design, and then transfers a large number of micro light-emitting diode chips to a TFT or CMOS backplane to form a high-density display panel. Compared with traditional LEDs, Micro LEDs have better strain relaxation, better light extraction efficiency, uniform current diffusion, and higher output performance. Micro LEDs also have advantages such as improved thermal effects, faster response speed, a wider operating temperature range, higher resolution, a wider color gamut, higher contrast, lower power consumption, and higher current density. Micro light-emitting diodes are regarded as the next-generation display technology and are receiving increasing attention.

[0003] However, there are still many problems with existing micro light-emitting diode chips. For example, the light extraction efficiency (Wall-Plug Efficiency, WPE, also known as the electro-optical conversion efficiency) is too low and needs to be further improved. Summary of the Invention

[0004] In view of some or all of the problems in the prior art, the present invention first provides a first micro light-emitting diode chip, comprising:

[0005] A micro light-emitting diode array, the micro light-emitting diode array comprising a plurality of micro light-emitting diodes configured to emit light, wherein the micro light-emitting diode comprises a light-emitting mesa; and

[0006] A bonding layer disposed at the bottom of the light-emitting mesa, wherein the bonding layer comprises:

[0007] A first metal layer located under the light-emitting mesa; and

[0008] A second metal layer located at the bottom layer of the bonding layer, wherein the contour of the first metal layer is smaller than the contour of the second metal layer.

[0009] Further, one or more third metal layers are also disposed between the first metal layer and the second metal layer.

[0010] Further, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or

[0011] The material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or

[0012] The material of the third metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

[0013] Further, the micro light-emitting diode chip further includes:

[0014] A driving module, the driving module includes a driving backplane.

[0015] Further, the micro light-emitting diode chip further includes:

[0016] A current spreading structure, the current spreading structure is located between the micro light-emitting diodes, and the current spreading structure is arranged to surround the micro light-emitting diodes in an electrically contacting manner.

[0017] Further, the micro light-emitting diode chip further includes:

[0018] A microlens, the microlens is arranged above the micro light-emitting diode.

[0019] Further, the driving backplane includes driving electrodes, each micro light-emitting diode corresponds to one driving electrode, and the driving electrode is electrically connected to the bonding layer.

[0020] Further, the material of the driving electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0021] Further, the micro light-emitting diode further includes:

[0022] An ohmic contact layer, the ohmic contact layer is located on the lower surface of the light-emitting mesa, and the ohmic contact layer is electrically connected to the bonding layer;

[0023] A top conductive layer, the top conductive layer is located on the side and top surfaces of the light-emitting mesa, and the top conductive layer is electrically connected to the current spreading structure; and

[0024] A passivation isolation layer, the passivation isolation layer at least partially covers the side surface of the light-emitting mesa, and the passivation isolation layer is located between the light-emitting mesa and the top conductive layer.

[0025] Further, the profile of the ohmic contact layer is larger than the profile of the bottom of the light-emitting mesa.

[0026] Further, the profile of the ohmic contact layer is equal to the profile of the bottom of the light-emitting mesa.

[0027] Further, the profile of the ohmic contact layer is smaller than the profile of the bottom of the light-emitting mesa.

[0028] Further, the electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer.

[0029] Further, adjacent top conductive layers are connected to each other so that all top conductive layers are integrated into one body.

[0030] Further, adjacent passivation isolation layers are connected, and all passivation isolation layers are integrated into one body.

[0031] Further, the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0032] Further, the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension.

[0033] Further, the inclination angle range of the side wall of the light-emitting mesa is: 60° to 85°.

[0034] Further, the bottom lateral dimension of the light-emitting mesa does not exceed 3 microns.

[0035] Further, the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns.

[0036] Further, the light-emitting mesa includes a first-type epitaxial layer, a second-type epitaxial layer, and a light-emitting layer located therebetween.

[0037] Further, the first-type epitaxial layer is electrically connected to the ohmic contact layer;

[0038] The second-type epitaxial layer is electrically connected to the top conductive layer.

[0039] Further, the material of the first-type epitaxial layer is a material layer of a first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the second-type epitaxial layer is a material layer of a second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P;

[0040] The first conductive type is different from the second conductive type.

[0041] Further, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer.

[0042] Further, the bottoms of adjacent current spreading structures are connected, and all the current spreading structures are integrated into a whole.

[0043] Further, the longitudinal cross-section of adjacent current spreading structures presents a bifurcated peak shape.

[0044] Further, the longitudinal cross-section shape of adjacent current spreading structures is asymmetric.

[0045] Further, the material of the current spreading structure is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

[0046] Further, the microlens has an upper curvature portion and a lower spacer portion.

[0047] Further, the height of the lower spacer portion of the microlens is 0.5 to 3 microns; and / or

[0048] the height of the upper curvature portion of the microlens is 0.5 to 2 microns; and / or

[0049] the spherical width of the microlens is 3 to 4 microns.

[0050] Further, the microlens is a positive hemispherical shape.

[0051] Further, the material of the microlens is silicon oxide or silicon nitride or silicon carbide or titanium oxide or zirconium oxide or aluminum oxide.

[0052] Further, adjacent microlenses are spaced apart between the micro light-emitting diodes.

[0053] Further, the sides of adjacent microlenses are spaced apart to form a gap, and the bottom of the gap is higher than the top of the light-emitting mesa.

[0054] Further, the sides of adjacent microlenses are spaced apart to form a gap, and the bottom of the gap is lower than the top of the light-emitting mesa.

[0055] Further, the interior of the microlens includes a closed air gap.

[0056] The present invention also provides a first display panel, including the first micro light-emitting diode chip.

[0057] The present invention also provides a second micro light-emitting diode chip, including:

[0058] A micro light-emitting diode array, the micro light-emitting diode array including a plurality of micro light-emitting diodes configured to emit light, wherein the micro light-emitting diodes include:

[0059] A light-emitting mesa;

[0060] A top conductive layer located on the side and top surfaces of the light-emitting mesa and

[0061] A passivation isolation layer at least partially covering the side of the light-emitting mesa and located between the light-emitting mesa and the top conductive layer.

[0062] Further, the micro light-emitting diode chip further includes:

[0063] An ohmic contact layer located on the lower surface of the light-emitting mesa; and

[0064] A current spreading structure located between the micro light-emitting diodes, the current spreading structure being arranged to surround the micro light-emitting diodes in an electrically contacting manner, and the top conductive layer being electrically connected to the current spreading structure.

[0065] Further, the micro light-emitting diode chip further includes:

[0066] A driving module including a driving backplane and a bonding layer.

[0067] Further, the bonding layer is disposed at the bottom of the light-emitting mesa, wherein the bonding layer includes:

[0068] A first metal layer located under the light-emitting mesa; and

[0069] A second metal layer located at the bottom layer of the bonding layer, wherein the contour of the first metal layer is smaller than the contour of the second metal layer.

[0070] Further, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or

[0071] The material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

[0072] Further, the driving backplane includes driving electrodes, each micro light-emitting diode corresponding to one driving electrode, and the driving electrodes are electrically connected to the bonding layer.

[0073] Further, the material of the driving electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0074] Further, the contour of the ohmic contact layer is larger than the contour of the bottom of the light-emitting mesa; or

[0075] the contour of the ohmic contact layer is equal to the contour of the bottom of the light-emitting mesa; or

[0076] the contour of the ohmic contact layer is smaller than the contour of the bottom of the light-emitting mesa.

[0077] Further, the electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer.

[0078] Further, adjacent top conductive layers are connected to each other so that all top conductive layers are integrated into one body.

[0079] Further, adjacent passivation isolation layers are connected, and all the passivation isolation layers are integrated into one body.

[0080] Further, the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0081] Further, the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension.

[0082] Further, the inclination angle range of the side wall of the light-emitting mesa is: 60° to 85°.

[0083] Further, the bottom lateral dimension of the light-emitting mesa does not exceed 3 microns; and / or

[0084] the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns.

[0085] Further, the light-emitting mesa includes a first-type epitaxial layer, a second-type epitaxial layer, and a light-emitting layer located therebetween.

[0086] Further, the first-type epitaxial layer is electrically connected to the ohmic contact layer;

[0087] the second-type epitaxial layer is electrically connected to the top conductive layer.

[0088] Further, the material of the first-type epitaxial layer is a material layer of a first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the second-type epitaxial layer is a material layer of a second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P;

[0089] The first conductivity type is different from the second conductivity type.

[0090] Further, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, where the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer.

[0091] Further, the bottoms of adjacent current spreading structures are connected, and all the current spreading structures are integrated into a whole.

[0092] Further, the longitudinal cross-section of adjacent current spreading structures presents a bifurcated peak shape.

[0093] Further, the longitudinal cross-section shape of adjacent current spreading structures is asymmetric.

[0094] Further, the material of the current spreading structure is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

[0095] The present invention also provides a second display panel, including the second micro light-emitting diode chip.

[0096] The technical solution provided by the present invention has the following beneficial effects:

[0097] 1. For the two micro light-emitting diode chips provided by the present invention, by making the bonding layer have multiple metal layers, first, the total thickness of the bonding layer can be flexibly controlled by depositing multiple metal layers multiple times during the manufacturing process; second, the material selection of each metal layer is also more flexible. For example, the first metal layer directly contacting the ohmic contact layer can select metal materials such as Cr or Ti or Pt or Ni that are not easily diffused into the ohmic contact layer or will not cause serious consequences even if diffused, or metal materials such as Ni or Au with a small contact resistance with the ohmic contact layer. The intermediate layer can select metals such as Ti or Pt or Au or Sn that can form a good alloy, and the second metal layer at the bottom layer can select metal materials such as Cr or Ti or Pt or Ni with good bonding properties to the driving backplane.

[0098] 2. For the two micro light-emitting diode chips provided by the present invention, by making the contour of the first metal layer directly contacting the bottom of the light-emitting mesa smaller than the contour of the second metal layer at the bottom layer of the bonding layer (the bonding surface size is the size of the bottom second metal layer), compared with the scheme of bonding the bottom of the light-emitting mesa to the driving backplane through a single bonding layer (the bonding surface size is the size of the top first metal layer), the bonding surface of the light-emitting mesa can be increased. The increased bonding surface can improve the bonding strength.

[0099] 3. The first type of micro light-emitting diode chip provided by the present invention has microlenses separated between the micro light-emitting diodes, and a current spreading structure is arranged between the micro light-emitting diodes, which can avoid the optical crosstalk between adjacent micro light-emitting diodes; the microlenses can effectively focus the light emitted by the micro light-emitting diodes onto the main emission angle, reducing the problem of optical crosstalk between the micro light-emitting diodes; the current spreading structure can reflect the light emitted by the micro light-emitting diodes, improving the luminous brightness of the micro light-emitting diode display chip, thereby improving the light extraction efficiency of the micro light-emitting diodes.

[0100] 4. The second type of micro light-emitting diode chip provided by the present invention has a current spreading structure capable of reflecting light arranged between the micro light-emitting diodes, which can avoid the optical crosstalk between adjacent micro light-emitting diodes. In addition, the current spreading structure can reflect the light emitted by the micro light-emitting diodes, improving the luminous brightness of the micro light-emitting diode display chip, thereby improving the light extraction efficiency of the micro light-emitting diodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] To further clarify the above and other advantages and features of the embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present invention and will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0102] Figure 1 A top view schematic diagram of the first type of micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0103] Figure 2 A longitudinal cross-sectional schematic diagram of the first type of micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0104] Figure 3 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode and a driving module according to an embodiment of the present invention is shown;

[0105] Figure 4 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode and a driving module according to another embodiment of the present invention is shown;

[0106] Figure 5 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode and a driving module according to still another embodiment of the present invention is shown;

[0107] Figure 6 A top view schematic diagram of the current spreading structure of the first type of micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0108] Figure 7Schematic longitudinal sectional view of the first type of micro light-emitting diode chip according to another embodiment of the present invention;

[0109] Figure 8 Schematic longitudinal sectional view of the first type of micro light-emitting diode chip according to yet another embodiment of the present invention;

[0110] Figure 9 Schematic longitudinal sectional view of the first type of micro light-emitting diode chip according to still another embodiment of the present invention;

[0111] Figure 10 Schematic top view of the second type of micro light-emitting diode chip according to an embodiment of the present invention; and

[0112] Figure 11 Schematic longitudinal sectional view of the second type of micro light-emitting diode chip according to an embodiment of the present invention. Detailed implementation manners

[0113] In the following description, the present invention is described with reference to the embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in combination with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for the purpose of explanation, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the embodiments shown in the drawings are illustrative representations and not necessarily drawn to scale.

[0114] In the present invention, the reference to "an embodiment" or "the embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" that appears throughout the present invention does not necessarily refer to the same embodiment.

[0115] In the present invention, unless otherwise specified, "arranged on", "arranged above", and "arranged thereon" do not exclude the presence of an intermediate member therebetween. In addition, "arranged on or above" only represents the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged under or below", and vice versa.

[0116] In the present invention, unless otherwise specified, "upper surface", "lower surface", and "side surface" are only used to describe and distinguish the surfaces of the same component.

[0117] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements, and the quantifiers "multiple" and "many" refer to one or more than one element.

[0118] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving this technical effect, and these technical means become obvious under the teachings of the present application.

[0119] In the present invention, the term "at the bottom of the light-emitting mesa" refers to the side of the light-emitting mesa facing away from the microlens, the term "at the top of the light-emitting mesa" refers to the side of the light-emitting mesa facing the microlens, and the term "sides of the light-emitting mesa" refers to the two sides between the top and the bottom.

[0120] In the present invention, the term "outline of the metal layer" refers to the maximum dimension, such as length, in the plane (or the plane perpendicular to the thickness) formed by the length and width of the metal layer. Similarly, the bottom outline of the light-emitting mesa refers to the maximum dimension, such as length, of the light-emitting mesa in the bottom plane (i.e., the plane perpendicular to the thickness at the bottom).

[0121] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.

[0122] First, a first type of micro light-emitting diode chip and a display panel will be described.

[0123] Figure 1 A top view schematic diagram of a first type of micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 1 It includes a micro light-emitting diode 101, a microlens 102, and a current spreading structure 103. Figure 2 A longitudinal cross-sectional schematic diagram of a first type of micro light-emitting diode chip according to an embodiment of the present invention is shown. As shown in the figure, the first type of micro light-emitting diode chip includes a driving module, a micro light-emitting diode 101, a current spreading structure 103, and a microlens 102. A bonding layer 110 is disposed at the bottom of the light-emitting mesa. The micro light-emitting diode 101 includes: a light-emitting mesa 105, an ohmic contact layer 104, a top conductive layer 107, and a passivation isolation layer 106. The micro light-emitting diode 101 is disposed on the upper surface of the driving module. The current spreading structure 103 is located between the micro light-emitting diodes 101, and the current spreading structure 103 is arranged to surround the micro light-emitting diodes 101 in an electrically contacting manner. The microlens 102 is disposed on the upper surface of the micro light-emitting diodes, and adjacent microlenses 102 are spaced apart between the micro light-emitting diodes 101. In one embodiment, the driving module includes a driving backplane 108.

[0124] The size of each micro light-emitting diode chip does not exceed 1 cm, preferably not exceeding 5 mm. The micro light-emitting diodes are formed in an array in the micro light-emitting diode display chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light-emitting diode structure is at the nanometer level, for example, 20 nm to 100 nm. Each micro light-emitting diode can form at least a part of the pixel elements on the micro light-emitting diode display chip.

[0125] For convenience, "upward" is used to indicate away from the driving backplane 108, "downward" indicates toward the driving backplane 108, and other directional terms such as top, bottom, above, below, directly below, underneath, etc. are also interpreted accordingly. In one embodiment, the driving backplane 108 includes a substrate, a driving circuit, and a driving electrode 109. Each micro light-emitting diode corresponds to a driving electrode, and the driving electrode 109 is electrically connected to the bonding layer 110. In one embodiment, the material of the driving electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au. In one embodiment, the substrate is a Si substrate. In another embodiment, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is about 700 microns thick. The driving circuit forms individual pixel drivers to control the operation of each individual pixel LED device. The driving circuit includes, for example, complementary metal oxide semiconductor (CMOS) devices or TFT devices, etc.

[0126] In one embodiment, the micro light-emitting diode can be bonded to the surface of the driving backplane 108 through the bonding layer 110, and the bonding can be completed by means of eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding. In one embodiment, the bonding layer 110 can be disposed on the driving backplane 108. In another embodiment, the bonding layer 110 grows on the driving backplane 108. In one embodiment, the thickness of the bonding layer 110 is 0.1 micron to 3 microns. In a preferred embodiment, the thickness of the bonding layer 110 is 0.6 micron.

[0127] Figures 3 - 5 The longitudinal cross-sectional schematic diagram of the micro light-emitting diode and the driving module of the first type of micro light-emitting diode chip showing three different embodiments of the present invention is shown. As Figures 3 - 5As shown, the bonding layer 110 includes a first metal layer and a second metal layer. The first metal layer is in direct contact with the ohmic contact layer at the bottom of the light-emitting mesa, and the second metal layer is located at the bottom layer of the bonding layer, wherein the contour of the first metal layer is smaller than that of the second metal layer. In one embodiment, one or more third metal layers are further provided between the first metal layer and the second metal layer. By making the bonding layer have multiple metal layers, firstly, the total thickness of the bonding layer can be flexibly controlled by depositing multiple metal layers multiple times during the manufacturing process; secondly, the material selection of each metal layer is also more flexible. For example, the first metal layer in direct contact with the bottom of the ohmic contact layer can select a metal material that is not easily diffused into the ohmic contact layer or will not cause serious consequences even if diffused, or a metal material with a small contact resistance with the ohmic contact layer. The intermediate layer can select a metal material with good conductivity, and the second metal layer at the bottom layer can select a metal material with good bonding property with the driving backplane. In one embodiment, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the third metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bonding layer 110 can also be used as a reflector to reflect the light emitted from the LED structure above.

[0128] As Figure 3 shown, the driving backplane 208 includes a driving electrode 209, and the driving electrode 209 is electrically connected to the bonding layer 210. The micro light-emitting diode 201 includes: a light-emitting mesa 205, an ohmic contact layer 204, a top conductive layer 207, and a passivation isolation layer 206. The ohmic contact layer 204 is electrically connected to the bonding layer 210. The light-emitting mesa 205 includes a first-type epitaxial layer 2052, a second-type epitaxial layer 2051, and a light-emitting layer 2053 located therebetween. The bonding layer 210 includes a first metal layer 2101 and a second metal layer 2102. The first metal layer 2101 is the metal layer in direct contact with the ohmic contact layer at the bottom of the light-emitting mesa 205, and the second metal layer 2102 is the bottom-layer metal of the bonding layer 110, that is, the metal layer far from the bottom of the light-emitting mesa. The contour of the first metal layer 2101 is smaller than that of the second metal layer 2102, and the contour of the ohmic contact layer 204 is larger than that of the bottom of the light-emitting mesa.

[0129] As Figure 4As shown, the driving backplane 308 includes driving electrodes 309, and the driving electrodes 309 are electrically connected to the bonding layer 310. The micro light-emitting diode 301 includes: a light-emitting mesa 305, an ohmic contact layer 304, a top conductive layer 307, and a passivation isolation layer 306. The ohmic contact layer 304 is electrically connected to the bonding layer 310. The light-emitting mesa 305 includes a first-type epitaxial layer 3052, a second-type epitaxial layer 3051, and a light-emitting layer 3053 located therebetween. The bonding layer 310 includes a first metal layer 3101 and a second metal layer 3102. The first metal layer 3101 is the metal layer in direct contact with the ohmic contact layer 304 at the bottom of the light-emitting mesa 305, and the second metal layer 3102 is the bottom metal layer of the bonding layer 310, i.e., the metal layer far from the bottom of the light-emitting mesa. The contour of the first metal layer 3101 is smaller than the contour of the second metal layer 1102, and the contour of the ohmic contact layer 304 is equal to the contour of the bottom of the light-emitting mesa.

[0130] As Figure 5 As shown, the driving module includes a driving backplane 408 and a bonding layer 410. The driving backplane 408 includes driving electrodes 409, and the driving electrodes 409 are electrically connected to the bonding layer 410. The micro light-emitting diode 401 includes: a light-emitting mesa 405, an ohmic contact layer 404, a top conductive layer 407, and a passivation isolation layer 406. The ohmic contact layer 404 is electrically connected to the bonding layer 410. The light-emitting mesa 405 includes a first-type epitaxial layer 4052, a second-type epitaxial layer 4051, and a light-emitting layer 4053 located therebetween. The bonding layer 410 includes a first metal layer 4101 and a second metal layer 4102. The first metal layer 4101 is the metal layer in direct contact with the ohmic contact layer 404 at the bottom of the light-emitting mesa 405, and the second metal layer 4102 is the bottom metal layer of the bonding layer 410, i.e., the metal layer far from the bottom of the light-emitting mesa. The contour of the first metal layer 4101 is smaller than the contour of the second metal layer 4102, and the contour of the ohmic contact layer 404 is smaller than the contour of the bottom of the light-emitting mesa.

[0131] In the present invention, by making the contour of the first metal layer in direct contact with the bottom of the light-emitting mesa smaller than the contour of the second metal layer at the bottom of the bonding layer (the bonding surface size is the size of the bottom second metal layer), compared with the solution of bonding the bottom of the light-emitting mesa to the driving backplane through a single bonding layer (the bonding surface size is the size of the top first metal layer), the bonding surface of the light-emitting mesa can be increased. The increased bonding surface can improve the bonding strength.

[0132] In some embodiments, the driving backplane 108 may adopt an integrated circuit (IC) board. The micro light-emitting diodes are electrically connected to the driving backplane 108, and the driving backplane 108 is used to control the lighting and extinguishing of the micro light-emitting diodes. In some embodiments, the integrated circuit board may be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode may be individually electrically controlled by the integrated circuit board. In some embodiments, the integrated circuit board may be electrically connected to the electrodes of the micro light-emitting diode display chip through metal interconnections. In some embodiments, a dielectric layer may be formed in the gaps between the micro light-emitting diodes. In some embodiments, the dielectric layer may also be formed in the gaps between the interconnections.

[0133] The micro light-emitting diode chip includes a plurality of micro light-emitting diode arrays, and each micro light-emitting diode array includes a plurality of micro light-emitting diodes. The driving method of the micro light-emitting diodes is, for example, passive matrix (PM) driving, in which the cathodes of all the micro light-emitting diodes in each array are commonly connected to the cathode line NL, and the micro light-emitting diodes with the same number in each array are respectively connected to the corresponding anode lines PL. Thus, the on / off and light-emitting brightness of each light-emitting diode can be individually controlled by controlling the signals on the corresponding cathode and anode lines.

[0134] In some embodiments, the micro light-emitting diodes may be arranged on the upper surface of the driving module in a regular or irregular manner as the pixel points of the micro light-emitting diode chip. The micro light-emitting diode includes: an ohmic contact layer 104 located on the lower surface of the light-emitting mesa 105, and the ohmic contact layer 104 is electrically connected to the bonding layer 110. A top conductive layer 107 is located on the side and top surfaces of the light-emitting mesa 105, and the top conductive layer 107 is electrically connected to the current spreading structure 103. A passivation isolation layer 106 at least partially coats the side surface of the light-emitting mesa, and the passivation isolation layer 106 is located between the light-emitting mesa 105 and the top conductive layer 107. In some embodiments, the passivation isolation layer 106 covers a part of the top surface of the light-emitting mesa 105.

[0135] In some embodiments, the electrode polarity of the ohmic contact layer 104 is opposite to that of the top conductive layer 107. For example, the ohmic contact layer 104 can be a P electrode or an anode electrode, and the top conductive layer 107 is an electrode with a polarity opposite to that of the ohmic contact layer 104, such as an N electrode or a cathode electrode. In one embodiment, the ohmic contact layer, the top conductive layer, and their connecting components can be one or more combinations of materials such as graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0136] In one embodiment, adjacent top conductive layers are connected, and all top conductive layers are integrated into one body. In one embodiment, adjacent passivation isolation layers are connected, and all passivation isolation layers are integrated into one body. In one embodiment, the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0137] In some embodiments, a top conductive layer can be formed on the top surface of the micro light-emitting diode array. In some embodiments, the top conductive layer can be shared by all the micro light-emitting diodes in the micro light-emitting diode array. In some embodiments, the light-emitting layer can include at least one quantum well layer. In some embodiments, the micro light-emitting diode array can include a single-layer micro light-emitting diode structure. In some embodiments, the micro light-emitting diode array can include multiple vertically stacked micro light-emitting diode structures.

[0138] In one embodiment, the light-emitting mesa can be a trapezoidal platform, and the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension. In one embodiment, the inclination angle range of the sidewall of the light-emitting mesa is 60° to 85°. In one embodiment, the bottom lateral dimension of the light-emitting mesa does not exceed 3 microns. In one embodiment, the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns. In one embodiment, the lateral dimension of the bonding layer is larger than the bottom lateral dimension of the light-emitting mesa.

[0139] As Figure 2As shown, the light-emitting mesa 105 includes a first-type epitaxial layer 1052, a second-type epitaxial layer 1051, and a light-emitting layer 1053 therebetween. The first-type epitaxial layer is electrically connected to the ohmic contact layer. The second-type epitaxial layer is electrically connected to the top conductive layer. In some embodiments, the light-emitting mesa of each micro light-emitting diode in the micro light-emitting diode array can be a micron-scale light-emitting mesa. In some embodiments, the micron-scale light-emitting mesa can include, from bottom to top, a first-type epitaxial layer, a light-emitting layer, and a second-type epitaxial layer. That is to say, in the three-layer structure, the first-type epitaxial layer is closest to the driving backplane 108; the light-emitting layer is located above the first-type epitaxial layer and is farther from the driving backplane 108; the second-type epitaxial layer is located above the light-emitting layer and is the farthest from the driving backplane 108. In some embodiments, the light-emitting layer is formed by a plurality of stacked quantum well layers, especially superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type epitaxial layer is a semiconductor material of a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first-type light-emitting mesa can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type epitaxial layer can include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer can be formed below the window layer. In some embodiments, the second-type epitaxial layer is a semiconductor material of a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second-type epitaxial layer can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type epitaxial layer can include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer can be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0140] In some embodiments, the first type of epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer can be a material layer composed of at least two or more elements of the second conductive type including Ga, N, As, Al, In, and P, and the first type of epitaxial layer can be a material layer composed of at least two or more elements of the first conductive type including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer further includes an electron blocking layer, and the electron blocking layer is disposed on a first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type of epitaxial layer can also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer is an N-type GaN layer or an N-type AlGaN layer.

[0141] In some embodiments, the light-emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times that of y.

[0142] In some embodiments, one of the first type of epitaxial layer and the second type of epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3 . The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is from 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is from 50 nm to 75 nm, for example 65 nm.

[0143] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is from 0.3 to 0.5, for example x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is from 10 nm to 30 nm, for example 20 nm.

[0144] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is from 50 nm to 70 nm, for example 65 nm.

[0145] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, for example 30 nm.

[0146] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, for example x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example 20 nm.

[0147] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0148] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0149] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0150] The current spreading structure 103 can reflect the light emitted by the micro light-emitting diode, thereby significantly increasing the total light output. At the same time, the current spreading structure 103 can also isolate light and prevent light crosstalk between adjacent light-emitting diodes. By arranging the current spreading structure 103 to surround the micro light-emitting diode in an electrical contact manner and being electrically connected to the top conductive layer 107, the electrical contact area between the current spreading structure 103 and the micro light-emitting diode can be significantly increased, so that the active layer (light-emitting layer) of the micro light-emitting diode can emit light more uniformly, effectively avoiding the situation that only the electrical contact part or its vicinity emits light or the light emission brightness of the electrical contact part or its vicinity is too high.

[0151] Figure 6 Shows a top view schematic diagram of the current spreading structure of the first micro light-emitting diode chip according to an embodiment of the present invention. AsFigure 6 As shown, the bottoms of adjacent current spreading structures 103 are connected, and all the current spreading structures are integrated into a whole. Figure 6 In [description], the top view shape (i.e., cross-sectional shape) of the micro light-emitting diode is circular, and the top view shape of the overall current spreading structure is the remaining grid shape after removing the circle. In one embodiment, the top view shape of the micro light-emitting diode may also be other suitable shapes, such as rectangle, square or regular polygon, etc., and the top view shape of the overall current spreading structure is the remaining shape after removing the other suitable shape, such as the remaining grid shape after removing rectangle, square or polygon. As Figure 2 As shown, the longitudinal profile of adjacent current spreading structures presents a forked peak shape. In one embodiment, the longitudinal profile shapes of adjacent current spreading structures are asymmetric and the heights may not be the same, which is not limited herein.

[0152] In one embodiment, the material of the current spreading structure is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

[0153] Figure 2 In [description], the lateral dimension of the bottom of the microlens 102 is greater than the lateral dimension of the light-emitting area of the micro light-emitting diode. In some embodiments, the lateral dimension of the bottom of the microlens 102 may be equal to the lateral dimension of the light-emitting area of the micro light-emitting diode.

[0154] In some embodiments, one microlens 102 may cover multiple micro light-emitting diodes without lenses. Multiple microlenses form a microlens array. The microlens array is disposed above the micro light-emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro light-emitting diode. The microlens is mainly used for converging and / or collimating light, for example, by adjusting parameters such as the thickness and curvature of the microlens, the focal point of the microlens can be located in the light-emitting mesa of the micro light-emitting diode. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. As Figure 2 As shown, in one embodiment, the microlens 102 includes an upper curvature portion 1021 and a lower spacer portion 1022. In one embodiment, the typical shape of the lower spacer portion of each microlens 102 includes circle, square, rectangle, and hexagon. The microlenses in the microlens array of the display panel may be the same or different in terms of shape, curvature, optical power, size, base, spacer, etc.

[0155] In one embodiment, the centers of curvature at various positions on the sidewalls of the lower spacer do not coincide with the centers of curvature at various positions of the upper curvature portion. The thickness of the lower spacer is set such that the focal point of the microlens is located in the light-emitting mesa of the micro light-emitting diode. In one embodiment, the height of the lower spacer of the microlens is 0.5 to 3 micrometers, and / or the height of the upper curvature portion of the microlens is 0.5 to 2 micrometers, and / or the spherical width of the microlens is 3 to 4 micrometers. In yet another embodiment, the microlens may be, for example, a positive hemisphere.

[0156] In some embodiments, the shape of the microlens 102 may be a curved hemisphere. In some embodiments, the height of the microlens 102 is not greater than 2 micrometers. In some embodiments, the height of the microlens 102 is not greater than 1 micrometer. In some embodiments, the height of the microlens 102 is not greater than 0.5 micrometer. In some embodiments, the width of the microlens 102 is not greater than 4 micrometers. In some embodiments, the width of the microlens 102 is not greater than 3 micrometers. In some embodiments, the width of the microlens 102 is not greater than 2 micrometers. In some embodiments, the width of the microlens 102 is not greater than 1 micrometer. In some embodiments, the ratio of the width to the height of the microlens 102 is greater than 1.5.

[0157] In some embodiments, the microlens 102 may be made of various materials that are transparent to light of various wavelengths emitted by the micro light-emitting diode. Exemplary transparent materials for the microlens 102 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 102 is made of a photoresist. In some embodiments, the microlens is directly deposited on the surface of the micro light-emitting diode by chemical vapor deposition (CVD) technology.

[0158] Figure 7 A longitudinal cross-sectional schematic diagram of a first type of micro light-emitting diode chip according to another embodiment of the present invention is shown. As shown, the micro light-emitting diode chip includes a driving backplane 508, a bonding layer 510, a micro light-emitting diode, a current spreading structure 503, and a microlens 502. The driving backplane 508 includes a driving electrode 509, and the driving electrode 509 is electrically connected to the bonding layer 510. The microlens 502 includes an upper curvature portion 5021 and a lower spacer portion 5022.

[0159] In one embodiment, the bonding layer 510 includes a first metal layer and a second metal layer. The first metal layer is in direct contact with the ohmic contact layer at the bottom of the light-emitting mesa, and the second metal layer is located at the bottom layer of the bonding layer, wherein the contour of the first metal layer is smaller than the contour of the second metal layer.

[0160] The micro light-emitting diode includes: a light-emitting mesa 505, an ohmic contact layer 504, a top conductive layer 507, and a passivation isolation layer 506. The micro light-emitting diode is disposed on the upper surface of the driving module, and the micro light-emitting diode has a light-emitting mesa. A current spreading structure 503 is located between the micro light-emitting diodes, and the current spreading structure 503 is arranged to surround the micro light-emitting diodes in an electrically contacting manner.

[0161] As Figure 7 shown, a microlens 502 is disposed above the micro light-emitting diode. Adjacent microlenses 502 are connected between the micro light-emitting diodes. The sides of adjacent microlenses 502 are spaced apart to form a gap, and the bottom of the gap is higher than the top of the light-emitting mesa. In some embodiments, the driving backplane 508 may employ an integrated circuit (IC) board. The micro light-emitting diode is electrically connected to the driving backplane 508, and the driving backplane 508 is used to control the lighting and extinguishing of the micro light-emitting diode. In some embodiments, the micro light-emitting diodes may be arranged in a regular or irregular manner on the upper surface of the driving module as pixel points of the micro light-emitting diode chip. The ohmic contact layer 504 is located on the lower surface of the light-emitting mesa 505, and the ohmic contact layer 504 is electrically connected to the bonding layer 510. The top conductive layer 507 is located on the side and top surfaces of the light-emitting mesa 505, and the top conductive layer 507 is electrically connected to the current spreading structure 503. The passivation isolation layer 506 at least partially coats the side of the light-emitting mesa, and the passivation isolation layer 506 is located between the light-emitting mesa 505 and the top conductive layer 507. In some embodiments, the passivation isolation layer 506 covers a part of the top surface of the light-emitting mesa 505. The light-emitting mesa 505 includes a first-type epitaxial layer 5052, a second-type epitaxial layer 5051, and a light-emitting layer 5053 located therebetween. The first-type epitaxial layer is electrically connected to the ohmic contact layer. The second-type epitaxial layer is electrically connected to the top conductive layer.

[0162] Figure 7 For the micro light-emitting diode chip shown, adjacent microlenses are spaced apart from each other, and the bottom of the space is higher than the top of the light-emitting mesa, so that all the light emitted upward will not enter the adjacent micro light-emitting diodes, and the light emitted laterally will be reflected by the current spreading structures on both sides, thereby enabling all the light to exit from the corresponding microlenses. In addition, the shorter space will facilitate the simplification of the microlens forming process.

[0163] Figure 8The longitudinal cross-sectional schematic diagram of the first type of micro light-emitting diode chip according to another embodiment of the present invention is shown. As shown in the figure, the micro light-emitting diode chip includes a driving backplane 608, a bonding layer 610, a micro light-emitting diode, a current spreading structure 603, and a microlens 602. The driving backplane 608 includes a driving electrode 609, and the driving electrode 609 is electrically connected to the bonding layer 610. The microlens 602 includes an upper curvature portion 6021 and a lower spacing portion 6022.

[0164] In one embodiment, the bonding layer 610 includes a first metal layer and a second metal layer. The first metal layer is in direct contact with the ohmic contact layer at the bottom of the light-emitting mesa, and the second metal layer is located at the bottom layer of the bonding layer, wherein the profile of the first metal layer is smaller than that of the second metal layer.

[0165] The micro light-emitting diode includes: a light-emitting mesa 605, an ohmic contact layer 604, a top conductive layer 607, and a passivation isolation layer 606. The micro light-emitting diode is arranged on the upper surface of the driving module, and the micro light-emitting diode includes a light-emitting mesa. The current spreading structure 603 is located between the micro light-emitting diodes, and the current spreading structure 603 is arranged to surround the micro light-emitting diodes in an electrically contacting manner.

[0166] As Figure 8 shown, the microlens 602 is arranged on the upper surface of the micro light-emitting diode, adjacent microlenses 602 are connected between the micro light-emitting diodes, the sides of adjacent microlenses 602 are separated to form a gap, and the bottom of the gap is lower than the top of the light-emitting mesa. In some embodiments, the driving backplane 608 can be an integrated circuit (IC) board. The micro light-emitting diode is electrically connected to the driving backplane 608, and the driving backplane 608 is used to control the lighting and extinguishing of the micro light-emitting diode. In some embodiments, the micro light-emitting diodes can be arranged on the upper surface of the driving module in a regular or irregular manner as the pixel points of the micro light-emitting diode chip. The ohmic contact layer 604 is located on the lower surface of the light-emitting mesa 605, and the ohmic contact layer 604 is electrically connected to the bonding layer 610. The top conductive layer 307 is located on the side and top of the light-emitting mesa 605, and the top conductive layer 607 is electrically connected to the current spreading structure 603. The passivation isolation layer 606 at least partially covers the side of the light-emitting mesa, and the passivation isolation layer 606 is located between the light-emitting mesa 605 and the top conductive layer 607. In some embodiments, the passivation isolation layer 606 covers a part of the top surface of the light-emitting mesa 605. The light-emitting mesa 605 includes a first-type epitaxial layer 6052, a second-type epitaxial layer 6051, and a light-emitting layer 6053 located therebetween. The first-type epitaxial layer is electrically connected to the ohmic contact layer. The second-type epitaxial layer is electrically connected to the top conductive layer.

[0167] Figure 8The shown micro light-emitting diode chip has adjacent microlenses with a connecting portion and a gap on the side, and the gap is located above the connecting portion and the bottom of the gap is lower than the top of the light-emitting mesa. Thus, the light emitted to the side can be significantly suppressed from invading adjacent micro light-emitting diodes. This is particularly advantageous when a spacer is provided to increase the distance between the microlens and the light-emitting mesa (for example, such that the focal point of the microlens falls on the light-emitting mesa), because in this case, the side is extended, and the longer gap between the sides of the microlenses can significantly suppress the light in the side direction from invading adjacent micro light-emitting diodes.

[0168] Figure 9 A longitudinal cross-sectional schematic view of a first type of micro light-emitting diode chip according to another embodiment of the present invention is shown. As shown, the micro light-emitting diode chip includes a driving backplane 708, a bonding layer 710, a micro light-emitting diode, a current spreading structure 703, and a microlens 702. The driving backplane 708 includes a driving electrode 709, and the driving electrode 709 is electrically connected to the bonding layer 710. The micro light-emitting diode includes: a light-emitting mesa 705, an ohmic contact layer 704, a top conductive layer 707, and a passivation isolation layer 706. The micro light-emitting diode is arranged on the upper surface of the driving module, and the micro light-emitting diode includes a light-emitting mesa. The current spreading structure 703 is located between the micro light-emitting diodes, and the current spreading structure 703 is arranged to surround the micro light-emitting diodes in an electrically contacting manner. The microlens 702 includes an upper curvature portion 7021 and a lower spacer portion 7022.

[0169] In one embodiment, the bonding layer 710 includes a first metal layer and a second metal layer. The first metal layer is in direct contact with the ohmic contact layer at the bottom of the light-emitting mesa, and the second metal layer is located at the bottom layer of the bonding layer, wherein the profile of the first metal layer is smaller than the profile of the second metal layer.

[0170] As Figure 9As shown, the microlens 702 is disposed on the upper surface of the micro light-emitting diode. Adjacent microlenses 702 are connected between the micro light-emitting diodes. The sides of adjacent microlenses 702 are spaced apart to form a gap. The interior of the microlens 702 includes a closed air gap 7023. In some embodiments, the driving backplane 708 may employ an integrated circuit (IC) board. The micro light-emitting diode is electrically connected to the driving backplane 708, and the driving backplane 708 is used to control the lighting and extinguishing of the micro light-emitting diode. In some embodiments, the micro light-emitting diodes may be arranged on the upper surface of the driving module in a regular or irregular manner as pixel points of the micro light-emitting diode chip. The ohmic contact layer 704 is located on the lower surface of the light-emitting mesa 705, and the ohmic contact layer 704 is electrically connected to the bonding layer 710. The top conductive layer 707 is located on the side and top surfaces of the light-emitting mesa 705, and the top conductive layer 707 is electrically connected to the current spreading structure 703. The passivation isolation layer 706 at least partially covers the side surface of the light-emitting mesa, and the passivation isolation layer 706 is located between the light-emitting mesa 705 and the top conductive layer 707. In some embodiments, the passivation isolation layer 706 covers a part of the top surface of the light-emitting mesa 705. The light-emitting mesa 705 includes a first-type epitaxial layer 7052, a second-type epitaxial layer 7051, and a light-emitting layer 7053 located therebetween. The first-type epitaxial layer is electrically connected to the ohmic contact layer. The second-type epitaxial layer is electrically connected to the top conductive layer.

[0171] Figure 9 For the shown micro light-emitting diode chip, a void is provided within the microlens, and light entering adjacent micro light-emitting diodes can be suppressed through this void, thereby suppressing optical crosstalk. For example, this void can be arranged between the light-emitting mesa and the current spreading structure, or at the connection between two microlenses, such as between the forked peaks of the current spreading structure. Thus, the position for preventing optical crosstalk can be flexibly arranged within the microlens.

[0172] In some embodiments, the micro light-emitting diode array may include blue micro light-emitting diodes. In some embodiments, the pitch of the micro light-emitting diode array, i.e., the minimum center-to-center distance between micro light-emitting diodes, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0173] In one embodiment of the present invention, a first display panel is further provided, and this display panel includes the above-mentioned first micro light-emitting diode display chip.

[0174] Next, a second micro light-emitting diode chip and display panel will be described.

[0175] Figure 10The top view schematic diagram of the second type of micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 10 It includes a micro light-emitting diode 801 and a current spreading structure 803. Figure 11 The longitudinal cross-sectional schematic diagram of the second type of micro light-emitting diode chip according to an embodiment of the present invention is shown. As shown in the figure, the second type of micro light-emitting diode chip includes a driving module, a micro light-emitting diode 801, and a current spreading structure 803. The driving module includes a driving backplane 808 and a bonding layer 810. The micro light-emitting diode 801 includes: a light-emitting mesa 805, an ohmic contact layer 804, a top conductive layer 807, and a passivation isolation layer 806. The micro light-emitting diode 801 is arranged on the upper surface of the driving module. The current spreading structure 803 is located between the micro light-emitting diodes 801, and the current spreading structure 803 is arranged to surround the micro light-emitting diode 801 in an electrically contacting manner. The ohmic contact layer 804 is electrically connected to the bonding layer 810. The top conductive layer 807 is located on the side and top surface of the light-emitting mesa 805, and the top conductive layer 807 is electrically connected to the current spreading structure 803. The passivation isolation layer 806 at least partially covers the side of the light-emitting mesa, and the passivation isolation layer 806 is located between the light-emitting mesa 805 and the top conductive layer 807. In some embodiments, the passivation isolation layer 806 covers a part of the top surface of the light-emitting mesa 805.

[0176] As Figure 11 shown, the bonding layer 810 includes a first metal layer 8101 and a second metal layer 8102. The first metal layer 8101 is in direct contact with the ohmic contact layer 804 at the bottom of the light-emitting mesa 805, and the second metal layer 8102 is located at the bottom layer of the bonding layer 810, wherein the contour of the first metal layer 8101 is smaller than the contour of the second metal layer 8102. In one embodiment, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bonding layer 810 can also be used as a reflector to reflect the light emitted from the LED structure above.

[0177] The size of each micro light-emitting diode chip does not exceed 1 cm, preferably not exceeding 5 mm. The micro light-emitting diodes are formed in an array in the micro light-emitting diode display chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro light-emitting diode structure is in the nanometer range, for example, 20 nm to 100 nm. Each micro light-emitting diode can form at least a part of the pixel element on the micro light-emitting diode display chip.

[0178] For convenience, "upward" is used to indicate away from the driving backplane 808, "downward" indicates toward the driving backplane 808, and other directional terms such as top, bottom, above, below, directly below, beneath, etc. are interpreted accordingly. In one embodiment, the driving backplane 808 includes a substrate, a driving circuit, and driving electrodes 809. Each micro light-emitting diode corresponds to one driving electrode, and the driving electrode 809 is electrically connected to the bonding layer 810. In one embodiment, the material of the driving electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au. In one embodiment, the substrate is a Si substrate. In another embodiment, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is approximately 700 microns thick. The driving circuit forms individual pixel drivers to control the operation of each individual pixel LED device. The driving circuit includes, for example, complementary metal oxide semiconductor (CMOS) devices or TFT devices, etc.

[0179] In one embodiment, the micro light-emitting diodes can be bonded to the surface of the driving backplane 808 through the bonding layer 810, and the bonding can be completed by means of eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding. In one embodiment, the bonding layer 810 can be disposed on the driving backplane 808. In another embodiment, the bonding layer 810 grows on the driving backplane 808. In one embodiment, the thickness of the bonding layer 810 is from 0.1 micron to 3 microns. In a preferred embodiment, the thickness of the bonding layer 810 is 0.6 microns.

[0180] In some embodiments, the driving backplane 808 can employ an integrated circuit (IC) board. The micro light-emitting diodes are electrically connected to the driving backplane 808, and the driving backplane 808 is used to control the lighting and extinguishing of the micro light-emitting diodes. In some embodiments, the integrated circuit board can be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode can be individually electrically controlled by the integrated circuit board. In some embodiments, the integrated circuit board can be electrically connected to the electrodes of the micro light-emitting diode display chip through metal interconnections. In some embodiments, a dielectric layer can be formed in the gaps between the micro light-emitting diodes. In some embodiments, the dielectric layer can also be formed in the gaps between the interconnections.

[0181] The micro light-emitting diode chip includes a plurality of micro light-emitting diode arrays, and each micro light-emitting diode array includes a plurality of micro light-emitting diodes. The driving method of the micro light-emitting diodes is, for example, passive matrix (PM) driving, in which the cathodes of all the micro light-emitting diodes in each array are commonly connected to the cathode line NL, and the micro light-emitting diodes with the same number in each array are respectively connected to the corresponding anode line PL. Thus, the on / off and light-emitting brightness of each light-emitting diode can be individually controlled by controlling the signals on the corresponding cathode line and anode line.

[0182] In some embodiments, the micro light-emitting diodes may be arranged on the upper surface of the driving module in a regular or irregular manner as the pixel points of the micro light-emitting diode chip.

[0183] In some embodiments, the electrode polarity of the ohmic contact layer 804 is opposite to that of the top conductive layer 807. The ohmic contact layer 804 may be, for example, a P electrode or an anode electrode, and the top conductive layer 807 is an electrode with a polarity opposite to that of the ohmic contact layer 804, such as an N electrode or a cathode electrode. In one embodiment, the ohmic contact layer, the top conductive layer, and their connecting components may be a combination of one or more of, for example, graphene, indium tin oxide (ITO), antimony doped zinc oxide (AZO), fluorine doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0184] In one embodiment, adjacent top conductive layers are connected, and all the top conductive layers are connected into a whole. In one embodiment, adjacent passivation isolation layers are connected, and all the passivation isolation layers are connected into a whole. In one embodiment, the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0185] In some embodiments, a top conductive layer may be formed on the top surface of the micro light-emitting diode array. In some embodiments, the top conductive layer may be shared by all the micro light-emitting diodes in the micro light-emitting diode array. In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro light-emitting diode array may include a single-layer micro light-emitting diode structure. In some embodiments, the micro light-emitting diode array may include a plurality of vertically stacked micro light-emitting diode structures.

[0186] In one embodiment, the light-emitting mesa can be a trapezoidal platform, and the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension. In one embodiment, the inclination angle range of the sidewall of the light-emitting mesa is from 60° to 85°. In one embodiment, the bottom lateral dimension of the light-emitting mesa does not exceed 3 microns. In one embodiment, the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns. In one embodiment, the lateral dimension of the bonding layer is larger than the bottom lateral dimension of the light-emitting mesa.

[0187] As Figure 11 shown, the light-emitting mesa 805 includes a first-type epitaxial layer 8052, a second-type epitaxial layer 8051, and a light-emitting layer 8053 located therebetween. The first-type epitaxial layer 8052 is electrically connected to the ohmic contact layer 804. The second-type epitaxial layer 8051 is electrically connected to the top conductive layer 807. In some embodiments, the light-emitting mesa of each micro light-emitting diode in the micro light-emitting diode array can be a micron-scale light-emitting mesa. In some embodiments, the micron-scale light-emitting mesa can include, from bottom to top, a first-type epitaxial layer, a light-emitting layer, and a second-type epitaxial layer. That is to say, in the three-layer structure, the first-type epitaxial layer is closest to the driving backplane 808; the light-emitting layer is located above the first-type epitaxial layer and is farther from the driving backplane 808; the second-type epitaxial layer is located above the light-emitting layer and is the farthest from the driving backplane 808. In some embodiments, the light-emitting layer is formed by a plurality of stacked quantum well layers, especially superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type epitaxial layer is a semiconductor material of a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first-type light-emitting mesa can be, but is not limited to, composed of materials such as Ga, N, As, P, In, or Al, etc. In addition, the first-type epitaxial layer can include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer can be formed below the window layer. In some embodiments, the second-type epitaxial layer is a semiconductor material of a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second-type epitaxial layer can be, but is not limited to, composed of materials such as Ga, N, As, P, In, or Al, etc. In addition, the second-type epitaxial layer can include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer can be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0188] In some embodiments, the first type of epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer can be a material layer composed of at least two or more elements including Ga, N, As, Al, In, and P of the second conductive type, and the first type of epitaxial layer can be a material layer composed of at least two or more elements including Ga, N, As, Al, In, and P of the first conductive type. In some embodiments, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer further includes an electron blocking layer, and the electron blocking layer is disposed on a first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type of epitaxial layer can also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer is an N-type GaN layer or an N-type AlGaN layer.

[0189] In some embodiments, the light-emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9, and the range of y is 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0190] In some embodiments, one of the first type of epitaxial layer and the second type of epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3 . The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is from 50 nm to 75 nm, for example 65 nm.

[0191] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is from 0.3 to 0.5, for example x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is from 10 nm to 30 nm, for example 20 nm.

[0192] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is from 50 nm to 70 nm, for example 65 nm.

[0193] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, such as 30 nm.

[0194] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, such as x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is 10 nm to 30 nm, such as 20 nm.

[0195] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0196] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0197] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0198] The current spreading structure 803 can reflect the light emitted by the micro light-emitting diode, thereby significantly increasing the total light output. At the same time, the current spreading structure 803 can also isolate the light and prevent light crosstalk between adjacent light-emitting diodes. By arranging the current spreading structure 803 to surround the micro light-emitting diode in an electrical contact manner and being electrically connected to the top conductive layer 807, the electrical contact area between the current spreading structure 803 and the micro light-emitting diode can be significantly increased, so that the light-emitting layer of the micro light-emitting diode can emit light more uniformly, effectively avoiding the situation that only the electrical contact part or its vicinity emits light or the light emission brightness of the electrical contact part or its vicinity is too high.

[0199] In some embodiments, the micro light-emitting diode array may include blue micro light-emitting diodes. In some embodiments, the pitch of the micro light-emitting diode array, i.e., the minimum center-to-center distance between the micro light-emitting diodes, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0200] In one embodiment of the present invention, a second display panel is further provided, and the display panel includes the above-mentioned second micro light-emitting diode display chip.

[0201] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It will be apparent to those skilled in the relevant art that various combinations, variations, and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the above-described exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A micro light-emitting diode chip, characterized in that, Comprising: A micro light-emitting diode array, the micro light-emitting diode array comprising a plurality of micro light-emitting diodes configured to emit light, wherein the micro light-emitting diodes comprise a light-emitting mesa; And A bonding layer disposed at the bottom of the light-emitting mesa, wherein the bonding layer comprises: A first metal layer located beneath the light-emitting mesa; And A second metal layer located at the bottom layer of the bonding layer, wherein the contour of the first metal layer is smaller than the contour of the second metal layer.

2. The micro light-emitting diode chip according to claim 1, wherein One or more third metal layers are further disposed between the first metal layer and the second metal layer.

3. The micro light-emitting diode chip according to claim 2, wherein: The material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or The material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or The material of the third metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

4. The micro light-emitting diode chip according to claim 1, characterized in that Further comprising: A driving module, the driving module comprising a driving backplane.

5. The micro light-emitting diode chip according to claim 1, wherein Further comprising: A current spreading structure located between the micro light-emitting diodes, the current spreading structure being arranged to surround the micro light-emitting diodes in an electrically contacting manner.

6. The micro light-emitting diode chip according to claim 1, characterized in that, Further comprising: A microlens disposed above the micro light-emitting diodes.

7. The micro light-emitting diode chip according to claim 4, wherein The driving backplane comprises driving electrodes, each micro light-emitting diode corresponding to one driving electrode, and the driving electrodes are electrically connected to the bonding layer.

8. The micro light-emitting diode chip according to claim 7, wherein The material of the driving electrodes is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

9. The micro light-emitting diode chip according to claim 1, wherein The micro light-emitting diodes further comprise: An ohmic contact layer located on the lower surface of the light-emitting mesa, and the ohmic contact layer is electrically connected to the bonding layer; A top conductive layer located on the side and top surfaces of the light-emitting mesa, the top conductive layer being electrically connected to the current spreading structure; and A passivation isolation layer at least partially covering the side surface of the light-emitting mesa, and the passivation isolation layer is located between the light-emitting mesa and the top conductive layer.

10. The micro light-emitting diode chip according to claim 9, wherein The contour of the ohmic contact layer is larger than the contour of the bottom of the light-emitting mesa.

11. The micro light-emitting diode chip according to claim 9, wherein The contour of the ohmic contact layer is equal to the contour of the bottom of the light-emitting mesa.

12. The micro light-emitting diode chip according to claim 9, wherein The contour of the ohmic contact layer is smaller than the contour of the bottom of the light-emitting mesa.

13. The micro light-emitting diode chip according to claim 9, wherein the electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer.

14. The micro light-emitting diode chip according to claim 9, wherein adjacent top conductive layers are connected to each other such that all top conductive layers are integrated into a whole.

15. The micro light-emitting diode chip according to claim 9, wherein adjacent passivation isolation layers are connected, and all passivation isolation layers are integrated into a whole.

16. The micro light-emitting diode chip according to claim 9, wherein the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

17. The micro light-emitting diode chip according to claim 1, wherein the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension.

18. The micro light-emitting diode chip according to claim 1, wherein the inclination angle range of the sidewall of the light-emitting mesa is: 60° to 85°.

19. The micro light-emitting diode chip according to claim 1, wherein the bottom lateral dimension of the light-emitting mesa does not exceed 3 microns.

20. The micro light-emitting diode chip according to claim 1, wherein the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns.

21. The micro light-emitting diode chip according to claim 1, wherein the light-emitting mesa includes a first-type epitaxial layer, a second-type epitaxial layer, and a light-emitting layer located therebetween.

22. The micro light-emitting diode chip according to any one of claims 9-21, wherein the first-type epitaxial layer is electrically connected to the ohmic contact layer; the second-type epitaxial layer is electrically connected to the top conductive layer.

23. The micro light-emitting diode chip according to claim 21, wherein the material of the first-type epitaxial layer is a material layer of a first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the second-type epitaxial layer is a material layer of a second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P; the first conductive type is different from the second conductive type.

24. The micro light-emitting diode chip according to claim 21, wherein the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer.

25. The micro light-emitting diode chip according to claim 5, wherein the bottoms of adjacent current spreading structures are connected, and all current spreading structures are integrated into a whole.

26. The micro light-emitting diode chip according to claim 5, wherein the longitudinal cross-section of adjacent current spreading structures presents a forked peak shape.

27. The micro light-emitting diode chip according to claim 5, wherein The longitudinal sectional shape adjacent to the current spreading structure is asymmetric.

28. The micro light-emitting diode chip according to claim 5, wherein the material of the current spreading structure is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

29. The micro light-emitting diode chip according to claim 6, wherein the microlens has an upper curvature portion and a lower spacer portion.

30. The micro light-emitting diode chip according to claim 29, wherein the height of the lower spacer portion of the microlens is 0.5 to 3 microns; and / or the height of the upper curvature portion of the microlens is 0.5 to 2 microns; and / or the spherical width of the microlens is 3 to 4 microns.

31. The micro light-emitting diode chip according to claim 6, wherein the microlens is a positive hemisphere.

32. The micro light-emitting diode chip according to claim 6, wherein the material of the microlens is silicon oxide or silicon nitride or silicon carbide or titanium oxide or zirconium oxide or aluminum oxide.

33. The micro light-emitting diode chip according to claim 6, wherein adjacent microlenses are spaced apart between the micro light-emitting diodes.

34. The micro light-emitting diode chip according to claim 6, wherein the sides of adjacent microlenses are spaced apart to form a gap, and the bottom of the gap is higher than the top of the light-emitting mesa.

35. The micro light-emitting diode chip according to claim 6, wherein the sides of adjacent microlenses are spaced apart to form a gap, and the bottom of the gap is lower than the top of the light-emitting mesa.

36. The micro light-emitting diode chip according to claim 6, wherein the interior of the microlens includes a closed air gap.

37. A display panel, characterized in that, including the micro light-emitting diode display chip according to any one of claims 1-36.

38. A micro light-emitting diode chip, characterized in that, Including: a micro light-emitting diode array, the micro light-emitting diode array including a plurality of micro light-emitting diodes configured to emit light, wherein the micro light-emitting diodes include: a light-emitting mesa; a top conductive layer located on the side and top of the light-emitting mesa and a passivation isolation layer that at least partially coats the side of the light-emitting mesa, and the passivation isolation layer is located between the light-emitting mesa and the top conductive layer.

39. The micro light-emitting diode chip according to claim 38, wherein Further including: an ohmic contact layer located on the lower surface of the light-emitting mesa; and a current spreading structure located between the micro light-emitting diodes, the current spreading structure being arranged to surround the micro light-emitting diodes in an electrically contacting manner, and the top conductive layer is electrically connected to the current spreading structure.

40. The micro light-emitting diode chip according to claim 38, wherein, Further including: a driving module including a driving backplane and a bonding layer.

41. The micro light-emitting diode chip according to claim 40, wherein the bonding layer is disposed at the bottom of the light-emitting mesa, and wherein the bonding layer includes: a first metal layer located under the light-emitting mesa; and A second metal layer, which is located at the bottom layer of the bonding layer, wherein the profile of the first metal layer is smaller than that of the second metal layer.

42. The micro light-emitting diode chip according to claim 41, wherein: The material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or The material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

43. The micro light-emitting diode chip according to claim 40, wherein The driving backplane includes driving electrodes, each micro light-emitting diode corresponding to one driving electrode, and the driving electrode is electrically connected to the bonding layer.

44. The micro light-emitting diode chip according to claim 43, wherein The material of the driving electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

45. The micro light-emitting diode chip according to claim 39, wherein The profile of the ohmic contact layer is larger than the profile of the bottom of the light-emitting mesa; or The profile of the ohmic contact layer is equal to the profile of the bottom of the light-emitting mesa; or The profile of the ohmic contact layer is smaller than the profile of the bottom of the light-emitting mesa.

46. The micro light-emitting diode chip according to claim 39, wherein The electrode polarity of the ohmic contact layer is opposite to that of the top conductive layer.

47. The micro light-emitting diode chip according to claim 38, wherein Adjacent top conductive layers are connected to each other such that all top conductive layers are connected into a whole.

48. The micro light-emitting diode chip according to claim 38, wherein Adjacent passivation isolation layers are connected, and all the passivation isolation layers are connected into a whole.

49. The micro light-emitting diode chip according to claim 38, wherein The material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

50. The micro light-emitting diode chip according to claim 38, wherein The bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension.

51. The micro light-emitting diode chip according to claim 38, wherein The inclination angle range of the side wall of the light-emitting mesa is: 60° to 85°.

52. The micro light-emitting diode chip according to claim 38, wherein The bottom lateral dimension of the light-emitting mesa does not exceed 3 microns; and / or The top lateral dimension of the light-emitting mesa does not exceed 1.5 microns.

53. The micro light-emitting diode chip according to claim 38, wherein The light-emitting mesa includes a first type epitaxial layer, a second type epitaxial layer, and a light-emitting layer located therebetween.

54. The micro light-emitting diode chip according to any one of claims 38-53, wherein The first type epitaxial layer is electrically connected to the ohmic contact layer; The second type epitaxial layer is electrically connected to the top conductive layer.

55. The micro light-emitting diode chip according to claim 53, wherein the material of the first type epitaxial layer is a material layer of a first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the second type epitaxial layer is a material layer of a second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P; the first conductive type is different from the second conductive type.

56. The micro light-emitting diode chip according to claim 53, wherein the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer.

57. The micro light-emitting diode chip according to claim 39, wherein the bottoms of adjacent current spreading structures are connected, and all the current spreading structures are integrated into one body.

58. The micro light-emitting diode chip according to claim 39, wherein the longitudinal profile of adjacent current spreading structures presents a forked peak shape.

59. The micro light-emitting diode chip according to claim 39, wherein the longitudinal profile shape of adjacent current spreading structures is asymmetric.

60. The micro light-emitting diode chip according to claim 39, wherein the material of the current spreading structure is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

61. A display panel, characterized in that, including the micro light-emitting diode display chip according to any one of claims 38-60.

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