Miniature light emitting diode chip

Abstract

The invention provides a micro light-emitting diode chip. The micro light-emitting diode chip comprises a substrate; the bottom dielectric layer is located on the substrate; the light-emitting area is located on the bottom dielectric layer, the light-emitting area is provided with a micro light-emitting diode array, and the micro light-emitting diode array is provided with a plurality of micro mesas; and the bottom metal layer is located between the micro light emitting diode array and the bottom dielectric layer, and the bottom metal layer is not electrically connected with the substrate. According to the invention, the alignment error after bonding can be obviously inhibited, so that the need of bonding alignment error compensation or adjustment is eliminated.

Description

Technical Field

[0001] The present invention relates to the field of micro-light-emitting technology, and particularly to a micro light-emitting diode chip. Background Art

[0002] A micro light-emitting diode (Micro Light Emitting Diode) is a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. It integrates an array of micron-scale micro light-emitting diodes on an active addressing driving panel to achieve the lighting and individual control of the micro light-emitting diodes, thereby outputting the desired display image. The core structure of the micro light-emitting diode is a micro mesa, which includes a PN junction diode composed of a direct bandgap semiconductor material. When a forward bias voltage is applied to the micro light-emitting diode between the upper and lower electrodes to cause current to pass through, electrons and holes recombine in the active region, and at the same time, single-color light photons are emitted.

[0003] Currently, in the current manufacturing process of micro light-emitting diode chips, the separately fabricated micro mesas and the driving backplane are usually bonded through a metal bonding layer. Especially when manufacturing products with inverted trapezoidal micro mesas, after the metal bonding process is completed, the overall wafer source will show an offset phenomenon, and this offset direction has no regular pattern, resulting in the offset amount being unable to be uniformly considered, and only compensation or adjustment can be carried out separately according to the results of each exposure (shot). When entering the cathode (N) surface process, each wafer needs to set an exposure program separately. In this way, not only does the workload increase significantly, but the work difficulty also rises sharply, bringing great challenges to the entire manufacturing process. Summary of the Invention

[0004] Starting from the prior art, the task of the present invention is to provide a micro light-emitting diode chip, through which the alignment error after bonding can be significantly suppressed, thereby eliminating the need for bonding alignment error compensation or adjustment.

[0005] According to the present invention, this task is solved by a micro light-emitting diode chip, which includes:

[0006] A light-emitting region having a micro light-emitting diode array with a plurality of micro mesas; and

[0007] A bottom metal layer located at the bottom of the light-emitting region and in contact with the bottom of each of the micro mesas.

[0008] In an embodiment of the present invention, the micro light-emitting diode chip further includes: a bottom dielectric layer located on the outer surface of the bottom metal layer.

[0009] In another embodiment of the present invention, the micro light-emitting diode chip further comprises:

[0010] a substrate;

[0011] an intermediate dielectric layer located on the upper surface of the substrate;

[0012] The bottom dielectric layer is located on the upper surface of the intermediate dielectric layer.

[0013] In another embodiment of the present invention, the interface between the intermediate dielectric layer and the bottom dielectric layer is integrated.

[0014] In another embodiment of the present invention, the micro light-emitting diode chip further comprises: a sidewall dielectric layer covering the sidewalls of the micro mesa, and the bottom metal layer covering the surface of the sidewall dielectric layer and the bottom of the micro mesa.

[0015] In another embodiment of the present invention, the sidewall dielectric layer covers between adjacent micro mesas and at least covers the sidewalls of the micro mesas; the bottom metal layer between adjacent micro mesas is continuous; in the area of the micro light-emitting diode array, the top of the bottom dielectric layer has a structure conforming to the bottom metal layer, such that the bottom metal layer is embedded between the bottom dielectric layer and the sidewall dielectric layer.

[0016] In another embodiment of the present invention, the sidewall dielectric layer between adjacent micro mesas is also located on top of the gap between the micro mesas.

[0017] In another embodiment of the present invention, the bottom metal layer between adjacent micro mesas has a first protrusion; the bottom dielectric layer also has a second protrusion conforming to the first protrusion. The first protrusion is a tip structure; the bottom metal layer is a continuous layer; the first protrusion is a raised ring; the raised ring surrounds the micro mesa.

[0018] In another embodiment of the present invention, the micro light-emitting diode chip further comprises a top conductive layer located at least on top of the micro light-emitting diode array.

[0019] In another embodiment of the present invention, the top conductive layer has a plurality of sidewalls and a hollowed-out area formed by the plurality of sidewalls; the micro mesa has a plurality of light-emitting units, each light-emitting unit comprising N micro mesas, and the hollowed-out area exposes the N micro mesas in the light-emitting unit; the sidewalls are located on the periphery above each light-emitting unit; N is a positive integer.

[0020] In another embodiment of the present invention, the top of the micro mesa has an upward protrusion, the protrusion has a first surface, and the bottom of the top conductive layer is located on the first surface of the protrusion.

[0021] In another embodiment of the present invention, the micro light-emitting diode chip further includes a top electrode layer, which is located above the entire micro light-emitting diode array peripherally and on at least a part of the surface of the top conductive layer.

[0022] In another embodiment of the present invention, the top electrode layer is located on the surface of the top conductive layer at the edge of the micro light-emitting diode array.

[0023] In another embodiment of the present invention, the bottom metal layer is not electrically connected to the substrate; the bottom metal layer has a second surface that extends outward beyond the area of the micro light-emitting diode array; and

[0024] a bottom electrode layer, which is located on the second surface of the bottom metal layer outside the area of the micro light-emitting diode array.

[0025] In another embodiment of the present invention, the second surface is located on one side of the area of the micro light-emitting diode array; in a direction parallel to the top electrode layer, there is a spacer medium between the bottom electrode layer and the top electrode layer.

[0026] In another embodiment of the present invention, the tops of adjacent micro mesa are continuously unbroken; there is also a microlens array on the micro light-emitting diode array.

[0027] The present invention has at least the following technical effects: The present invention realizes dielectric bonding between the micro light-emitting diode and the substrate through the bottom dielectric layer, and preferably eliminates the bonding alignment error. The reasons are as follows. Dielectric bonding of dielectrics such as silicon dioxide refers to the process of connecting two or more dielectric molecules through covalent bonds. The hardness and strength of dielectric bonding are very high. Dielectric fusion bonding can complete alignment and pre-bonding at room temperature, which can eliminate the bonding alignment error caused by thermal expansion, and further eliminates the need to compensate for the bonding alignment error after bonding. Therefore, the chip quality is improved and the manufacturing cost is reduced. Description of the Drawings

[0028] The present invention will be further described below with reference to the accompanying drawings in conjunction with specific embodiments.

[0029] Figure 1 A schematic diagram of a micro light-emitting diode chip according to the present invention is shown;

[0030] Figure 2A - Figure 2D A flowchart of a method for forming a micro light-emitting diode chip according to the present invention is shown; and

[0031] Figure 3 A top view of a micro light-emitting diode chip according to the present invention is shown. Detailed implementation manners

[0032] It should be noted that the components in the respective drawings may be exaggeratedly shown for illustration purposes and are not necessarily to scale. In the respective drawings, the same or functionally identical components are provided with the same reference numerals.

[0033] In the present invention, unless otherwise specified, "arranged on", "arranged above", and "arranged over" do not exclude the existence of an intermediate object therebetween. In addition, "arranged on or above" only represents the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged under or below", and vice versa.

[0034] In the present invention, the respective embodiments are only intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0035] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0036] In the present invention, the term "connected" can refer to both direct connection between the two and indirect connection between the two through an intermediate element.

[0037] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving this technical effect, and these technical means become obvious under the teaching of the present invention.

[0038] It should also be noted here that in the embodiments of the present invention, for clarity and simplicity, only a part of the components or assemblies may be shown, but those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario requirements. Additionally, unless otherwise stated, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of the disclosure or the scope of the record of this application.

[0039] It should also be noted here that within the scope of the present invention, expressions such as "the same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow for a certain reasonable error, that is, the said expressions also cover "substantially the same", "substantially equal", and "substantially equal to". By analogy, in the present invention, the directional terms "perpendicular to", "parallel to", etc. also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0040] In the present invention, the term "configured" refers to setting the shape, structure, material, and / or function of an object to achieve a desired technical effect, where "configured" encompasses various alternative technical means for achieving this technical effect, and these technical means become obvious under the teachings of the present invention.

[0041] In the present invention, the term "light-emitting side of the micro mesa" refers to the side from which the micro mesa (or micro mesa) outputs light, that is, the side from which the light generated by the micro mesa exits the micro mesa and is output outward. For example, the light-emitting side of the micro mesa is the side where the microlens is located. Similarly, the term "side of the micro mesa opposite to the light-emitting side" refers to the side of the micro mesa opposite to the light-emitting side, for example, the side facing the driving circuit or the driving circuit.

[0042] Figure 1 A schematic diagram of a micro light-emitting diode chip 100 according to the present invention is shown.

[0043] As Figure 1 shown, the micro light-emitting diode chip 100 according to the present invention includes an upper stack 100A and a lower stack 100B, wherein the upper stack 100A and the lower stack 100B are dielectrically bonded at the interface A to form a complete micro light-emitting diode chip 100. The structures and components of the upper stack 100A and the lower stack 100B are described in detail below.

[0044] Upper laminate

[0045] The upper stack 100A includes a first dielectric layer 106-1, a micro mesa (or light-emitting mesa, where in this application, the light-emitting mesa and the micro mesa can be used interchangeably) 102, a top conductive layer 109, a first electrode 110 (such as a cathode, or top electrode layer), a second electrode 105 (such as an anode 105), and a microlens 101. Each component is described separately below. In the present invention, the first electrode and the cathode are used interchangeably, and the second electrode and the anode are used interchangeably, but it should be understood that this is merely exemplary, and in other embodiments, the first electrode can be an anode and the second electrode can be a cathode.

[0046] · The first dielectric layer 106-1 (or insulating layer), which is configured to accommodate at least a part of the micro mesa 102 and provide electrical insulation therefor. Here, the first dielectric layer 106-1 has a recess 112, which is configured to accommodate a part 102D-1 of the first epitaxial layer 102D of the micro mesa 102, the light-emitting layer 102C, the second epitaxial layer 102B, and the auxiliary structures of the micro mesa 102. For a detailed description of the micro mesa 102 and its auxiliary structures (such as the passivation layer 103, the bottom transparent conductive layer 102D, etc.), reference may be made to the micro mesa 102 and its description. Here, it should be noted that the recess 112 may be formed after the micro mesa 102, that is, the micro mesa 102 and its auxiliary structures are first formed on the temporary substrate, and then the first dielectric layer 106-1 surrounding them is formed on the micro mesa 102 and its auxiliary structures. The material of the first dielectric layer 106-1 may be, for example, an insulating material such as silicon dioxide, silicon nitride, a high-k material (such as hafnium oxide, aluminum oxide, etc.). The formation method of the first dielectric layer 106-1 may include thermal oxidation, chemical vapor deposition (CVD), etc. The thickness of the first dielectric layer 106-1 is, for example, 1 to 3 μm, preferably 2 μm, and more preferably 0.6 to 1.4 μm. In addition, the first dielectric layer 106-1 may be planarized at the interface A (for example, by chemical mechanical polishing CMP) to facilitate dielectric bonding with the second dielectric layer 106-2.

[0047] The first dielectric layer 106-1 is transparent to the light emitted from the micro mesa 102. In some embodiments, the first dielectric layer 106-1 is made of a dielectric material such as a solid inorganic material. In some embodiments, the solid inorganic material includes silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or any combination thereof. In some embodiments, the first dielectric layer 106-1 facilitates the passage of the light emitted from the micro mesa 102. In some embodiments, the first dielectric layer 106-1 may include multiple parts, such as three embedded dielectric parts and two bonding dielectric parts. The embedded dielectric part refers to the dielectric layer surrounding each light-emitting diode structure; while the bonding dielectric part refers to the dielectric layer between two light-emitting diode structures. The embedded dielectric part and the bonding dielectric part may have the same or different compositions. In one embodiment, according to the position relative to the micro mesa 102, the dielectric layer 106 of the micro light-emitting diode chip 102 can also be divided into: a bottom dielectric layer (i.e., the first dielectric layer 106-1), an intermediate dielectric layer (i.e., the second dielectric layer 106-2), and a sidewall dielectric layer, where the bottom dielectric layer 106-1 is located on the outer surface of the bottom metal layer 104, and the intermediate dielectric layer 106-2 is located on the upper surface of the substrate. The interface between the intermediate dielectric layer 106-2 and the bottom dielectric layer 106-1 is integrated, and the integration can be achieved, for example, through dielectric bonding. The sidewall dielectric layer 106-3 covers the sidewalls of the micro mesa 102, and the bottom metal layer 104 is coated on the surface of the sidewall dielectric layer 106-3 and the bottom of the micro mesa 102. The sidewall dielectric layer 106-3 can, for example, cover at least a part of the gap between adjacent micro mesas 102, such as covering the gap between adjacent micro mesas 102, and at least cover the sidewalls of the micro mesa 102. The bottom metal layer 106-1 between adjacent micro mesas 102 is continuous; in the area of the micro light-emitting diode array, the top of the bottom dielectric layer 106-1 has a structure that conforms to the bottom metal layer 104, such that the bottom metal layer 104 is embedded between the bottom dielectric layer 106-1 and the sidewall dielectric layer 106-3, for example, the top of the bottom dielectric layer 106-1 is in a shape-matching fit with the bottom depression of the bottom metal layer 104. The sidewall dielectric layer 106-3 between adjacent micro mesas 102 is also located on the top of the gap between the micro mesas 102, for example, completely filling the gap between the micro mesas 102

[0048] · The micro mesa 102 is configured to emit light, wherein the area of the top surface (i.e., the upper surface) of the micro mesa 102 is larger than the area of the bottom surface (i.e., the lower surface) of the micro mesa, presenting an "inverted trapezoid" shape. The inclination angle of the micro mesa 102 can be, for example, 90° to 135°. The micro mesa 102 includes a first epitaxial layer 102D, a light-emitting layer 102C, and a second epitaxial layer 102B, wherein the first epitaxial layer 102D is disposed on the top or the upper surface of the micro mesa, i.e., on the side facing the light-emitting surface, the light-emitting layer 102C is disposed in the recess 112 and between the first epitaxial layer 102D and the second epitaxial layer 102B, and the second epitaxial layer 102B is disposed on the bottom or the lower surface of the micro mesa 102, i.e., on the side facing the substrate 108. The light-emitting layer 102C includes, for example, a multiple quantum well layer and an electron blocking layer. In an embodiment of the present invention, the first epitaxial layer 102D is an N-type GaN layer or an N-type AlGaN layer, and the second epitaxial layer 102B is a P-type GaN layer or a P-type AlGaN layer, that is, the material of the second epitaxial layer 102B can be a material layer of a second conductive type composed of two or more elements selected from Ga, N, As, Al, In, and P, and the first epitaxial layer 102D can be a material layer of a first conductive type composed of two or more elements selected from Ga, N, As, Al, In, and P. The multiple quantum well layer is an InGaN / GaN multiple quantum well layer or an InGaN / AlGaN multiple quantum well layer or an InGaAs / AlGaAs multiple quantum well layer. The electron blocking layer is disposed on the first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment of the present invention, the first epitaxial layer can also be a P-type GaN layer or a P-type AlGaN layer, and the second epitaxial layer is an N-type GaN layer or an N-type AlGaN layer. The top width of the micro mesa 102 is, for example, 0.5 to 3 μm, preferably 1.0 to 2.0 μm. The thickness of the first epitaxial layer 102D is, for example, 4000 to 5000 angstroms, the thickness of the light-emitting layer 102C is, for example, 3500 to 4000 angstroms, and the thickness of the second epitaxial layer 102B is, for example, 2500 to 3500 angstroms. 1 angstrom = 10^(-10) meters. From Figure 3It can be seen that the first epitaxial layer 102D extends beyond the recess 112, that is, the first epitaxial layer 102D includes a first portion 102D-1 within the recess 112 and a second portion 102D-2 that extends beyond the recess 112 and extends along both sides of the micro mesa; while the light-emitting layer 102C and the second epitaxial layer 102B are located within the recess 112. In this way, the surface area of the first epitaxial layer 102D is not limited by the opening area of the recess 112, but can be significantly larger than the opening area of the recess 112, thereby significantly increasing the area and thickness of the first epitaxial layer 102D; in addition, since only the light-emitting layer 102C and the second epitaxial layer 102B need to be accommodated within the recess 112, these two layers also have a larger area and thickness compared with the structure that needs to accommodate three layers in the prior art. Therefore, the area and thickness of the epitaxial layer 102 are better increased, and the light emission amount is improved. It can also be seen here that the side portion of the first epitaxial layer 102D, that is, the second portion 102D-2, is electrically connected to the first electrode 110, and the first epitaxial layers 102D of adjacent micro mesas 102 are connected to each other. Thus, in the case of a common cathode structure, that is, the first epitaxial layers of all the micro light-emitting diodes in the same array are connected to a common cathode, such as the cathode 110. Here, the cathode 110 is in electrical contact with the first epitaxial layer 102D through the top conductive layer 109. In this embodiment, the top conductive layer 109 only extends on a part of the surface of the first epitaxial layer 102D. In addition, in this embodiment, the top surface of the micro mesa 102, that is, the first epitaxial layer 102D, has a rough structure 111. For example, the surface of the first epitaxial layer 102D facing the light-emitting side is roughened to form the rough structure 111 so as to guide the light transmitted therefrom to multiple directions, for example, the emitted light can be homogenized. In addition, the top of the micro mesa 102 may have an upward protrusion, and the protrusion has a first surface, and the bottom of the top conductive layer 109 is located on the first surface of the protrusion. In one embodiment, the tops of adjacent micro mesas 102 are continuous without interruption

[0049] The micro mesa 102 further includes accessory structures such as a passivation layer 103, a bottom metal layer 104 (which serves as an anode conductor), a bottom transparent conductive layer 102A, etc. The passivation layer 103 is disposed between the micro mesa 102 and the bottom metal layer 104 and optionally extends on the upper surface of the first dielectric layer 106-1, while the passivation layer 613 is disposed between the inner wall of the recess 112 and the bottom metal layer 104 and optionally extends on the upper surface of the first dielectric layer 106-1. In addition, the bottom metal layer 104 extends beyond the recess 112 and extends to one or both sides of the micro mesa 102, and can be electrically connected to the anode 105 through the top conductive layer 109 at the end. In another embodiment, the passivation layer 103 does not extend on the upper surface of the first dielectric layer 106-1. Instead, it only extends up to the upper surface of the first dielectric layer 106-1, and the upper surface of the first dielectric layer 106-1 is covered by another dielectric layer or dielectric layer (or called a dielectric layer). The function of the passivation layer 103 is not only to reduce current leakage at the sidewalls, but also to passivate sidewall defects, block damage to the micro mesa caused by water, oxygen, etc. during operation, and prevent metal in the bottom metal layer 104, anode 105, etc. from diffusing into the first dielectric layer 611 or the micro mesa 102. In addition, the passivation layer also has the function of electrical insulation, so it is also called the "passivation isolation layer". The passivation layer 103 can be formed by depositing SiO2 material using the CVD process or by depositing Al2O3 material using the ALD process. The bottom transparent conductive layer 102A is disposed between the second epitaxial layer 102B and the bottom metal layer 104. The bottom transparent conductive layer 102A is configured to electrically connect the second epitaxial layer 102B of the micro mesa 102 to the bottom metal layer 104 and then to the anode 105. The material of the bottom transparent conductive layer 102A is, for example, a metal oxide such as indium tin oxide ITO, zinc oxide ZnO, etc., and its forming methods include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), sol-gel method, solution coating method, etc. In this embodiment, the sidewall dielectric layer 103 between adjacent micro mesas 102 is also located at the top of the gap between the micro mesas 102.

[0050] In some embodiments, the light-emitting layer is formed by a plurality of stacked quantum well layers, particularly superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first epitaxial layer is a first-type epitaxial layer and the second epitaxial layer is a second-type epitaxial layer, or vice versa. The first-type epitaxial layer is a semiconductor material having a first conduction type and includes a plurality of semiconductor layers. The main matrix material of the first type of micro mesa can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type epitaxial layer may include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second-type epitaxial layer is a semiconductor material having a second conduction type and includes a plurality of semiconductor layers. The main matrix material of the second-type epitaxial layer can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type epitaxial layer may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment, the first conduction type is different from the second conduction type.

[0051] In one embodiment, the first-type epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second-type epitaxial layer is a P-type GaN layer or a P-type AlGaN layer, that is, the material of the second-type epitaxial layer can be a material layer composed of at least two or more elements of the second conduction type including Ga, N, As, Al, In, P, and the first-type epitaxial layer can be a material layer composed of at least two or more elements of the first conduction type including Ga, N, As, Al, In, P. In one embodiment, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In another embodiment, the first-type epitaxial layer can also be a P-type GaN layer or a P-type AlGaN layer, and the second-type epitaxial layer is an N-type GaN layer or an N-type AlGaN layer.

[0052] · The first electrode 110, which is a cathode here, is conductively disposed on the top conductive layer 109. The cathode 110 is arranged, for example, to surround one or more micro - mesa 102. The anode 105 and its connecting components can be made of materials such as metals (such as copper, silver or aluminum), graphene, ITO, aluminum - doped zinc oxide (AZO) or fluorine - doped tin oxide (FTO), or any combination of the above materials. In yet another embodiment of the present invention, the anode 105 and its connecting components can be made of non - transparent or transparent conductive materials, such as indium tin oxide (ITO). In a preferred embodiment, the cathode 110 is made of a reflective metal (such as copper, silver or aluminum). In this way, the cathode 110 can reflect the light from the micro - mesa 102 while optically isolating adjacent micro - mesa 102 from each other. For example, the light is reflected upward to the microlens 101, thereby increasing the light output. In another embodiment, a reflective layer, such as a silver layer, can be coated on the surface of the cathode 110 to provide the reflective ability. Here, the surface of the cathode 110 facing the micro - mesa 102D is, for example, an inclined surface and is inclined to both sides (i.e., inclined from the bottom surface to both sides), so that the light falling on it can be reflected upward, that is, toward the light - emitting side.

[0053] · The second electrode, which is the anode 105 here, is electrically connected to the bottom metal layer 104 (or bottom conductive reflective layer) that serves as the anode conductor. The bottom metal layer 104 is configured to electrically connect the bottoms of the micro - mesa 102 to each other and optionally reflect the light from the micro - mesa 102 upward (i.e., serve as a mirror layer), while the anode 105 leads out the bottom mirror layer 105 and is electrically connected to an external unit (such as a drive circuit, a control circuit, a power supply, etc.). The material of the anode 105 can include metals (such as gold, nickel, titanium, platinum), metal oxides (such as indium tin oxide, indium zinc oxide, zinc oxide), carbon - based materials (such as graphene, carbon nanotubes), conductive polymers (such as polybenzodifuran diketone), etc. The anode 105 is electrically insulated from the top conductive layer 109, the first epitaxial layer 102D, etc. through an insulator 107, for example. The anode 105 can be arranged to conduct electricity directly on the bottom metal layer 105 or be electrically connected to it through a conductor. The bottom metal layer 104 has an inclined surface on the side facing the micro - mesa 102, and its inclination angle is, for example, the same as the inclination angle of the micro - mesa, which is 90° to 135°. In this embodiment, the bottom metal layer has a tip structure, and the bottom metal layer is a continuous layer and has a plurality of raised rings that surround the micro - mesa 102. The bottom metal layer 104 between adjacent micro - mesas 102 has a first protrusion 104 - 1, and the bottom dielectric layer 106 also has a second protrusion 106 - 4 that conforms to the first protrusion 104 - 1. The first protrusion 104 - 1 is a tip structure, the bottom metal layer 104 is a continuous layer, the first protrusion 104 - 1 is a raised ring, and the first protrusion 104 - 1 surrounds the micro - mesa. For example, the first protrusion 104 - 1 is a flat - topped ring surrounding the light - emitting mesa, and its cross - section is a hollow trapezoid, and the inside of the hollow trapezoid is partially or completely filled by the second protrusion 106 - 4. In this embodiment, the bottom metal layer 104 has a second surface that extends outward beyond the top electrode layer and has a bottom conductive layer located on the bottom surface of the micro - mesa. The second surface of the bottom metal layer 104 is higher than the bottom of the bottom metal layer located at the bottom of the micro - mesa 102. Optionally, the material of the bottom metal layer 104 can include ITO.

[0054] Here, the bottom metal layer 104 has a side structure, a bottom surface structure, and an edge structure, where the side structure and the bottom surface structure constitute the main body of the anode 104. The side structure covers at least a part of the side surface of the micro mesa 102. Both the side structure and the bottom surface structure are configured to reflect the light from the micro mesa 102 upward, and the bottom surface structure is further configured to electrically connect the bottom transparent conductive layer 102A. The edge structure 102 extends to both sides of the micro mesa 102 and is optionally electrically connected to the bottom metal layer 104 of the adjacent micro mesa 102. In this embodiment, the side structure covers the side surface of the part of the micro mesa 102 within the recess 112, and the side structure is formed between the passivation layer 103 and the inner wall of the recess 112 of the dielectric layer. Due to the presence of the passivation layer 103, the side structure may or may not have an atomic layer deposition layer on the side facing the micro mesa 102. In the case of having an atomic layer deposition layer, it is possible to further prevent the metal in the bottom metal layer 104 from penetrating through the passivation layer 103 into the micro mesa 102. The side structure has an inclined surface on the side facing the micro mesa 102 to reflect the light from the micro mesa upward, and its inclined angle is, for example, the same as the inclined angle of the micro mesa 102, which is 90° to 135°. The bottom surface structure covers at least a part of the bottom surface of the micro mesa 102. In this embodiment, the bottom surface structure covers the bottom transparent conductive layer 102A of the micro mesa 102. The bottom surface structure 104B may, for example, have an atomic layer deposition layer on the side facing the micro mesa 102. The atomic layer deposition layer can block the metal from the reflective metal layer to prevent its diffusion without substantially affecting light reflection.

[0055] The bottom metal layer 104 can be formed, for example, by evaporation, sputtering, chemical vapor deposition (CVD), etc., where the atomic layer deposition layer 201 of the bottom metal layer 104 is formed by atomic layer deposition. The thickness of the passivation layer 103 between the bottom metal layer 104 and the micro mesa 102 is 800 to 2000 angstroms, preferably 1000 to 1100 angstroms. The bottom metal layer 104 and its connecting components can be made of materials such as metals (such as copper, silver, or aluminum), graphene, ITO, aluminum-doped zinc oxide (AZO), or fluorine-doped tin oxide (FTO), or any combination of the above materials. Here, from Figure 1As can be seen, the bottom metal layer 104 is not electrically connected to the substrate 108, that is, there is no electrical connection between them. This is because the upper stack 100A and the stack 100B are joined to each other by dielectric bonding, especially silicon dioxide bonding, so preferably no conductor such as metal passes through the bonding interface A. By doing so, a pure dielectric bonding can be ensured, and the bonding alignment shift caused by reasons such as thermal expansion and contraction can be avoided. When the bottom metal layer 104 is not led out from the bottom substrate 108, it can be led out from the side. For example, the bottom metal layer 105 can be led out from positions on both sides of the microtable 102 and electrically connected to the anode 105 through the top conductive layer 109. In this embodiment, the bottom metal layer 104 is also located in the gap between adjacent microtables 102, and is coated on the surface of the sidewall dielectric layer 103 or separated from the microtable 102 by the side dielectric layer 103. In one embodiment, in a direction parallel to the top electrode layer 105, there is a gap between the second surface of the bottom metal layer 104 and the top electrode layer 105. The gap is formed by an edge dielectric layer, for example, and the bottom conductive layer is also located on the second surface and not in the area where the gap is located. In addition, a bottom electrode layer can also be arranged on the bottom conductive layer on the second surface.

[0056] · The top conductive layer 109 is disposed on the first epitaxial layer 102D and electrically connects it to the cathode 110. In addition, the top conductive layer 109 is also disposed on the bottom metal layer 109 and electrically connects it to the anode 105. The function of the top conductive layer 109 is, for example, to facilitate the electrical contact between the first epitaxial layer 102D and the cathode 110 and the electrical contact between the bottom metal layer 109 and the anode 105. Here, the top conductive layer 109 extends only on a part of the first epitaxial layer 102D, but does not cover the rough structure 111 on the first epitaxial layer 102D. In other embodiments, the top conductive layer 109 may also completely cover the first epitaxial layer 102D, thereby providing a good electrical contact between the anode 105, the first epitaxial layer 102D and the cathode 110, thus expanding the power supply area for the first epitaxial layer 102D. The top conductive layer 109 is preferably made of a transparent conductive material, and its materials are, for example, metal oxides such as indium tin oxide ITO, zinc oxide ZnO, etc. Its forming methods include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), sol-gel method, solution coating method, etc. The top conductive layer 109 may, for example, have a hollowed-out area and sidewalls, and the sidewalls are located at the periphery of N micro-tabletops; N is a positive integer. The top conductive layer 109 has a plurality of sidewalls 109-2 and a hollowed-out area 109-1 surrounded by the plurality of sidewalls 109-2. The sidewalls 109-2 may, for example, form a part of the cathode 110 or exist independently. For example, the chip 100 has a plurality of light-emitting units, each light-emitting unit includes N micro-tabletops 102, and the hollowed-out area 109-1 exposes the N micro-tabletops 102 in the light-emitting unit; the sidewalls are located at the periphery above each light-emitting unit; N is a positive integer. In this embodiment, N = 2, but N may also be other numbers.

[0057] · The microlens 101 is disposed above the microtable 102 for shaping the light emitted therefrom, such as converging or collimating. The microlens includes a lens portion 101A and a spacer portion 101B. The lens portion 101A is arranged on the outermost side, i.e., the uppermost side, and is configured to shape the light from the microtable 102. The spacer portion 101B is arranged between the lens portion 101A and the microtable 102 to adjust the focal position of the lens portion 101A. For example, by adjusting parameters such as the thickness of the spacer portion 101B and the curvature of the lens portion 101A, the focal point of the lens portion 101A can be exactly located in the microtable 102 of the micro light-emitting diode. The focal length of the lens portion can be, for example, below the spacer portion 101B. The width of the microlens 101 is, for example, 0.8 to 4 μm, preferably 1 to 3 μm. The distance between the lens portion 101A and the anode 105 is, for example, 0.05 to 4 μm, preferably 0.1 to 0.3 μm. The microlenses 101 and the microtables 102 are in one-to-one correspondence. At the same time, in this embodiment, there is a gap between adjacent microlenses 101 and their bottoms are connected to each other through a connecting portion 101C. The connecting portion 101C especially connects the lens portions 101A of adjacent microlenses 101 to each other. The microlens 101 can be formed by multiple depositions. During the formation of the microlens, first, an SiO2 film layer needs to be deposited, and then ion etching is performed. The microlens is formed at the positions on the surface of the transparent conductive layer 109 corresponding to the respective microtables 102. There may be a gap between adjacent lens portions 101A, and a partial surface of the spacer portion 101B may be exposed at the bottom of the gap.

[0058] Lower laminate

[0059] The lower stack 100B includes a second dielectric layer 106-2 and a substrate 108. Each component will be described separately below.

[0060] · The second dielectric layer 106-2 is disposed on the substrate 108 and is configured to be dielectrically bonded to the first dielectric layer 106-1. The material of the second dielectric layer 106-2 can be, for example, silicon dioxide, silicon nitride, high-k materials (such as hafnium oxide, aluminum oxide, etc.), and so on. The second dielectric layer 106-2 can be formed on the substrate 108, for example, by thermal oxidation, chemical vapor deposition (CVD), etc. The thickness of the second dielectric layer 106-2 is, for example, 1 to 3 μm, preferably 2 μm, more preferably 0.6 to 1.4 μm. In addition, the second dielectric layer 106-2 can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to facilitate dielectric bonding with the first dielectric layer 106-1.

[0061] The second dielectric layer 106-2 can be transparent to the light emitted from the micro mesa 102. In some embodiments, the second dielectric layer 106-2 is made of a dielectric or electrically insulating material such as a solid inorganic material. In some embodiments, the solid inorganic material includes silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or any combination thereof. In some embodiments, the second dielectric layer 106-2 facilitates the passage of the light emitted from the micro mesa 102. In some embodiments, the second dielectric layer 106-2 may include multiple portions, such as three embedded dielectric portions and two bonding dielectric portions. The embedded dielectric portions refer to the dielectric layers surrounding each light emitting diode structure; while the bonding dielectric portions refer to the dielectric layers between two light emitting diode structures. The embedded dielectric portions and the bonding dielectric portions may have the same or different compositions.

[0062] After the lower stack 100A and the upper stack 100B are formed, the lower stack 100A is joined to the upper stack 100A by dielectric bonding such that the first dielectric layer 106-1 is bonded to the second dielectric layer 106-2. The present invention solves the bonding alignment error problem by separately fabricating the upper stack 100A and the lower stack 100B and then joining the two to each other by dielectric bonding (especially silicon dioxide bonding).

[0063] · A substrate 108, which is configured to carry a light-emitting diode array. In addition, the substrate 108 can be used to grow a dielectric layer, such as silicon dioxide. Optionally, the substrate 108 can be either a non-conductive substrate or act as a driving circuit (referred to as a driving backplane in this case). In this case, the driving backplane can have an interconnection of a conductive line layer to a corresponding bottom metal layer 104 and can be, for example, a thin-film transistor (TFT) driving circuit, and can include a 2T1C driving circuit, a 3T1C driving circuit, and a 5T2C driving circuit. The substrate 108 can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate 108 can also be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer. In one embodiment, the bottom metal layer 104 is not electrically connected to the substrate 108. For example, the two are electrically insulated by a dielectric layer 106, and there is no via contact between them. The bottom metal layer 104 has a second surface 104-2 that extends outward beyond the micro-light-emitting diode array region, and a bottom electrode layer 109-1 is located on the second surface 104-2 outside the region of the bottom metal layer 104 that extends beyond the micro-light-emitting diode array region. The second surface 104-2 is located on one side of the micro-light-emitting diode array region; in a direction parallel to the top electrode layer 109, there is a spacer dielectric (such as the material of a microlens, such as silicon dioxide) between the bottom electrode layer 109-1 and the top electrode layer 109.

[0064] An example of dielectric bonding can include:

[0065] First, perform dielectric-to-dielectric preliminary bonding (i.e., preliminary bonding between the first dielectric layer 106-1 and the second dielectric layer 106-2): At room temperature, an extremely flat and smooth dielectric surface obtained by chemical mechanical polishing (CMP) is activated by methods such as plasma treatment and then closely contacted at room temperature to achieve preliminary bonding. Since the covalent bond between silicon dioxides is relatively tight, after preliminary bonding, the first dielectric layer 106-1 and the second dielectric layer 106-2 are tightly bonded, which can prevent offset during subsequent heating.

[0066] Then, heat the upper and lower stacks to 200 - 400 °C for annealing treatment to strengthen the dielectric bonding, thereby achieving dielectric bonding.

[0067] Figures 2A - 2D Shows the flow of a method for forming a micro-light-emitting diode chip according to the present invention.

[0068] As Figure 2AAs shown, in step S1, a temporary substrate 100C is provided, and a micro mesa 102 and its associated structures (such as a passivation layer, a bottom metal layer, a bottom transparent conductive layer, etc.) and a first dielectric layer 106-1 are formed on the temporary substrate 100A. The micro mesa 102 and the first dielectric layer 106-1 constitute the upper stack 100A. The temporary substrate 106 is used for the epitaxial growth of the epitaxial layer, i.e., the first epitaxial layer, the light-emitting layer, and the second epitaxial layer, and is used to carry the epitaxial layer and the transparent conductive layer in subsequent processes. The thickness of the temporary substrate 100C can be, for example, 600 to 1000 μm, preferably 800 μm. After the relevant processes are completed, the temporary substrate 100C can be removed, for example, by debonding and grinding, such as CMP to remove the temporary substrate 106. The first dielectric layer 106-1 is preferably SiO2. For example, during the formation of the first dielectric layer 106-1, multiple growth-grinding processes can be performed to improve the quality of the bonding interface A of the first dielectric layer 106-1.

[0069] As Figure 2B shown, in step S2, a substrate 108 is provided and a second dielectric layer 106-2 is formed on the substrate 108. The substrate 108 and the second dielectric layer 106-2 constitute the lower stack 100B. The second dielectric layer 106-2 is preferably SiO2. For example, during the formation of the second dielectric layer 106-2, multiple growth-grinding processes can be performed to improve the quality of the bonding interface A of the second dielectric layer 106-2.

[0070] As Figure 2C shown, in step S3, the temporary substrate 100C is removed, and the upper stack 100A and 100B are bonded to each other by dielectric bonding. The method of removing the temporary substrate includes, for example, debonding and grinding, such as CMP. Dielectric bonding can include the following steps: First, perform dielectric-to-dielectric preliminary bonding (i.e., preliminary bonding between the first dielectric layer 106-1 and the second dielectric layer 106-2, and after bonding, a dielectric layer 106 is formed): At room temperature, the extremely flat and smooth dielectric surface obtained by chemical mechanical polishing (CMP) is activated by methods such as plasma treatment and then closely contacted at room temperature to achieve preliminary bonding. Since the covalent bond between silica is relatively tight, after preliminary bonding, the first dielectric layer 106-1 and the second dielectric layer 106-2 are tightly bonded, which can prevent offset during the subsequent heating process; then, the upper and lower stacks are heated to 200-400 °C for annealing treatment to strengthen the dielectric bonding, thereby achieving dielectric bonding.

[0071] As Figure 2D shown, in step S4, other structures of the micro light-emitting diode chip, such as a microlens 101, a top conductive layer 109, a cathode, etc., are formed on the upper stack 100A. The forming method includes, for example, etching, deposition, photolithography, grinding, etc.

[0072] As can be seen from the above, the present invention realizes dielectric bonding between the micro light-emitting diode and the substrate through the bottom dielectric layer, which preferably eliminates the bonding alignment error, and the reasons are as follows. Dielectric bonding of dielectrics such as silicon dioxide refers to the process of connecting two or more dielectric molecules together through covalent bonds. The hardness and strength of dielectric bonding are very high. Dielectric fusion bonding can complete alignment and pre-bonding at room temperature, which can eliminate the bonding alignment error caused by thermal expansion, and further eliminates the need to compensate for the bonding alignment error after bonding. Therefore, the chip quality is improved and the manufacturing cost is reduced.

[0073] Figure 3 A top view of a micro light-emitting diode chip according to the present invention is shown.

[0074] As Figure 3 shown, it can be seen from the top view that the micro light-emitting diode chip includes an active region 200, a bottom metal layer 104, an anode 105, and an insulator 201. The active region includes a plurality of micro diodes 201 and a top conductive layer 109 for connecting the micro light-emitting diodes 201 to the anode 105. The bottom metal layer 104 and the anode 105 are implemented as top metal layers herein and are electrically insulated from each other by the insulator 201. The insulator 201 can be a passivation layer, a part of a dielectric layer, or an insulating isolation strip formed separately.

[0075] Although some embodiments of the present invention have been described in this application document, those skilled in the art can understand that these embodiments are merely shown as examples. Those skilled in the art can conceive of numerous variant schemes, alternative schemes, and improvement schemes under the teaching of the present invention without exceeding the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover the methods and structures within the scope of these claims themselves and their equivalent transformations.

Claims

1. A micro light-emitting diode chip, characterized in that, Comprising: A light-emitting region having a micro light-emitting diode array with a plurality of micro mesa surfaces; And A bottom metal layer located at the bottom of the light-emitting region and in contact with the bottom of each of the micro mesa surfaces at the bottom of each micro mesa surface.

2. The micro light-emitting diode chip according to claim 1, characterized in that, The micro light-emitting diode chip further comprises: A bottom dielectric layer located on the outer surface of the bottom metal layer.

3. The micro light-emitting diode chip according to claim 1, wherein Further comprising: A substrate; An intermediate dielectric layer located on the upper surface of the substrate; The bottom dielectric layer is located on the upper surface of the intermediate dielectric layer.

4. The micro light-emitting diode chip according to claim 3, wherein, The interface between the intermediate dielectric layer and the bottom dielectric layer is integrated.

5. The micro light-emitting diode chip according to claim 2, characterized in that Further comprising: A sidewall dielectric layer covering the sidewalls of the micro mesa surfaces, and the bottom metal layer covering the surface of the sidewall dielectric layer and the bottom of the micro mesa surfaces.

6. The micro light-emitting diode chip according to claim 5, characterized in that, The sidewall dielectric layer covers between adjacent micro mesa surfaces and at least covers the sidewalls of the micro mesa surfaces; the bottom metal layer between adjacent micro mesa surfaces is continuous; in the region of the micro light-emitting diode array, the top of the bottom dielectric layer has a structure conforming to the bottom metal layer such that the bottom metal layer is embedded between the bottom dielectric layer and the sidewall dielectric layer.

7. The micro light-emitting diode chip according to claim 5, characterized in that, The sidewall dielectric layer between adjacent micro mesa surfaces is also located on top of the gap between the micro mesa surfaces.

8. The micro light-emitting diode chip according to claim 2, wherein The bottom metal layer between adjacent micro mesa surfaces has a first protrusion; the bottom dielectric layer also has a second protrusion conforming to the first protrusion, and the first protrusion is a tip structure; The bottom metal layer is a continuous layer; the first protrusion is a raised ring; the raised ring surrounds the micro mesa surface.

9. The micro light-emitting diode chip according to claim 1, wherein The micro light-emitting diode chip further comprises a top conductive layer located at least on top of the micro light-emitting diode array.

10. The micro light-emitting diode chip according to claim 9, characterized in that, The top conductive layer has a plurality of sidewalls and a hollowed-out region formed by the plurality of sidewalls; The micro light-emitting diode chip has a plurality of light-emitting units, each light-emitting unit including N micro mesa surfaces, and the hollowed-out region exposes the N micro mesa surfaces in the light-emitting unit; The sidewalls are located on the periphery above each light-emitting unit; N is a positive integer.

11. The micro light-emitting diode chip according to claim 10, characterized in that, The top of the micro mesa surface has an upward protrusion with a first surface, and the bottom of the top conductive layer is located on the first surface of the protrusion.

12. The micro light-emitting diode chip according to claim 9, wherein Further comprising a top electrode layer located on the periphery above the entire micro light-emitting diode array and on at least a part of the surface of the top conductive layer.

13. The micro light-emitting diode chip according to claim 12, wherein The top electrode layer is located on the surface of the top conductive layer at the edge of the micro light-emitting diode array.

14. The micro light-emitting diode chip according to claim 3, wherein The bottom metal layer is not electrically connected to the substrate; the bottom metal layer has a second surface extending outward beyond the region of the micro light-emitting diode array; And A bottom electrode layer located on the second surface of the bottom metal layer outside the region of the micro light-emitting diode array.

15. The micro light-emitting diode chip according to claim 14, wherein, The second surface is located on one side of the region of the micro light-emitting diode array; in a direction parallel to the top electrode layer, there is a spacer dielectric between the bottom electrode layer and the top electrode layer.

16. The micro light-emitting diode chip according to claim 1, wherein The tops of adjacent micro mesa surfaces are continuous without interruption; a microlens array is further provided on the micro light-emitting diode array.

Images