Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a pixel circuit, a data line and a reset signal line, wherein the data line and the reset signal line extend along a first direction; one pixel circuit is overlapped with one data line and one reset signal line respectively; every two adjacent pixel circuits in the second direction are in a symmetrical relation. A node connecting line is connected between a first via hole in the pixel circuit and a grid electrode of the driving transistor, and a data line is connected with the data writing transistor through a second via hole; the first pixel circuit and the second pixel circuit are adjacent in the second direction, a first connecting part in the first pixel circuit is located between the first via hole and the second via hole, and the first connecting part is connected between the reset signal line and a first transistor in the first pixel circuit; a dummy line segment in the second pixel circuit is located between the first via hole and the second via hole. According to the invention, the symmetry of wiring structures in two adjacent pixel circuits can be improved, and the problem of four-direction color cast can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) has the characteristic of self-luminescence. OLED display screens have the advantages of being thin, light, high in brightness, low in power consumption, fast in response, high in clarity, good in flexibility, and high in luminous efficiency, and can meet the new demands of consumers for display technologies. At present, some display panels still have the problem of four-direction color shift, which affects the overall display effect. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to improve the four-direction color shift problem of the display panel and enhance the overall display effect.

[0004] In a first aspect, embodiments of the present invention provide a display panel. The display panel includes a pixel circuit, a data line extending along a first direction, and a reset signal line; along a direction perpendicular to the plane where the display panel is located, one pixel circuit overlaps with a data line and a reset signal line respectively; two adjacent pixel circuits in a second direction are symmetric about a first virtual line, the first virtual line extends along the first direction, and the second direction intersects with the first direction. The pixel circuit includes a driving transistor, a data writing transistor, a first transistor, a first via, and a second via. A node connection line is connected between the first via and the gate of the driving transistor, and the data line is connected to the data writing transistor through the second via. The adjacent pixel circuits in the second direction include a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first connection part, the first connection part is located between the first via and the second via, and the first connection part is connected between the reset signal line and the first transistor in the first pixel circuit. The second pixel circuit includes a dummy segment, and the dummy segment is located between the first via and the second via.

[0005] In a second aspect, based on the same inventive concept, embodiments of the present invention further provide a display device, and the display device includes the display panel provided in any embodiment of the present invention.

[0006] The display panel and the display device provided by the embodiments of the present invention have the following beneficial effects: Two pixel circuits adjacent in the second direction are in a symmetrical relationship. In the first pixel circuit and the second pixel circuit adjacent in the second direction, a first connection portion is provided between a first via hole and a second via hole in the first pixel circuit, and a dummy line segment is additionally provided between the first via hole and the second via hole in the second pixel circuit. The position of the dummy line segment in the second pixel circuit is basically symmetrical to the position of the first connection portion in the first pixel circuit. Thereby, the symmetry of the wiring structure in two pixel circuits adjacent in the second direction can be improved, which is beneficial to improving the four-direction color shift problem and enhancing the display effect. In addition, since the first via hole in the pixel circuit is connected to the gate of the driving transistor through a node connection line, and the second via hole is connected to the data line, after the dummy line segment provided between the first via hole and the second via hole is connected to a constant voltage, it can also play a shielding role, reduce the parasitic capacitance between the data line and the node connection line, improve the crosstalk problem, and enhance the display effect of the display panel. Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0008] Figure 1 It is a schematic diagram of a pixel circuit provided by an embodiment of the present invention; Figure 2 It is a partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 3 It is another schematic diagram of a display panel provided by an embodiment of the present invention; Figure 4 For Figure 3 It is a superimposed schematic diagram of a semiconductor layer and a first metal layer; Figure 5 For Figure 3 It is a superimposed schematic diagram of a second metal layer, a third metal layer, and a fourth metal layer; Figure 6 It is another partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 7 For Figure 6 It is a partial schematic diagram of a second connection portion; Figure 8 It is another partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 9 It is another partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 10Another schematic diagram of a display panel provided by an embodiment of the present invention; Figure 11 Another schematic diagram of a display panel provided by an embodiment of the present invention; Figure 12 Another partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 13 is Figure 12 A superimposed schematic diagram of the second metal layer, the third metal layer, and the fourth metal layer in Figure 14 A schematic diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0010] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0011] In some related technologies, a mirror design is adopted for the pixel circuit. Mirroring the pixel circuit means that two adjacent transistors in the pixel circuit are in a symmetric relationship, so that adjacent pixel circuits can share some signal lines, thereby achieving the purpose of saving the wiring space of the display panel. However, currently, the panel using the mirror design of the pixel circuit has the problem of four-direction color shift, which affects the display effect.

[0012] To solve the problems existing in the prior art, an embodiment of the present invention provides a display panel. In the display panel, the pixel circuit adopts a mirror design, and a dummy line segment is added in one of two adjacent pixel circuits, so that the symmetry of the wiring structure in the two pixel circuits is better, thereby improving the problem of four-direction color shift of the display panel and enhancing the display effect.

[0013] Figure 1 A schematic diagram of a pixel circuit provided by an embodiment of the present invention. As Figure 1As shown, the pixel circuit includes a driving transistor Tm, a gate reset transistor M1, an electrode reset transistor M2, a data writing transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor Cst. The driving transistor Tm is connected in series between the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The first light-emitting control transistor M5 is connected to the positive power supply voltage Pvdd, and one electrode of the light-emitting device PD is connected to the negative power supply voltage Pvee. The operation process of the pixel circuit at least includes a reset stage, a writing stage, and a light-emitting stage. In the reset stage, the gate reset transistor M1 is turned on under the control of the scan signal S1 to write the reset signal Vref1 to the gate of the driving transistor Tm, and the electrode reset transistor M2 is turned on under the control of the scan signal S1 to write the reset signal Vref2 to the electrode of the light-emitting device PD. In the writing stage, the data writing transistor M3 and the threshold compensation transistor M4 are turned on under the control of the scan signal S2 to write the data voltage Data to the gate of the driving transistor Tm and perform self-check and compensation on the threshold voltage of the driving transistor Tm. In the light-emitting stage, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on under the control of the light-emitting control signal Emit, and the driving transistor Tm generates a driving current under the control of its gate voltage and supplies the driving current to the light-emitting device PD.

[0014] Figure 1 It is shown that the gate reset transistor M1 is connected to the reset signal Vref1, and the electrode reset transistor M2 is connected to the reset signal Vref2. Both the reset signal Vref1 and the reset signal Vref2 are constant voltage signals, but they have different voltage values. That is, two reset signals are required to drive the pixel circuit.

[0015] In some other embodiments, the gate reset transistor M1 and the electrode reset transistor M2 are connected to the same reset signal, that is, one reset signal is provided to drive the pixel circuit. This is not shown in the drawings here.

[0016] Figure 2 This is a partial schematic diagram of a display panel provided by an embodiment of the present invention. Figure 2 It schematically shows the schematic diagram at the positions of two pixel circuits 10. Figure 2 The positions of the transistors in the pixel circuit 10 are marked, and the connection relationship of the transistors in the pixel circuit 10 can be understood with reference to Figure 1 this.

[0017] As Figure 2 shown, the display panel further includes a data line 20 and a reset signal line 30 extending along the first direction y. Figure 2As can be seen from the schematic top view, in a direction perpendicular to the plane where the display panel is located, a pixel circuit 10 overlaps with a data line 20 and a reset signal line 30 respectively. Two pixel circuits 10 adjacent in the second direction x are symmetric about a first virtual line X1, and the first virtual line X1 extends along the first direction y, and the second direction x intersects with the first direction y. Two pixel circuits 10 adjacent in the second direction x being symmetric about the first virtual line X1 means that transistors with the same function in two adjacent pixel circuits 10 are symmetric in position about the first virtual line X1. Figure 2 It is shown in that the pixel circuits 10 adjacent in the second direction x include a first pixel circuit 11 and a second pixel circuit 12, and the first pixel circuit 11 and the second pixel circuit 12 are symmetric about the first virtual line X1. It can be understood that there is a first virtual line X1 between two pixel circuits 10 adjacent in the second direction x at any position.

[0018] The pixel circuit 10 includes a driving transistor Tm, a data writing transistor M3, a first transistor T1, a first via V1 and a second via V2. A node connection line 44 is connected between the first via V1 and the gate of the driving transistor Tm, and the data line 20 is connected to the data writing transistor M3 through the second via V2. A node connection line 44 is connected between the gate of the driving transistor Tm and the gate reset transistor M1. Figure 2 It is shown in that the electrode reset transistor M2 is the first transistor T1.

[0019] Among them, the first pixel circuit 11 includes a first connection portion 41, and the first connection portion 41 is located between the first via V1 and the second via V2. A first connection portion 41 is connected between the reset signal line 30 and the first transistor T1 in the first pixel circuit 11. The second pixel circuit 12 includes a dummy line segment 50, and the dummy line segment 50 is located between the first via V1 and the second via V2.

[0020] Since the first pixel circuit 11 and the second pixel circuit 12 are symmetric about the first virtual line X1, it can be known that the first via V1 of the first pixel circuit 11 and the first via V1 of the second pixel circuit 12 are symmetric about the first virtual line X1, and the second via V2 of the first pixel circuit 11 and the second via V2 of the second pixel circuit 12 are symmetric about the first virtual line X1. And the first connection portion 41 in the first pixel circuit 11 is located between the first via V1 and the second via V2, and the dummy line segment 50 in the second pixel circuit 12 is located between the first via V1 and the second via V2, so the positions of the first connection portion 41 and the dummy line segment 50 are also basically symmetric.

[0021] In the embodiment of the present invention, two pixel circuits 10 adjacent in the second direction x are in a symmetric relationship. In the first pixel circuit 11 and the second pixel circuit 12 adjacent in the second direction x, a first connection portion 41 is provided between the first via V1 and the second via V2 in the first pixel circuit 11. The first connection portion 41 is a structure for realizing circuit connection in the first pixel circuit 11. A dummy line segment 50 is additionally provided between the first via V1 and the second via V2 in the second pixel circuit 12. The position of the dummy line segment 50 in the second pixel circuit 12 is substantially symmetric to the position of the first connection portion 41 in the first pixel circuit 11. Thereby, the symmetry of the wiring structure in two pixel circuits 10 adjacent in the second direction x can be improved, which is beneficial to improving the four-direction color shift problem and enhancing the display effect.

[0022] In addition, since the first via V1 in the pixel circuit 10 is connected to the gate of the driving transistor Tm through the node connection line 44, and the second via V2 is connected to the data line 20, after the dummy line segment 50 provided between the first via V1 and the second via V2 is connected to a constant voltage, it can also play a shielding role, reduce the parasitic capacitance between the data line 20 and the node connection line 44, improve the crosstalk problem, and enhance the display effect of the display panel.

[0023] As Figure 2 shown, the display panel is also provided with a first scan line 61, a second scan line 62, a light emission control line 63, and an auxiliary signal line 64 extending along the second direction x. Among them, the first scan line 61 is electrically connected to the gates of the gate reset transistor M1 and the electrode reset transistor M2, the second scan line 62 is electrically connected to the gates of the data writing transistor M3 and the threshold compensation transistor M4, and the light emission control line 63 is electrically connected to the gates of the first light emission control transistor M5 and the second light emission control transistor M6. The auxiliary signal line 64 intersects and is electrically connected to the reset signal line 30 to form a grid-like wiring, thereby being able to reduce the voltage drop of the transmitted reset signal and improve the in-plane uniformity.

[0024] In some embodiments, as Figure 2 shown, the first connection portion 41 includes a first line segment 411, and the first line segment 411 is a partial line segment of the first connection portion 41. The first line segment 411 and the dummy line segment 50 are symmetric about the first virtual line X1. Such a setting makes the wiring in the first pixel circuit 11 and the wiring in the second pixel circuit 12 have better symmetry, which is more beneficial to improving the four-direction color shift problem and enhancing the display effect.

[0025] In some embodiments, as Figure 2As shown, the reset signal line 30 extending along the first direction x includes a first reset signal line 31 and a second reset signal line 32. Among them, the first reset signal line 31 overlaps with the first pixel circuit 11, and the second reset signal line 32 overlaps with the second pixel circuit 12; the first reset signal line 31 and the second reset signal line 32 are symmetric about the first virtual line X1. The pixel circuit 10 further includes a second transistor T2, and the second transistor T2 is electrically connected to the second reset signal line 30. Among them, the gate reset transistor M1 is the second transistor T2. That is, the first reset signal line 31 is electrically connected to the electrode reset transistor M2, the second reset signal line 32 is connected to the gate reset transistor M1, the first reset signal line 31 is used to provide a reset signal Vref2, and the second reset signal line 32 is used to provide a reset signal Vref1.

[0026] Optionally, the voltage value of the signal provided by the first reset signal line 31 is less than the voltage value of the signal provided by the second reset signal line 32. In the embodiment of the present invention, by providing a lower reset voltage to the electrode of the light-emitting device PD through the first reset signal line 31, the light-emitting device PD can be prevented from stealing light, and the low gray-scale display effect can be improved. At the same time, by providing a higher reset voltage to the gate of the driving transistor Tm through the second reset signal line 32, the threshold value of the gate of the driving transistor Tm can be captured more quickly. When applied to high-frequency display or low-brightness (or gray-scale) display, the threshold capture time of the gate of the driving transistor Tm is short, and the faster the threshold of the gate of the driving transistor Tm is captured, the more accurate the threshold capture can be, thus reducing display unevenness and improving the display effect. In some embodiments, as Figure 2 shown, the auxiliary signal line 64 extending along the second direction x includes a first auxiliary signal line 641 and a second auxiliary signal line 642; among them, the first auxiliary signal line 641 is electrically connected to the first reset signal line 31, and the second auxiliary signal line 642 is electrically connected to the second reset signal line 32. Figure 2 The fifth via V5 connecting the first auxiliary signal line 641 and the first reset signal line 31 and the sixth via V6 connecting the second auxiliary signal line 642 and the second reset signal line 32 are shown.

[0027] Figure 3 This is another schematic diagram of the display panel provided by the embodiment of the present invention. Figure 3 The transistors in the pixel circuit 10 are not marked in it. For the structure of the pixel circuit 10, reference can be made to Figure 2 for understanding. Figure 3 The pixel circuits 10 of 2 rows and 4 columns are shown, and the horizontal and vertical cross-wiring relationship between the reset signal line 30 and the auxiliary signal line 64 in the display panel can be seen more clearly. Figure 3Also shown is a power supply signal line 71 extending along the first direction y, and the power supply signal line 71 is used to supply a positive power supply voltage Pvdd to the pixel circuit 10. From Figure 3 It can be seen that in the second direction x, the first pixel circuits 11 and the second pixel circuits 12 are alternately arranged, and the adjacent first pixel circuits 11 and second pixel circuits 12 are symmetric about a first virtual line X1 extending along the first direction y.

[0028] Figure 3 Shown in is a fifth via V5 where the first auxiliary signal line 641 is connected to the first reset signal line 31, and a sixth via V6 where the second auxiliary signal line 642 is connected to the second reset signal line 32. From Figure 3 It can be seen that the first auxiliary signal line 641 and the first reset signal line 31 are cross-connected electrically to form a mesh trace, and the second auxiliary signal line 642 and the second reset signal line 32 are cross-connected electrically to form a mesh trace. Such an arrangement can reduce the voltage drop of the transmitted reset signal and improve the in-plane uniformity.

[0029] The display panel provided by the embodiment of the present invention at least includes a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer located above the substrate.

[0030] Figure 4 For Figure 3 is a schematic diagram of the superposition of the semiconductor layer and the first metal layer. In Figure 4 are marked the positions of the semiconductor layer 01, the first metal layer 02, and each transistor in a pixel circuit 10. Among them, the first scan line 61, the second scan line 62, and the light emission control line 63 are located in the first metal layer 02.

[0031] Figure 5 For Figure 3 is a schematic diagram of the superposition of the second metal layer, the third metal layer, and the fourth metal layer. Figure 5 are marked the second metal layer 03, the third metal layer 04, and the fourth metal layer 05, as well as the vias between the film layers. It can be seen that the first auxiliary signal line 641 and the second auxiliary signal line 642 are located in the second metal layer 03, the first reset signal line 31 and the second reset signal line 32 are located in the third metal layer 04, and the data line 20 and the power supply signal line 71 are located in the fourth metal layer 05.

[0032] In some embodiments of the present invention, the dummy line segment 50 is electrically connected to the reset signal line 30. Thereby, a constant voltage signal can be provided to the dummy line segment 50, so that the dummy line segment 50 plays a shielding role, thereby reducing the parasitic capacitance between the data line 20 and the node connection line 44, improving the crosstalk problem, and enhancing the display effect of the display panel.

[0033] In some embodiments, such as Figure 3As shown, the display panel includes a second connection portion 42, and the first transistor T1 in the first pixel circuit 11 and the first transistor T1 in the second pixel circuit 12 are respectively connected to the second connection portion 42. In combination with Figure 4 viewed, the second connection portion 42 includes a first sub-portion 421 and a second sub-portion 422, and the first sub-portion 421 and the second sub-portion 422 are symmetric about the first virtual line X1. The first connection portion 41 is connected to the first sub-portion 421 through a third via V3; the dummy line segment 50 is electrically connected to the second sub-portion 422. In this way, the dummy line segment 50 is connected to the reset signal line 30 through the second connection portion 42 and the first connection portion 41, so as to connect the dummy line segment 50 to the constant voltage signal. On the one hand, the setting of the dummy line segment 50 can improve the symmetry of the wiring structure in two adjacent pixel circuits 10 in the second direction x, which is beneficial to improving the four-direction color shift problem and enhancing the display effect. On the other hand, the dummy line segment 50 provided between the first via V1 and the second via V2 can also play a shielding role, reducing the parasitic capacitance between the data line 20 and the node connection line 44, improving the crosstalk problem, and enhancing the display effect of the display panel.

[0034] In some embodiments, as Figure 3 shown, the reset signal line 30 includes a first reset signal line 31 and a second reset signal line 32. The voltage values of the signals provided by the first reset signal line 31 and the second reset signal line 32 are different. The first connection portion 41 is electrically connected to the first reset signal line 31, so the constant voltage signal on the first reset signal line 31 is connected to the dummy line segment 50.

[0035] In some other embodiments, the electrode reset transistor M2 and the gate reset transistor M1 in the pixel circuit receive the same reset signal, so there is only a reset signal line 30 transmitting one voltage value arranged in the display panel, and the dummy line segment 50 is set to be connected to the reset signal line 30 through the second connection portion 42 and the first connection portion 41, which is not shown in the drawings here.

[0036] In some embodiments, as Figure 3 shown, the dummy line segment 50 is connected to the second sub-portion 422 (see Figure 4 the annotation in) through a fourth via V4; the third via V3 and the fourth via V4 are symmetric about the first virtual line X1. In this way, the symmetry between the dummy line segment 50 and the first connection portion 41 is better, and the symmetry of the wiring structure in two adjacent pixel circuits 10 is improved.

[0037] In some embodiments, the dummy line segment 50 is connected to the second sub-portion 422 through a fourth via V4; the dummy line segment 50 and the first connection portion 41 are located on the same layer. In combination with Figure 5As shown, the dummy line 50 and the first connection portion 41 are both located in the third metal layer 04. In this embodiment, the dummy line 50 and the first connection portion 41 can be fabricated in the same process, and the fourth via V4 and the third via V2 can also be fabricated in the same via process. When manufacturing the display panel, no additional process is added, and the process is simple.

[0038] In some other embodiments, Figure 6 is another partial schematic diagram of the display panel provided by the embodiment of the present invention. Figure 7 is Figure 6 a partial schematic diagram of the second connection portion in Figure 6 As shown, the display panel includes a second connection portion 42. The first transistor T1 in the first pixel circuit 11 and the first transistor T1 in the second pixel circuit 12 are respectively connected to the second connection portion 42. Combining Figure 7 to view, the second connection portion 42 includes a first sub-portion 421 and a second sub-portion 422. Among them, the first connection portion 41 is connected to the first sub-portion 421 through the third via V3; the dummy line 50 and the second sub-portion 422 are integrated. In this embodiment, the dummy line 50 and the second sub-portion 422 are located on the same layer, and both are located in the semiconductor layer. When manufacturing the display panel, by adjusting the mask pattern used in the patterning process of the semiconductor layer, the dummy line 50 can be fabricated in the process of the semiconductor layer, and the dummy line 50 is connected to the reset signal line 30 through the second connection portion 42 and the first connection portion 41, thereby connecting the dummy line 50 to the constant voltage signal.

[0039] Figure 6 In the embodiment, it is shown that the reset signal line 30 includes a first reset signal line 31 and a second reset signal line 32. The voltage values of the signals provided by the first reset signal line 31 and the second reset signal line 32 are different. The first connection portion 41 is electrically connected to the first reset signal line 31, so the constant voltage signal on the first reset signal line 31 is connected to the dummy line 50.

[0040] In some other embodiments, the electrode reset transistor M2 and the gate reset transistor M1 in the pixel circuit receive the same reset signal, so only one kind of reset signal line 30 is arranged in the display panel. The dummy line 50 and the second sub-portion 422 are integrated, and the dummy line 50 is connected to the reset signal line 30 through the second connection portion 42 and the first connection portion 41, and no further drawing is shown here.

[0041] In some other embodiments, Figure 8 is another partial schematic diagram of the display panel provided by the embodiment of the present invention. As Figure 8As shown, the dummy line 50 is electrically connected to the reset signal line 30 that overlaps with the second pixel circuit 12. The reset signal line 30 that overlaps with the second pixel circuit 12 is used to provide a constant voltage signal to the dummy line 50, so that the dummy line 50 between the first via V1 and the second via V2 can still play a shielding role after being connected to a constant voltage, reducing the parasitic capacitance between the data line 20 and the node connection line 44, improving the crosstalk problem, and enhancing the display effect of the display panel.

[0042] As Figure 8 shown, the reset signal line 30 includes a first reset signal line 31 and a second reset signal line 32. The first reset signal line 31 overlaps with the first pixel circuit 11, and the second reset signal line 32 overlaps with the second pixel circuit 12. In the pixel circuit, the gate reset transistor M1 is connected to the second reset signal line 32, and the electrode reset transistor M2 is connected to the first reset signal line 31. The dummy line 50 is connected to the constant voltage signal on the second reset signal line 32.

[0043] In some other embodiments, if the electrode reset transistor M2 and the gate reset transistor M1 in the pixel circuit receive the same reset signal, then only one type of reset signal line 30 is arranged in the display panel. The dummy line 50 is electrically connected to the reset signal line 30 that overlaps with the second pixel circuit 12, and no further drawing is shown here.

[0044] As Figure 8 shown, the dummy line 50 is electrically connected to the reset signal line 30 that overlaps with the second pixel circuit 12. The dummy line 50, the first connection part 41, and the reset signal line 30 are on the same layer. Then the dummy line 50 is in direct contact connection with the reset signal line 30 on the same layer, and the dummy line 50 and the reset signal line 30 are integrated. During manufacturing, the dummy line 50 and the reset signal line 30 can be fabricated in one process, and the dummy line 50 and the reset signal line 30 connected thereto are integrated, and the connection between the two does not require vias, resulting in better connection performance.

[0045] In some other embodiments, Figure 9 Another partial schematic diagram of the display panel provided by an embodiment of the present invention. As Figure 9 shown, the dummy line 50 is electrically connected to the reset signal line 30 that overlaps with the second pixel circuit 12 through the seventh via V7. Among them, the dummy line 50 and the data line 20 are on the same layer. The dummy line 50 can be fabricated in the same process as the data line 20, and the seventh via V7 is fabricated to achieve the electrical connection between the dummy line 50 and the reset signal line 30 without adding a new process, and the process is simple.

[0046] In some other embodiments, Figure 10 Another schematic diagram of the display panel provided by an embodiment of the present invention. As Figure 10As shown, the display panel includes a power supply signal line 71; the storage capacitor Cst in the pixel circuit 10 includes a first electrode plate C1 and a second electrode plate C2. A part of the first electrode plate C1 is multiplexed as the gate of the driving transistor Tm, and the second electrode plate C2 is electrically connected to the power supply signal line 71. Figure 10 The connection electrode 711 is shown. The power supply signal line 71 is connected to the connection electrode 711 through a via hole penetrating the insulating layer, and the connection electrode 711 is then connected to the second electrode plate C2 through a via hole penetrating the insulating layer. Among them, the dummy line segment 50 is electrically connected to the second electrode plate C2. Such a setting enables the dummy line segment 50 to receive the constant voltage signal provided by the power supply signal line 71, so that the dummy line segment 50 plays a shielding role, thereby reducing the parasitic capacitance between the data line 20 and the node connection line 44, improving the crosstalk problem, and enhancing the display effect of the display panel.

[0047] As Figure 10 shown, the pixel circuit 10 includes a second transistor T2 and a first shielding structure 72. A third connection part 43 is connected between the second transistor T2 and the first via hole V1; Figure 4 The position of the third connection part 43 is also marked in Figure 5 and the position of the first shielding structure 72 is marked in Figure 10 It can be seen from the schematic top view shown that along the direction perpendicular to the plane of the display panel, the first shielding structure 72 and the third connection part 43 at least partially overlap; the dummy line segment 50 is electrically connected to the second electrode plate C2 through the first shielding structure 72. It can be seen from Figure 10 that the first shielding structure 72 is connected to the second electrode plate C2 through a fourth connection part 45. The shielding effect of the first shielding structure 72 can ensure the stability of the signal in the third connection part 43, and further make the potential of the node connection line 44 connected to the first via hole V1 stable, that is, the potential of the gate of the driving transistor Tm in the pixel circuit is stable, and a better display effect can be provided. In the circuit layout, the dummy line segment 50 is adjacent to the first shielding structure 72. Setting the dummy line segment 50 to be electrically connected to the first shielding structure 72 does not require additional wire winding and is convenient to connect. A very small change to the circuit layout realizes connecting the constant voltage signal to the dummy line segment 50.

[0048] In some embodiments, the dummy line segment 50, the first shielding structure 72, and the second electrode plate C2 are located in the same layer, and all three are located in the second metal layer 03. Such a setting can fabricate the dummy line segment 50, the first shielding structure 72, and the second electrode plate C2 in the same process, and the dummy line segment 50 and the first shielding structure 72 can be directly in contact and connected as a whole, and the connection between the two does not require a via hole and has better connection performance.

[0049] In some embodiments, Figure 11 This is another schematic diagram of the display panel provided by the embodiment of the present invention. AsFigure 11 As shown, a plurality of data lines 20 are arranged in the display area AA of the display panel. The data lines 20 include a first data line 21 and a second data line 22. The first data line 21 is connected to a pad (not labeled in the figure) in the non-display area through a data connection line 23 located in the display area AA. Figure 11 The second data line 22 directly extends from the display area AA to the non-display area and is connected to the corresponding pad. Such a setting can reduce the area occupied by the fan-out lines in the non-display area, which is beneficial to the narrowing of the border. In Figure 11 the embodiment, the setting of the data connection line 23 in the display area AA results in the problem of uneven metal patterns in the display area AA. Therefore, dummy signal lines are additionally provided in the display area AA to improve the problem of metal pattern uniformity.

[0050] Figure 12 Another partial schematic diagram of the display panel provided by the embodiment of the present invention is shown in Figure 12 As shown, a first dummy signal line 73 extending along the first direction y and a second dummy signal line 74 extending along the second direction x are arranged in the display panel. The first dummy signal line 73 and the second dummy signal line 74 are electrically connected through an eighth via V8. Figure 12 That is, Figure 3 on the basis of the above, the first dummy signal line 73 and the second dummy signal line 74 are added. For the pixel circuit structure and other wiring, reference can be made to the relevant descriptions in Figure 3 . It can be seen that Figure 12 in the embodiment, two adjacent pixel circuits 10 in the second direction x are symmetric. A dummy segment 50 is additionally provided in the second pixel circuit 12. On the one hand, it can improve the symmetry of the wiring structure in two adjacent pixel circuits 10 in the second direction x, which is beneficial to improving the four-direction color shift problem and enhancing the display effect. On the other hand, after the dummy segment 50 provided between the first via V1 and the second via V2 is connected to a constant voltage, it can also play a shielding role, reduce the parasitic capacitance between the data line 20 and the node connection line 44, improve the crosstalk problem, and enhance the display effect of the display panel.

[0051] In the display panel provided with the data connection line 23, the first dummy signal line 73 and the second dummy signal line 74, the film layer position of the dummy segment 50 and the connection manner with the relevant structures in the second pixel circuit 12 can be set with reference to the above relevant embodiments, and will not be elaborated here.

[0052] In addition, Figure 12 the superposition pattern of the semiconductor layer and the first metal layer is the same as that in the above Figure 4 embodiment. Figure 13 is Figure 12 a superposition schematic diagram of the second metal layer, the third metal layer and the fourth metal layer in Figure 13It can be seen that the first dummy signal line 73 is located in the fourth metal layer 05, and the second dummy signal line 74 is located in the third metal layer 04. The first reset signal line 31 and the second reset signal line 32 extend along the first direction y. Therefore, the first reset signal line 31 and the second reset signal line 32 will cross the second dummy signal line 74. Crosspoint lines 46 are respectively arranged at the positions where the first reset signal line 31 and the second reset signal line 32 cross the second dummy signal line 74, thereby enabling the reset signal lines and the second dummy signal line 74 to cross insulatively. Optionally, the crosspoint lines 46 are located in the fourth metal layer 05.

[0053] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 14 A schematic diagram of a display device provided by an embodiment of the present invention is shown in Figure 14 As shown, the display device includes the display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be elaborated here. The display device provided by the embodiment of the present invention may be, for example, an electronic device with a display function such as a mobile phone, a tablet computer, a computer, a television, a smart wearable product, etc.

[0054] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a pixel circuit, a data line extending in a first direction, and a reset signal line; in a direction perpendicular to the plane of the display panel, one pixel circuit overlaps with one data line and one reset signal line respectively; two adjacent pixel circuits in a second direction are symmetric about a first virtual line, the first virtual line extends in the first direction, and the second direction intersects with the first direction. The pixel circuit includes a driving transistor, a data writing transistor, a first transistor, a first via, and a second via. A node connection line is connected between the first via and the gate of the driving transistor, and the data line is connected to the data writing transistor through the second via. The pixel circuits adjacent in the second direction include a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first connection portion, the first connection portion is located between the first via and the second via, and the first connection portion is connected between the reset signal line and the first transistor in the first pixel circuit. The second pixel circuit includes a dummy segment, and the dummy segment is located between the first via and the second via.

2. The display panel according to claim 1, wherein the first connection portion includes a first segment, and the first segment and the dummy segment are symmetric about the first virtual line.

3. The display panel according to claim 1, wherein the dummy segment is electrically connected to the reset signal line.

4. The display panel according to claim 3, wherein the display panel includes a second connection portion, the first transistors in the first pixel circuit and the second pixel circuit are respectively connected to the second connection portion; the second connection portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are symmetric about the first virtual line; the first connection portion is connected to the first sub-portion through a third via; the dummy segment is electrically connected to the second sub-portion.

5. The display panel according to claim 4, wherein the dummy segment is connected to the second sub-portion through a fourth via; the third via and the fourth via are symmetric about the first virtual line.

6. The display panel according to claim 5, wherein the dummy segment and the first connection portion are on the same layer.

7. The display panel according to claim 4, wherein the dummy segment and the second sub-portion are integral.

8. The display panel according to claim 3, wherein the dummy segment is electrically connected to the reset signal line overlapping with the second pixel circuit.

9. The display panel according to claim 8, wherein the dummy segment is on the same layer as the first connection portion, or on the same layer as the data line.

10. The display panel according to claim 1, wherein the display panel includes a power supply signal line. The pixel circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, a part of the first electrode plate is multiplexed as the gate of the driving transistor, and the second electrode plate is electrically connected to the power supply signal line; The dummy line is electrically connected to the second electrode plate.

11. The display panel according to claim 10, wherein The pixel circuit includes a second transistor and a first shielding structure, and a third connection part is connected between the second transistor and the first via; in a direction perpendicular to the plane of the display panel, the first shielding structure and the third connection part overlap at least partially; The dummy line is electrically connected to the second electrode plate through the first shielding structure.

12. The display panel according to claim 11, wherein The dummy line, the first shielding structure, and the second electrode plate are located in the same layer.

13. The display panel according to claim 1, wherein The reset signal line includes a first reset signal line and a second reset signal line; The first reset signal line overlaps with the first pixel circuit, and the second reset signal line overlaps with the second pixel circuit; the first reset signal line and the second reset signal line are symmetric about the first virtual line; The pixel circuit further includes a second transistor, and the second transistor is electrically connected to the second reset signal line.

14. The display panel according to claim 13, wherein The display panel further includes a first auxiliary signal line and a second auxiliary signal line extending along the second direction; The first auxiliary signal line is electrically connected to the first reset signal line, and the second auxiliary signal line is electrically connected to the second reset signal line.

15. A display device, characterized in that, A display panel including any one of claims 1 to 14.

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