Display module and display device

Abstract

The invention relates to a display module and a display device. The display module is provided with a display area, the display area comprises a first display area and a second display area which are sequentially arranged in the first direction, the display area comprises a plurality of pixel units, and each pixel unit comprises a plurality of sub-pixels of different colors; the display module comprises a plurality of data line groups arranged in a display area, each data line group comprises a plurality of data lines, the plurality of data lines are correspondingly connected with a plurality of sub-pixels with different colors in the same pixel unit respectively, and the pixel units connected with different data line groups are different; the first connecting wires are arranged in the display area, the first ends of the first connecting wires are connected with the data lines located in the first display area, and the second ends of the first connecting wires are located between every two adjacent data lines in the second display area; at least one first connecting line and the adjacent data line located in the second display area correspond to the sub-pixel of the same color. And frames are reduced, and crosstalk is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display module and a display device. Background Art

[0002] Display devices with Real RGB pixel arrangements have the characteristics of high display clarity, sharp edges of text and images, and accurate color reproduction. With the continuous development of display technologies, people have higher and higher requirements for the appearance state of display devices. It is particularly important to reduce the border of the display screen with Real RGB pixel arrangement and increase the screen-to-body ratio. Summary of the Invention

[0003] Based on this, it is necessary to provide a display module and a display device, aiming to solve the problem of the wide border of the display screen with Real RGB pixel arrangement.

[0004] In a first aspect, an embodiment of the present application provides a display module. The display module is provided with a display area, and the display area includes a first display area and a second display area arranged in sequence along a first direction. The display area includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels of different colors. The display module includes:

[0005] A plurality of data line groups are arranged in the display area. Each data line group includes a plurality of data lines, and the plurality of data lines are respectively connected to a plurality of sub-pixels of different colors in the same pixel unit. Different data line groups are connected to different pixel units;

[0006] A plurality of first connection traces are arranged in the display area. The first ends of the plurality of first connection traces are respectively connected to a plurality of data lines located in the first display area, and the second ends of the first connection traces are located between two adjacent data lines in the second display area; at least one first connection trace corresponds to sub-pixels of the same color as the adjacent data line located in the second display area.

[0007] In a second aspect, an embodiment of the present application further provides a display device, and the display device includes the display module provided in the first aspect.

[0008] The display module and the display device provided by the embodiments of the present application connect the data lines in the first display area to between the data lines in the second display area through the first connection traces, meeting the requirement of reducing the border. At the same time, by setting at least one first connection trace to correspond to sub-pixels of the same color as the adjacent data line located in the second display area, the crosstalk between the first connection trace and the data line in the second display area is reduced. Description of the Drawings

[0009] Figure 1 It is one of the schematic diagrams of the traces in the display area of the display module provided by the embodiment of the present application;

[0010] Figure 2 The second schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application;

[0011] Figure 3 The third schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application;

[0012] Figure 4 The fourth schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application;

[0013] Figure 5 The fifth schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application;

[0014] Figure 6 The sixth schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application;

[0015] Figure 7 The first schematic diagram of the display module provided by the embodiment of the present application;

[0016] Figure 8 The second schematic diagram of the display module provided by the embodiment of the present application;

[0017] Figure 9 The structural schematic diagram of the display device provided by the embodiment of the present application. Detailed implementation manners

[0018] For ease of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intermediate elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can also be one or more intermediate elements. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate elements.

[0021] In the case of using "comprising", "having", and "including" described in this text, unless explicit limiting terms are used, such as "only", "consisting of", etc., another component may also be added. Unless otherwise mentioned, terms in the singular form may include the plural form and should not be construed as having a quantity of one.

[0022] It should be understood that although terms such as "first" and "second" may be used in this text to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of this application, the first connection trace may be referred to as the second connection trace, and similarly, the second connection trace may be referred to as the first connection trace.

[0023] It should also be understood that when interpreting a component, although not explicitly described, the component is interpreted as including an error range, which should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximately", or "substantially" may mean within one or more standard deviations, which is not defined herein.

[0024] In addition, in the specification, the phrase "planar distribution schematic diagram" refers to the accompanying drawing when observing the target part from above, and the phrase "cross-sectional schematic diagram" refers to the accompanying drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0025] In addition, the accompanying drawings are not drawn to a 1:1 scale, and the relative sizes of the components are only drawn by way of example in the accompanying drawings and not necessarily to the actual scale.

[0026] In a display device with a Real RGB pixel arrangement, each pixel unit includes independent red, blue, and green sub-pixels. Compared with the typical pixel arrangement where some sub-pixels are shared between two pixel units, it avoids sharpness loss, makes the edges of text clearer and sharper, and at the same time, the color reproduction is more accurate. However, the display device with a Real RGB pixel arrangement has the problem of a large border.

[0027] Based on the above technical problems, the inventor's research found that in a display device with a Real RGB pixel arrangement, by connecting the pixel driving circuit connected to the data line in the edge display area to the middle display area, the border of the display device can be reduced. Based on this, the inventor further developed the technical solution of the embodiment of this application.

[0028] Specifically, the display module provided by the embodiments of the present application is provided with a display area, the display area includes a first display area and a second display area arranged in sequence along a first direction, the display area includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels of different colors; the display module includes: a plurality of data line groups and a plurality of first connection traces provided in the display area; each data line group includes a plurality of data lines, and the plurality of data lines are respectively connected to a plurality of sub-pixels of different colors in the same pixel unit, and the pixel units connected by different data line groups are different; the first ends of the plurality of first connection traces are respectively connected to a plurality of data lines located in the first display area, and the second ends of the first connection traces are located between two adjacent data lines in the second display area; at least one first connection trace corresponds to sub-pixels of the same color as the adjacent data line located in the second display area.

[0029] By adopting the above technical solution, the data lines in the first display area can be connected to the data lines in the second display area through the first connection traces, thereby reducing the border of the display device. At the same time, by setting at least one first connection trace to correspond to sub-pixels of the same color as the adjacent data line located in the second display area, the crosstalk between the first connection trace and the data line in the second display area is reduced. Thus, the problem of large borders of display devices with Real RGB pixel arrangements can be improved.

[0030] The above is the core idea of the present application. Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0031] Figure 1 FIG. 10 is one of the schematic diagrams of the traces in the display area of the display module provided by the embodiments of the present application. Exemplarily, the X direction may be Figure 1 the first direction shown, and the Y direction may be Figure 1 the second direction shown, and the first direction X and the second direction Y intersect; further, the first direction X and the second direction Y are perpendicular to each other. As Figure 1 shown, in this embodiment, a display module is provided. The display module is provided with a display area 10. The display area 10 includes a first display area 102 and a second display area 104 arranged in sequence along the first direction X. The display area 10 includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels of different colors. The display module includes a plurality of data line groups 202 provided in the display area 10 and a plurality of first connection traces 204 provided in the display area 10; in the figure, data lines 2021 and first connection traces 204 are distinguished by lines of different thicknesses. Among them, the data lines 2021 are thinner lines, and the first connection traces 204 are thicker lines.

[0032] Specifically, the display module has an AA area (Active Area) capable of displaying a picture. The display area can be understood as a part of the AA area. The first display area 102 and the second display area 104 are different areas arranged at intervals. As an example, the sub-pixels of different colors include red sub-pixels, blue sub-pixels, and green sub-pixels. Each sub-pixel includes a light-emitting unit and a pixel driving circuit connected to each other. The pixel driving circuit is used to drive the light-emitting unit to emit light according to the received data signal, generating the color corresponding to the sub-pixel.

[0033] Each data line group 202 includes multiple data lines 2021 arranged at intervals. The multiple data lines 2021 are respectively connected to multiple sub-pixels of different colors in the same pixel unit. Different data line groups 202 are connected to different pixel units, that is, the data line groups 202 and the pixel units are in one-to-one correspondence. The number of data lines 2021 in the data line group 202 is the same as the number of sub-pixels in the pixel unit.

[0034] It can be understood that if the pixel unit includes N1 sub-pixels of different colors, the number of data lines 2021 provided in the first display area 102 is an integer multiple of N1. According to the correspondence between the data lines 2021 and the pixel units, the data lines 2021 in the first display area 102 are divided into multiple data line groups 202. The data lines 2021 in the first display area 102 are arranged in sequence in the first direction X according to the data line groups 202. The second display area 104 is similar to the first display area 102 and will not be elaborated here.

[0035] The first ends of the multiple first connection traces 204 are respectively connected to the multiple data lines 2021 located in the first display area 102. The second ends of the first connection traces 204 are located between two adjacent data lines 2021 in the second display area 104. At least one first connection trace 204 corresponds to sub-pixels of the same color as the adjacent data lines 2021 located in the second display area 104.

[0036] It can be understood that the multiple first connection traces 204 are arranged at intervals. The number of first connection traces 204 is the same as the number of data lines 2021 in the first display area 102. The first ends of the first connection traces 204 are connected to the data lines 2021 in the first display area 102. The projection of the second ends of the first connection traces 204 in the second display area 104 is located between the projections of two adjacent data lines 2021 in the second display area 104. At least one first connection trace 204 connects sub-pixels of the same color as the sub-pixels corresponding to the adjacent data lines 2021 located in the second display area 104 corresponding to the second ends of the first connection traces 204. This application does not limit whether the first connection traces 204 and the data lines 2021 in the first display area 102 or the data lines 2021 in the second display area 104 are on the same layer.

[0037] In summary, for the display module provided in the embodiments of the present application, each data line 2021 in the first display area 102 is connected to the second display area 104 through the first connection trace 204, which can reduce the border of the display module. Moreover, by setting at least one first connection trace 204 to correspond to sub-pixels of the same color as the adjacent data line 2021 located in the second display area 104, the crosstalk between the first connection trace 204 and the data line 2021 in the second display area 104 is reduced. When all the first connection traces 204 correspond to sub-pixels of the same color as the adjacent data line 2021 located in the second display area 104, the crosstalk between the first connection trace 204 connected to the second display area 104 and the data line 2021 in the second display area 104 is minimized.

[0038] It can be understood that the design difficulty and the magnitude of crosstalk can be balanced by adjusting the number of the first connection traces 204 corresponding to sub-pixels of the same color as the adjacent data line 2021 located in the second display area 104.

[0039] In some embodiments, the number of data lines 2021 between the second ends of two adjacent first connection traces 204 is different. Through this setting, the position of the second end of the first connection trace 204 in the second display area 104 can be adjusted according to the crosstalk received by the data line 2021 in the second display area 104, reducing the overall crosstalk received by the data line 2021 in the second display area 104.

[0040] In some embodiments, the number of data lines 2021 between the second ends of two adjacent first connection traces 204 is the same; among them, the sorting of the pixel driving circuits corresponding to the data lines 2021 of multiple data line groups 202 in the second display area 104 is the same. The first connection trace 204 is inserted between the data lines 2021 in the second display area 104 at a preset period, reducing the design difficulty and the manufacturing difficulty of the display module.

[0041] Specifically, for the preset strip data lines 2021 with intervals, a second end of a first connection trace 204 (the orthographic projection of the second end of the first connection trace 204) is set in the second display area 104, that is, the first connection trace 204 and the data lines 2021 in the second display area 104 are set to N2 plug 1, where N2 is a positive integer greater than or equal to 1; the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 located in the second display area 104 are arranged in the same order. It can be understood that the order of the pixel driving circuits can be characterized by the colors of the sub-pixels including the pixel driving circuits, and in the subsequent embodiments, the order of the pixel driving circuits is exemplified by the colors of the sub-pixels. Taking the pixel unit including a red sub-pixel (R), a blue sub-pixel (B), and a green sub-pixel (G) as an example, at this time, the data line group 202 includes 3 data lines 2021, the red sub-pixel includes a red light-emitting unit and a red driving circuit, the blue sub-pixel includes a blue light-emitting unit and a blue driving circuit, the green sub-pixel includes a green light-emitting unit and a green driving circuit, and the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 located in the second display area 104 are all arranged in the same order, and the order of the pixel driving circuits is selected from one of RGB, RBG, BRG, BGR, GRB, and GBR. In the figure, the order of the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 in the second display area 104 is RGB for example.

[0042] See Figure 1 , in some embodiments, in the first direction X, the second end of the first connection trace 204 and the data lines 2021 in the second display area 104 are alternately arranged. Specifically, the preset plane includes a first projection and a second projection. The first projection is the orthographic projection of the second end of the first connection trace 204 in the preset plane, and the second projection is the orthographic projection of the data lines 2021 in the second display area 104 in the preset plane. Here, the preset plane is parallel to the plane including the first direction X and the second direction Y; the alternate arrangement here means that the first projection and the second projection are alternately arranged in sequence in the first direction X. This setting can further reduce the border of the display module. Moreover, it can reduce the area in the second display area 104 where the second end of the first connection trace 204 is inserted, reduce the area affected by crosstalk in the second display area 104, and reduce the middle area (the part of the second display area 104 far from the first display area 102) of the second display area 104 occupied by the insertion of the first connection trace 204, effectively avoiding the influence of the insertion of the first connection trace 204 on the display quality of the middle area of the display module, and thus improving the user's viewing experience.

[0043] It can be understood that the second ends of the first connection traces 204 and the data lines 2021 of the second display area 104 are alternately arranged, and the sorting of the pixel driving circuits corresponding to the data lines 2021 of the multiple data line groups 202 in the second display area 104 is the same, so that the colors of the sub-pixels connected by any one of the first connection traces 204 in the display module are the same as those of the sub-pixels corresponding to the data line 2021 adjacent to the second end of the first connection trace 204 and located on the second display area 104 side, and the crosstalk between the first connection traces 204 and the data lines 2021 in the second display area 104 is minimized.

[0044] Figure 2 This is the second schematic diagram of the traces in the display area of the display module provided by the embodiment of the present application. Refer to Figure 2 , in some embodiments, in the first direction X, the number of data lines 2021 between the second ends of two adjacent first connection traces 204 is equal to the number of sub-pixels in the same pixel unit. It can be understood that in the first direction X, the number of second projections between two adjacent first projections is equal to the number of sub-pixels in the same pixel unit. This setting reduces the ratio of the number of data lines 2021 to the number of second ends of the first connection traces 204 in the area where the second ends of the first connection traces 204 are located, and reduces the crosstalk between the first connection traces 204 and the data lines 2021 in this area. At the same time, the first connection traces 204 are periodically inserted between the data lines 2021 of the second display area 104, reducing the design difficulty and human error of the display module.

[0045] In some embodiments, in the first display area 102, there is at least one data line group 202 in which the sorting of the pixel driving circuits corresponding to the data lines 2021 is different from that of the pixel driving circuits corresponding to the data lines 2021 in other data line groups 202. This setting improves the design flexibility of the display module.

[0046] Refer to Figure 1 and Figure 2 , in some embodiments, in the first display area 102, the sorting of the pixel driving circuits corresponding to the multiple data lines 2021 in any two data line groups 202 is the same, that is, the sorting of the pixel driving circuits corresponding to the data lines 2021 in each data line group 202 in the first display area 102 is the same. This setting can reduce the design difficulty and process difficulty of the display module, and improve the preparation yield and display stability of the display module. Figure 1 and Figure 2 take each data line group 202 in the first display area 102 as an example, which includes 3 data lines 2021, and the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 are sorted in RGB order.

[0047] Refer to Figure 1and Figure 2 , in some embodiments, in the second display area 104, the sorting of the pixel driving circuits corresponding to the multiple data lines 2021 in any two data line groups 202 is the same, that is, the sorting of the pixel driving circuits corresponding to the data lines 2021 in each data line group 202 in the second display area 104 is the same. This setting can reduce the design difficulty and process difficulty of the display module, and improve the production yield and display stability of the display module. Figure 1 and Figure 2 The example in [reference] takes that each data line group 202 in the second display area 104 includes 3 data lines 2021, and the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 are sorted in the order of RGB.

[0048] Continue to refer to Figure 1 and Figure 2 , in some embodiments, the sorting of the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 of the first display area 102 is the same as the sorting of the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 of the second display area 104. That is, the sorting of the pixel driving circuits corresponding to the multiple data lines 2021 in any one data line group 202 of the first display area 102 is the same as the sorting of the pixel driving circuits corresponding to the multiple data lines 2021 in any one data line group 202 of the second display area 104. This setting can further reduce the design difficulty and process difficulty of the display module, and improve the production yield and display stability of the display module. It can be understood that the number of data lines 2021 in the data line group 202 of the first display area 102 is the same as that in the data line group 202 of the second display area 104, and the sorting of the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 of the first display area 102 is the same as the sorting of the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 of the second display area 104.

[0049] Refer to Figure 1 and Figure 2 , in some embodiments, in two adjacent data line groups 202 of the first display area 102, the second end of the first connection trace 204 corresponding to the data line group 202 close to the second display area 104 is close to the first display area 102. The data line groups 202 in the first display area 102 are sequentially inserted into the area of the second display area 104 close to the first display area 102, which simplifies the design difficulty and reduces the preparation difficulty and the probability of human error.

[0050] It can be understood that among two adjacent data line groups 202 in the first display area 102, the second ends of the plurality of first connection traces 204 corresponding to the data lines 2021 in the data line group 202 closer to the second display area 104 are close to the first display area 102. The sorting of the pixel driving circuits corresponding to the second ends of the first connection traces 204 connected by any data line group 202 is selected from one of RGB, RBG, BRG, BGR, GRB, and GBR.

[0051] See Figure 1 , in some embodiments, the first connection trace 204 includes: a first trace portion 2041 disposed at least partially in the first display area 102 and a second trace portion 2042 disposed in the second display area 104. One end of the first trace portion 2041 is connected to the corresponding data line 2021 in the first display area 102, the other end of the first trace portion 2041 is connected to one end of the second trace portion 2042, the other end of the second trace portion 2042 is aligned with one end of the data line 1021 in the second display area 104, and the second trace portion 2042 is located between two adjacent data lines 2021 in the second display area 104; the extending direction of the first trace portion 2041 and the extending direction of the second trace portion 2042 intersect, connecting the data line 1021 in the first display area 102 to the second display area 104 through the first trace portion 2041, and connecting the first trace portion 2041 to between two adjacent data lines 2021 in the second display area 104 through the second trace portion 2042, simplifying the design difficulty of the first connection trace 204 and reducing the crosstalk between the first connection trace 204 and the data lines in the second display area 104.

[0052] See Figure 1 , in some embodiments, the extending direction of the first trace portion 2041 and the extending direction of the second trace portion 2042 are perpendicular to each other, reducing the process difficulty of manufacturing the first connection trace 204 and improving the manufacturing yield and the stability of the display module.

[0053] See Figure 2 , in some embodiments, the data lines 2021 in the display area 10 extend along the second direction Y, and the multiple data lines 2021 in the display area 10 are arranged in sequence along the first direction X; wherein, the extending direction of the first trace portion 2041 is parallel to the first direction X, that is, the first trace portion 2041 extends along the first direction X, and the extending direction of the second trace portion 2042 intersects with the second direction Y. By setting the extending direction of the first trace portion 2041 to be the same as the arrangement direction of the data lines 2021, the design difficulty and process difficulty of the display module are reduced, and the manufacturing yield is improved.

[0054] Figure 3 This is the third schematic diagram of the traces in the display area of the display module provided by the embodiments of the present application. See Figure 3, in some embodiments, the data lines 2021 in the display area 10 extend along the second direction Y, and multiple data lines 2021 in the display area 10 are arranged in sequence along the first direction X; wherein, the extending direction of the second wiring portion 2042 is parallel to the second direction Y, that is, the second wiring portion 2042 extends along the second direction Y, and the extending direction of the first wiring portion 2041 intersects with the first direction X. By setting the extending direction of the second wiring portion 2042 to be the same as the extending direction of the data line 2021, the design difficulty and process difficulty of the display module are reduced, and the preparation yield is improved. At the same time, the distances between different positions of any second wiring portion 2042 and the adjacent data lines 2021 in the first direction X are the same, avoiding the influence of the difference in the distances between the data line 2021 and the adjacent second wiring portion 2042 on the crosstalk between the first connection wiring 204 and the data lines 2021 in the second display area 104. At the same time, the size of the display module in the first direction X is reduced.

[0055] Figure 4 FIG. 4 is a schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application. Figure 5 FIG. 5 is a schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application. Refer to Figure 4 and Figure 5 , in some embodiments, the data lines 2021 in the display area 10 extend along the second direction Y, and multiple data lines 2021 in the display area 10 are arranged in sequence along the first direction X; wherein, the extending direction of the first wiring portion 2041 is parallel to the first direction X, and the extending direction of the second wiring portion 2042 is parallel to the second direction Y, that is, the first wiring portion 2041 extends along the first direction X, and the second wiring portion 2042 extends along the second direction Y. By corresponding the extending direction of the wiring portion to the extending direction and arrangement direction of the data line 2021, the design difficulty and process difficulty can be further reduced, and the preparation yield is improved.

[0056] Refer to Figure 4 and Figure 5 , in some embodiments, among two adjacent data line groups 202 in the first display area 102, the lengths of the respective first wiring portions 2041 corresponding to the data line group 202 close to the second display area 104 are less than the lengths of the respective first wiring portions 2041 corresponding to the data line group 202 far from the second display area 104; and the lengths of the respective second wiring portions 2042 corresponding to the data line group 202 close to the second display area 104 are less than the lengths of the respective second wiring portions 2042 corresponding to the data line group 202 far from the second display area 104. By this setting, the length of the lower border of the first display area 102 can be narrowed.

[0057] Figure 6 FIG. 6 is a schematic diagram of the wiring in the display area of the display module provided by the embodiment of the present application. Refer to Figure 6, in some embodiments, the display module further includes: a plurality of second connection traces 106; the second connection traces 106 are disposed in the second display area 104, the plurality of second connection traces 106 are respectively arranged corresponding to the plurality of second trace portions 2042, and are on the extension lines of the plurality of second trace portions 2042, and are separated from the corresponding second trace portions 2042. It can be understood that the orthographic projection of the second connection trace 106 on the preset plane is located on the extension line of the orthographic projection of the second trace portion 2042 on the preset plane, and the extension direction of the second connection trace 106 is the same as the extension direction of the second trace portion 2042. Through this setting, the layout uniformity of the signal lines for transmitting data signals in the second display area 104 is improved, and the problem of mura in the off-screen state is suppressed. The influence of various optical effects on the dimensional structure differences during the exposure preparation process is reduced, thereby improving the preparation yield of the display module.

[0058] Figure 7 One of the schematic diagrams of the display module provided by the embodiment of the present application, see Figure 7 , in some embodiments, the display module further has a fan-out area 20 and a chip area 30, and the display area 10, the fan-out area 20 and the chip area 30 are arranged in sequence along the second direction Y; in the second direction Y, the fan-out area 20 is adjacent to the second display area 104, and the second direction Y intersects with the first direction X; further, the first direction X and the second direction Y are perpendicular to each other. The display module further includes: a plurality of pin groups 206 and a plurality of fan-out traces, the plurality of pin groups 206 are respectively arranged corresponding to the plurality of data line groups 202 in the display area 10, that is, the number of pin groups 206 is the same as the number of data line groups 202, and the plurality of fan-out traces are respectively connected corresponding to the plurality of data lines 2021 in the display area 10.

[0059] The plurality of pin groups 206 are disposed in the chip area 30, each pin group 206 includes a plurality of pins 2061, the plurality of pins 2061 are respectively connected corresponding to the plurality of data lines 2021 of the same data line group 202, and the number of pins 2061 in the pin group 206 is the same as the number of data lines 2021 in the data line group 202; the pins 2061 are used to transmit corresponding data signals to the pixel driving circuits connected correspondingly, and the pixel driving circuits drive the corresponding light-emitting units to emit light according to the received data signals. It can be understood that the sorting of the pixel driving circuits corresponding to the data signals transmitted by the pins 2061 in any one of the plurality of pin groups 206 is selected from one of RGB, RBG, BRG, BGR, GRB and GBR.

[0060] Multiple fan-out traces are provided in the fan-out area 20. One ends of the multiple fan-out traces are respectively connected to the second ends of the multiple first connection traces 204 and the multiple data lines 2021 in the second display area 104. The other ends of the multiple fan-out traces connected to the same data line group 202 are respectively connected to multiple pins 2061 in the same pin group 206. Through the fan-out traces, the connection between the pin 2061 and the second end of the first connection trace 204 in the second display area 104 or the data line 2021 in the second display area 104 is realized, and the transmission of the narrow border and the data signal is realized.

[0061] See Figure 7 , in some embodiments, the sorting of the pixel driving circuits corresponding to the data signals transmitted by the multiple pins 2061 in any two pin groups 206 is the same, and is selected from one of RGB, RBG, BRG, BGR, GRB, and GBR, which simplifies the connection between the pins 2061 of the pin group 206 and the fan-out traces. In the drawings, the pins 2061 in the pin group 206 corresponding to the first display area 102 and the second display area 104 are distinguished by lines of different thicknesses. Among them, the pins 2061 corresponding to the first display area 102 are thicker lines, and the pins 2061 corresponding to the second display area 104 are thinner lines.

[0062] Figure 8 This is the second schematic diagram of the display module provided by the embodiment of the present application. See Figure 8 , in some embodiments, the sorting of the pixel driving circuits corresponding to the data signals transmitted by the multiple pins 2061 in each pin group 206 corresponding to each data line group 202 in the first display area 102 is the same, and the sorting of the pixel driving circuits corresponding to the data signals transmitted by the multiple pins 2061 in each pin group 206 corresponding to each data line group 202 in the second display area 104 is the same, and is different from the sorting of the pixel driving circuits corresponding to the data signals transmitted by the multiple pins 2061 in each pin group 206 corresponding to each data line group 202 in the first display area 102, and are respectively selected from two of RGB, RBG, BRG, BGR, GRB, and GBR, which reduces the design difficulty of the transmission of each pin 2061 and the corresponding data signal and simplifies the control of the transmission of the data signal.

[0063] See Figure 7 and Figure 8 , in some embodiments, the sorting of the pixel driving circuits corresponding to the second ends of the multiple first connection traces 204 corresponding to the same data line group 202 is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the multiple pins 2061 in the corresponding connected pin group 206, and this setting can simplify the jumper between the second end of the first connection trace 204 and the pin 2061.

[0064] See Figure 7 and Figure 8, in some embodiments, the fan-out region 20 includes a first jumper region 108 and a first fan-out region 110. The first fan-out region 110 is located between the first jumper region 108 and the chip region 30. The display module further includes: a plurality of first jumpers 208; the plurality of first jumpers 208 are disposed in the first jumper region 108. The first ends of the plurality of first jumpers 208 are respectively connected to the second ends of the plurality of first connection traces 204 and the data lines 2021 of the second display region 104 correspondingly, that is, the first ends of the plurality of first jumpers 208 are respectively connected to the lead-out ends of the second ends of the plurality of first connection traces 204 and the lead-out ends of the data lines 2021 of the second display region 104 correspondingly. The plurality of fan-out traces include: a plurality of first fan-out trace groups 210 disposed in the first fan-out region 110.

[0065] Each first fan-out trace group 210 includes a plurality of first fan-out traces 2101 arranged at intervals. The first ends of the plurality of first fan-out traces 2101 in the plurality of first fan-out trace groups 210 are respectively connected to the second ends of the plurality of first jumpers 208 correspondingly. The colors of the sub-pixels corresponding to the first fan-out traces 2101 in the same first fan-out trace group 210 are the same; at least one sub-pixel corresponding to a first fan-out trace 2101 in the first fan-out trace group 210 and the sub-pixels corresponding to the adjacent first fan-out traces 2101 in the adjacent first fan-out trace group 210 belong to the same pixel unit. In the figure, the first fan-out traces 2101 corresponding to the data lines 2021 of the first display region 102 and the second display region 104 are distinguished by lines of different thicknesses. Among them, the first fan-out traces 2101 corresponding to the data lines 2021 of the first display region 102 are thicker lines, and the first fan-out traces 2101 corresponding to the data lines 2021 of the second display region 104 are thinner lines.

[0066] Through the first jumpers 208 in the first jumper region 108, the connection between the data lines 2021 of the display region 10 and the first fan-out traces 2101 is realized. The colors of the sub-pixels corresponding to the first fan-out traces 2101 in each first fan-out trace group 210 are the same, reducing the crosstalk between adjacent first fan-out traces 2101 and realizing signal matching. By setting that at least one sub-pixel corresponding to a first fan-out trace 2101 in the first fan-out trace group 210 and the sub-pixels corresponding to the adjacent first fan-out traces 2101 in the adjacent first fan-out trace group 210 belong to the same pixel unit, the crosstalk between adjacent first fan-out traces 2101 is further reduced.

[0067] See Figure 7 and Figure 8 , in some embodiments, the first fan-out traces 2101 extend along the second direction Y, and the plurality of first fan-out traces 2101 are arranged along the first direction X. By this setting, the length of the first fan-out traces 2101 and the size of the display module are reduced.

[0068] Continue to refer toFigure 7 and Figure 8 In some embodiments, the fan-out region 20 further includes a second via region 112 and a second fan-out region 114. In the second direction Y, the second via region 112 is located between the first fan-out region 110 and the second fan-out region 114, and the second fan-out region 114 is located between the second via region 112 and the chip region 30. The display module further includes a plurality of second vias 212 disposed in the second via region 112. The first ends of the plurality of second vias 212 are respectively and correspondingly connected to the second ends of the plurality of first fan-out traces 2101 of the plurality of first fan-out trace groups 210. The plurality of fan-out traces further includes a plurality of second fan-out trace groups 214 disposed in the second fan-out region 114.

[0069] Each second fan-out trace group 214 includes a plurality of second fan-out traces 2141. The plurality of second fan-out traces 2141 in the plurality of second fan-out trace groups 214 extend along the second direction Y and are arranged in sequence along the first direction X. The first ends of the plurality of second fan-out traces 2141 in the same second fan-out trace group 214 are respectively and correspondingly connected to the second ends of the plurality of second vias 212 corresponding to the same pixel unit. The second ends of the plurality of second fan-out traces 2141 in the same second fan-out trace group 214 are respectively and correspondingly connected to a plurality of pins 2061 in the same pin group 206. The sorting of the pixel driving circuits corresponding to the plurality of second fan-out traces 2141 in the second fan-out trace group 214 is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the pins 2061 in the corresponding pin group 206. In the figure, the second fan-out traces 2141 corresponding to the data lines 2021 in the first display region 102 and the second display region 104 are distinguished by lines of different thicknesses. Among them, the second fan-out traces 2141 corresponding to the data lines 2021 in the first display region 102 are thicker lines, and the second fan-out traces 2141 corresponding to the data lines 2021 in the second display region 104 are thinner lines.

[0070] Through the second vias 212 in the second via region 112, the first fan-out traces 2101 corresponding to the same pixel unit are connected to the second fan-out traces 2141 of the same second fan-out trace group 214 in the second fan-out region 114, realizing the transmission of the data signals corresponding to each pixel driving circuit. It can be understood that the number of the second fan-out traces 2141 in the second fan-out trace group 214 is the same as the number of sub-pixels in the pixel unit. The sorting of the pixel driving circuits corresponding to the second fan-out traces 2141 in the second fan-out trace group 214 is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the plurality of pins 2061 in the corresponding pin group 206, simplifying the connection between the second fan-out traces 2141 and the pins 2061.

[0071] participate Figure 7 and Figure 8, in some embodiments, the second display area 104 includes: a second edge display area 216 and a second middle display area 218.

[0072] The second end of the first connection trace 204 is disposed in the second edge display area 216; in the second direction Y, a plurality of first crossover traces 208 are disposed in the first crossover area 108 on one side of the second edge display area 216, and a plurality of first fan-out trace groups 210 are disposed in the first fan-out area 110 on one side of the second edge display area 216; in the first direction X, the second middle display area 218 is located on the side of the second edge display area 216 away from the first display area 102. By disposing the second end of the first connection trace 204 in the second edge display area 216 close to the first display area 102, the influence of the first connection trace 204 on the display quality of the second middle display area 218 is effectively avoided.

[0073] See Figure 7 , in some embodiments, the display module further includes: a plurality of third crossover traces 302; in the second direction Y, a plurality of third crossover traces 302 are disposed in the first crossover area 108 on one side of the second middle display area 218; the first ends of the plurality of third crossover traces 302 are respectively connected to a plurality of data lines 2021 in a plurality of data line groups 202 of the second middle display area 218; the plurality of fan-out traces further includes: a plurality of third fan-out trace groups 304; the plurality of third fan-out trace groups 304 are disposed in the first fan-out area 110 on one side of the second middle display area 218.

[0074] The third fan-out trace group 304 includes a plurality of third fan-out traces 3041. The first ends of the plurality of third fan-out traces 3041 in the plurality of third fan-out trace groups 304 are respectively connected to the second ends of the plurality of third crossover traces 302. The colors of the sub-pixels corresponding to the plurality of third fan-out traces 3041 in the same third fan-out trace group 304 are the same; the sub-pixels corresponding to the adjacent two third fan-out traces 3041 in the adjacent two third fan-out trace groups 304 belong to different pixel units.

[0075] Through the third crossover trace 302, the connection between the data line 2021 of the second middle display area 218 and the third fan-out trace 3041 of the first fan-out area 110 is realized. The colors of the sub-pixels corresponding to the third fan-out traces 3041 in the third fan-out trace group 304 are the same, reducing the crosstalk between the adjacent third fan-out traces 3041 and realizing signal matching.

[0076] Continue to refer to Figure 7, in some embodiments, the display module further includes: a plurality of fourth cross lines 306; in the second direction Y, the plurality of fourth cross lines 306 are disposed in the second cross line area 112 on one side of the second middle display area 218; the first ends of the plurality of fourth cross lines 306 are respectively and correspondingly connected to the second ends of the plurality of third fan-out lines 3041 of the plurality of third fan-out line groups 304; the plurality of fan-out lines further include: a plurality of fourth fan-out line groups 308 disposed in the second fan-out area 114 on one side of the second middle display area 218.

[0077] The fourth fan-out line group 308 includes a plurality of fourth fan-out lines 3081. The plurality of fourth fan-out lines 3081 in the plurality of fourth fan-out line groups 308 extend along the second direction Y and are arranged in sequence along the first direction X. The first ends of the plurality of fourth fan-out lines 3081 in the same fourth fan-out line group 308 are respectively and correspondingly connected to the second ends of the plurality of fourth cross lines 306 corresponding to the same pixel unit. The second ends of the plurality of fourth fan-out lines 3081 in the same fourth fan-out line group 308 are respectively and correspondingly connected to a plurality of pins 2061 in the same pin group 206. The sorting of the pixel driving circuits corresponding to the plurality of fourth fan-out lines 3081 in the fourth fan-out line group 308 is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the plurality of pins 2061 in the corresponding pin group 206.

[0078] Through the fourth cross lines 306 in the second cross line area 112, the third fan-out lines 3041 corresponding to the same pixel unit are connected to the fourth fan-out lines 3081 of the same fourth fan-out line group 308 in the second fan-out area 114, so as to realize the transmission of the data signals corresponding to the pixel driving circuits in the second middle display area 208. It can be understood that the number of the fourth fan-out lines 3081 in the fourth fan-out line group 308 is the same as the number of sub-pixels in the pixel unit. The sorting of the pixel driving circuits corresponding to the fourth fan-out lines 3081 in the fourth fan-out line group 308 is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the plurality of pins 2061 in the corresponding pin group 206, which simplifies the connection between the fourth fan-out lines 3081 and the pins 2061.

[0079] Continue to refer to Figure 7, in some embodiments, the display module further includes: a driving chip 310 disposed in the chip region 30; the driving chip 310 includes the plurality of pin groups 206, and a plurality of multiplexing circuit groups are provided inside the driving chip 310, that is, the driving chip 310 is an EMUX IC, and the plurality of pins 2061 in the same pin group 206 are respectively connected to the plurality of multiplexing circuit groups; the plurality of pins 2061 in the plurality of pin groups 206 corresponding to the sub-pixels of the same color are respectively connected to the same multiplexing circuit group, so as to realize the corresponding connection between the plurality of sub-pixels in the pixel unit and the multiplexing circuit, saving the cost of the driving chip and the OBL space. It can be understood that the number of multiplexing circuit groups is the same as the number of sub-pixels in the pixel unit, the multiplexing circuit group includes a plurality of multiplexing circuits, the plurality of multiplexing circuits are used to send data signals corresponding to the sub-pixels of the same color, the plurality of multiplexing circuits are respectively connected to the sub-pixels of the same color in the plurality of pixel units, and the number of multiplexing circuits in the multiplexing circuit group is the same as the number of pixel units in the display area.

[0080] Exemplarily, the pixel units in the display area include N3 pixel units, and the pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel. At this time, the driving chip 310 includes 3 multiplexing circuit groups, and each multiplexing circuit group includes N3 multiplexing circuits; the multiplexing circuit group corresponding to the red sub-pixel includes N3 multiplexing circuits for sending data signals corresponding to the red sub-pixel, the multiplexing circuit group corresponding to the blue sub-pixel includes N3 multiplexing circuits for sending data signals corresponding to the blue sub-pixel, and the multiplexing circuit group corresponding to the green sub-pixel includes N3 multiplexing circuits for sending data signals corresponding to the green sub-pixel.

[0081] In some embodiments, the plurality of sub-pixels of different colors include a first sub-pixel and a second sub-pixel, and the brightness value of the first sub-pixel is greater than the brightness value of the second sub-pixel, that is, the contribution of the first sub-pixel to the brightness of the pixel unit is greater than the contribution of the second sub-pixel to the brightness of the pixel unit; wherein, when the multiplexing circuit group corresponding to the first sub-pixel transmits the data signal, it is later than the time when the multiplexing circuit group corresponding to the second sub-pixel transmits the data signal. This setting can reduce the influence of crosstalk between the multiplexing circuits in the multiplexing circuit group on the brightness of the pixel unit.

[0082] In some embodiments, the plurality of sub-pixels of different colors in the same pixel unit include a red sub-pixel, a blue sub-pixel, and a green sub-pixel. The time when the multiplexing circuit corresponding to the red sub-pixel transmits the data signal is later than the time when the data signal multiplexing circuit corresponding to the blue sub-pixel transmits the data signal, and earlier than the time when the data signal multiplexing circuit corresponding to the green sub-pixel transmits the data signal. The brightness value of the green sub-pixel is greater than the brightness value of the red sub-pixel, and the brightness value of the red sub-pixel is greater than the brightness value of the blue sub-pixel. This setting can reduce the influence of crosstalk between the multiplexing circuits in the multiplexing circuit group on the brightness of the pixel unit.

[0083] such as Figure 7The display module shown has a display area 10, a fan-out area 20, and a chip area 30 arranged in sequence in the second direction Y. The display area 10 includes a first display area 102 and a second display area 104 arranged in sequence in the first direction X. The second display area 104 includes a second edge display area 216 and a second middle display area 218 arranged in the first direction X. In the second direction Y, the fan-out area 20 is adjacent to the second display area 104. The fan-out area 20 includes a first via area 108, a first fan-out area 110, a second via area 112, and a second fan-out area 114 arranged in sequence along the second direction. The display area includes a plurality of pixel units, and each pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel. Each sub-pixel includes a corresponding light-emitting unit and a pixel driving circuit. The data line group 202 in the first display area 102 includes 3 data lines 2021, and the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 are all sorted in the order of RGB. The data line group 202 in the second display area 104 includes 3 data lines 2021, and the pixel driving circuits corresponding to the data lines 2021 in the data line group 202 are also sorted in the order of RGB. The first end of the first connection trace 204 is connected to the data line 2021 in the first display area 102, and the second end of the first connection trace 204 is located between adjacent data lines 2021 in the second edge display area 216 of the second display area 104. In the first direction X, the second end of the first connection trace 204 and the data lines 2021 in the second display area 104 are alternately arranged. Assuming that in the first direction X, the total length of the first display area 102 and the second display area 104 is L0, then the total length L01 of the first display area 102 and the second edge display area 216 is less than or equal to one-half of L0. The pixel driving circuits corresponding to the data signals transmitted by the pin group 206 corresponding to the data line group 202 in the first display area 102 are sorted in the order of RGB. The pixel driving circuits corresponding to the data signals transmitted by the pin group 206 corresponding to the data line group 202 in the second display area 104 are sorted in the order of RGB. The first connection trace 204 connects the 3 data lines 2021 in the data line group 202 in the first display area 102 to the second display area 104 in the order of RGB. At this time, the pixel driving circuits corresponding to the data line 1021 in the second display area 102 and the second end of the first connection trace 204 are sorted in the order of RRGGBB repeatedly. The pixel driving circuits corresponding to the first fan-out traces 2101 in the first fan-out area 110 are sorted in the order of RRGGBB. Two first fan-out traces 2101 of adjacent and corresponding same-color sub-pixels form a first fan-out trace group 210, that is, the first fan-out traces 2101 corresponding to RR, GG, and BB respectively form a first fan-out trace group 210. The adjacent first fan-out traces 2101 in two adjacent first fan-out trace groups 210 belong to the same pixel unit, that is, adjacent R and G belong to the same pixel unit, adjacent G and B belong to the same pixel unit, and adjacent B and R belong to the same pixel unit;The first cross-line 208 in the first cross-line area 108 enables the data lines 1021 of the second display area 102 and the second end of the first connection trace 204 to be connected to the first fan-out trace 2101; wherein, according to whether the corresponding data line 2021 is located in the first display area 102 or the second display area 104, the first fan-out area 110 is arranged in a cycle of 12 first fan-out traces 2101, the first cross-line area 108 is arranged in a cycle of 12 first cross-lines 208, and according to the color of the sub-pixels corresponding to the corresponding data line 2021, the first fan-out area 110 is arranged in a cycle of 6 first fan-out traces 2101. The pixel driving circuits corresponding to the data signals transmitted by the pins 2061 are sorted in the order of RGBRGBRGB in sequence; the sorting of the pixel driving circuits corresponding to the second fan-out traces 2141 in the second fan-out area 114 is the same as the sorting of the pins 2061, which is also RGBRGBRGB, and 3 second fan-out traces 2141 corresponding to the pixel driving circuits with the sorting of RGB corresponding to the same pixel unit form a second fan-out trace group 214; the second cross-line 212 in the second cross-line area 112 enables the connection between the first fan-out trace 2101 corresponding to the same pixel unit and the second fan-out trace 2141 in the same second fan-out trace group 214 in the second fan-out area 114, and the second cross-line 112 intersects with less than or equal to 3 second cross-lines 1112. Wherein, according to whether the corresponding data line 2021 is located in the first display area 102 or the second display area 104, the second fan-out area 114 is arranged in a cycle of 6 second fan-out traces 214, and in sequence, the data lines 2021 corresponding to 3 second fan-out traces 2141 are located in the second display area 104, the data lines 2021 corresponding to 3 second fan-out traces 2141 are located in the first display area 102, the second cross-line area 112 is arranged in a cycle of 12 second cross-lines 212, and according to the color of the sub-pixels corresponding to the corresponding data line 2021, the second fan-out area 114 is arranged in a cycle of 3 second fan-out traces 2141. The driving chip 310 includes a pin group 206, and there are 3 multiplexing circuit groups inside the driving chip 310. The first multiplexing circuit group includes multiple multiplexing circuits 1, denoted as MUX1, the second multiplexing circuit group includes multiple multiplexing circuits 2, denoted as MUX2, and the third multiplexing circuit group includes multiple multiplexing circuits 3, denoted as MUX3; wherein, MUX1, MUX2, and MUX3 transmit data signals at different times. MUX1 transmits data signals first, and after MUX1 stops transmitting data signals, MUX2 transmits data signals, and after MUX2 stops transmitting data signals, MUX3 transmits data signals; the pins 2061 corresponding to the red sub-pixels in each pin group 206 are respectively connected to the multiplexing circuits 1 in the first multiplexing circuit group, the pins 2061 corresponding to the green sub-pixels are respectively connected to the multiplexing circuits 2 in the second multiplexing circuit group, and the pins 2061 corresponding to the blue sub-pixels are respectively connected to the multiplexing circuits 3 in the third multiplexing circuit group.;

[0084] Furthermore, additional circuits such as shorting bars, PCDs, and ESDs can be added between the first fan-out region 110 and the second crossover region 112.

[0085] Figure 8 The difference between the shown display module and Figure 7 the corresponding display module is that in the first direction X, there are 3 data lines 2021 of the second display area 104 between the second ends of adjacent first connection traces 204. The total length L01 of the first display area 102 and the second edge display area 216 is less than or equal to one-fourth of L0. The pixel driving circuits corresponding to the data signals transmitted by the pin group 206 corresponding to the data line group 202 of the first display area 102 are sorted in BGR order. The data lines 1021 of the second display area 102 and the pixel driving circuits corresponding to the second ends of the first connection traces 204 are sorted in the order of RBGBRGGBRRGB repeatedly. At least one sub-pixel corresponding to a first fan-out trace 2101 in the first fan-out trace group 210 and the sub-pixels corresponding to the adjacent first fan-out traces 2101 in the adjacent first fan-out trace group 210 belong to the same pixel unit, and there are sub-pixels corresponding to the first fan-out trace 2101 in the first fan-out trace group 210 and the adjacent first fan-out traces 2101 in the adjacent first fan-out trace group 210 that do not belong to the same pixel unit. The pixel driving circuits corresponding to the data signals transmitted by the pin 2061 are sorted in the order of RGBBGRRGBRGB in sequence; the sorting of the pixel driving circuits corresponding to the second fan-out traces 2141 in the second fan-out region 114 is the same as the sorting of the pin 2061, which is also RGBBGRRGBRGB. The second crossover 112 intersects with less than or equal to 5 second crossovers 1112. According to whether the corresponding data lines 2021 are located in the first display area 102 or the second display area 104, the second fan-out region 114 is arranged in a cycle of 12 second fan-out traces 214. In sequence, the data lines 2021 corresponding to 3 second fan-out traces 2141 are located in the second display area 104, the data lines 2021 corresponding to 3 second fan-out traces 2141 are located in the first display area 102, and the data lines 2021 corresponding to 6 second fan-out traces 2141 are located in the second display area 104.

[0086] Based on the same inventive concept, an embodiment of the present application also provides a display device. Figure 9 It is a schematic structural diagram of the display device 200 provided by the embodiment of the present application, as Figure 9 shown. The display device 200 includes the display module 100 in any of the above embodiments. Exemplarily, as Figure 9As shown, the display device 200 includes a display module 100. Therefore, the display device 200 also has the beneficial effects of the display module 100 in the above embodiments. For the same parts, reference may be made to the explanations of the display module 100 above, and details will not be repeated hereinafter.

[0087] The display device 200 provided in the embodiment of the present application can be Figure 9 the mobile phone shown in the figure, or any electronic product with a display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, industrial control equipment, medical display screen, touch interaction terminal, etc. The embodiment of the present application does not make special limitations on this.

[0088] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0089] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A display module, characterized in that, The display module is provided with a display area, the display area includes a first display area and a second display area arranged in sequence along a first direction, the display area includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels of different colors; the display module includes: A plurality of data line groups are arranged in the display area, each data line group includes a plurality of data lines, and the plurality of data lines are respectively connected to a plurality of sub-pixels of different colors in the same pixel unit, and the pixel units connected by different data line groups are different; A plurality of first connection traces are arranged in the display area, the first ends of the plurality of first connection traces are respectively connected to the plurality of data lines located in the first display area, and the second ends of the first connection traces are located between two adjacent data lines in the second display area; at least one of the first connection traces corresponds to a sub-pixel of the same color as the adjacent data line located in the second display area.

2. The display module according to claim 1, wherein, The sub-pixel includes a light-emitting unit and a pixel driving circuit, and there are the same number of data lines between the second ends of two adjacent first connection traces; Wherein, the sorting of the pixel driving circuits corresponding to the data lines of the plurality of data line groups in the second display area is the same.

3. The display module according to claim 2, wherein In the first direction, the second ends of the first connection traces and the data lines are alternately arranged.

4. The display module according to claim 2, wherein In the first direction, the number of data lines between the second ends of two adjacent first connection traces is equal to the number of sub-pixels in the same pixel unit.

5. The display module according to claim 1, wherein The sub-pixel includes a light-emitting unit and a pixel driving circuit, the display module is further provided with a chip area and a fan-out area, the display area, the fan-out area and the chip area are arranged in sequence along a second direction, the fan-out area is adjacent to the second display area, and the second direction intersects with the first direction; The display module further includes: A plurality of pin groups are arranged in the chip area, the pin group includes a plurality of pins, and the plurality of pins are respectively connected to the plurality of data lines of the same data line group, and the pins are used to transmit corresponding data signals to the pixel driving circuits connected correspondingly; A plurality of fan-out traces are arranged in the fan-out area, one ends of the plurality of fan-out traces are respectively connected to the second ends of the plurality of first connection traces and the plurality of data lines in the second display area, and the other ends of the plurality of fan-out traces connected by the same data line group are connected to the same pin group correspondingly.

6. The display module according to claim 5, wherein The sorting of the pixel driving circuits corresponding to the second ends of the first connection traces is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the plurality of pins in the corresponding pin group.

7. The display module according to claim 1, characterized in that, In the first display area, among two adjacent data line groups, the second end of the first connection trace corresponding to the data line group closer to the second display area is closer to the first display area.

8. The display module according to claim 1, wherein The sorting of the pixel driving circuits corresponding to the data lines in the data line group of the first display area is the same as the sorting of the pixel driving circuits corresponding to the data lines in the data line group of the second display area.

9. The display module according to claim 5, characterized in that The first connection trace includes: The first wiring portion is at least partially disposed in the first display area, and one end of the first wiring portion is connected to the data line corresponding to the first display area; the first wiring portion extends along the first direction; The second wiring portion is disposed in the second display area, one end of the second wiring portion is connected to the other end of the first wiring portion, and the other end of the second wiring portion is located between two adjacent data lines in the second display area; the second wiring portion extends along the second direction; Wherein, the data lines extend along the second direction, and multiple data lines are arranged in sequence along the first direction.

10. The display module according to claim 9, characterized in that, Among two adjacent data line groups in the first display area, the lengths of the respective first wiring portions corresponding to the data line group closer to the second display area are smaller than the lengths of the respective first wiring portions corresponding to the data line group farther from the second display area; and the lengths of the respective second wiring portions corresponding to the data line group closer to the second display area are smaller than the lengths of the respective second wiring portions corresponding to the data line group farther from the second display area.

11. The display module according to claim 9, wherein, The display module further includes: Multiple second connection wirings are disposed in the second display area, the multiple second connection wirings are respectively arranged corresponding to the multiple second wiring portions, and are on the extension lines of the multiple second wiring portions and are separated from the corresponding second wiring portions.

12. The display module according to claim 5, wherein The fan-out area includes a first crossover area and a first fan-out area, and the first fan-out area is located between the first crossover area and the chip area; the display module further includes: Multiple first crossovers are disposed in the first crossover area, and the first ends of the multiple first crossovers are respectively connected to the second ends of the multiple first connection wirings and the multiple data lines in the second display area; The multiple fan-out wirings include: Multiple first fan-out wiring groups are disposed in the first fan-out area, each first fan-out wiring group includes multiple first fan-out wirings, the first ends of the multiple first fan-out wirings in the multiple first fan-out wiring groups are respectively connected to the second ends of the multiple first crossovers, and the colors of the sub-pixels corresponding to the multiple first fan-out wirings in the same first fan-out wiring group are the same; at least one sub-pixel corresponding to a first fan-out wiring in the first fan-out wiring group and the sub-pixels corresponding to adjacent first fan-out wirings in an adjacent first fan-out wiring group belong to the same pixel unit.

13. The display module according to claim 12, characterized in that, The first fan-out wiring extends along the second direction, and multiple first fan-out wirings are arranged along the first direction.

14. The display module according to claim 12, wherein The fan-out area further includes: a second fan-out area and a second crossover area, the second crossover area is located between the first fan-out area and the second fan-out area, and the second fan-out area is located between the second crossover area and the chip area; the display module further includes: Multiple second crossovers are disposed in the second crossover area, and the first ends of the multiple second crossovers are respectively connected to the second ends of the multiple first fan-out wirings in the multiple first fan-out wiring groups; The multiple fan-out wirings further include: A plurality of second fan-out wiring groups are disposed in the second fan-out area. The second fan-out wiring groups include a plurality of second fan-out wirings. The plurality of second fan-out wirings in the plurality of second fan-out wiring groups extend along the second direction and are arranged in sequence along the first direction. The first ends of the plurality of second fan-out wirings in the same second fan-out wiring group are respectively correspondingly connected to the second ends of the plurality of second cross-wirings corresponding to the same pixel unit. The second ends of the plurality of second fan-out wirings in the same second fan-out wiring group are respectively correspondingly connected to a plurality of pins in the same pin group. The sorting of the pixel driving circuits corresponding to the plurality of second fan-out wirings in the second fan-out wiring group is the same as the sorting of the pixel driving circuits corresponding to the data signals transmitted by the pins in the corresponding pin group.

15. The display module according to claim 12, wherein The second display area includes: A second edge display area, where the second end of the first connection wiring is disposed in the second edge display area; in the second direction, the plurality of first cross-wirings are disposed in the first cross-wiring area on one side of the second edge display area, and the plurality of first fan-out wiring groups are disposed in the first fan-out area on one side of the second edge display area; A second middle display area, located on the side of the second edge display area away from the first display area.

16. The display module according to claim 15, wherein The display module further includes: A plurality of third cross-wirings are disposed in the first cross-wiring area on one side of the second middle display area. The first ends of the plurality of third cross-wirings are respectively correspondingly connected to a plurality of data lines in the plurality of data line groups in the second middle display area; The plurality of fan-out wirings further include: A plurality of third fan-out wiring groups are disposed in the first fan-out area on one side of the second middle display area. The third fan-out wiring groups include a plurality of third fan-out wirings. The first ends of the plurality of third fan-out wirings in the plurality of third fan-out wiring groups are respectively correspondingly connected to the second ends of the plurality of third cross-wirings. The sub-pixels corresponding to the plurality of third fan-out wirings in the same third fan-out wiring group have the same color; the sub-pixels corresponding to the adjacent two third fan-out wirings in the adjacent two third fan-out wiring groups belong to different pixel units.

17. The display module according to claim 5, wherein The sorting of the pixel driving circuits corresponding to the plurality of pins transmitting data signals in any two pin groups is the same; and / or In the first display area, the sorting of the pixel driving circuits corresponding to the plurality of data lines in any two data line groups is the same; and / or The sorting of the pixel driving circuits corresponding to the plurality of data lines in any data line group in the first display area is the same as the sorting of the pixel driving circuits corresponding to the plurality of data lines in any data line group in the second display area.

18. The display module according to claim 5, wherein, The display module further includes: A driving chip is disposed in the chip area and includes the plurality of pin groups. A plurality of multiplexing circuit groups are provided inside the driving chip. The plurality of pins in the same pin group are respectively correspondingly connected to the plurality of multiplexing circuit groups; the plurality of pins in the plurality of pin groups corresponding to the sub-pixels of the same color are respectively correspondingly connected to the same multiplexing circuit group.

19. The display module according to claim 18, wherein The multiple sub-pixels of different colors include a first sub-pixel and a second sub-pixel, and the brightness value of the first sub-pixel is greater than that of the second sub-pixel; Wherein, the time when the multiplexing circuit group corresponding to the first sub-pixel transmits a data signal is later than the time when the multiplexing circuit group corresponding to the second sub-pixel transmits a data signal.

20. The display module according to claim 19, wherein The multiple sub-pixels of different colors in the same pixel unit include a red sub-pixel, a blue sub-pixel, and a green sub-pixel. The time when the multiplexing circuit corresponding to the red sub-pixel transmits a data signal is later than the time when the data signal multiplexing circuit corresponding to the blue sub-pixel transmits a data signal, and earlier than the time when the data signal multiplexing circuit corresponding to the green sub-pixel transmits a data signal.

21. A display device, characterized in that, It includes the display module according to any one of claims 1 to 20.

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