Multi-core memory controller

Abstract

This disclosure provides systems, methods, and apparatus for a memory system that operates at least a portion of a memory core at a lower frequency than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core to schedule a first memory operation for a first portion of a clock cycle of a memory clock, and includes a second core to schedule a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 059,937, filed on November 29, 2022, entitled "MULTIPLE - CORE MEMORY CONTROLLER", the entire content of which is hereby incorporated by reference in its entirety. Technical Field

[0003] In general, aspects of the present disclosure relate to computer information systems, and more particularly to memory systems for storing data. Some features can implement and provide improved memory capabilities for interfacing a host device to a memory. Background Art

[0004] Computing devices (e.g., laptop computers, mobile phones, etc.) may include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions, etc. Memory is an important component of a computing device. The processor may be coupled to the memory to perform the above - mentioned computing functions. For example, the processor may obtain instructions from the memory to perform computing functions, and / or store temporary data for processing these computing functions within the memory, and so on. Summary of the Invention

[0005] Some aspects of the present disclosure are outlined below to provide a basic understanding of the technologies discussed. This summary is not an extensive review of all the expected features of the present disclosure, and is neither intended to identify the key or important elements of all aspects of the present disclosure, nor to delineate the scope of any or all aspects of the present disclosure. Its sole purpose is to present some concepts of one or more aspects of the present disclosure in an overview form as a prelude to the more detailed description that follows.

[0006] A device according to at least one embodiment includes a memory controller configured to perform communication from a host device to a memory. The memory includes a memory array configured to store data. The memory is configured to provide data stored in the memory array to the host when performing a computing function upon request of the memory controller. The memory controller may include a plurality of cores configured to schedule memory operations for the memory. In some aspects, the memory controller may interface with the memory at a first speed (e.g., memory clock frequency). The cores of the memory controller may operate at a second speed (e.g., memory controller clock frequency) that is lower than the memory speed (e.g., memory clock frequency). The bandwidth or speed of transferring data to and / or from the memory is proportional to the memory clock. The configuration for the memory controller according to aspects described herein provides for operating a plurality of cores at a speed slower than the memory, where the utilization of the bandwidth available from the memory based on the memory clock is slightly reduced or not reduced. A device according to at least one embodiment includes a host device having a memory controller configured with a plurality of cores to communicate with a memory according to aspects described herein.

[0007] In one aspect of the present disclosure, a method for scheduling memory operations based on memory requests received from components of a host device includes: scheduling, by a first core of a plurality of cores of a memory controller, a first memory operation for a first portion of a clock cycle of a memory clock; scheduling, by a different second core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock; and during the clock cycle of the memory clock, sending, via a memory physical (PHY) interface of the memory controller, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation.

[0008] In further aspects of the present disclosure, a device includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform operations including: scheduling, by a first core of a plurality of cores of a memory controller, a first memory operation for a first portion of a clock cycle of a memory clock; scheduling, by a different second core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock; and during the clock cycle of the memory clock, sending, via a memory physical (PHY) interface of the memory controller, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation. The processor may be a processor, controller, or other logic circuit in a host. The processor may alternatively be a controller embedded in a memory device.

[0009] In another aspect of the present disclosure, an apparatus includes: a unit for scheduling, by a first core of a plurality of cores of a memory controller, a first memory operation for a first portion of a clock cycle for a memory clock; a unit for scheduling, by a different second core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle for the memory clock; and a unit for transmitting, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation through a memory physical (PHY) interface of the memory controller.

[0010] In a further aspect of the present disclosure, an apparatus may include: a memory controller operating at a memory controller clock frequency based on a first clock, wherein the memory controller includes a memory physical (PHY) interface operating at a memory clock frequency based on the memory clock and a plurality of cores, each of the plurality of cores operating at the memory controller clock frequency less than the memory clock frequency, coupled to a memory through a channel by the memory physical (PHY) interface, configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and configured to perform operations including: scheduling, by a first core of the plurality of cores of the memory controller, a first memory operation for a first portion of a clock cycle for the memory clock; scheduling, by a different second core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle for the memory clock; and transmitting, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation through the memory physical (PHY) interface of the memory controller.

[0011] In another aspect of the present disclosure, an apparatus may include a memory controller as part of a host device configured to communicate with a memory through a channel according to aspects of the disclosure herein. The host device may include components configured to share the content of the memory and access the memory through the channel and the memory controller. For example, the host device may include components such as a processor, a graphics processor, a neural processor including one or more neural processing cores, and / or a digital signal processor (DSP). In some embodiments, the host device is integrated in a single semiconductor package having the memory controller and / or the memory.

[0012] In another aspect of the present disclosure, a device (such as a wireless device) includes: at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory via a memory controller coupled to a channel that couples the processor to the memory. The processor can be a processor, controller, or other logic circuit in a host.

[0013] In another aspect of the present disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein with respect to aspects of the present disclosure.

[0014] The memory in the present disclosure can be embedded within a processor on a semiconductor die or be part of a different semiconductor die. The memory can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash memory, or NOR flash memory, etc.

[0015] In the present disclosure, methods and apparatuses are presented by way of non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, LPDDR memory operates according to LPDDR specifications published by the Joint Electron Device Engineering Council (JEDEC). One such LPDDR specification can be LPDDR5. Another such LPDDR specification can be LPDDR6.

[0016] For those of ordinary skill in the art, other aspects, features, and implementations will become apparent when reading the following description of specific exemplary aspects in conjunction with the accompanying drawings. Although the following may discuss certain features with respect to some aspects and the drawings, each aspect can include one or more of the advantageous features discussed herein. In other words, although one or more aspects may be discussed as having certain advantageous features, one or more of such features can also be used according to each aspect. In a similar manner, although the exemplary aspects may be discussed below as device, system, or method aspects, the exemplary aspects can be implemented in various devices, systems, and methods.

[0017] The method can be embedded in a computer-readable medium as computer program code including instructions to cause a processor to perform the steps of the method. In some embodiments, the processor can be part of a mobile device including a first network adapter configured to send data (such as an image or video in a record or as streaming data) on a first network connection of a plurality of network connections. The processor can be coupled to the first network adapter and a memory for storing data to support processing and communication operations performed by the processor. The network adapter can support communication on a wireless communication network such as a 5G NR communication network. The processor can cause transmission of data stored in the memory over the wireless communication network.

[0018] The foregoing has outlined rather broadly the features and technical advantages of examples according to the present disclosure so that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter. The disclosed concepts and specific examples can readily be used as a basis for modifying or designing other structures for accomplishing the same purposes as the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein, both as to their organization and method of operation, as well as associated advantages, will be better understood when considered in conjunction with the accompanying drawings. Each drawing is provided for the purpose of illustration and description and is not to be construed as a definition of the limits of the claims.

[0019] While aspects and implementations are described herein by way of some examples, those skilled in the art will understand that additional implementations and use cases can be realized in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects and / or uses can be realized via integrated chip implementations and other non-module component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial devices, retail / purchase devices, medical devices, devices implementing artificial intelligence (AI), etc.). While some examples may be specifically targeted at a use case or application, or may not be specifically targeted at a use case or application, there can be a wide variety of applicability of the innovations described. Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the innovative solutions described. In some practical settings, devices incorporating the aspects and features described may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily includes multiple components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.). The innovations described herein are intended to be implementable in a variety of devices, chip-level components, systems, distributed arrangements, or end-user devices having different sizes, shapes, and configurations. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] A further understanding of the nature and advantages of the present disclosure can be realized by reference to the following drawings. In the drawings, like components or features may have the same reference numeral. Additionally, various components of the same type can be distinguished by following the reference numeral with a dash and a second numeral, which is used to distinguish among similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0021] Figure 1 A block diagram is shown of an example computing system including a host, a memory, and a channel coupling the host to the memory, in accordance with one or more aspects of the present disclosure.

[0022] Figure 2 A block diagram is shown of an example computing system including a host, a memory, and a channel coupling the host and the memory in another implementation employing a channel, in accordance with one or more aspects of the present disclosure.

[0023] Figure 3A is an example timing diagram for sending commands from different cores on different clock edges according to some aspects of the present disclosure.

[0024] Figure 3B is an example timing diagram for sending timestamped commands from different cores on different clock edges according to some aspects of the present disclosure.

[0025] Figure 4 is a block diagram illustrating a memory controller with asymmetric cores according to one aspect of the present disclosure.

[0026] Figure 5 is a flowchart of an example method of operation for a memory controller with multiple cores according to some aspects of the present disclosure.

[0027] Figure 6A and Figure 6B illustrates waveforms for transferring data through an example channel in a write operation according to certain aspects of the present disclosure.

[0028] Figure 7A and Figure 7B illustrates waveforms for transferring data through an example channel in a read operation according to certain aspects of the present disclosure.

[0029] Like reference numerals and names in the various figures indicate like elements. Detailed Description

[0030] The "Detailed Description" set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to limit the scope of the present disclosure. Rather, for the purpose of providing a thorough understanding of the innovative subject matter, the Detailed Description includes specific details. It will be apparent to those skilled in the art that these specific details are not required in every instance and that in some instances, well-known structures and components are shown in block diagram form for clarity of presentation.

[0031] The present disclosure provides systems, apparatuses, methods, and computer-readable media that support data processing, including techniques for interfacing a memory controller to a memory in an electronic device, such as a wireless communication device. The memory controller may interface with the memory at a first speed, e.g., a memory clock frequency. Cores of the memory controller may operate at a second speed, e.g., a clock rate, that is lower than the memory speed, e.g., the memory clock. The bandwidth or speed of transferring data to and / or from the memory is proportional to the memory clock. Configurations for the memory controller according to aspects described herein provide for operating multiple cores at a speed slower than the memory, with little or no reduction in the utilization of the bandwidth available to the memory based on the memory clock.

[0032] Specific implementations of the subject matter described in this disclosure can be realized to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides reduced cost by allowing portions of the memory controller to operate at a slower speed, which can reduce the complexity of circuit design and manufacturing. In some aspects, this disclosure provides reduced power consumption because power consumption can scale with the clock frequency, and the lower frequency at each of the cores significantly reduces the power consumption in the memory controller.

[0033] Figure 1 Apparatus 100 is shown including host 110, memory 150, and channel 190 that couples host 110 and memory 150. Apparatus 100 can be, for example, a device such as: a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop computer, a cellular phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a stand-alone digital camera or digital video camcorder, a wireless communication device phone equipped with a camera, such as a mobile phone, a cellular or satellite wireless phone, a personal digital assistant (PDA), a panel or tablet computer, a gaming device, a computing device such as a webcam, a video surveillance camera, or other devices having digital imaging or video capabilities) and / or a multimedia system (e.g., a television, a compact disc player, a streaming device).

[0034] Host 110 can include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). Host 110 can be configured to communicate with memory 150 (e.g., memory 150-1 to 150-4) and couple to memory 150 (e.g., memory 150-1 to 150-4) via channel 190 (e.g., channels 190-1 to 190-4) when performing a computing function (such as one of data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc.). For example, memory 150-1 to 150-4 can store instructions or data for the host to perform the computing function.

[0035] The host 110 may include a memory controller 130, which may include controller PHY modules 134-1 to 134-4. Each of the controller PHY modules 134-1 to 134-4 may be coupled to a respective one of memories 150-1 to 150-4 via respective channels 190-1 to 190-4. For ease of reference, reads and writes are referenced from the perspective of the host 110. For example, in a read operation, the host 110 may receive stored data from one or more of memories 150-1 to 150-4 via one or more of channels 190-1 to 190-4. In a write operation, the host 110 may provide data to be written for storage into one or more of memories 150-1 to 150-4 via one or more of channels 190-1 to 190-4. The memory controller 130 may be configured to control various aspects of the communication to and from memories 150-1 to 150-4, such as the logical layer. The controller PHY modules 134-1 to 134-4 may be configured to respectively control the electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) of the signals provided or received on channels 190-1 to 190-4.

[0036] In some examples, memories 150-1 to 150-4 may be LPDDR DRAMs (e.g., LPDDR5, LPDDR6). In some examples, memories 150-1 to 150-4 may be different types of memories respectively (such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM). The host 110, memories 150-1 to 150-4, and / or channels 190-1 to 190-4 may operate according to the LPDDR (e.g., LPDDR5, LPDDR6) specification. In some examples, each of channels 190-1 to 190-4 may include 16-bit data (e.g., 16 DQs). In some examples, each of channels 190-1 to 190-4 may operate on 32-bit data (e.g., 32 DQs). In Figure 1 which, four channels are shown. However, the device 100 may include more or fewer channels, such as 8 or 16 channels.

[0037] Figure 2 The configurations of the host 110, the memory 150, and the channel 190 according to some aspects of the present disclosure are shown in more detail in Figure 2 is illustrated with Figure 1Another representation of apparatus 100 with host 110, memory 150, and channel 190. The channel 190 between host 110 and memory 150 may include multiple connections, some of which carry data (e.g., user data or application data), and some of which carry non-data (e.g., addresses and other signaling information). For example, the non-data connections in channel 190 may include: a data clock (e.g., WCK) for providing data to respective memories 150 on a per-byte basis, and a read data strobe (e.g., RDQS) for receiving data from respective memories 150 on a per-byte basis. Channel 190 may further include data mask (e.g., DM, sometimes referred to as data mask invert DMI, to indicate multiple functions performed by signal connections) signaling for masking certain portions of data during a write operation. Channel 190 may further include command and address (e.g., CA[0:n]) and an associated CA clock to provide commands (e.g., read or write commands) to memory 150.

[0038] Host 110 may include at least one processor 120, which may include CPU 122, GPU 123, and / or NPU 124. Host 110 may further include a memory controller 130 having a controller PHY module 134 and logic circuitry 132. Memory controller 130 may be coupled to at least one processor 120 via a bus system 115 when performing various computing functions. The term "bus system" may provide that elements coupled to the "bus system" may exchange information directly or indirectly with each other. In different embodiments, the "bus system" may include multiple physical connections and intermediate stages such as buffers, latches, registers, etc. Modules may be implemented in hardware, software, or a combination of hardware and software. Logic circuitry 132 may coordinate the execution of memory requests received on bus system 115, such as by scheduling the transmission of signals on connections of channel 190 via control controller PHY module 134.

[0039] Memory controller 130 may send data blocks to other modules (such as at least one processor 120 and / or memory 150) and / or receive data blocks. Memory 150 may include a memory I / O module 160 (e.g., PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) to provide or receive signals on connections of channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Example techniques for communicating on channel 190 between memory I / O module 160 and memory controller 130 are in Figures 6A - 6Bshown in the examples of FIGS. 7A-7B. The memory 150 may further include a memory array 175, which may include a plurality of memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) that store values. The host 110 may read data stored in the memory array 175 and write data into the memory array 175 via the channel 190 and the memory I / O module 160. The memory array 175 may be divided into a plurality of banks, where each bank is organized as a plurality of pages accessed by columns.

[0040] Application or user data may be processed by the processor 120 and the memory controller 130, which are instructed to store and / or retrieve such data from the memory 150. For example, data may be generated during the execution of an application (such as a spreadsheet program that calculates values based on other data). As another example, data may be generated during the execution of an application by receiving user input, such as in a spreadsheet program. As another example, data may be generated during the execution of a game application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0041] The host 110 is coupled to the memory 150 via the channel 190, which is shown for data bytes DQ[0:7]. The channel 190 and the signaling between the host 110 and the memory 150 may be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As shown, the channel 190 includes signal connections for DQ, read data strobe (RDQS), data mask (DM), data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). The host 110 may use the read data strobe RDQS to strobe (e.g., provide a clock for) the data in a read operation to receive the data on DQ. The memory 150 may use the data mask DM to mask certain portions of the data from being written during a write operation. The memory 150 may use the data clock WCK to sample the data on DQ for a write operation. The memory 150 may use the command and address clock CK to clock (e.g., receive) the CA. The signal connections for each signaling may include pins at the host 110, pins at the memory 150, and one or more conductive traces that electrically connect these pins. The one or more conductive traces may be part of a single integrated circuit (IC) on a silicon chip that includes the processor 120 and the memory 150, may be part of a package on package (PoP) that includes the processor 120 and the memory 150, or may be part of a printed circuit board (PCB) that is coupled to both the processor 120 and the memory 150.

[0042] Memory 150 may include a memory I / O module 160 (e.g., PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Before long-term storage in memory array 175, the information transmitted across channel 190 may be stored in registers (as temporary or short-term storage locations) in memory I / O module 160 of memory 150.

[0043] Memory 150 may further include a memory array 175, which may include a plurality of memory cells (e.g., DRAM memory cells) that store information. Host 110 may read data stored in memory array 175 and write data into memory array 175 via channel 190.

[0044] Memory controller 130 may operate at a memory controller clock frequency based on a clock signal generated from an external clock signal supplied to or within memory controller 130. The memory controller clock frequency is typically the same as the memory clock of memory 150. Operating memory controller 130 and memory 150 at the same clock frequency maintains high efficiency, latency, and bandwidth. As the memory device frequency increases, the design and manufacture of a memory controller operating at an increased clock frequency may be challenging. Reducing the memory controller clock frequency from the memory clock frequency may reduce the challenge, but the reduced operating rate of the memory controller may reduce the bandwidth utilization of the memory (e.g., the maximum bandwidth that can be provided by the memory), thus reducing the performance of the device.

[0045] According to aspects of the present disclosure, memory controller 130 may include a plurality of cores, each core including logic circuitry for scheduling operations at memory 150 to implement memory requests. In some embodiments, the cores are symmetric such that each core is capable of generating the same set of commands for output to the memory. In some embodiments, the cores are asymmetric such that each core is capable of generating different (overlapping or non-overlapping) sets of commands for output to the memory. Each processing core 132A-N may operate at a memory clock frequency that is lower than the memory clock frequency. Although each core may not fully utilize memory 150 due to the lower operating frequency of each core, multiple cores operating together may increase the utilization of memory 150 and achieve the efficiency and bandwidth achievable by a single core operating at the memory clock frequency. Using multiple cores may improve the balance among high performance, low power, and low cost.

[0046] Multiple cores 132A-N can be configured to schedule commands that can be sent to the memory 150 together. Two examples are shown in Figures 3A - 3B FIG.

[0047] Figure 3A FIG. is an example timing diagram for sending commands from different cores on different clock edges according to some aspects of the present disclosure. The memory controller clock signal is shown as having edges 302A, 302B, 304A, and 304B. When there are two or more cores in the memory controller, the memory controller clock signal can have a longer cycle time than the clock to the memory device (e.g., a lower frequency than the clock to the memory device). In some embodiments, the memory clock controller frequency is a ratio 1 / N of the memory clock, where N corresponds to the number of cores in the memory controller. As further described with respect to Figure 3A FIG., in a dual-core embodiment, one memory controller core sends commands at half the memory clock frequency on the positive edge, and the other memory controller core sends commands at half the memory clock frequency on the negative edge. The memory clock (which is twice (or some other ratio) the frequency of the memory controller clock) receives commands on each of the memory clock cycles. For example, the memory device receives command 312A on the first clock of the memory, and then receives command 312B on the second clock of the memory, and then receives command 314A and then receives command 314B. The result is that the memory device receives commands faster than either memory controller core sends commands. In an embodiment with two memory controller cores operating at half the memory clock frequency, the memory device can receive commands for each clock of the memory.

[0048] Edges 302A and 304A are rising clock edges where the clock transitions from low to high. Edges 302B and 304B are falling clock edges where the clock transitions from high to low. One clock cycle begins with the rising clock edge at edge 302A and continues until the rising clock edge at edge 304A.

[0049] Commands 312A, 312B, 314A, and 314B can be sent from the memory controller 130 to the memory 150 via the memory PHY interface 134. The first core can schedule commands 312A and 314A, and the second core can schedule commands 312B and 314B. Although the two cores may not be able to generate commands separately for each memory clock cycle, the commands from the cores can be interleaved to increase memory utilization. For example, the first core can signal commands on the rising clock edges of edges 302A and 304A, and the second core can signal commands on the falling clock edges of edges 302B and 304B. In some embodiments, two or more cores can be assigned specific clock edges for scheduling commands, and these assignments can be static or dynamic. For example, in some embodiments, the two cores are respectively assigned to the rising edge and the falling edge. In other embodiments, each core can be dynamically assigned a specific edge by a high-level scheduler. For example, the cores can be configured to generate different (overlapping or non-overlapping) commands, and the cores are dynamically assigned to certain clock edges by the high-level scheduler based on the upcoming operation schedule in the command queue.

[0050] Example signals can include column addresses for commands 312A and 314A and activation signals for commands 312B and 314B. The core can schedule commands 312A-B and 314A-B and signal the memory controller PHY interface 134 to generate signals on channel 190 to transfer the commands to the memory 150. Although Figure 3A The example illustrates two cores that schedule commands for opposite clock edges, but other configurations can be used. For example, four cores can schedule commands, with each core scheduling for every second rising or falling edge. In this configuration, each of the four cores can operate at a clock frequency that is one quarter of the memory clock frequency. Other multiples of cores and clock edges can be used, such as eight cores that divide the memory clock cycle. Additionally, the configuration can not require each core to operate only at certain clock edges, but can allow the cores to operate at different clock edges within the memory clock cycle.

[0051] Figure 3A Commands can be queued by the core at certain clock edges to facilitate command timing and ordering. In some aspects of the present disclosure, commands can have associated timestamps to indicate the timing and / or ordering of the commands.

[0052] Figure 3Bis an example timing diagram for sending commands with timestamps from different cores on different clock edges according to some aspects of the present disclosure. Each of commands 322A, 322B, 324A, and 324B can have an associated timestamp. The timestamp can be any counter used to indicate the expected sequence of commands 322A - B and 324A - B. Alternatively, the timestamp can be an identification value that matches the memory clock cycle to which the command should be attached. Yet another example of a timestamp is an offset value used to indicate the relative position of the command with respect to a certain memory clock cycle. When the timestamp is sent with the command, the command can be sent to the memory PHY interface 134 on the same clock edge or different clock edges. Figure 3B The example of Figure 3B shows command 322A provided at clock edge 302A along with command 322B. The memory PHY interface 134 can use the accompanying timestamp to first send command 322A on channel 190 and then send command 322B on the next clock edge on channel 190.

[0053] In some aspects, the logic circuits or cores of the memory controller can be configured similarly in a symmetric manner such that each core is capable of scheduling the same commands. In other aspects, the logic circuits or cores of the memory controller can be configured asymmetrically such that each core has different capabilities or responsibilities, but the capabilities or responsibilities may overlap between the cores. The asymmetric configuration can have less flexibility but uses less circuitry, resulting in a smaller die area and a lower - cost controller.

[0054] Figure 4 An example implementation of a memory controller for accommodating asymmetric cores is shown in Figure 4 . Figure 4 is a block diagram illustrating a memory controller with asymmetric cores according to one aspect of the present disclosure. The memory controller 130 includes logic circuitry 132, and the logic circuitry 132 includes a command queue 140. The command queue 140 can receive and temporarily store memory requests received on the bus system 115 from system components. A scheduler 170 processes the requests in the command queue 140 and controls the memory PHY interface 134 to control signaling to the memory 150. The scheduler 170 can include two logic circuits (e.g., cores) 152 and 154. Core 152 can include a column scheduler 152A that processes the prioritization and scheduling of column commands present in the command queue 140. Core 154 can include a pre - charge and activation scheduler.

[0055] The memory PHY interface 134 of the memory controller 130 may include a plurality of buffers 162 and 164. In some embodiments, the number of buffers may correspond to the number of cores in the scheduler 170, although different configurations may be used. The PHY interface 134 may select outputs from the cores 152 and 154 for output to the memory 150 via the switch 166. In some aspects, decision logic 168 may be used to perform timestamp matching between the outputs of the buffers 162 and 164 to order commands in a desired sequence. The cores 152 and 154 may be synchronized via communication between the cores such that consistency is obtained between the two cores 152 and 154. For example, when the first core 152 sends a command, the second core 154 knows the command sent by the first core 152 and then sends a command accordingly such that the expectations of the memory device are met. In some embodiments, a standard document for the memory or other specification document may specify the required command sequence that the cores 152 and 154 must jointly follow to obtain a valid output from the memory. In some aspects, the PHY interface 134 may alternate between the buffers 162 and 164 for sending command signals. In some aspects, the PHY interface 134 may use the timestamps of the commands in the buffers 162 and 164 to order signals to the memory 150.

[0056] Figure 5 Shown therein is a method of operating a memory from a memory controller according to some aspects described. Figure 5 is a flowchart of an example method of operation for a memory controller having multiple cores according to some aspects of the present disclosure.

[0057] Method 500 includes, at block 502, scheduling a first memory operation by scheduling, in a first core of a memory controller, a first memory operation for a first portion of a clock cycle of a memory clock. The first core may execute based on a clock signal having a clock frequency lower than the memory clock frequency at which the memory or the memory PHY interface operates. Although the lower clock frequency may cause the first core to be unable to determine a memory operation for a memory that utilizes all available memory bandwidth at the memory clock frequency, multiple cores operating at the lower clock frequency may improve the utilization of memory bandwidth. In some embodiments, multiple cores may be configured to fully utilize the memory bandwidth. In some aspects, the first core may determine a memory operation for a particular portion of the clock cycle of the memory. For example, the first core may always schedule a memory operation for the rising edge of the memory clock. As another example, the first core may schedule an operation regardless of the portion of the clock cycle in which the memory operation may be executed as determined by the memory PHY interface.

[0058] At block 504, method 500 includes scheduling a second memory operation by scheduling a second portion of a clock cycle for a memory clock in a second core of a memory controller. The second core may execute based on a clock signal having a lower clock frequency than the memory clock frequency at which the memory or the memory PHY interface operates. The second core may have the same or a different clock frequency than the first core. In some aspects, the second core may schedule memory operations for a particular portion of a clock cycle of the memory. For example, the second core may always schedule memory operations for the falling edge of the memory clock. As another example, the first core may schedule operations regardless of the portion of the clock cycle in which the memory operations may be executed as determined by the memory PHY interface.

[0059] In one example operation, retrieving a memory request from a command queue may cause the first core to determine a column command and the second core to determine an activate command. In another example operation, retrieving a memory request from a command queue may cause the first core to determine a column address and the second core to determine another column address.

[0060] At block 506, method 500 includes: sending a first signal corresponding to a first operation to the memory during a first portion of a clock cycle, and sending a second signal corresponding to a second operation during a second portion of the clock cycle. The sending may be performed by a memory PHY interface that receives outputs from the first and second cores. The sending may include: receiving a first memory operation in a first buffer (e.g., a first-in first-out (FIFO) buffer), and receiving a second memory operation in a second buffer (e.g., a second first-in first-out (FIFO) buffer).

[0061] In some aspects, as part of the scheduling of memory operations determined by the first core at block 502 and the second core at block 504, a timestamp is determined. For example, a first memory operation may have an associated first timestamp, and a second memory operation may have an associated second timestamp. The memory PHY interface may use the timestamps to determine which memory operation to transmit next on the channel.

[0062] Although two cores are described in many examples, the memory controller may be configured with additional cores, such as three cores, four cores, five cores, six cores, or more cores. The additional cores may be clocked at similar or different clock frequencies from each other. In some embodiments, N cores are each clocked at a frequency of (1 / N)*(memory clock) such that the combined memory operations from each of the N cores may fully utilize the memory bandwidth.

[0063] Example read and write operations that can be performed by the determination of commands by a first core and a second core are shown in Figures 6A - 6B the read operation of Figures 7A - 7B and the write operation of

[0064] Figure 6A and Figure 6B show waveforms for transferring data through an example channel in a write operation. The command and address clock (CK) can be differential signals with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), a CAS command can be provided by the host 110 for a write operation to the memory 150. At T1, the host 110 can provide a write command to the memory 150.

[0065] After a write latency (WL) period of time, the host 110 can switch the data clock WCK0_t and WCK0_c to provide a clock to the memory 150 for receiving data for writing on the DQ signal connections. At Tc0 - Tc2, the memory 150 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, and the data is clocked by the data clock WCK0_t and WCK0_c. The memory 150 can serially receive (e.g., based on the data clock WCK0_t and WCK0_c) 16 - bit data mask DM0 to mask certain portions of the received data to avoid write operations. In some examples, 16 bytes of data and 16 - bit data mask DM0 can be received by the memory 150, where each bit of the data mask DM0 masks the corresponding byte of the received data. At Tc0 - Tc2, the RDQS_t signal connection can be in a Hi - Z state. In a read operation, the RDQS_t signal connection can be configured to provide the read data strobe (RDQS) from the memory 150 to the host 110.

[0066] Figure 7A and Figure 7BDescribe waveforms for transmitting data through an example channel in a read operation. The command and address clock (CK) can be a differential signal having CK_t and CK_c signal connections. The data clock WCK can be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), a CAS command can be provided by the host 110 for a read operation on the memory 150. At T1, a read command can be provided by the host 110 to the memory 150.

[0067] After a read latency (RL) period of time, the memory 150 can switch the read data strobe RDQS to provide a clock to the host 110 to receive data for the read operation on the DQ signal connection. At Tc0 - Tc2, the host 110 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, and the data is clocked by the read data strobes RDQS_t and RDQS_c. Thus, in this example, the host 110 receives 16 bytes of data.

[0068] At Tc0 - Tc2, the data mask DM0 signal connection can be in a Hi-Z state. In a write operation, the DM signal connection can be configured to provide a data mask from the host 110 to the memory 150, which is clocked by WCK0_t and WCK0_c.

[0069] A wireless communication device can include a memory configured to transfer data to the memory as described at least Figure 1 and 2 as illustrated, and in accordance with any of the aspects disclosed herein, it can be provided in or integrated into any processor-based device. Examples include but are not limited to set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radio units, satellite radio units, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0070] In one or more aspects, techniques for memory storage and retrieval may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations may include means configured for: scheduling, by a first core of a plurality of cores, a first memory operation for a first portion of a clock cycle of a memory clock; scheduling, by a second core of the plurality of cores, a second memory operation for a second portion of the clock cycle of the memory clock; and transmitting, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation via a memory physical (PHY) interface.

[0071] Additionally, the means may perform or operate according to one or more aspects described below. In some implementations, the means includes a wireless device, such as a UE. In some embodiments, the means includes a remote server, such as a cloud-based computing solution, which receives image data for processing to determine an output image frame. In some implementations, the means may include at least one processor and a memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the means. In some other implementations, the means may include a non-transitory computer-readable medium having program code recorded thereon, and the program code may be executable by a computer to cause the computer to perform the operations described herein with reference to the means. In some implementations, the means may include one or more units configured to perform the operations described herein. In some implementations, a method of wireless communication may include one or more operations described herein with reference to the means.

[0072] In a second aspect, in combination with the first aspect, the means is further configured to schedule the first memory operation as a column address; and schedule the second memory operation as an activation command.

[0073] In a third aspect, in combination with one or more of the first aspect or the second aspect, the first portion of the clock cycle of the memory clock includes a portion starting at the rising clock edge of the memory clock; and the second portion of the clock cycle of the memory clock includes a portion starting at the falling clock edge of the memory clock.

[0074] In a fourth aspect, in combination with one or more of the first aspect to the third aspect, scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation, determining the second memory operation includes scheduling a second timestamp corresponding to the second memory operation, and transmitting the first signal and the second signal is based on the first timestamp and the second timestamp.

[0075] In a fifth aspect, in combination with one or more of the first to fourth aspects, the first timestamp corresponds to the rising clock edge of the memory clock, and the second timestamp corresponds to the falling clock edge of the memory clock.

[0076] In a sixth aspect, in combination with one or more of the first to fifth aspects, a memory physical (PHY) interface includes a first buffer configured to store a first memory operation from a first core and a second buffer configured to store a second memory operation from a second core.

[0077] In a seventh aspect, in combination with one or more of the first to sixth aspects, the first core includes a first logic circuit configured to schedule at least a first type of memory operation, wherein the first logic circuit is coupled to the first buffer; and the second core includes a second logic circuit configured to schedule at least a second type of memory operation, wherein at least one of the at least second type is different from the first type, and wherein the second logic circuit is coupled to the second buffer.

[0078] In an eighth aspect, in combination with one or more of the first to seventh aspects, the first logic circuit is configured to schedule at least column address operations; and the second logic circuit is configured to schedule at least precharge operations or activation operations.

[0079] In a ninth aspect, in combination with one or more of the first to eighth aspects, the memory controller is configured to output back-to-back column addresses on the rising and falling clock edges of the memory clock.

[0080] In a tenth aspect, in combination with one or more of the first to ninth aspects, the memory physical (PHY) interface is configured to operate at the memory clock frequency.

[0081] In an eleventh aspect, in combination with one or more of the first to tenth aspects, a device may include: a host device that includes a memory controller according to one or more of these aspects, wherein the device includes a memory, and the host device is configured to communicate with the memory via a channel.

[0082] In a twelfth aspect, in combination with the eleventh aspect, the host device may include a processor coupled to the memory controller.

[0083] In a thirteenth aspect, in combination with one or more of the eleventh to twelfth aspects, the host device further includes a graphics processor coupled to the memory controller; and a neural processor coupled to the memory controller, wherein the memory controller includes a command queue configured to receive memory requests from the processor, the graphics processor, and the neural processor.

[0084] In a fourteenth aspect, in combination with one or more of the first to thirteenth aspects, a graphics processor, a neural processor, a processor, and a memory are integrated in a single semiconductor package.

[0085] In the description of the embodiments herein, numerous specific details (such as examples of specific components, circuits, and processes) are set forth in order to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" means directly connected or connected through one or more intermediate components or circuits. Additionally, in the following description and for purposes of explanation, specific terms are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will understand that implementing the teachings disclosed herein may not require these specific details. In other instances, well-known circuits and devices are shown in block diagram form in order to avoid obscuring the teachings of the present disclosure.

[0086] Certain portions of the detailed description that follows are presented in terms of processes, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, the processes, logic blocks, processing, etc. are conceived of as a self-consistent sequence of steps or instructions leading to a desired result. These steps are those requiring physical manipulation of physical quantities. Although not necessarily, typically, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

[0087] In the figures, a single block may be described as performing one or more functions. The one or more functions performed by the block may be performed in a single component or across multiple components, and / or may be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described hereinafter generally in terms of their functionality. Whether the functionality is implemented as hardware or software depends upon the particular application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present disclosure. Moreover, an example device may include components other than those shown, including well-known components such as processors, memories, and the like.

[0088] Unless otherwise specified, it will be apparent from the following discussion that, throughout this application, discussions using terms such as "access", "receive", "send", "use", "select", "determine", "normalize", "multiply", "average", "monitor", "compare", "apply", "update", "measure", "derive", "set", "generate", "schedule", etc. refer to the actions and processes of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system.

[0089] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more parts that can implement at least some parts of the present disclosure. Although the description and examples herein use the term "device" to describe various aspects of the present disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or a part of a device for performing the described operations.

[0090] Certain components in a device or apparatus described as a "unit for access", "unit for receive", "unit for send", "unit for use", "unit for select", "unit for determine", "unit for normalize", "unit for multiply", or other similarly named terms referring to one or more operations on data (such as image data) can refer to a processing circuit (e.g., an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a central processing unit (CPU)) configured to perform the functions by a combination of hardware, software, or hardware configured by software.

[0091] Those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0092] As regards in this article Figures 1 - 2The described components, functional blocks, and modules can include processors, electronic devices, hardware devices, electronic components, logic circuits, memories, software code, firmware code, and other examples or any combination thereof. Software, whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, should be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, and / or functions, etc. Additionally, the features discussed herein can be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0093] Those skilled in the art refer to Figure 1 , Figure 2 or Figure 4 One or more blocks (or operations) described can be combined with one or more blocks (or operations) described in another figure of the accompanying drawings. For example, Figures 3A - 3B One or more blocks (or operations) of Figure 1 or Figure 2 can be combined with one or more blocks (or operations) of Figure 5 , 6A -6B or 7A-7B can be combined with one or more blocks associated with Figure 1 , 2 or 4 (or operations).

[0094] Those of ordinary skill in the art should also understand that the various illustrative logical blocks, modules, circuits, and algorithmic steps described in connection with the present disclosure can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps have been generally described herein in terms of their functionality. Implementing this functionality as hardware or software depends on the particular application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present disclosure. Those skilled in the art will also readily recognize that the order or combination of the components, methods, or interactions described herein is merely exemplary, and the components, methods, or interactions of the various aspects of the present disclosure can be combined or performed in ways different from those shown and described herein.

[0095] The various illustrative logical, logical blocks, modules, circuits, and algorithmic processes described in connection with the implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Implementing such functionality as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0096] The hardware and data processing apparatus for implementing the various illustrative logical, logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed using a general purpose single chip or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, the processor may be implemented as a combination of computing devices, such as, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry specific to a given function.

[0097] In one or more aspects, the functionality may be implemented in hardware, digital electronic circuitry, computer software, firmware (including the structures disclosed in this specification and their structural equivalents thereof), or any combination thereof. Implementations of the subject matter described in this specification may also be implemented as one or more computer programs (which are one or more modules of computer program instructions) encoded on a computer storage medium for execution by, or to control the operation of, a data processing apparatus.

[0098] If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. The processes of the methods or algorithms disclosed herein may be implemented in a processor-executable software module, which may reside on a computer-readable medium. A computer-readable medium includes both a computer storage medium and a communication medium, and the communication medium includes any medium that can be enabled to transfer a computer program from one place to another. The storage medium may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection may suitably be termed a computer-readable medium. As used herein, disk and optical disks include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may be a code and instruction combination or collection on a machine-readable medium and a computer-readable medium, and these codes and instructions may be incorporated into a computer program product.

[0099] Various modifications to the implementations described in this disclosure may be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to some other implementations without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0100] In addition, those of ordinary skill in the art will readily understand that relative terms such as "above" and "below" or "front" and "back" or "top" and "bottom" or "forward" and "backward" are sometimes used to facilitate the description of the drawings and indicate relative positions corresponding to the orientation of the drawings on a correctly oriented page, and may not reflect the correct orientation of any device implemented.

[0101] As used herein, the term "coupled to" in the various tensors of the verb "couple" can mean that element A is directly connected to element B or other elements can be connected between element A and element B (i.e., element A is indirectly connected to element B) to operate certain intended functions. In the case of electrical components, the term "coupled to" can also be used herein to mean electrically connecting element A and element B (and any combination of electrical connections therebetween) using wires, traces, or other conductive materials. In some examples, the term "coupled to" means transferring electrical energy between element A and element B to operate certain intended functions.

[0102] In some examples, the term "electrically connected" means having a current or being configurable to have a current flowing between element A and element B. For example, in addition to wires, traces, or other conductive materials and components, element A and element B can be connected via a resistor, transistor, or inductor. Additionally, for radio frequency functions, element A and element B can be "electrically connected" via a capacitor.

[0103] The terms "first", "second", "third", etc. are employed for ease of reference and may not carry a substantive meaning. Similarly, the names of components / modules may be adopted for ease of reference and may not limit the components / modules.

[0104] Certain features described in the context of separate implementations in this specification can also be implemented combinatorially in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately or in any suitable sub-combination in multiple implementations. Additionally, although the features may be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination can be removed from the combination, and the claimed combination can relate to a sub-combination or a variation of a sub-combination.

[0105] Similarly, although the operations are depicted in the drawings in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown in the drawings or in sequential order, or that all illustrated operations be performed to achieve the desired results. Further, the drawings may schematically depict one or more example processes in the form of a flowchart. However, other operations not depicted may be incorporated into the example processes schematically shown. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the operations shown. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of the various system components in the implementations described above should not be construed as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Further, some other implementations are within the scope of the appended claims. In some cases, the acts recited in the claims can be performed in a different order and still achieve the desired results.

[0106] As used herein (including in the claims), the term "or" when used in a list of two or more items means that any one of the listed items can be employed individually or that any combination of two or more of the listed items can be employed. For example, if a composition is described as including components A, B, or C, the composition can include: only A; only B; only C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Additionally, as used herein (including in the claims), "or" as used in a list of items that ends with "at least one of" indicates a disjunctive list such that, for example, a list of "at least one of A, B, or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination thereof.

[0107] As will be understood by those of ordinary skill in the art, the term "substantially" is defined as largely but not necessarily completely the designated object (and includes the designated object; e.g., substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any of the disclosed implementations, the term "substantially" can be replaced with "[percentage] within" the specified content, where the percentage includes 0.1%, 1%, 5%, or 10%.

[0108] The foregoing description of the disclosure is provided to enable those skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: A memory controller that operates at a memory controller clock frequency based on a first clock, wherein the memory controller: Includes a memory physical (PHY) interface that operates at a memory clock frequency based on a memory clock and a plurality of cores, each of the plurality of cores operating at a memory controller clock frequency less than the memory clock frequency, Is coupled to a memory through a channel by the memory physical (PHY) interface, Is configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and Is configured to perform operations including: Scheduling, by a first core of the plurality of cores, a first memory operation for a first portion of a clock cycle of the memory clock; Scheduling, by a second core of the plurality of cores, a second memory operation for a second portion of the clock cycle of the memory clock; and During the clock cycle of the memory clock, sending a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation through the memory physical (PHY) interface.

2. The apparatus according to claim 1, wherein: Scheduling the first memory operation includes scheduling a column address; and Scheduling the second memory operation includes scheduling an activation command.

3. The apparatus according to claim 2, wherein: The first portion of the clock cycle of the memory clock includes a portion that starts at the rising clock edge of the memory clock; And The second portion of the clock cycle of the memory clock includes a portion that starts at the falling clock edge of the memory clock.

4. The apparatus according to claim 3, wherein: Scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation, Scheduling the second memory operation includes determining a second timestamp corresponding to the second memory operation, and Sending the first signal and the second signal is based on the first timestamp and the second timestamp.

5. The device according to claim 4, wherein, The first timestamp corresponds to the rising clock edge of the memory clock, and the second timestamp corresponds to the falling clock edge of the memory clock.

6. The apparatus according to claim 1, wherein: The memory physical (PHY) interface includes: a first buffer configured to store the first memory operation from the first core, and a second buffer configured to store the second memory operation from the second core.

7. The apparatus according to claim 6, wherein: The first core includes a first logic circuit configured to schedule at least a first type of memory operation, wherein the first logic circuit is coupled to the first buffer; and The second core includes a second logic circuit configured to schedule at least a second type of memory operation, wherein at least one of the at least second type is different from the first type, wherein the second logic circuit is coupled to the second buffer.

8. The apparatus according to claim 7, wherein: The first logic circuit is configured to schedule at least column address operations; and The second logic circuit is configured to schedule at least precharge operations or activation operations.

9. The apparatus according to claim 8, wherein, The memory controller is configured to output back-to-back column addresses on the rising and falling clock edges of the memory clock.

10. The apparatus according to claim 1, wherein The memory physical (PHY) interface is configured to operate at the memory clock frequency.

11. The device according to claim 1, wherein, The memory controller is configured to communicate with a memory including a low power double data rate (LPDDR6) memory module.

12. A method, comprising:[[]]END]] Scheduling, in a first core of a memory controller, a first memory operation for a first portion of a clock cycle of a memory clock; Scheduling, in a second core of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock; And Sending, during the first portion of the clock cycle, a first signal corresponding to the first memory operation to the memory and sending, during the second portion of the clock cycle, a second signal corresponding to the second memory operation to the memory, wherein the memory clock has a memory clock frequency higher than a memory controller frequency of the memory controller.

13. The method according to claim 12, wherein: Scheduling the first memory operation includes scheduling a column address; and Scheduling the second memory operation includes scheduling an activation command.

14. The method according to claim 13, wherein: The first portion of the clock cycle of the memory clock includes a portion starting at the rising clock edge of the memory clock; And The second portion of the clock cycle of the memory clock includes a portion starting at the falling clock edge of the memory clock.

15. The method according to claim 14, wherein: Scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation, Scheduling the second memory operation includes determining a second timestamp corresponding to the second memory operation, and Sending the first signal and the second signal is based on the first timestamp and the second timestamp.

16. The method according to claim 15, wherein, The first timestamp corresponds to the rising clock edge of the memory clock, and the second timestamp corresponds to the falling clock edge of the memory clock.

17. The method according to claim 12, further comprising: Storing the first memory operation from the first core in a first buffer of a memory physical (PHY) interface of the memory controller; And Storing the second memory operation from the second core in a second buffer of the memory physical (PHY) interface of the memory controller, Wherein sending the first signal and the second signal includes receiving the first memory operation from the first buffer and receiving the second memory operation from the second buffer.

18. The method according to claim 17, wherein: Scheduling the first memory operation for the first portion includes: scheduling a first type of memory operation in the first core, and Scheduling the second memory operation for the second portion includes: scheduling a second type of memory operation in the second core that is different from the first type of memory operation.

19. The method according to claim 18, wherein: Scheduling the first memory operation for the first portion includes scheduling a column address operation, and Scheduling the second memory operation for the second portion includes scheduling at least one of a precharge operation or an activation operation.

20. The method according to claim 18, wherein: Scheduling the first memory operation for the first portion includes scheduling a first column address operation, Scheduling the second memory operation for the second portion includes scheduling a second column address operation, and Transmitting the first signal and the second signal includes transmitting back-to-back column addresses on the rising clock edge and the falling clock edge of the memory clock.

21. The method according to claim 12, wherein The memory physical (PHY) interface is configured to operate at the memory clock frequency.

22. The method according to claim 12, wherein, The memory controller is configured to communicate with a memory including a low power double data rate (LPDDR6) memory module.

23. An apparatus, comprising: A memory; A host device configured to communicate with the memory via a channel, The host device includes a memory controller coupled to the channel, wherein the memory controller: Includes a memory physical (PHY) interface operating at the memory clock frequency based on a memory clock, and a plurality of cores, each of the plurality of cores operating at a memory controller clock frequency less than the memory clock frequency, Is coupled to the memory via the channel through the memory physical (PHY) interface, Is configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and Is configured to perform operations including: Scheduling, by a first core of the plurality of cores, a first memory operation for a first portion of a clock cycle of the memory clock; Scheduling, by a second core of the plurality of cores, a second memory operation for a second portion of the clock cycle of the memory clock; and During the clock cycle of the memory clock, transmitting, through the memory physical (PHY) interface, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation.

24. The apparatus according to claim 23, wherein: Scheduling the first memory operation includes scheduling a column address; and Scheduling the second memory operation includes scheduling an activation command.

25. The apparatus according to claim 24, wherein: The first portion of the clock cycle of the memory clock includes a portion starting at the rising clock edge of the memory clock; And The second portion of the clock cycle of the memory clock includes a portion starting at the falling clock edge of the memory clock.

26. The apparatus according to claim 25, wherein: Scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation, Scheduling the second memory operation includes determining a second timestamp corresponding to the second memory operation, and Transmitting the first signal and the second signal is based on the first timestamp and the second timestamp.

27. The apparatus according to claim 23, wherein: The memory physical (PHY) interface includes: a first buffer configured to store the first memory operation from the first core, and a second buffer configured to store the second memory operation from the second core.

28. The apparatus according to claim 23, wherein, The host device includes a processor coupled to the memory controller.

29. The apparatus according to claim 28, wherein, The host device further includes: A graphics processor coupled to the memory controller; and A neural processor coupled to the memory controller, wherein the memory controller includes a command queue configured to receive memory requests from the processor, the graphics processor, and the neural processor.

30. The apparatus according to claim 29, wherein, The graphics processor, the neural processor, the processor, and the memory are integrated in a single semiconductor package.

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