Method for forming metal gasket for inline machine

Abstract

A method of forming a metal liner layer for an inline machine uses a multi-metal deposition process to produce a reduced thickness liner. The back-end-of-line packaging process may include forming a metal liner layer by depositing a ruthenium layer having a first thickness of about 5 angstroms or less and depositing a first cobalt layer having a second thickness of about 20 angstroms or less. In some embodiments, a ruthenium layer may be deposited on a previously formed barrier layer and then subjected to a treatment process prior to depositing the first cobalt layer. In some embodiments, the first cobalt layer may be deposited on the ruthenium layer or the ruthenium layer may be deposited on the first cobalt layer. In some embodiments, a ruthenium layer is deposited on a first cobalt layer and a second cobalt layer is deposited on the ruthenium layer.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to semiconductor processing of semiconductor substrates. Background Art

[0002] To increase the density of components on a chip, critical dimensions (CDs) are scaled to continuously reduce size. The smaller size directly affects the performance of the interconnects that provide electrical paths for semiconductor structures. During back-end-of-line (BEOL) packaging processes, the smaller size typically results in an increase in the resistivity of the interconnects. Since the liner thickness cannot be reduced without affecting liner performance, the inventors have observed that in some cases the resistivity can be attributed to a reduced copper gap-fill volume due to CD reduction.

[0003] Accordingly, the inventors have provided methods of forming metal liners that improve copper gap-fill volume, allow for increased density of interconnects, and simultaneously improve interconnect resistivity. Summary of the Invention

[0004] Methods of forming enhanced metal liner layers are provided herein.

[0005] In some embodiments, a method of forming a metal liner layer for an interconnect may include depositing a metal liner layer on at least a portion of an underlying copper interconnect layer during a BEOL packaging process, the deposition of the metal liner layer including depositing a first ruthenium layer having a first thickness of about 5 angstroms or less and depositing a first cobalt layer having a second thickness of about 20 angstroms or less.

[0006] In some embodiments, the method of forming a metal liner layer may further include depositing a first ruthenium layer on a previously formed barrier layer, performing a processing step, and after the processing step, depositing a first cobalt layer on the first ruthenium layer; depositing a copper gap-fill material in an opening in which the metal liner layer has been deposited, and annealing the copper gap-fill material to reflow the copper gap-fill material into the opening; forming an interface layer between the first ruthenium layer and the first cobalt layer to increase the thermal stability of the metal liner layer; depositing a first ruthenium layer on the first cobalt layer; depositing a first cobalt layer on the first ruthenium layer; depositing a first cobalt layer, depositing a first ruthenium layer on the first cobalt layer, and depositing a second cobalt layer on the first ruthenium layer; wherein the second thickness is about 10 angstroms or less, the first thickness is about 5 angstroms, and a third thickness of the second cobalt layer is about 10 angstroms or less; wherein the second thickness is about 12 angstroms or less; and / or depositing a first ruthenium layer, wherein the first thickness is about 2.5 angstroms or less, depositing a first cobalt layer on the first ruthenium layer, and depositing a second ruthenium layer on the first cobalt layer, wherein a third thickness of the second ruthenium layer is about 2.5 angstroms or less.

[0007] In some embodiments, a method of forming a metal liner layer for an inner interconnect may include depositing a metal liner layer on at least a portion of a conductive material in an underlying inner interconnect layer during a back-end-of-line packaging process. Depositing the metal liner layer includes depositing a first metal layer of a first metal material that, when having a first thickness less than 30 angstroms, has a property of impeding migration of the conductive material on the first metal layer to reduce a reflux rate, and depositing a second metal layer of a second metal material different from the first metal material that has a property of enhancing migration of the conductive material on the metal liner layer to increase the reflux rate of the conductive material, wherein the second metal layer has a second thickness that is about 5% to about 30% of the first thickness.

[0008] In some embodiments, a non-transitory computer-readable medium has instructions stored thereon that, when executed, cause a method of forming a metal liner layer for an inner interconnect to be performed. The method may include depositing a metal liner layer on at least a portion of an underlying copper inner interconnect layer during a back-end-of-line packaging process. Depositing the metal liner layer includes depositing a first ruthenium layer having a first thickness of about 5 angstroms or less, and depositing a first cobalt layer having a second thickness of about 20 angstroms or less.

[0009] Other and further embodiments will be disclosed later. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention briefly summarized above and discussed in detail below may be understood by reference to the illustrative embodiments of the present invention depicted in the drawings. However, the drawings only illustrate typical embodiments of the present invention and are therefore not to be considered limiting of the scope, as the present invention may admit to other equivalent embodiments.

[0011] Figure 1 A cross-sectional view of a plurality of inner interconnect layers on a substrate according to some embodiments of the present invention is depicted.

[0012] Figure 2 A cross-sectional view of a metal liner layer formed in an opening of a substrate according to some embodiments of the present invention is depicted.

[0013] Figure 3 A cross-sectional view of an underlying metal inner interconnect layer migrating into an opening according to some embodiments of the present invention is depicted.

[0014] Figure 4 A cross-sectional view of a metal liner layer formed of a plurality of metal materials according to some embodiments of the present invention is depicted.

[0015] Figure 5 A cross-sectional view of a metal liner layer according to some embodiments of the present invention is depicted.

[0016] Figure 6 A cross-sectional view depicting portions of a metal liner layer deposited before and after a processing step in accordance with some embodiments of the present invention.

[0017] Figure 7 A method of forming an interconnect layer on a conductive material in a BEOL packaging process in accordance with some embodiments of the present invention.

[0018] Figure 8 A method of forming a metal liner layer on a conductive material in accordance with some embodiments of the present invention.

[0019] Figure 9 A method of forming a metal liner layer on a conductive material in accordance with some embodiments of the present invention.

[0020] Figure 10 A cluster tool in accordance with some embodiments of the present invention is depicted.

[0021] For purposes of facilitating understanding, like reference numerals have been used, wherever possible, to refer to like elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0022] The present method provides an enhanced metal liner with reduced thickness, which allows for increased gap fill volume and reduced interconnect resistivity as the critical dimension (CD) decreases. The method deposits a doped (a metal layer combined with thin metal layers of different materials) metal liner layer for interconnect scaling through a chemical vapor deposition (CVD) process. In some embodiments, the use of the doped metal liner allows for scaling down the liner to only cobalt (Co) for the interconnect level while maintaining copper (Cu) backfill properties and preventing underlying Cu voiding caused by the use of a thick ruthenium (Ru) liner. The reduction in liner thickness allows for increased Cu gap fill with the attendant benefit of reduced liner resistivity.

[0023] Previously, cobalt liners have been used to provide a Cu reflow interface for Cu gap filling. Although Ru liners provide better Cu reflow properties compared to Co liners, the use of Ru liners is limited due to underlying Cu voids caused by Cu diffusion on the Ru liners. As the interconnect shrinks, the traditional Co liner thickness inhibits via contact resistance (Rc) and liner resistance (R) improvement, and thus liner thickness reduction is required for future technology nodes. The method disclosed herein uses a Ru / Co liner, which provides sufficient Cu reflow properties in small structures and prevents underlying Cu voids. The Ru-doped Co liner according to the present invention adds a small amount of Ru (e.g., a thickness of about 5 Å or less) to a Co layer (e.g., a thickness of about 20 Å or less), allowing the liner to be scaled down (e.g., a Ru-doped Co with a total metal liner layer thickness of about 25 Å or less) compared to 30 Å to 35 Å for traditional cobalt liners. The doped Ru provides better adhesion of Co to a barrier layer such as tantalum nitride (TaN) and aids in Cu reflow, while a small amount of Ru does not cause Cu voids.

[0024] The method of the present invention forms a metal liner layer for a back-end-of-line (BEOL) packaging process, which includes a Ru-doped Co liner, and during the CVD deposition of the liner, a small amount of Ru is incorporated into the Co liner. Ru doping can occur before, during, or after Co deposition depending on the design of the structure. The Ru-doped Co combination gives better metal liner stability compared to only Co liners when subjected to thermal annealing. The Ru-doped Co metal liner also has improved Cu gap filling ability (e.g., a 3 Å Ru layer + 17 Å Co layer vs. a 20 Å only Co layer) compared to only Co liners of the same thickness. Since the thinner Ru-doped Co liner allows more Cu gap filling compared to traditional only Co liners, the Ru-doped Co metal liner also gives a liner R benefit when compared to traditional only Co liners.

[0025] In Figure 1 view 100 of, a substrate 102 produced in, for example, a front-end-of-line (FEOL) process is shown as having a plurality of interconnect layers formed in a BEOL packaging process. The first interconnect layer, M0 104, can be formed using a thick ruthenium-containing liner layer since no underlying copper is present on the substrate 102. However, due to migration issues of underlying copper in previously formed interconnect layers, subsequent interconnect layers, such as MX1 106, MX2 108, and MXN 110 cannot be formed with ruthenium liner layers. As Figure 2As depicted in view 200, cobalt is then used as a liner material to create a cobalt liner layer 216 over the opening 214 of the MX layer 210. The cobalt liner layer 216 conventionally has a thickness 220 of 30 angstroms to 35 angstroms. The thickness 220 of the cobalt liner layer 216 directly affects the width 212 of the opening 214, reducing the gap fill opening width 218. Due to the CD reduction, the thickness 220 of the cobalt liner layer 216 will substantially affect the gap fill volume and significantly increase the on-chip resistance. The inventors studied the use of cobalt liners with a thickness of approximately 20 angstroms and found that a large number of defects would prohibit the use of such liners (a cobalt liner alone is not capable of filling small vias that result in voids). The method of the present invention provides a liner applicable to all on-chip levels.

[0026] As Figure 3 As depicted in view 300, the inventors also found that the use of a thick ruthenium liner layer 330 over the MX layer 210 results in a copper migration 336 problem from the underlying copper on-chip 340. Copper material migrates from the underlying copper on-chip 340 through the thick ruthenium liner layer 330 and into the opening 214, forming copper material 332 in the opening. The migrating copper from the underlying copper on-chip 340 leaves voids 334 in the underlying copper on-chip 340, degrading the performance of the underlying copper on-chip 340. The inventors further experimented with liners using ruthenium and cobalt as the metal liner materials.

[0027] As Figure 4 As depicted in view 400, the inventors found that by using a combination of materials in the metal liner layer 410, a thinner liner layer can be achieved while still preventing the migration of the underlying on-chip metal. In some embodiments, a first metal liner layer 402 (e.g., cobalt, etc.) is formed in the opening 214 with a first thickness 406 of approximately 20 angstroms or less. A second metal liner layer 404 (e.g., a doped layer of Ru, W, Mn, Ta, etc.) of a different material than the first metal liner layer 402 is formed over the first metal liner layer 402 with a second thickness 408 of approximately 5 angstroms or less. In an example, the metal liner layer 410 has a third thickness 412 of approximately 25 angstroms or less, substantially thinner compared to the conventional cobalt liner thickness of 30 to 35 angstroms, while still being able to fill small vias due to the adhesion of the second metal liner material. With the thinner metal liner, the gap fill opening width 218 increases, allowing for a greater volume of gap fill material and a substantially reduced on-chip resistance. In some embodiments, a cobalt layer of approximately 17 angstroms and a ruthenium layer of approximately 3 angstroms result in a metal liner layer with a liner layer thickness of approximately 20 angstroms and a void-free copper gap fill result. In some embodiments, a cobalt layer of approximately 12 angstroms and a ruthenium layer of approximately 3 angstroms result in a metal liner layer with a thickness of approximately 15 angstroms and a void-free copper gap fill result within 10% to 15% of the thicker 20 angstrom liner layer of the present invention.

[0028] In addition, the inventors have found that the dewetting tests of the liner show that the sheet resistance of the 15 Å metal liner layer and the 20 Å metal liner layer of the present invention at 400 °C for the first 30 minutes of annealing time (due to the thermal stability of the use of ruthenium) is substantially the same, with minor variations thereafter. In some embodiments, the second thickness 408 of the second metal liner layer 404 may be from about 5% to about 30% of the first thickness 406 of the first metal liner layer 402. The inventors have found that a balance can be achieved between the ratio of different metal materials of the metal liner layer and the required increase in the gap fill volume in a particular design. For example, if a higher performance (low resistivity, increased gap fill volume) interconnect is desired, the slightly increased void generation due to the use of the thinner metal liner layer of the present invention would be tolerable. During the deposition of different metal materials of the metal liner layer of the present invention, additional adjustment parameters may be used, such as, for example, temperature, precursor gas flow rate, and / or pressure.

[0029] In some embodiments, depicted in Figure 5 View 500A of, the first metal liner layer 402 is first deposited on the underlying conductive interconnect 506. The second metal liner layer 404 is deposited on the first metal liner layer 402. The metal material used for the deposition of the second metal liner layer 404 is different from the metal material used for the first metal liner layer 402. The inventors have found that the deposition of the first metal liner layer 402, such as cobalt, on the underlying conductive interconnect 506 allows the cobalt material of the first metal liner layer 402 to form a better first interface layer 504 with the underlying conductive interconnect 506. The deposition of the second metal liner layer 404, such as ruthenium, on the first metal liner layer 402 forms a second interface layer 502 with the first metal liner layer 402 and aids in the reflow of the gap fill material during subsequent annealing processes. In some embodiments, depicted in Figure 5 View 500B of, the second metal liner layer 404 is first deposited. The first metal liner layer 402 is deposited on the second metal liner layer 404. The metal material used for the deposition of the second metal liner layer 404 is different from the metal material used for the deposition of the first metal liner layer 402. The inventors have found that the deposition of the first metal liner layer 402, such as cobalt, on the second metal liner layer 404 forms a third interface layer 508 with the second metal liner layer 404 and provides improved thermal stability (i.e., less impact on resistance after applying heat) during subsequent annealing processes.

[0030] In some embodiments, shown in Figure 5In view 500C, a first metal liner layer 402A is first deposited. The first metal liner layer 402A may have a thickness of about 10 angstroms or less. A second metal liner layer 404 is deposited on the first metal liner layer 402A. A third metal liner layer 402B is deposited on the second metal liner layer 404. The third metal liner layer 402B is formed of the same metal material as the first metal liner layer 402A. The metal material used for depositing the second metal liner layer 404 is different from the metal materials used for depositing the first metal liner layer 402A and the third metal liner layer 402B. The third metal liner layer 402B may have a thickness of about 10 angstroms or less. During the deposition of these layers, a third interface layer 502A is formed between the first metal liner layer 402A and the second metal liner layer 404. A fourth interface layer 502B is formed between the second metal liner layer 404 and the third metal liner layer 402B. In some embodiments, depicted in Figure 6 In view 600, the second metal liner layer 404 may be deposited on the barrier layer 602 and then subjected to a processing step 604 prior to the deposition of the first metal liner layer 402. The processing step 604 may include plasma processing with argon and the like in a physical vapor deposition (PVD) chamber. In some examples, a metal material such as ruthenium for the second metal liner layer 404 may be used in forming the barrier layer 602, allowing for easy deposition of the first metal liner layer 402 and optimizing the barrier / liner layer processing.

[0031] In some embodiments, depicted in Figure 5 In view 500D, a first second metal liner layer 404A is first deposited. The first metal liner layer 402 is deposited on the first second metal liner layer 404A. The metal material used for depositing the first second metal liner layer 404A is different from the metal material used for depositing the first metal liner layer 402. The inventors have found that the deposition of the first metal liner layer 402 such as cobalt on the first second metal liner layer 404A forms a fourth interface layer 510 with the first second metal liner layer 404A and a fifth interface layer 512 with the second second metal liner layer 404B, and provides improved thermal stability during subsequent annealing processes (i.e., a smaller impact on resistance after applying heat).

[0032] In some embodiments, the BEOL encapsulation process may include a method 700 for forming an interconnect in a low-k material. In block 702, a barrier layer is deposited on a subsequently formed interconnect layer. In block 704, the barrier layer is processed with a processing technique such as argon treatment and similar treatments. In block 706, a metal liner layer of the present invention is deposited on the barrier layer. In some embodiments, the metal liner layer may be deposited using atomic layer deposition (ALD) processing, chemical vapor deposition (CVD) processing, or physical vapor deposition (PVD) processing in a single chamber or using multiple chambers. The metal liner has a first metal material (e.g., cobalt, and the like), which exhibits the property of a reduced reflow rate with a subsequently deposited conductive gap fill material when the thickness of the first metal material is less than 30 angstroms. By doping the cobalt material with a second metal material, such as ruthenium, tantalum, tungsten, manganese, and the like, which enhance the migration of the conductive gap fill on the metal liner, the reduced reflow rate of the first metal material can be increased while the overall thickness of the metal liner is reduced (compared to the conventional liner thickness). In block 708, a conductive gap fill material is deposited on the metal liner layer. In block 710, the conductive gap fill material is annealed to reflow the gap fill material and form a conductive interconnect. In some embodiments, the deposition method of the metal liner layer in block 706 may include some embodiments (706A, 706B, 706C) as depicted in Figure 8 views 800A, 800B, 800C, and 800D. In block 802A, a ruthenium layer is deposited with a thickness of about 5 angstroms or less (see, for example, Figure 5 view 500B). In block 804A, a cobalt layer of about 20 angstroms or less is deposited on the ruthenium layer (see, for example, Figure 5 view 500B). In some embodiments, other metal materials may be used to replace the ruthenium metal material, such as, for example, tungsten, manganese, tantalum, and so on.

[0033] In block 802B, a cobalt layer is deposited with a thickness of about 20 angstroms or less (see, for example, Figure 5 view 500A). In block 804B, a ruthenium layer of about 5 angstroms or less is deposited on the cobalt layer (see, for example, Figure 5 view 500A). In some embodiments, other metal materials may be used to replace the ruthenium metal material, such as, for example, tungsten, manganese, tantalum, and so on. In block 802C, a first cobalt layer is deposited with a thickness of about 10 angstroms or less (see, for example, Figure 5 view 500C). In block 804C, a ruthenium layer of about 5 angstroms or less is deposited on the cobalt layer (see, for example, Figure 5 view 500C). In block 806C, a second cobalt layer is deposited with a thickness of about 10 angstroms or less (see, for example, Figure 5View 500C). In some embodiments, other metal materials can be used to replace the ruthenium metal material, such as, for example, tungsten, manganese, tantalum, and so on. In block 802D, the first ruthenium layer is deposited with a thickness of about 2.5 angstroms or less (see, for example, Figure 5 View 500D). In block 804D, a cobalt layer of about 20 angstroms or less is deposited on the cobalt layer (see, for example, Figure 5 View 500D). In block 806D, the second ruthenium layer is deposited with a thickness of about 2.5 angstroms or less (see, for example, Figure 5 View 500D). In some embodiments, other metal materials can be used to replace the ruthenium metal material, such as, for example, tungsten, manganese, tantalum, and so on.

[0034] In some embodiments, the BEOL encapsulation process can include a method 900 for forming internal interconnects in low-k materials. In block 902, a barrier layer is deposited on the subsequently formed internal interconnect layer. In block 904, a ruthenium layer of about 5 angstroms or less is deposited on the barrier layer. In block 906, the barrier layer is processed by a processing technique such as PVD argon treatment and similar treatments. In block 908, the cobalt layer of the present invention is deposited on the ruthenium layer with a thickness of about 20 angstroms or less. In block 910, a conductive gap filling material is deposited on the metal liner layer. In block 912, the conductive gap filling material is annealed to reflow the gap filling material and form a conductive internal interconnect. The incorporation of ruthenium deposition in the barrier deposition process allows for a more optimized encapsulation process. In some embodiments, other metal materials can be used to replace the ruthenium and cobalt metal materials, such as, for example, tungsten, manganese, tantalum, and so on.

[0035] The methods described herein can be performed in a single processing chamber or executed in a single processing chamber or multiple processing chambers, which can be provided as part of a cluster tool, such as the integration tool 1000 (i.e., the cluster tool) described later with respect to Figure 10 The advantage of using the integration tool 1000 is that there is no vacuum break between chambers and thus no degassing and pre-cleaning are required before processing or deposition in the chambers. For example, in some embodiments, the inventive methods described above can be advantageously performed in an integration tool such that there is limited or no vacuum break between processes, limiting or preventing contamination of the substrate such as oxidation and the like. The integration tool 1000 includes a vacuum-sealed processing platform 1001, a factory interface 1004, and a system controller 1002. The processing platform 1001 includes a plurality of processing chambers, such as 1014A, 1013B, 1014C, 1014D, 1014E, and 1014F, operatively coupled to a vacuum substrate transfer chamber (transfer chambers 1003A, 1003B). The factory interface 1004 is operatively connected through one or more load lock chambers (two load lock chambers, such as Figure 10shown as 1006A and 1006B) and coupled to the transfer chamber 1003A.

[0036] In some embodiments, the factory interface 1004 includes at least one docking station 1007, at least one factory interface robot 1038 to facilitate the transfer of semiconductor substrates. The docking station 1007 is configured to receive one or more front-opening unified pods (FOUPs). Four FOUPs, such as 1005A, 1005B, 1005C, and 1005D are shown in Figure 10 the embodiments. The factory interface robot 1038 is configured to transfer substrates from the factory interface 1004 through load lock chambers (such as 1006A and 1006B) to the processing platform 1001. Each of the load lock chambers 1006A and 1006B has a first port coupled to the factory interface 1004 and a second port coupled to the transfer chamber 1003A. The load lock chambers 1006A and 1006B are coupled to a pressure control system (not shown), which pumps the load lock chambers 1006A and 1006B back and evacuates them to facilitate the passage of substrates between the vacuum environment of the transfer chamber 1003A and the substantially ambient (e.g., atmospheric pressure) environment of the factory interface 1004. The transfer chambers 1003A, 1003B have vacuum robots 1042A, 1042B, disposed in the respective transfer chambers 1003A, 1003B. The vacuum robot 1042A is capable of transferring substrates 1021 between the load lock chambers 1006A, 1006B, the processing chambers 1014A and 1014F, and the cooling station 1040 or the pre-cleaning station 1042. The vacuum robot 1042B is capable of transferring substrates 1021 between the cooling station 1040 or the pre-cleaning station 1042 and the processing chambers 1014B, 1014C, 1014D, and 1014E.

[0037] In some embodiments, the processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F are coupled to the transfer chambers 1003A, 1003B. The processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F may include, for example, a pre-cleaning chamber, an ALD processing chamber, a PVD processing chamber, a remote plasma chamber, a CVD chamber, or the like. The chambers may include any chamber suitable to perform all or part of the methods described herein, as described above, such as a CVD chamber or an ALD chamber and the like. In some embodiments, one or more optional service chambers (shown as 1016A and 1016B) may be coupled to the transfer chamber 1003A. The service chambers 1016A and 1016B may be configured to perform other substrate processing, such as degassing and argon treatment, and the like.

[0038] The system controller 1002 controls the operation of the tool 1000, either by directly controlling the processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F, or by controlling a computer (or controller) associated with the processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F and the tool 1000. In operation, the system controller 1002 is capable of collecting data and feedback from the individual chambers and the system to optimize the performance of the tool 1000. The system controller 1002 generally includes a central processing unit (CPU) 1030, a memory 1034, and support circuitry 1032. The CPU 1030 can be any form of general-purpose computer processor that can be used in an industrial setting. The support circuitry 1032 is conventionally coupled to the CPU 1030 and can include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. Software routines (such as the methods described above) can be stored in the memory 1034, and when implemented by the CPU 1030, transform the CPU 1030 into a special-purpose computer (system controller) 1002. The software routines can also be stored and / or executed by a second controller (not shown) that is remote from the tool 1000.

[0039] Embodiments in accordance with the present invention can be implemented in hardware, firmware, software, or any combination of the foregoing. Embodiments can also be implemented as instructions stored on one or more computer-readable media that can be read and executed by one or more processors. The computer-readable media can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform or a "virtual machine" running on one or more computing platforms). For example, the computer-readable media can include any suitable form of volatile or non-volatile memory. In some embodiments, the computer-readable media can include non-transitory computer-readable media.

[0040] Although the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention can be conceived without departing from the basic scope of the invention.

Claims

1. A method of forming a metal liner layer for an inner interconnect, the method comprising: Depositing the metal liner layer on at least a portion of a underlying copper inner interconnect layer during a back-end-of-line packaging process, depositing the metal liner layer comprising: Depositing a first ruthenium layer having a first thickness of about 5 angstroms or less; And Depositing a first cobalt layer having a second thickness of about 20 angstroms or less.

2. The method of claim 1, the method further comprising: Depositing the first ruthenium layer on a previously formed barrier layer; Performing a processing step; and After the processing step, depositing the first cobalt layer on the first ruthenium layer.

3. The method of claim 1, the method further comprising: Depositing a copper gap filling material in an opening in which the metal liner layer has been deposited; and Annealing the copper gap filling material to reflow the copper gap filling material into the opening.

4. The method of claim 1, the method further comprising: Forming an interface layer between the first ruthenium layer and the first cobalt layer to increase the thermal stability of the metal liner layer.

5. The method of claim 1, the method further comprising: Depositing the first ruthenium layer on the first cobalt layer.

6. The method of claim 1, the method further comprising: Depositing the first cobalt layer on the first ruthenium layer.

7. The method of claim 1, the method further comprising: Depositing the first cobalt layer; Depositing the first ruthenium layer on the first cobalt layer; and Depositing a second cobalt layer on the first ruthenium layer.

8. The method of claim 7, wherein the second thickness is about 10 angstroms or less, the first thickness is about 5 angstroms or less, and a third thickness of the second cobalt layer is about 10 angstroms or less.

9. The method of claim 1, wherein the second thickness is about 12 angstroms or less.

10. The method of claim 1, the method further comprising: Depositing the first ruthenium layer, wherein the first thickness is about 2.5 angstroms or less; Depositing the first cobalt layer on the first ruthenium layer; and Depositing a second ruthenium layer on the first cobalt layer, wherein a third thickness of the second ruthenium layer is about 2.5 angstroms or less.

11. A method of forming a metal liner layer for an inner interconnect, the method comprising: Depositing the metal liner layer on at least a portion of a conductive material in a underlying inner interconnect layer during a back-end-of-line packaging process, depositing the metal liner layer comprising: Depositing a first metal layer of a first metal material, the first metal layer having a property of impeding migration of the conductive material on the first metal layer to reduce a reflow rate when a first thickness of the first metal layer is less than 30 angstroms; And Deposit a second metal layer of a second metal material different from the first metal material, the second metal layer having the property of enhancing the migration of the conductive material on the metal liner layer to increase the reduced reflux rate of the conductive material, wherein the second metal layer has a second thickness that is about 5% to about 30% of the first thickness.

12. The method of claim 11, wherein the first metal material is cobalt, the second metal material is ruthenium, tungsten, manganese, or tantalum, and the conductive material is copper.

13. The method of claim 12, wherein the second thickness is about 5 angstroms or less and the first thickness is about 20 angstroms or less.

14. The method of claim 11, wherein the metal liner layer has a liner thickness of about 25 angstroms or less.

15. The method of claim 11, the method further comprising: Depositing the second metal layer on a previously formed barrier layer; Performing a processing operation; and After the processing operation, depositing the first metal layer on the second metal layer.

16. The method of claim 11, the method further comprising: Depositing a conductive gap filling material in an opening in which the metal liner layer has been deposited; and Annealing the conductive gap filling material to reflux the conductive gap filling material into the opening.

17. The method of claim 11, the method further comprising: Depositing the second metal layer on the first metal layer; or Depositing the first metal layer on the second metal layer.

18. The method of claim 11, the method further comprising: Depositing the first metal layer; Depositing the second metal layer on the first metal layer; and Depositing a third metal layer of the first metal material on the second metal layer.

19. A non-transitory computer-readable medium having instructions stored thereon that, when executed, cause a method of forming a metal liner layer for an inner interconnect to be performed, the method comprising: Depositing the metal liner layer on at least a portion of an underlying copper inner interconnect layer during a back-end-of-line packaging process, depositing the metal liner layer including: Depositing a first ruthenium layer having a first thickness of about 5 angstroms or less; And Depositing a first cobalt layer having a second thickness of about 20 angstroms or less.

20. The non-transitory computer-readable medium of claim 19, the method further comprising one of the following a, b, c, d, or e: (a) Depositing the first ruthenium layer on a previously formed barrier layer; Performing a processing operation; and After the processing operation, depositing the first cobalt layer on the first ruthenium layer; or (b) Deposit the first ruthenium layer on the first cobalt layer; Or (c) Depositing the first cobalt layer on the first ruthenium layer; or (d) Depositing the first cobalt layer, wherein the second thickness is about 10 angstroms or less; Depositing the first ruthenium layer on the first cobalt layer; And Depositing a second cobalt layer on the first ruthenium layer, wherein the third thickness of the second cobalt layer is about 10 angstroms or less; or (e) Deposit the first ruthenium layer, wherein the first thickness is about 2.5 angstroms or less; Deposit the first cobalt layer on the first ruthenium layer; And Deposit a second ruthenium layer, wherein a third thickness of the second ruthenium layer is about 2.5 angstroms or less.

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