Semiconductor device
By setting a low impurity concentration region and a high impurity concentration region in the second part of the gate electrode, combined with the surface orientation characteristics of silicon carbide, the problem of electric field concentration at the end of the gate electrode is solved, and breakdown suppression and resistance reduction of the semiconductor device are achieved.
Patent Information
- Application Number
- CN202480004947.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-22
- Filing Date
- 2024-02-05
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, silicon carbide semiconductor devices are prone to breakdown near the end of the gate electrode, resulting in electric field concentration and insulation breakdown.
By providing a low impurity concentration region in the second part of the gate electrode and combining the surface orientation characteristics of silicon carbide, the electric field strength is reduced, and a high impurity concentration region is provided in the third part connected to the wiring part to reduce the resistance and avoid current concentration.
It effectively suppresses the increase in the resistance of the gate electrode and the breakdown of the semiconductor device, improves the uniformity of the electric field, and prevents the occurrence of insulation breakdown.
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Figure CN120266594A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a semiconductor device. Background Art
[0002] There are semiconductor devices using silicon carbide. For semiconductor devices, a technique capable of suppressing the occurrence of breakdown is required.
[0003] Prior Art Documents
[0004] Patent Documents
[0005] Patent Document 1: Japanese Patent No. 7176206 Gazette Summary of the Invention
[0006] Problems to be Solved by the Invention
[0007] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the occurrence of breakdown.
[0008] Means for Solving the Problems
[0009] The semiconductor device of the embodiment includes a first electrode, a semiconductor layer, a second electrode, a gate electrode, and a third electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type provided above the first electrode, a second semiconductor region of a second conductivity type provided above the first semiconductor region, and a third semiconductor region of the first conductivity type provided above the second semiconductor region. The semiconductor layer contains silicon carbide. The second electrode is provided above the second semiconductor region and the third semiconductor region. The gate electrode faces the second semiconductor region with a gate insulating layer interposed therebetween in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The gate electrode includes a first portion, a second portion, and a third portion. The first portion also faces the third semiconductor region. The second portion is located at an end of the gate electrode in a third direction perpendicular to the first direction and the second direction. The third portion is located between the first portion and the second portion in the third direction. The impurity concentration of the second portion is lower than the impurity concentration of the third portion. The third electrode includes a wiring portion provided above the third portion. The third electrode is electrically connected to the gate electrode and separated from the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 is a top view showing the semiconductor device of the embodiment.
[0011] Figure 2 is Figure 1 a magnified top view of Part II of
[0012] Figure 3 is Figure 2 the III-III cross-sectional view of
[0013] Figure 4 is Figure 2 the IV-IV cross-sectional view of
[0014] Figure 5 is Figure 2 the V-V cross-sectional view of
[0015] Figure 6 (a) of Figure 6 (b) of
[0016] Figure 7 (a) of Figure 7 (b) of
[0017] Figure 8 (a) of Figure 8 (b) of
[0018] Figure 9 (a) of Figure 9 (b) of
[0019] Figure 10 (a) of Figure 10 (b) of
[0020] Figure 11 is the top view showing a part of the semiconductor device of the first modification of the embodiment.
[0021] Figure 12 is Figure 11 the XII-XII cross-sectional view of
[0022] Figure 13 is the top view showing a part of the semiconductor device of the second modification of the embodiment.
[0023] Figure 14 is Figure 13 the XIV-XIV cross-sectional view of Detailed Description of the Invention
[0024] Hereinafter, each embodiment of the present invention will be described with reference to the accompanying drawings. The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as in reality. In addition, even when the same part is shown, there are cases where the mutual dimensions and ratios are shown differently depending on the accompanying drawings. In the specification and each figure of the present application, for elements that are the same as those already described, the same reference numerals are assigned and the detailed description is appropriately omitted.
[0025] In the following description, n + , n -- and p + , p, p - expressions represent the relative levels of impurity concentrations in each conductivity type. That is, the impurity concentration of the expression marked with “+” is higher than the impurity concentration of the expression not marked with either “+” or “-”. The impurity concentration of the expression marked with “-” is lower than the impurity concentration of the expression not marked with either “+” or “-”. The impurity concentration of the expression marked with “--” is lower than the impurity concentration of the expression marked with “-”. Regarding each of the embodiments described below, each embodiment can also be implemented by reversing the p-type and n-type of each semiconductor region.
[0026] Figure 1 is a top view of a semiconductor device according to an embodiment. Figure 2 is Figure 1 a magnified top view of part II of Figures 3 to 5 are respectively Figure 2 a cross-sectional view taken along line III-III, a cross-sectional view taken along line IV-IV, and a cross-sectional view taken along line V-V of
[0027] The semiconductor device according to the embodiment is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). As Figures 1 to 5 shown, the semiconductor device 1 according to the embodiment includes a semiconductor layer 10, a gate electrode 20, a first electrode 31, a second electrode 32, a third electrode 33, and an insulating layer 35.
[0028] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the first part 21 toward the semiconductor layer 10 is set as the Z direction (first direction). The two directions perpendicular to the Z direction and orthogonal to each other are set as the X direction (third direction) and the Y direction (second direction). In addition, for the sake of explanation, the direction from the first part 21 toward the semiconductor layer 10 is called “up”, and the opposite direction is called “down”. These directions are based on the relative positional relationship between the first part 21 and the semiconductor layer 10 and are independent of the direction of gravity.
[0029] AsFigure 1 As shown, a second electrode 32 and a third electrode 33 are provided on the upper surface of the semiconductor device 1. The second electrode 32 and the third electrode 33 are separated from each other and electrically isolated. The third electrode 33 includes a wiring portion 33a extending in one direction and a pad portion 33b extending in the X-Y plane. The wiring portion 33a is electrically connected to the pad portion 33b. A bonding wire or the like is connected to the pad portion 33b. The outer periphery of the semiconductor device 1 is covered with an insulating layer 35.
[0030] As Figure 2 shown, a semiconductor layer 10, a gate electrode 20, etc. are provided under the second electrode 32 and the third electrode 33. In addition, Figure 2 in, the insulating layer 35 is omitted, and the second electrode 32 and the wiring portion 33a are shown by dashed lines.
[0031] As Figures 3 to 5 shown, a first electrode 31 is provided on the lower surface of the semiconductor device 1. The semiconductor layer 10 is provided above the first electrode 31.
[0032] The semiconductor layer 10 includes an n -- -type (first conductivity type) drift region 11 (first semiconductor region), a p - -type (second conductivity type) substrate region 12 (second semiconductor region), an n + -type source region 13 (third semiconductor region), a p-type shielding region 14 (fourth semiconductor region), a p + -type contact region 15a, a p + -type contact region 15b, and an n + -type drain region 16.
[0033] The n + -type drain region 16 is provided above the first electrode 31 and is electrically connected to the first electrode 31. The n -- -type drift region 11 is provided above the n + -type drain region 16. The n-type impurity concentration of the n -- -type drift region 11 is lower than the n-type impurity concentration of the n + -type drain region 16.
[0034] The p - -type substrate region 12 is provided above the n -- -type drift region 11. The n + -type source region 13 and the p + -type contact region 15a are selectively provided above the p - -type substrate region 12. The p-type impurity concentration of the p + -type contact region 15a is higher than the p-type impurity concentration of the p - -type substrate region 12.
[0035] AsFigures 2 to 4 As shown, the gate electrode 20 faces the p-type substrate region 12 in the Y direction with a gate insulating layer 25 therebetween. - The gate electrode 20 includes a first portion 21, a second portion 22, and a third portion 23. As Figure 2 and Figure 3 shown, the first portion 21 also faces the n-type source region 13 with the gate insulating layer 25 therebetween. + As Figure 2 and Figure 5 shown, the second portion 22 is located at the end of the gate electrode 20 in the X direction and is separated from the first portion 21. The third portion 23 is located between the first portion 21 and the second portion 22 in the X direction.
[0036] The gate electrode 20 has conductivity and contains polysilicon and impurities. The impurities contained in the gate electrode 20 can be n-type or p-type. In the gate electrode 20, the impurity concentration of the second portion 22 is lower than that of the first portion 21 and lower than that of the third portion 23.
[0037] The length of the first portion 21 in the X direction is longer than the lengths of the second portion 22 and the third portion 23 in the X direction respectively. For example, the length of the third portion 23 in the Z direction is longer than the lengths of the first portion 21 and the second portion 22 in the Z direction respectively.
[0038] As Figure 2 , Figure 4 and Figure 5 shown, the wiring portion 33a is located above the third portion 23. By making the wiring portion 33a contact the third portion 23, the third electrode 33 is electrically connected to the gate electrode 20.
[0039] The p-type shielding region 14 is provided between the n-type drift region 11 and the gate electrode 20 in the Z direction and is in contact with the gate insulating layer 25. The p-type impurity concentration of the p-type shielding region 14 is higher than that of the p-type substrate region 12. For example, as -- and - shown, a part of the p-type shielding region 14 faces the second portion 22 in the X direction and is connected to the p-type substrate region 12. Figure 2 and Figure 5 As - shown, the second electrode 32 is located above the n-type source region 13 and the p-type contact region 15a and is connected to the p-type substrate region 12, the n-type source region 13, and the p-type
[0040] As Figure 3 shown, the second electrode 32 is located above the n-type source region 13 and the p-type contact region 15a and is connected to the p-type substrate region 12, the n-type source region 13, and the p-type + type source region 13 and the p + type contact region 15a above, and is connected to the p - type substrate region 12, the n + type source region 13 and the p +The type contact region 15a is electrically connected. An insulating layer 35 is provided between the gate electrode 20 and the second electrode 32, and the gate electrode 20 and the second electrode 32 are electrically separated from each other.
[0041] As Figure 2 shown, the p - -type substrate region 12, the n + -type source region 13, the p + -type contact region 15a and the gate electrode 20 are respectively provided in plurality in the Y direction. Each p - -type substrate region 12, each n + -type source region 13, each p + -type contact region 15a and each gate electrode 20 extend along the X direction. The wiring portion 33a extends along the Y direction above the plurality of third portions 23.
[0042] The p + -type contact region 15b is provided above the outer periphery of the p - -type substrate region 12 and is located around the plurality of p + -type contact regions 15a in the X-Y plane. The end portions in the X direction of each p + -type contact region 15a are connected to the p + -type contact region 15b. A part of the second electrode 32 is provided above the p + -type contact region 15b, and the p + -type contact region 15b is electrically connected to the second electrode 32.
[0043] An example of the material of each component will be described. The semiconductor layer 10 contains silicon carbide. As the n-type impurity, arsenic, phosphorus or antimony can be used. As the p-type impurity, boron can be used. The gate electrode 20 has conductivity and contains polysilicon and an impurity. The gate insulating layer 25 and the insulating layer 35 include insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The first electrode 31, the second electrode 32 and the third electrode 33 include metals such as aluminum.
[0044] The operation of the semiconductor device 1 will be described.
[0045] In a state where a positive voltage is applied to the first electrode 31 with respect to the second electrode 32, a voltage equal to or higher than the threshold value is applied to the gate electrode 20. As a result, a channel (inversion layer) is formed in the p - -type substrate region 12, and the semiconductor device 1 becomes a conducting state. Electrons flow from the second electrode 32 through the channel to the n -- -type drift region 11 and move toward the first electrode 31. As a result, a current flows through the semiconductor device 1. If the voltage applied to the gate electrode 20 becomes lower than the threshold value, the channel in the p - -type substrate region 12 disappears, and the semiconductor device 1 becomes a cut-off state.
[0046] Figure 6 (a) to Figure 9 (b) of the figure is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment. Figure 6 (a) to Figure 9 (b) represents Figure 2 the manufacturing process at the V-V cross-section of the figure.
[0047] First, prepare a semiconductor substrate including an n + -type semiconductor layer 16x and an n -- -type semiconductor layer 11x. The n -- -type semiconductor layer 11x is provided above the n + -type semiconductor layer 16x. Ion-implant p-type impurities into a specified region above the n -- -type semiconductor layer 11x. As shown in Figure 6 (a) of the figure, form a p - -type semiconductor region 12x, a p-type semiconductor region 14x, and a p + -type semiconductor region 15x. In addition, by sequentially ion-implanting n-type impurities and p-type impurities into an unillustrated region, form Figure 2 and Figure 3 the n + -type source region 13 and the p + -type contact region 15a shown in the figure. The p + -type contact region 15a can also be formed simultaneously with the p + -type semiconductor region 15x.
[0048] Remove a part of the n -- -type semiconductor layer 11x and a part of the p - -type semiconductor region 12x to form an opening OP. The p-type semiconductor region 14x is located at the bottom of the opening OP. A plurality of openings OP are formed in the Y direction, and each opening OP extends in the X direction. Ion-implant p-type impurities into the side surfaces in the X direction of the opening OP. As shown in Figure 6 (b) of the figure, form a p-type semiconductor region 14y.
[0049] After that, perform post-processing on the opening OP. In the post-processing, perform chemical dry etching (CDE) or annealing in a hydrogen atmosphere. Through the post-processing, the corners at the bottom of the opening OP become smooth and the curvature of the corners becomes smaller. After that, activate the implanted impurities by heat treatment.
[0050] Form an insulating layer 35x above the outer periphery of the p - -type semiconductor region 12x by chemical vapor deposition (CVD). Form an insulating layer 25x along the inner surface of the opening OP and the surface of the insulating layer 35x by CVD. Deposit polysilicon on the insulating layer 25x by CVD to form a conductive layer 20x. As shown inFigure 7 As shown in (a) of, the opening OP is filled with the conductive layer 20x.
[0051] As Figure 7 shown in (a) of, the conductive layer 20x includes a central portion p1, an end portion p2, an intermediate portion p3, and an outer peripheral portion p4. The central portion p1, the end portion p2, and the intermediate portion p3 are located inside the opening OP. The end portion p2 is located at the end of the opening OP in the X direction. The intermediate portion p3 is located between the central portion p1 and the intermediate portion p3. The outer peripheral portion p4 is located above the central portion p1, the end portion p2, and the intermediate portion p3, and is located on the outer periphery of the p - type semiconductor region 12x.
[0052] As Figure 7 shown in (b) of, a protective film 36 is formed to cover the end portion p2 and the outer peripheral portion p4. The central portion p1 and the intermediate portion p3 are exposed without being covered by the protective film 36. The material of the protective film 36 is arbitrary. For example, silicon oxide or silicon nitride is used.
[0053] With the end portion p2 and the outer peripheral portion p4 covered, impurities are diffused into the central portion p1 and the intermediate portion p3. As a specific example, by performing heat treatment in a gas environment containing impurities, the impurities are diffused into the central portion p1 and the intermediate portion p3 of the conductive layer 20x. For example, a gas containing POC13 (phosphorus trichloride) is used. It is also possible to perform heat treatment after depositing a layer containing impurities on the conductive layer 20x and the protective film 36, thereby diffusing the impurities from the layer containing impurities into the conductive layer 20x.
[0054] The impurities diffuse from the central portion p1 and the intermediate portion p3 to the end portion p2 and the outer peripheral portion p4. Therefore, the impurity concentration of each of the end portion p2 and the outer peripheral portion p4 is lower than the impurity concentration of the central portion p1 and lower than the impurity concentration of the intermediate portion p3. In the end portion p2, a gradient of impurity concentration is formed in the direction from the central portion p1 toward the end portion p2.
[0055] The protective film 36 is removed. The outer peripheral portion p4 is removed, and the upper surfaces of the central portion p1 and the end portion p2 are recessed. Thus, as Figure 8 shown in (a) of, the upper surface of the intermediate portion p3 is located above the upper surfaces of the central portion p1 and the end portion p2.
[0056] An insulating layer 35y is formed by CVD to cover the conductive layer 20x and the insulating layer 25x. By removing a part of the insulating layer 35y, as Figure 8 shown in (b) of, the intermediate portion p3 and the p + type semiconductor region 15x are exposed.
[0057] A metal layer is formed on the insulating layer 35y by sputtering. By patterning the metal layer, asFigure 9 As shown in (a) of, the second electrode 32 and the third electrode 33 are formed. For n + The back surface of the n-type semiconductor layer 16x is ground until the n + type semiconductor layer 16x becomes a specified thickness. As Figure 9 As shown in (b) of, the first electrode 31 is formed on the ground back surface by sputtering. Through the above processes, the semiconductor device 1 of the embodiment is manufactured.
[0058] The advantages of the embodiment will be described.
[0059] When the semiconductor device 1 is used, a voltage is applied to the gate electrode 20. For example, in some cases, a voltage that is negative with respect to the first portion 21 and the second portion 22 is applied to the gate electrode 20. At this time, n -- the potential difference between the n-type drift region 11 and the gate electrode 20 increases, and the electric field strength near the gate electrode 20 increases. In particular, near the second portion 22 at the end of the gate electrode 20, there is a tendency for the electric field strength to be larger than that in other portions. If electric field concentration occurs near the second portion 22, dielectric breakdown of the gate insulating layer 25 will occur. The first electrode 31 and the third electrode 33 are conducted, causing the semiconductor device 1 to be broken down.
[0060] Figure 10 (a) of and Figure 10 (b) of are top views showing the second portion of the gate electrode.
[0061] In particular, when the semiconductor layer 10 contains silicon carbide, breakdown is more likely to occur near the second portion 22 for the following reasons. As described in the manufacturing method, after the opening OP is formed, post-treatment of the opening OP is performed. Through the post-treatment, the curvature of the corner at the bottom of the opening OP becomes smaller. As a result, the curvature of the corner at the bottom of the gate electrode 20 formed later can be reduced. As a result, when a voltage is applied to the gate electrode 20, electric field concentration at the corner at the bottom of the gate electrode 20 can be suppressed.
[0062] On the other hand, when the semiconductor layer 10 contains silicon carbide, through the post-treatment, a plane parallel to the plane orientation of silicon carbide appears at the X-direction end of the opening OP. As a result, the gate electrode 20 and the gate insulating layer 25 also have a plane parallel to the plane orientation of silicon carbide. In Figure 10 the example of (a) of, the gate insulating layer 25 has side surfaces S1, S2, end surfaces E1, and end surfaces E2. The side surfaces S1 and S2 are parallel to the X-Z plane. The end surfaces E1 and E2 are inclined with respect to the X-Z plane. In Figure 10In the example of (b), the gate insulating layer 25 has side surfaces S1 and S2 and end surfaces E3 to E5. The end surfaces E3 and E5 are inclined with respect to the X-Z plane. The end surface E4 is parallel to the Y-Z plane. The end surfaces E1 to E5 are substantially parallel to the crystal plane of silicon carbide. By the appearance of the end surfaces E1 to E5, the curvature of the angle between the surfaces becomes larger. As a result, near the second portion 22, electric field concentration is more likely to occur.
[0063] In the semiconductor device 1 of the embodiment, the impurity concentration of the second portion 22 is lower than the impurity concentration of the third portion 23. Therefore, the resistivity of the second portion 22 is higher than the resistivity of the third portion 23. When a voltage is applied to the gate electrode 20, current hardly flows in the second portion 22 compared with the first portion 21 and the third portion 23. The voltage of the second portion 22 can be made smaller than the voltages of the first portion 21 and the third portion 23 respectively. As a result, the electric field intensity near the second portion 22 can be reduced. As a result, the gate insulating layer 25 is hardly broken down by insulation, and the occurrence of breakdown of the semiconductor device 1 can be suppressed.
[0064] In addition, the wiring portion 33a is connected to a third portion 23 different from the second portion 22. The impurity concentration of the third portion 23 is higher than the impurity concentration of the second portion 22. Therefore, even when the impurity concentration of the second portion 22 is reduced, an increase in the resistance between the gate electrode 20 and the wiring portion 33a can be suppressed.
[0065] According to the embodiment, an increase in the resistance of the gate electrode 20 can be suppressed, and the occurrence of breakdown of the semiconductor device 1 can be suppressed.
[0066] The impurity concentration of the second portion 22 is preferably less than 0.5 times the impurity concentration of the third portion 23. In this way, compared with the first portion 21 and the third portion 23, an increase in the voltage of the second portion 22 can be effectively suppressed, and the electric field intensity near the second portion 22 can be sufficiently reduced. More preferably, the impurity concentration of the second portion 22 is greater than 0.001 times the impurity concentration of the third portion 23 and less than 0.1 times the impurity concentration of the third portion 23.
[0067] The gate electrode 20 preferably contains phosphorus. By using phosphorus, the resistance of the gate electrode 20 can be reduced and the threshold voltage can be further lowered compared with the case of using other impurities.
[0068] The semiconductor layer 10 preferably includes a p-type shielding region 14. The p-type shielding region 14 is provided in n --Between the p-type drift region 11 and the gate electrode 20. By providing the p-type shielding region 14, the electric field intensity near the bottom of the gate electrode 20 can be mitigated. Thereby, generation of dielectric breakdown of the gate insulating layer 25 can be further suppressed. In particular, by disposing the p-type shielding region 14 to face at least a part of the second portion 22 with the gate insulating layer 25 therebetween, the electric field intensity near the second portion 22 can be further reduced.
[0069] (First Modification Example)
[0070] Figure 11 is a top view showing a part of the semiconductor device according to the first modification example of the embodiment. Figure 12 is Figure 11 the XII-XII cross-sectional view. In addition, in Figure 11 the insulating layer 35 is omitted, and the second electrode 32 and the wiring portion 33a are indicated by dashed lines.
[0071] In the semiconductor device 2 of the first modification example, as Figure 11 and Figure 12 shown, a part of the p-type shielding region 14 faces the second portion 22 in the Y direction with the gate insulating layer 25 therebetween. This part of the p-type shielding region 14 is connected to the p - type substrate region 12. A part of the p-type shielding region 14 may also face the third portion 23.
[0072] In the illustrated example, p-type shielding regions 14 are provided on both sides of the second portion 22 in the Y direction. The p-type shielding region 14 may be provided only on one side of the second portion 22 in the Y direction. The configuration of the part of the p-type shielding region 14 connected to the p - type substrate region 12 can be changed as appropriate.
[0073] (Second Modification Example)
[0074] Figure 13 is a top view showing a part of the semiconductor device according to the second modification example of the embodiment. Figure 14 is Figure 13 the XIV-XIV cross-sectional view. In addition, in Figure 13 the insulating layer 35 is omitted, and the second electrode 32 and the wiring portion 33a are indicated by dashed lines.
[0075] In the semiconductor device 3 of the second modification example, as Figure 13 and Figure 14 shown, the gate insulating layer 25 includes a first insulating region 25a and a second insulating region 25b.
[0076] The first insulating region 25a is disposed between the semiconductor layer 10 and the gate electrode 20 in the Y direction. The first insulating region 25a is in contact with the first portion 21, the second portion 22, and the third portion 23 in the Y direction. The second insulating region 25b is disposed between the semiconductor layer 10 and the gate electrode 20 in the X direction. The second insulating region 25b is in contact with the second portion 22 in the X direction.
[0077] The thickness of the second insulating region 25b is greater than the thickness of the first insulating region 25a. The thickness of the first insulating region 25a corresponds to the distance between the semiconductor layer 10 and the gate electrode 20 in the Y direction. The thickness of the second insulating region 25b corresponds to the distance between the semiconductor layer 10 and the gate electrode 20 in the X direction.
[0078] After forming the opening OP as shown in (b) of Figure 6 , an insulating layer is formed only at the end portion in the Y direction of the opening OP. Thereafter, the same method as that after (a) of Figure 7 is performed. Thus, the gate insulating layer 25 including the second insulating region 25b thicker than the other portions is formed.
[0079] By including the second insulating region 25b in the gate insulating layer 25, the electric field strength near the second portion 22 can be further reduced. According to the second modification example, compared with the semiconductor device 1, the generation of breakdown of the semiconductor device 3 can be further suppressed.
[0080] Embodiments of the present invention may include the following structures.
[0081] (Structure 1)
[0082] A semiconductor device, comprising:
[0083] A first electrode;
[0084] A semiconductor layer including a first semiconductor region of a first conductivity type disposed above the first electrode, a second semiconductor region of a second conductivity type disposed above the first semiconductor region, and a third semiconductor region of the first conductivity type disposed above the second semiconductor region, and containing silicon carbide;
[0085] A second electrode disposed above the second semiconductor region and the third semiconductor region;
[0086] A gate electrode facing the second semiconductor region with a gate insulating layer interposed therebetween in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region,
[0087] The gate electrode includes a first portion, a second portion, and a third portion,
[0088] The first part is also opposite to the third semiconductor region.
[0089] The second part is located at an end of the gate electrode in a third direction perpendicular to the first direction and the second direction.
[0090] The third part is located between the first part and the second part in the third direction.
[0091] The impurity concentration of the second part is lower than that of the third part; and
[0092] A third electrode, including a wiring part disposed on the third part, is electrically connected to the gate electrode and separated from the second electrode.
[0093] (Structure 2)
[0094] The semiconductor device according to Structure 1, wherein
[0095] The semiconductor layer further includes a fourth semiconductor region of a second conductivity type disposed between the first semiconductor region and the gate electrode.
[0096] The fourth semiconductor region is connected to the second semiconductor region.
[0097] (Structure 3)
[0098] The semiconductor device according to Structure 2, wherein
[0099] A part of the fourth semiconductor region is opposite to the third part across the gate insulating layer in the second direction or the third direction.
[0100] (Structure 4)
[0101] The semiconductor device according to any one of Structures 1 to 3, wherein
[0102] The impurity concentration of the second part is less than 0.5 times that of the third part.
[0103] (Structure 5)
[0104] The semiconductor device according to any one of Structures 1 to 4, wherein
[0105] A plurality of gate electrodes are provided in the second direction.
[0106] The wiring part is located on a plurality of the third parts.
[0107] (Structure 6)
[0108] The semiconductor device according to any one of Structures 1 to 5, wherein
[0109] The gate insulating layer includes a first insulating region disposed between the gate electrode and the semiconductor layer in the second direction and a second insulating region disposed between the gate electrode and the semiconductor layer in the third direction.
[0110] The thickness of the second insulating region is greater than the thickness of the first insulating region.
[0111] (Structure 7)
[0112] The semiconductor device according to any one of Structures 1 to 6, wherein
[0113] The length of the third part in the first direction is longer than the length of the first part in the second direction and longer than the length of the second part in the second direction.
[0114] According to the embodiments described above, an increase in the resistance of the gate electrode can be suppressed, and the occurrence of breakdown of the semiconductor device can be suppressed.
[0115] Regarding the relative levels of impurity concentrations between the semiconductor regions in the above-described embodiments, for example, a scanning capacitance microscope (SCM) can be used to confirm. In addition, the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, regarding the relative levels of carrier concentrations between the semiconductor regions, SCM can also be used to confirm. In addition, regarding the impurity concentration in each semiconductor region, for example, it can be measured by secondary ion mass spectrometry (SIMS).
[0116] Several embodiments of the present invention have been illustrated above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are included in the invention described in the claims and its equivalents. In addition, the above-described embodiments can be implemented in combination with each other.
[0117] Description of Reference Numerals
[0118] 1 to 3: Semiconductor device; 10: Semiconductor layer; 11: n -- -type drift region; 11x: n -- -type semiconductor layer; 12: p - -type substrate region; 12x: p - -type semiconductor region; 13: n +Type source region; 14: p-type shielding region; 14x, 14y: p-type semiconductor regions; 15a, 15b: p + type contact regions; 15x: p + type semiconductor region; 16: n + type drain region; 16x: n + type semiconductor layer; 20: gate electrode; 20x: conductive layer; 21: first part; 22: second part; 23: third part; 25: gate insulating layer; 25a: first insulating region; 25b: second insulating region; 25x: insulating layer; 31: first electrode; 32: second electrode; 33: third electrode; 33a: wiring part; 33b: pad part; 35, 35x, 35y: insulating layers; 36: protective film; 100: semiconductor device; E1 to E5: end faces; OP: opening; S1, S2: side faces; p1: central part; p2: end part; p3: middle part; p4: outer peripheral part.
Claims
1. A semiconductor device, characterized in that, Comprising: A first electrode; A semiconductor layer, including a first semiconductor region of a first conductivity type disposed on the first electrode, a second semiconductor region of a second conductivity type disposed on the first semiconductor region, and a third semiconductor region of the first conductivity type disposed on the second semiconductor region, and containing silicon carbide; A second electrode disposed on the second semiconductor region and the third semiconductor region; A gate electrode facing the second semiconductor region across a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, The gate electrode includes a first portion, a second portion, and a third portion, The first portion also faces the third semiconductor region, The second portion is located at an end of the gate electrode in a third direction perpendicular to the first direction and the second direction, The third portion is located between the first portion and the second portion in the third direction, The impurity concentration of the second portion is lower than the impurity concentration of the third portion; And A third electrode, including a wiring portion disposed on the third portion, electrically connected to the gate electrode, and separated from the second electrode.
2. The semiconductor device according to claim 1, wherein The semiconductor layer further includes a fourth semiconductor region of the second conductivity type disposed between the first semiconductor region and the gate electrode, The fourth semiconductor region is connected to the second semiconductor region.
3. The semiconductor device according to claim 2, wherein A part of the fourth semiconductor region faces the third portion across the gate insulating layer in the second direction or the third direction.
4. The semiconductor device according to any one of claims 1 to 3, wherein The impurity concentration of the second portion is less than 0.5 times the impurity concentration of the third portion.
5. The semiconductor device according to any one of claims 1 to 3, wherein A plurality of gate electrodes are provided in the second direction, The wiring portion is located on a plurality of the third portions.
6. The semiconductor device according to any one of claims 1 to 3, wherein The gate insulating layer includes a first insulating region provided between the gate electrode and the semiconductor layer in the second direction and a second insulating region provided between the gate electrode and the semiconductor layer in the third direction, The thickness of the second insulating region is greater than the thickness of the first insulating region.
7. The semiconductor device according to any one of claims 1 to 3, wherein The length of the third portion in the first direction is longer than the length of the first portion in the second direction and longer than the length of the second portion in the second direction.