Semiconductor device

Abstract

Provided is a semiconductor device which can be miniaturized or highly integrated. The semiconductor device includes a first conductor, a first insulator, a second conductor on the first insulator, an oxide semiconductor, a second insulator, a third conductor, a third insulator, and a fourth insulator. The first insulator and the second conductor are provided with an opening that reaches the first conductor. A portion of the oxide semiconductor is disposed in the opening and is in contact with the top surface of the first conductor. The other portion of the oxide semiconductor is disposed above the opening and is in contact with at least a portion of the top surface of the second conductor. The second insulator is disposed on the oxide semiconductor such that at least a portion thereof is located in the opening. The third conductor is disposed on the second insulator such that at least a part of the third conductor is located in the opening. The third insulator is disposed between a side wall of the opening and the oxide semiconductor so as to be located in the opening. The fourth insulator is disposed between the side wall of the opening and the third insulator so as to be located in the opening. The third insulator includes a metal oxide. The fourth insulator includes silicon nitride.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a storage device, and an electronic device. In addition, one aspect of the present invention relates to a method for manufacturing a storage device or a semiconductor device. In addition, one aspect of the present invention relates to a semiconductor wafer and a module.

[0002] Note that, in the present specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are also one aspect of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification and the like relates to an object, a method, or a manufacturing method. In addition, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit formed by processing a semiconductor wafer to form a chip (including at least transistors and a memory) and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on a circuit board, for example, a printed wiring board, and are used as one of the components of various electronic devices.

[0006] In addition, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known, and oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, in recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit.

[0009] Furthermore, if a vertical transistor can be realized, the density of integrated circuits can be increased. For example, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0010] [Prior technical literature]

[0011] [Patent Document]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0013] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0014] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0015] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0016] [Non-patent literature]

[0017] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention

[0018] Technical problem to be solved by the invention

[0019] One of the objects of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with good reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with less non-uniformity in the electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another object of one embodiment of the present invention is to provide a low-power semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0020] Note that the description of these objects does not preclude the existence of other objects. Note that one embodiment of the present invention does not need to achieve all of the above objects. Note that objects other than the above can be known and extracted from the descriptions in the specification, drawings, claims, etc.

[0021] Means for Solving Technical Problems

[0022] One embodiment of the present invention is a semiconductor device including: a first conductor; a first insulator; a second conductor on the first insulator; an oxide semiconductor; a second insulator; a third conductor; a third insulator; and a fourth insulator. An opening reaching the first conductor is provided in the first insulator and the second conductor. A part of the oxide semiconductor is disposed in the opening and in contact with the top surface of the first conductor, and another part of the oxide semiconductor is disposed above the opening and in contact with at least a part of the top surface of the second conductor. The second insulator is disposed on the oxide semiconductor such that at least a part of it is located in the opening. The third conductor is disposed on the second insulator such that at least a part of it is located in the opening. The third insulator is disposed between the side wall of the opening and the oxide semiconductor in the opening. The fourth insulator is disposed between the side wall of the opening and the third insulator in the opening. The third insulator contains a metal oxide, and the fourth insulator contains silicon nitride.

[0023] In the above semiconductor device, preferably, the first insulator includes a first layer, a second layer on the first layer, and a third layer on the second layer. Both the first layer and the third layer contain silicon nitride, and the second layer contains silicon oxide.

[0024] In addition, in the above semiconductor device, the side surface of the second conductor may also be in contact with the fourth insulator.

[0025] In addition, in the above semiconductor device, a part of the bottom surface of the second conductor may also be in contact with the upper end portions of the third insulator and the fourth insulator.

[0026] In addition, in the above semiconductor device, a part of the bottom surface of the third layer may also be in contact with the upper end portions of the third insulator and the fourth insulator.

[0027] In addition, in the above semiconductor device, preferably, when viewed in cross section, the width of the opening is greater than the height of the opening.

[0028] In addition, in the above semiconductor device, preferably, it further includes a fifth insulator containing silicon oxide, and the fifth insulator is disposed between the third insulator and the oxide semiconductor so as to be located in the opening.

[0029] In addition, in the above semiconductor device, preferably, a part of the fourth insulator is disposed below the third insulator, and a part of the fourth insulator is in contact with the lower end portion of the third insulator and the side surface of the fifth insulator.

[0030] In addition, in the above semiconductor device, preferably, the metal oxide contains hafnium.

[0031] Another aspect of the present invention is a semiconductor device, including: a first conductor; a second conductor; a third conductor; a fourth conductor; an oxide semiconductor; a first insulator; a second insulator; a third insulator; a fourth insulator; and a fifth insulator. Among them, the second conductor is located on the first insulator, the second insulator is located on the second conductor, the third conductor is located on the second insulator, an opening reaching the first conductor is provided in the first insulator, the second conductor, the second insulator and the third conductor, a part of the oxide semiconductor is disposed in the opening and in contact with the top surface of the first conductor, another part of the oxide semiconductor is in contact with at least a part of the top surface of the third conductor outside the opening, the third insulator is disposed on the oxide semiconductor so that at least a part of it is located in the opening, the fourth conductor is disposed on the third insulator so that at least a part of it is located in the opening, the fourth insulator is disposed between the second conductor and the oxide semiconductor so as to be located in the opening, the fifth insulator is disposed between the second conductor and the fourth insulator so as to be located in the opening, the fourth insulator contains a metal oxide, and the fifth insulator contains silicon nitride.

[0032] In the above semiconductor device, preferably, both the first insulator and the second insulator contain silicon nitride.

[0033] In addition, in the above semiconductor device, the side surface of the third conductor may also be in contact with the fifth insulator.

[0034] In addition, in the above-described semiconductor device, a part of the bottom surface of the third conductor may also be in contact with the upper end portions of the fourth insulator and the fifth insulator.

[0035] In addition, in the above-described semiconductor device, a part of the bottom surface of the second insulator may also be in contact with the upper end portions of the fourth insulator and the fifth insulator.

[0036] In addition, in the above-described semiconductor device, preferably, when viewed in cross-section, the width of the opening is greater than the height of the opening.

[0037] In addition, in the above-described semiconductor device, preferably, it further includes a sixth insulator containing silicon oxide, and the sixth insulator is disposed between the fourth insulator and the oxide semiconductor so as to be located in the opening.

[0038] In addition, in the above-described semiconductor device, preferably, a part of the fifth insulator is disposed below the fourth insulator, and a part of the fifth insulator is in contact with the lower end portion of the fourth insulator and the side surface of the sixth insulator.

[0039] In addition, in the above-described semiconductor device, preferably, the metal oxide contains hafnium.

[0040] Advantages of the Invention

[0041] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one aspect of the present invention, a semiconductor device with less non-uniformity in the electrical characteristics of transistors can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one aspect of the present invention, a low-power semiconductor device can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0042] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the descriptions in the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a perspective view showing an example of a semiconductor device.

[0044] Figure 2AIt is a plan view showing an example of a semiconductor device. Figures 2B to 2E It is a cross-sectional view showing an example of a semiconductor device.

[0045] Figure 3 It is a cross-sectional view showing an example of a semiconductor device.

[0046] Figure 4A It is a plan view showing an example of a semiconductor device. Figures 4B to 4E It is a cross-sectional view showing an example of a semiconductor device.

[0047] Figure 5A It is a plan view showing an example of a semiconductor device. Figures 5B to 5E It is a cross-sectional view showing an example of a semiconductor device.

[0048] Figures 6A to 6C It is a cross-sectional view showing an example of a semiconductor device.

[0049] Figures 7A to 7D It is a cross-sectional view showing an example of a semiconductor device.

[0050] Figures 8A to 8E It is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 9A It is a plan view showing an example of a semiconductor device. Figures 9B to 9D It is a cross-sectional view showing an example of a semiconductor device.

[0052] Figure 10A It is a plan view showing an example of a manufacturing method of a semiconductor device. Figure 10B and Figure 10C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0053] Figure 11A It is a plan view showing an example of a manufacturing method of a semiconductor device. Figure 11B and Figure 11C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0054] Figure 12A It is a plan view showing an example of a manufacturing method of a semiconductor device. Figure 12B and Figure 12C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0055] Figure 13A It is a plan view showing an example of a manufacturing method of a semiconductor device. Figure 13B and Figure 13C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0056] Figure 14A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 14B And Figure 14C It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0057] Figure 15A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 15B And Figure 15C It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0058] Figure 16A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 16B And Figure 16C It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0059] Figure 17A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 17B And Figure 17C It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0060] Figure 18A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 18B And Figure 18C It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0061] Figure 19A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 19B And Figure 19C It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0062] Figures 20A to 20F It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0063] Figures 21A to 21F It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0064] Figure 22A It is a plan view showing an example of a storage device. Figure 22B And Figure 22C It is a cross-sectional view showing an example of a storage device. Figure 22D It is a circuit diagram for explaining an example of the structure of a storage device.

[0065] Figure 23A It is a plan view showing an example of a storage device. Figure 23BIt is a cross-sectional view showing an example of a storage device.

[0066] Figure 24A It is a plan view showing an example of a storage device. Figure 24B It is a cross-sectional view showing an example of a storage device.

[0067] Figure 25A It is a plan view showing an example of a storage device. Figure 25B It is a cross-sectional view showing an example of a storage device.

[0068] Figure 26 It is a cross-sectional view showing an example of a storage device.

[0069] Figure 27A It is a plan view showing an example of a storage device. Figure 27B and Figure 27C It is a cross-sectional view showing an example of a storage device. Figure 27D It is a circuit diagram for explaining an example of the structure of a storage device.

[0070] Figures 28A to 28E It is a cross-sectional view for explaining a method of depositing a metal oxide according to one aspect of the present invention.

[0071] Figures 29A to 29D It is a cross-sectional view of a metal oxide according to one aspect of the present invention.

[0072] Figures 30A to 30D It is a cross-sectional view for explaining a method of depositing a metal oxide according to one aspect of the present invention.

[0073] Figures 31A to 31C It is a cross-sectional view for explaining a method of depositing a metal oxide according to one aspect of the present invention.

[0074] Figure 32 It is a block diagram for explaining an example of the structure of a storage device.

[0075] Figure 33A It is a schematic diagram for explaining an example of the structure of a storage device. Figure 33B It is a circuit diagram for explaining an example of the structure of a storage device.

[0076] Figure 34A and Figure 34B It is a schematic diagram for explaining an example of the structure of a storage device.

[0077] Figure 35 It is a circuit diagram for explaining an example of the structure of a storage device.

[0078] Figure 36A and Figure 36B It is a schematic diagram of a semiconductor device according to one aspect of the present invention.

[0079] Figure 37A and Figure 37B is a diagram illustrating an example of an electronic component.

[0080] Figures 38A to 38E is a schematic diagram of a storage device according to one aspect of the present invention.

[0081] Figures 39A to 39H is a diagram showing an electronic device according to one aspect of the present invention.

[0082] Figure 40A is a diagram showing an example of a storage system that can be used in a data center. Figure 40B is a diagram showing an example of a space device. Detailed Embodiments

[0083] Hereinafter, embodiments will be described with reference to the drawings. Note that those of ordinary skill in the art can easily understand the fact that the embodiments can be implemented in many different forms, and the ways and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the embodiments shown below.

[0084] In addition, in the drawings, for the sake of clarity, the sizes, thicknesses of layers, or regions are sometimes exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and thus are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned due to processes such as etching, but are sometimes not reflected in the drawings for the sake of easy understanding. In addition, in the drawings, the same reference numerals are sometimes used commonly between different drawings to denote the same parts or parts having the same functions, and the repeated description thereof is omitted. In addition, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching reference numerals.

[0085] In addition, especially in a plan view (also referred to as a "top view") or a perspective view, etc., for the sake of easy understanding of the invention, the description of some constituent elements is sometimes omitted. In addition, the description of some hidden lines is sometimes omitted.

[0086] In addition, in this specification, etc., for convenience, ordinal numbers such as first and second are added, and they do not represent the process order or the stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third", etc. for description. In addition, the ordinal numbers described in this specification, etc. are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0087] In addition, in this specification and the like, for convenience, terms such as "upper" and "lower" are used to describe the positional relationship of components with reference to the accompanying drawings. In addition, the positional relationship of components is appropriately changed according to the directions in which the components are described. Therefore, the terms described in the specification are not limited, and the terms can be appropriately changed according to the circumstances.

[0088] For example, in this specification and the like, the connection between X and Y means the electrical connection between X and Y. Here, the electrical connection between X and Y means a connection through which an electrical signal can be transmitted between X and Y when there is an object (such as a component like a switch, transistor, or diode, or a circuit including the component and wiring) between X and Y. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected. Here, the direct connection between X and Y means a connection through which an electrical signal can be transmitted between X and Y through wiring (or electrodes) etc. without passing through the above object. In other words, the direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0089] In addition, in this specification and the like, a transistor means an element including at least three terminals: a gate, a drain, and a source. Furthermore, the transistor has a region (hereinafter, also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region means a region where current mainly flows.

[0090] In addition, in the case of using transistors with different polarities or when the direction of current changes during the operation of a circuit, etc., the functions of the source or the drain sometimes swap with each other. Therefore, in this specification and the like, the source or the drain can sometimes be swapped with each other.

[0091] Note that impurities in a semiconductor, for example, refer to elements other than the main components constituting the semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, an increase in the density of defect states of the semiconductor and a decrease in crystallinity sometimes occur. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, for example, there are Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. In addition, for example, the incorporation of impurities sometimes leads to the formation of oxygen vacancies (also referred to as V O : oxygen vacancy) in the oxide semiconductor.

[0092] Note that in this specification and the like, oxynitride refers to a substance in which the oxygen content in its composition is more than the nitrogen content. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. In addition, nitride oxide refers to a substance in which the nitrogen content in its composition is more than the oxygen content. Examples of nitride oxides include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.

[0093] In addition, in this specification and the like, "insulator" can be alternatively referred to as an insulating film or an insulating layer. In addition, "conductor" can be alternatively referred to as a conductive film or a conductive layer. In addition, "semiconductor" can be alternatively referred to as a semiconductor film or a semiconductor layer.

[0094] In addition, in this specification and the like, "parallel" means a state where the angle formed by two straight lines is -10 degrees or more and 10 degrees or less. Therefore, it also includes the state where the angle is -5 degrees or more and 5 degrees or less. In addition, "substantially parallel" means a state where the angle formed by two straight lines is -30 degrees or more and 30 degrees or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80 degrees or more and 100 degrees or less. Therefore, it also includes the state where the angle is 85 degrees or more and 95 degrees or less. In addition, "substantially perpendicular" means a state where the angle formed by two straight lines is 60 degrees or more and 120 degrees or less.

[0095] In addition, in this specification and the like, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (grounding potential), "voltage" can also be referred to as "potential". Note that the ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit, etc. also change according to the change of the reference potential.

[0096] In this specification and the like, when multiple components use the same symbol and it is necessary to distinguish them, sometimes symbols for identification such as "_1", "[n]", or "[m, n]" are attached to the symbol.

[0097] Note that in this specification and the like, "height consistency" refers to a structure in which the heights from a reference plane (e.g., a flat plane such as a substrate surface) in a cross section are equal. For example, in the manufacturing process of a semiconductor device, planarization processing (typically CMP) is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the heights of the processed surfaces of the CMP processing from the reference plane are equal. Note that depending on the processing apparatus, processing method, or material of the processed surface during CMP processing, the heights of multiple layers may sometimes be different. In this specification and the like, "height consistency" also includes the above cases. For example, in the case of a layer having two heights with respect to a reference plane (hereinafter referred to as the first layer and the second layer), when the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, it is also referred to as "height consistency".

[0098] Note that in this specification and the like, "end consistency" refers to a case where at least a part of the outlines of stacked layers overlap when viewed from a plane. For example, it includes cases where the upper layer and the lower layer are processed using the same mask pattern or a part thereof using the same mask pattern. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is inside the outline of the lower layer or the outline of the upper layer is outside the outline of the lower layer, and these cases can also be said to be "end consistent".

[0099] Note that generally, it is difficult to clearly distinguish between "perfect consistency" and "substantially consistent". Therefore, in this specification and the like, "consistency" includes both cases of perfect consistency and cases of substantial consistency.

[0100] Note that in this specification and the like, the always-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. In addition, the always-off characteristic refers to a state in which current does not flow through the transistor when no voltage is applied to the gate or when a ground potential is supplied to the gate.

[0101] In addition, in this specification and the like, the off-state current is sometimes denoted as the leakage current. In addition, in this specification and the like, the off-state current sometimes refers to, for example, the current flowing between the source and the drain when the transistor is in the off state.

[0102] (Embodiment 1)

[0103] In this embodiment, with reference to Figure 1 FIGS. 27 to 27, an example of a semiconductor device of one aspect of the present invention and a manufacturing method thereof will be described. In addition, an example of a storage device using the semiconductor device will be described.

[0104] <Structural example of semiconductor device>

[0105] With reference to Figures 1 to 3Describe the structure of a semiconductor device including the transistor 200. Figure 1 Is a perspective view of the semiconductor device. Figures 2A to 2E Is a plan view and a cross-sectional view of the semiconductor device. Figure 2A Is a plan view of the semiconductor device. Additionally, Figure 2B and Figure 2C are cross-sectional views of the semiconductor device. Here, Figure 2B is a cross-sectional view of the portion indicated by the dash-dot line A1 - A2 in Figure 2A . Additionally, Figure 2C is a cross-sectional view of the portion indicated by the dash-dot line A3 - A4 in Figure 2A . Additionally, Figure 2D is a cross-sectional view along the XY plane of the layer including the insulator 280b. Additionally, Figure 2E is a cross-sectional view along the XY plane of the layer including the conductor 240. Additionally, Figure 3 is a magnified view corresponding to Figure 2B . Note that, for clarity, Figure 1 the perspective view of Figure 2A and the plan view of

[0106] Note that sometimes arrows indicating the X direction, Y direction, and Z direction are attached to the drawings in this specification, etc. Note that in this specification, etc., the "X direction" refers to the direction along the X-axis, and unless otherwise specified, the forward and reverse directions are sometimes not distinguished. The same applies to the "Y direction" and "Z direction". Additionally, the X direction, Y direction, and Z direction are mutually intersecting directions. More specifically, the X direction, Y direction, and Z direction are mutually orthogonal directions. In this specification, etc., the X direction, Y direction, or Z direction is sometimes referred to as the "first direction". Additionally, sometimes the other one is referred to as the "second direction". Additionally, sometimes the remaining one is referred to as the "third direction".

[0107] Figure 1 and Figures 2A to 2C The semiconductor device shown includes: an insulator 122 on a substrate (not shown); an insulator 280 (including insulator 280a, insulator 280b, and insulator 280c) on the insulator 122; a transistor 200 with a part thereof embedded in an opening 290 formed in the insulator 280; and an insulator 283 on the transistor 200. The insulator 122, insulator 280, and insulator 283 are used as interlayer films.

[0108] The transistor 200 includes: a conductor 120 formed in a manner of being embedded in an insulator 122; a conductor 240 on the insulator 280; an oxide semiconductor 230; an insulator 250 on the oxide semiconductor 230; and a conductor 260 on the insulator 250. The oxide semiconductor 230 is used as a semiconductor layer, the conductor 260 is used as a gate electrode, the insulator 250 is used as a gate insulator, the conductor 120 is used as one of a source electrode and a drain electrode, and the conductor 240 is used as the other of the source electrode and the drain electrode.

[0109] Figure 2B and Figure 2C As shown in Figure 2C , an opening 290 reaching the conductor 120 is provided in the insulator 280 and the conductor 240. At least a part of the components of the transistor 200 is disposed in the opening 290. Here, the bottom of the opening 290 is the top surface of the conductor 120, and the side walls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240. The side walls of the opening 290 are preferably perpendicular to the top surface of the conductor 120. At this time, the opening 290 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the semiconductor device can be achieved.

[0110] At least a part of the oxide semiconductor 230 is disposed in the opening 290. Here, the oxide semiconductor 230 includes a region in contact with the top surface of the conductor 120 in the opening 290 and a region in contact with at least a part of the top surface of the conductor 240 above the opening 290. The insulator 250 provided in contact with the top surface of the oxide semiconductor 230 is disposed in such a manner that at least a part of it is located in the opening 290. The conductor 260 provided in contact with the top surface of the insulator 250 is disposed in such a manner that at least a part of it is located in the opening 290. In addition, as Figure 2B and Figure 2C shown in Figure 2C , the conductor 260 is preferably disposed in such a manner that at least a part of it is embedded in the opening 290.

[0111] Furthermore, an insulator 254 is disposed between the side wall of the opening 290 and the oxide semiconductor 230 in a manner of being located in the opening 290, an insulator 252 is disposed between the side wall of the opening 290 and the insulator 254, and an insulator 256 is disposed between the insulator 254 and the oxide semiconductor 230.

[0112] The insulator 252 is in contact with the side surface of the insulator 280, the side surface of the conductor 240, the bottom surface of the oxide semiconductor 230 above the conductor 240, the side surface and the lower end of the insulator 254, the side surface of the insulator 256, and the top surface of the conductor 120. As Figure 2B and Figure 2CAs shown, when viewed in cross-section, a protruding portion is formed in a part of the insulator 252 that contacts the top surface of the conductor 120. At the end of the protruding portion, the insulator 252 contacts the insulator 256. The protruding portion of the insulator 252 has a shape that protrudes more toward the center of the opening 290 than other parts. That is, when viewed in cross-section in a direction perpendicular to the Z-axis (which can also be said to be a direction perpendicular to the channel length direction), the insulator 252 has a so-called L shape (including an L shape reversed left and right).

[0113] The insulator 252 preferably has a hydrogen barrier property, and particularly preferably has a high ability to suppress hydrogen diffusion. For example, silicon nitride or the like can be used as the insulator 252. In addition, insulators having a hydrogen barrier property can be referred to the insulators described in [Insulator]. By providing the above-described insulator 252, excessive hydrogen can be suppressed from diffusing from the outside of the transistor 200 into the insulator 254, the insulator 256, and the oxide semiconductor 230.

[0114] The insulator 254 contacts the side surface and the top surface of the protruding portion of the insulator 252, the bottom surface of the oxide semiconductor 230 located above the conductor 240, and the side surface of the insulator 256. Figure 2B and Figure 2C As shown, when viewed in cross-section, the side surface of the insulator 254 sometimes aligns with the side end portion of the protruding portion of the insulator 252.

[0115] The insulator 254 preferably has a hydrogen barrier property, and particularly preferably has a high ability to capture or fix (also referred to as gettering) hydrogen. For example, a metal oxide such as hafnium oxide can be used as the insulator 254. In addition, insulators having a hydrogen barrier property can be referred to the insulators described in [Insulator]. By providing the above-described insulator 254, hydrogen in the insulator 256 that contacts the oxide semiconductor 230 can be captured or fixed by the insulator 254.

[0116] The insulator 256 contacts the side surface of the protruding portion of the insulator 252, the side surface of the insulator 254, the bottom surface and the side surface of the oxide semiconductor 230, and the top surface of the conductor 120. The insulator 256 is preferably an oxygen-containing insulator. For example, silicon oxide can be used as the insulator 256. In addition, oxygen-containing insulators can be referred to the oxygen-containing insulators described in the insulators described in [Insulator]. By forming an oxygen-containing insulator 256 in contact with the oxide semiconductor 230, oxygen vacancies (hereinafter also referred to as V O ) and defects formed by hydrogen entering the oxygen vacancies (hereinafter also referred to as V O H) can be suppressed. In addition, by using an insulator containing oxygen released during heating (hereinafter also referred to as excess oxygen) as the insulator 256, oxygen can be supplied to the oxide semiconductor 230.

[0117] Figure 2A This is a plan view showing the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290. Note that the opening 290 provided in the insulator 280 is shown by a dashed line. As Figure 2A shown, the conductor 240 includes the opening 290 in the region overlapping with the conductor 120.

[0118] The configurations of the insulator 252, the insulator 254, the insulator 256, the oxide semiconductor 230, the insulator 250, and the conductor 260 in the opening 290 reflect the shape of the opening 290. Therefore, the insulator 252 is provided so as to cover the side wall of the opening 290, the insulator 254 is provided so as to contact the inner side surface of the insulator 252, the insulator 256 is provided so as to contact the inner side surface of the insulator 254, the oxide semiconductor 230 is provided so as to cover the bottom of the opening 290 and the inner side surface of the insulator 256, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to be embedded in the recess of the insulator 250 that reflects the shape of the opening 290.

[0119] Thus, as Figure 2D shown, from the cross-sectional structure of the layer including the insulator 280b, the insulator 252, the insulator 254, the insulator 256, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in a concentric circle. In addition, as Figure 2E shown, the cross-sectional structure of the layer including the conductor 240 is the same. In addition, although not shown, the cross-sectional structures of the layer including the insulator 280a and the layer including the insulator 280c are also the same.

[0120] Note that this embodiment shows an example in which the shape of the opening 290 when viewed from the plane is circular, but the present invention is not limited thereto. For example, the shape of the opening 290 when viewed from the plane may also be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are rounded.

[0121] The oxide semiconductor 230 includes a channel formation region and a source region and a drain region provided so as to sandwich the channel formation region.

[0122] One of the source region and the drain region of the transistor 200 is in contact with the conductor 120 of the oxide semiconductor 230. The other of the source region and the drain region of the transistor 200 is in contact with the conductor 240 of the oxide semiconductor 230. As Figures 2A to 2E shown, the conductor 240 is in contact with the entire outer periphery of the oxide semiconductor 230 outside the opening 290.

[0123] The channel formation region of the oxide semiconductor 230 is at least a part of the region between one of the source region and the drain region and the other of the source region and the drain region. That is to say, the channel formation region of the transistor 200 is located in the region between the conductor 120 and the conductor 240 of the oxide semiconductor 230. In addition, it can also be said that the channel formation region of the transistor 200 is located in the region in contact with or near the insulator 256 of the oxide semiconductor 230.

[0124] The channel length of the transistor 200 is the distance between the source region and the drain region. That is to say, it can be said that the channel length of the transistor 200 depends on the thickness of the insulator 280 on the conductor 120 and the thickness of the conductor 240. In addition, it can also be said that the channel length of the transistor 200 depends on the height H of the opening 290. Figure 3 The height H of the opening 290 is indicated by a double-headed arrow with a double-dashed line in the figure. In addition, more precisely, the channel length of the transistor 200 includes the distance between the portion where the oxide semiconductor 230 protrudes from the opening 290 and the portion where the oxide semiconductor 230 contacts the conductor 240. Therefore, when viewed in cross section, the channel of the transistor 200 can be regarded as an inverted L shape (including the inverted L shape with left and right reversed). Note that the inverted L shape means an L shape with the top and bottom reversed.

[0125] In existing transistors, the channel length is set according to the exposure limit of photolithography, but in the present invention, the channel length can be set according to the thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less and 1 nm or more or 5 nm or more). Thereby, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved.

[0126] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290 and its vicinity. Therefore, compared with existing transistors in which the channel formation region, the source region, and the drain region are separately provided in the XY plane, the occupied area of the transistor 200 can be reduced. Thereby, the semiconductor device can be highly integrated.

[0127] Thus, since the source region and the drain region in the transistor 200 are located at different heights, the current flowing through the semiconductor flows in the Z-axis direction. That is to say, it can be said that the channel length direction has a component in the height direction (longitudinal direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a longitudinal transistor, a longitudinal channel transistor, etc. In addition, the above-mentioned longitudinal transistor can also be called a CFET (Columnar Field Effect Transistor) from its shape.

[0128] In addition, on the XY plane of the channel formation region including the oxide semiconductor 230, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in a concentric circle shape. Therefore, the side surface of the conductor 260 provided at the center faces the side surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. That is to say, when viewed from the plane, the entire outer periphery of the oxide semiconductor 230 is a channel formation region. At this time, for example, the channel width of the transistor 200 is determined according to the length of the outer periphery of the oxide semiconductor 230. That is to say, it can be said that the channel width of the transistor 200 depends on the size of the width D of the opening 290. In Figure 3 FIG., the width D of the opening 290 is shown by a double-headed arrow with a dashed line. By increasing the width D of the opening 290, the channel width per unit area can be increased to increase the on-state current. Therefore, the width D of the opening 290 is preferably larger than the height H of the opening 290, and more preferably 2 times or more the height H of the opening 290. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0129] Here, the width D of the opening 290 can be appropriately calculated according to the shape of the uppermost part of the opening 290. For example, when the opening is rectangular when viewed from the plane, the width D of the opening 290 can be the length of the diagonal of the uppermost part of the opening 290.

[0130] In addition, by forming the opening 290 to have a circular shape when viewed from the plane, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in a concentric circle shape. Thereby, the distance between the conductor 260 and the oxide semiconductor 230 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor 230 substantially uniformly.

[0131] In the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer, preferably, compared with the source region and the drain region, there are fewer oxygen vacancies or the impurity concentration of hydrogen, nitrogen, metal elements, etc. is low. In addition, hydrogen near the oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V OH), electrons that become carriers are generated, so V in the channel formation region O H is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0132] Therefore, as described above, by forming the insulators 252, 254, and 256 near the oxide semiconductor 230, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. As a result, the oxygen vacancies and V in the oxide semiconductor 230 O H can be reduced, and thus a semiconductor device with good electrical characteristics and high reliability can be provided.

[0133] In addition, the source region and the drain region of a transistor using an oxide semiconductor for the semiconductor layer are regions where the carrier concentration increases due to more oxygen vacancies, more V O H, or a higher impurity concentration of hydrogen, nitrogen, metal elements, etc. compared to the channel formation region, and thus the resistance is lowered. That is, compared to the channel formation region, the source region and the drain region of the transistor are n-type regions with a higher carrier concentration and a lower resistance.

[0134] Note that although Figure 2B and Figure 2C show the opening 290 provided such that the side wall of the opening 290 is perpendicular to the top surface of the conductor 120, the present invention is not limited thereto. For example, the side wall of the opening 290 may be tapered.

[0135] Note that in this specification and the like, the tapered shape means a shape in which at least a part of the side surface of the component is inclined with respect to the substrate surface or the surface to be formed. For example, a region having an angle (also referred to as a cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed greater than 0 degrees and less than 90 degrees is preferred. Here, the side surface, the substrate surface, and the surface to be formed of the component do not necessarily have to be completely flat, and may be an approximately planar shape with a small curvature or an approximately planar shape with fine irregularities.

[0136] As Figure 2B and Figure 2C show, a part of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240. Note that although Figure 2B shows a structure in which the oxide semiconductor 230 is disconnected in the X direction, the present invention is not limited thereto. For example, the oxide semiconductor 230 may also be provided to extend in the X direction. Note that in this case, the oxide semiconductor 230 is also disconnected in the Y direction.

[0137] In addition, Figure 2CA structure is shown in which the side end portion of the oxide semiconductor 230 is located inside the side end portion of the conductor 240. Note that the present invention is not limited thereto. For example, a structure in which the side end portions of the oxide semiconductor 230 and the conductor 240 coincide in the Y direction may also be employed. Alternatively, a structure in which the side end portion of the oxide semiconductor 230 is located outside the side end portion of the conductor 240 may also be employed.

[0138] The bandgap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a large bandgap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current in a memory cell, the stored content can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, thereby sufficiently reducing the power consumption of the semiconductor device. Note that the frequency of the refresh operation of a general DRAM needs to be about 1 time / 60 msec, but the frequency of the refresh operation of the semiconductor device according to one embodiment of the present invention can be about 1 time / 10 sec, which is a refresh operation frequency more than 10 times or more than 100 times that of a general DRAM. Note that by using the semiconductor device according to one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.

[0139] In addition, as the oxide semiconductor 230, a single layer or a stack of the metal oxides described in [Metal Oxides] to be described later can be used.

[0140] Specifically, as the oxide semiconductor 230, a metal oxide having a composition such as In:M:Zn = 1:3:2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:3:4 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:2 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof can be used. In addition, the composition in the vicinity includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0141] In addition, when depositing the metal oxide by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide.

[0142] For the analysis of the composition of the metal oxide used for the oxide semiconductor 230, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used. In addition, analysis can also be performed by combining multiple of the above methods. Note that due to the influence of analysis accuracy, the actual content rate of an element with a sometimes low content rate may be different from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis may sometimes be lower than the actual content rate.

[0143] The formation of the metal oxide can appropriately use the sputtering method or the atomic layer deposition (ALD) method. Note that when the metal oxide is formed by the sputtering method, the composition of the formed metal oxide is sometimes different from the composition of the sputtering target. In particular, the zinc content rate of the formed metal oxide sometimes decreases to about 50% of the zinc content rate in the sputtering target.

[0144] The oxide semiconductor 230 preferably has crystallinity. Examples of the oxide semiconductor having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, single crystal oxide semiconductor, etc. CAAC-OS or nc-OS is preferably used for the oxide semiconductor 230, and CAAC-OS is particularly preferably used.

[0145] CAAC-OS preferably has a plurality of layered crystal regions and its c-axis is oriented in the normal direction of the formation surface. For example, the oxide semiconductor 230 preferably includes layered crystals substantially parallel to the side surface of the insulator 256. By adopting such a structure, the layered crystals of the oxide semiconductor 230 are substantially parallel to the channel length direction of the transistor 200, so the on-state current of the transistor can be increased.

[0146] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by performing a heat treatment at a temperature at which the metal oxide is not polycrystallized (e.g., 400 °C or higher and 600 °C or lower) after forming the metal oxide, CAAC-OS can have a denser structure with higher crystallinity. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0147] In addition, distinct grain boundaries are not easily observed in CAAC-OS, so a decrease in electron mobility due to grain boundaries is not likely to occur. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has heat resistance and high reliability.

[0148] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 230, oxygen extraction from the oxide semiconductor 230 by the source electrode or the drain electrode can be suppressed. Thus, even when a heat treatment is performed, oxygen extraction from the oxide semiconductor 230 can be suppressed, so the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0149] The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). In addition, analysis can also be performed by combining multiple of the above methods.

[0150] Note that although Figure 2B and Figure 2C show a structure in which the oxide semiconductor 230 is a single layer, the present invention is not limited thereto. The oxide semiconductor 230 may also have a stacked structure of a plurality of oxide layers with different chemical compositions. For example, a structure in which a variety of metal oxides described in [Metal Oxide] below are appropriately stacked may also be employed.

[0151] For example, as Figure 3 shown, the oxide semiconductor 230 may also have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b on the oxide semiconductor 230a.

[0152] The conductivity of the material for the oxide semiconductor 230a is preferably different from the conductivity of the material for the oxide semiconductor 230b.

[0153] For example, the oxide semiconductor 230a may use a material with a higher conductivity than the oxide semiconductor 230b. By using a material with a high conductivity for the conductor 120 serving as the source electrode or the drain electrode and the oxide semiconductor 230a in contact with the conductor 240, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced. Thus, a transistor with a large on-state current can be realized.

[0154] Here, when a material with a high conductivity is used for the oxide semiconductor 230b provided on the side of the conductor 260 serving as the gate electrode, sometimes the threshold voltage of the transistor drifts, so that the drain current flowing when the gate voltage is 0V (hereinafter, also referred to as the cut-off current) becomes large. Specifically, when the transistor 200 is an n-channel transistor, sometimes the threshold voltage decreases. Therefore, the oxide semiconductor 230b preferably uses a material with a lower conductivity than the oxide semiconductor 230a. Thus, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cut-off current can be realized. Note that the state with a small cut-off current is sometimes referred to as normally off.

[0155] By making the oxide semiconductor 230 have a stacked structure as described above and using a material with a higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a normally off transistor with a large on-state current can be realized. Thus, a semiconductor device with low power consumption and high performance can be realized.

[0156] In addition, the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b. By increasing the carrier concentration of the oxide semiconductor 230a, the conductivity becomes higher, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced. Thus, a transistor with a large on-state current can be realized. By reducing the carrier concentration of the oxide semiconductor 230b, the conductivity becomes lower, and thus a normally off transistor can be realized.

[0157] Here, although an example of using a material with a higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a is shown, one embodiment of the present invention is not limited thereto. The oxide semiconductor 230a may also use a material with a lower conductivity than the oxide semiconductor 230b. The carrier concentration of the oxide semiconductor 230a may be lower than the carrier concentration of the oxide semiconductor 230b.

[0158] The band gap of the first metal oxide for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide for the oxide semiconductor 230b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0159] The band gap of the first metal oxide for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide for the oxide semiconductor 230b. Thereby, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and thereby a transistor with a large on-state current can be realized. In addition, in the case where the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and thereby a normally-off transistor can be realized.

[0160] Here, although an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, one aspect of the present invention is not limited thereto. The band gap of the first metal oxide can be larger than the band gap of the second metal oxide.

[0161] As described above, the band gap of the first metal oxide for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide for the oxide semiconductor 230b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the composition of the first metal oxide different from the composition of the second metal oxide, the band gap can be controlled. For example, the content rate of the element M in the first metal oxide is preferably lower than the content rate of the element M in the second metal oxide. Specifically, in the case where the first metal oxide and the second metal oxide are In-M-Zn oxides, the composition of the first metal oxide can be set to In:M:Zn = 1:1:1 [atomic ratio] or around it, and the composition of the second metal oxide can be set to In:M:Zn = 1:3:2 [atomic ratio] or around it. As the element M, it is particularly preferable to use one or more of gallium, aluminum, and tin.

[0162] The first metal oxide may not contain the element M. For example, the first metal oxide for the oxide semiconductor 230a can be an In-Zn oxide, and the second metal oxide for the oxide semiconductor 230b can be an In-M-Zn oxide. Specifically, the first metal oxide can be an In-Zn oxide, and the second metal oxide can be an In-Ga-Zn oxide. More specifically, the composition of the first metal oxide can be set to In:Zn = 1:1 [atomic ratio] or around it or In:Zn = 4:1 [atomic ratio] or around it, and the composition of the second metal oxide can be set to In:Ga:Zn = 1:1:1 [atomic ratio] or around it.

[0163] Here, although an example in which the content rate of element M in the first metal oxide is lower than the content rate of element M in the second metal oxide is shown, one aspect of the present invention is not limited thereto. The content rate of element M in the first metal oxide may also be higher than the content rate of element M in the second metal oxide. In addition, as long as the compositions of the first metal oxide and the second metal oxide are different, the content rates of elements other than element M may also be different.

[0164] The thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0165] The thickness of each layer constituting the oxide semiconductor 230 (here, the oxide semiconductor 230a and the oxide semiconductor 230b) may be determined so that the thickness of the oxide semiconductor 230 is within the above range. The thickness of the oxide semiconductor 230a may be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within the required range. In addition, the thickness of the oxide semiconductor 230b may be determined so that the threshold voltage of the transistor is within the required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.

[0166] In addition, between the oxide semiconductor 230a and the oxide semiconductor 230b, the ratio of the thickness of the portion where the top surface of the conductor 240 is the formation surface to the thickness of the portion where the side surfaces of the conductor 240 and the insulator 280 are the formation surfaces may sometimes be different.

[0167] Figure 3 An example in which the oxide semiconductor 230 has a stacked structure of two layers, the oxide semiconductor 230a and the oxide semiconductor 230b, is shown, but the present invention is not limited thereto. The oxide semiconductor 230 may also have a stacked structure of three or more layers.

[0168] When the oxide semiconductor 230 has a three-layer stacked structure, for example, the following structure can also be adopted: A metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or a composition in the vicinity thereof or a metal oxide having a composition of In:Zn = 4:1 [atomic ratio] or a composition in the vicinity thereof, and a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof are sequentially provided from the side of the conductor 120. By adopting this structure, the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with less non-uniformity can be realized.

[0169] As the insulator 250, a single layer or a stack of insulators described in [Insulator] below can be used. As the insulator 250, for example, silicon oxide or silicon oxynitride can be used. Since silicon oxide and silicon oxynitride have thermal stability, they are preferred.

[0170] In addition, as the insulator 250, a material having a high relative dielectric constant, that is, a so-called high-k material, described in [Insulator] below can also be used. For example, hafnium oxide or aluminum oxide can also be used.

[0171] The thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 1 nm or more and 12 nm or less, and further preferably 2 nm or more and 10 nm or less. At least a part of the insulator 250 may be a region having the above thickness.

[0172] The impurity concentration of water, hydrogen, etc. in the insulator 250 is preferably reduced. Thereby, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230 can be suppressed.

[0173] As Figure 2B and Figure 2C shown, a part of the insulator 250 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. At this time, the insulator 250 preferably covers the side end portion of the oxide semiconductor 230. Thereby, a short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. In addition, the insulator 250 preferably covers the side end portion of the conductor 240. Thereby, a short circuit between the conductor 260 and the conductor 240 can be prevented.

[0174] Note that a single-layer insulator 250 is shown in Figure 2B and Figure 2C However, the present invention is not limited thereto. The insulator 250 may also have a stacked structure.

[0175] For example, as Figure 3As shown, the insulator 250 may also have a stacked structure including an insulator 250a, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c.

[0176] The insulator 250b is preferably made of a material with a low relative permittivity as described in [Insulator] below. In particular, silicon oxide and silicon oxynitride are preferred because of their thermal stability. In this case, the insulator 250b contains at least oxygen and silicon. By adopting such a structure, the parasitic capacitance generated between the conductor 260 and the conductor 240 can be reduced. In addition, it is preferable that the impurity concentration of water, hydrogen, etc. in the insulator 250b is reduced.

[0177] The insulator 250a is preferably an insulator with oxygen barrier properties as described in [Insulator] below. The insulator 250a has a region in contact with the oxide semiconductor 230. When the insulator 250a has oxygen barrier properties, oxygen detachment from the oxide semiconductor 230 during heat treatment or the like can be suppressed. Therefore, the formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. Thereby, the electrical characteristics of the transistor 200 can be improved and the reliability can be enhanced. As the insulator 250a, for example, alumina is preferably used. In this case, the insulator 250a contains at least oxygen and aluminum.

[0178] The insulator 250c preferably has hydrogen barrier properties, and in particular, a high ability to capture or fix hydrogen. That is, the insulator 250d can use the same insulating material as the insulator 254. For example, hafnium oxide can be used. Thereby, hydrogen in the oxide semiconductor 230 can be captured or fixed more effectively. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced. In this case, the insulator 250c contains at least oxygen and hafnium. In addition, this insulator may also have an amorphous structure.

[0179] The insulator 250d preferably has hydrogen barrier properties, and in particular, a high ability to suppress hydrogen diffusion. That is, the insulator 250d can use the same insulating material as the insulator 252. For example, silicon nitride can be used. Thereby, the diffusion of impurities in the conductor 260 into the oxide semiconductor 230 can be suppressed more effectively. Silicon nitride has high hydrogen barrier properties and is suitable for the insulator 250d. In this case, the insulator 250d contains at least nitrogen and silicon.

[0180] The insulator 250d may also have oxygen barrier properties. The insulator 250d is provided between the insulator 250b and the conductor 260. Therefore, oxygen in the insulator 250b can be prevented from diffusing into the conductor 260, thereby suppressing the oxidation of the conductor 260. In addition, a decrease in the amount of oxygen supplied to the channel formation region of the oxide semiconductor 230 can be suppressed.

[0181] In order to miniaturize the transistor 200, it is preferable that the thicknesses of the insulators 250a to 250d are thin, and preferably their thicknesses are within the above ranges. Typically, the thicknesses of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. By adopting such a structure, even if the transistor 200 is miniaturized or highly integrated, it can have good electrical characteristics.

[0182] Although Figure 3 The insulator 250 is shown as a stacked structure of four layers, namely the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 can also adopt a stacked structure of two layers, three layers, or five or more layers. At this time, each layer in the insulator 250 can be appropriately selected from the insulators 250a to 250d.

[0183] As the conductor 260, a single layer or a stack of conductors described in [Conductor] below can be used. As the conductor 260, for example, a highly conductive material such as tungsten can be used.

[0184] In addition, as the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion. As such a conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. In addition, ruthenium can also be used for the conductor 260. Thereby, a decrease in the conductivity of the conductor 260 can be suppressed.

[0185] Although Figure 2B and Figure 2C show an example in which the conductor 260 is a single layer, the present invention is not limited thereto. The conductor 260 can also have a stacked structure. For example, as shown in Figure 3 The conductor 260 can also adopt a stacked structure of the conductor 260a and the conductor 260b on the conductor 260a. At this time, for example, titanium nitride can be used as the conductor 260a, and tungsten can be used as the conductor 260b. By providing a layer containing tungsten in this way, the conductivity of the conductor 260 can be improved and its function as a wiring can be fully exerted.

[0186] Although Figure 3 shows an example in which the conductor 260 adopts a stacked structure of two layers, namely the conductor 260a and the conductor 260b, the present invention is not limited thereto. The conductor 260 can also adopt a stacked structure of three or more layers. For example, in the case of adopting a three-layer structure, a conductor similar to the conductor 260a can be further provided above the conductor 260b in the structure of Figure 3 .

[0187] AlthoughFigure 2B and Figure 2C An example is shown in which the conductor 260 is disposed so as to be embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the central portion of the conductor 260, and a part of the concave portion is located in the opening 290. At this time, the concave portion may be filled with an inorganic insulating material or the like.

[0188] In addition, as Figure 2B and Figure 2C shown, a part of the conductor 260 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. Although Figure 2B shows a structure in which the side end portion of the conductor 260 coincides with the side end portion of the oxide semiconductor 230, the present invention is not limited thereto. For example, the side end portion of the conductor 260 may be located inside the side end portion of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. In addition, the side end portion of the conductor 260 may also be located outside the side end portion of the oxide semiconductor 230.

[0189] As the conductor 240, the conductor described in [Conductor] below may be used singly or in a stacked layer. For example, as the conductor 240, a highly conductive material such as tungsten may be used.

[0190] Similar to the conductor 260, the conductor 240 is also preferably made of a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride) and a conductive material containing oxygen (for example, ruthenium oxide, indium tin oxide added with silicon, etc.). In addition, a structure in which ruthenium is used for the conductor 260 may also be adopted. By adopting such a structure, peroxidation of the conductor 240 caused by the oxide semiconductor 230 or the like can be suppressed. Thereby, a decrease in the conductivity of the conductor 240 can be suppressed.

[0191] Although Figure 2B and Figure 2C show an example in which the conductor 240 is a single layer, the present invention is not limited thereto. The conductor 240 may also adopt a stacked structure. For example, as Figure 3 shown, the conductor 240 may also adopt a stacked structure of the conductor 240a, the conductor 240b on the conductor 240a, and the conductor 240c on the conductor 240b. At this time, for example, titanium nitride may be used for the conductor 240a and the conductor 240c, and tungsten may be used for the conductor 240b. By providing a layer containing tungsten in this way, the conductivity of the conductor 240 can be improved and its function as a wiring can be fully exerted.

[0192] Although Figure 3An example in which the conductor 240 has a stacked structure of three layers, i.e., the conductor 240a to the conductor 240c, is shown, but the present invention is not limited thereto. The conductor 240 may also have a stacked structure of two layers or a stacked structure of four or more layers. For example, in the case of a two-layer structure, a structure may be adopted that only uses the conductor 240b and the conductor 240c in the structure of Figure 3 In this case, similarly to the above, a structure may be adopted in which the conductor 240c uses titanium nitride and the conductor 240b uses tungsten. In addition, a structure may also be adopted in which the conductor 240b uses indium tin oxide added with silicon and the conductor 240c uses ruthenium.

[0193] In addition, although Figure 2B and Figure 2C show a structure in which the region that does not overlap with the conductor 240 of the insulator 250 has a region in contact with the top surface of the insulator 280, the present invention is not limited thereto. For example, a structure may also be adopted in which the conductor 240 is provided in such a manner as to be embedded in an insulator provided on the insulator 280 and the insulator 250 does not contact the insulator 280. At this time, the height of the top surface of the conductor 240 is preferably the same as the height of the top surface of the insulator. By adopting such a structure, the physical distance from the conductor 260 to the conductor 240 (especially the side end portion of the conductor 240) can be increased, and short circuit between the conductor 260 and the conductor 240 can be prevented.

[0194] In addition, since the oxide semiconductor 230 is in contact with the conductor 240, a low-resistance region is formed in the oxide semiconductor 230. Thereby, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

[0195] As Figure 2B and Figure 2C shown, the insulator 280 preferably has a stacked structure of the insulator 280a, the insulator 280b on the insulator 280a, and the insulator 280c on the insulator 280b. However, the present invention is not limited thereto. For example, the insulator 280 may also have a single-layer structure with only the insulator 280b or a single-layer structure with only the insulator 280c.

[0196] In order for the insulator 280b to function as an interlayer film, it is preferable that its relative permittivity is low. By using a material with a low relative permittivity for the interlayer film, the parasitic capacitance between wirings can be reduced. As the insulator 280b, a single layer or a stack of insulators containing a material with a low relative permittivity described in [Insulator] below can be used. Silicon oxide and silicon oxynitride have thermal stability, so they are preferable. In this case, the insulator 280b contains at least oxygen and silicon. In addition, as the insulator 280b, TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) formed by plasma CVD method can be used. Thereby, the productivity can be improved. In addition, even if the insulator 280b uses a film type with a high impurity concentration (for example, hydrogen concentration, etc.) in the film, one embodiment of the present invention employs a structure in which the insulator 280b is surrounded by the insulator 280a, the insulator 280c, and the insulator 252. Therefore, even if the impurity concentration in the film of the insulator 280b is high, impurities (for example, hydrogen) in the film will not diffuse to the outside or the possibility of diffusion to the outside is low, and thus a highly reliable semiconductor device can be realized.

[0197] In addition, it is preferable to reduce the impurity concentration of water, hydrogen, etc. in the insulator 280b. Thereby, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230 can be suppressed.

[0198] The insulator 280b is preferably formed by a deposition method such as sputtering method or plasma enhanced chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition) method. In particular, when using the sputtering method, by depositing using a deposition method that does not use hydrogen gas as a deposition gas, a film with extremely low hydrogen content can be realized. Therefore, the supply of hydrogen to the semiconductor 230 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized.

[0199] It is preferable that both the insulator 280a and the insulator 280c have hydrogen barrier properties, and it is particularly preferable that their ability to suppress hydrogen diffusion is high. That is to say, the insulator 280a and the insulator 280c can use the same insulating material as the insulator 252. For example, silicon nitride can be used. In this case, the insulator 280a and the insulator 280c contain at least nitrogen and silicon. Thereby, the diffusion of hydrogen from the outside of the transistor through the insulator 280a or the insulator 280c to the oxide semiconductor 230 can be suppressed. Since the silicon nitride film has characteristics of less release of impurities (for example, water and hydrogen) from itself and being difficult to permeate oxygen and hydrogen, it is suitable for the insulator 280a and the insulator 280c. In addition, the insulator 280a and the insulator 280c can use the same material or different materials.

[0200] In addition, both the insulator 280a and the insulator 280c preferably have oxygen barrier properties. By providing the insulator 280a between the insulator 280b and the conductor 120, oxidation of the conductor 120 by oxygen in the insulator 280b, which would cause an increase in resistance, can be suppressed. In addition, by providing the insulator 280c between the insulator 280b and the conductor 240, oxidation of the conductor 240 by oxygen in the insulator 280b, which would cause an increase in resistance, can be suppressed.

[0201] In addition, in the oxide semiconductor 230, the amount of oxygen supplied to the region in contact with the insulator 280c is smaller than the amount of oxygen supplied to the region in contact with the insulator 256. Therefore, the region of the oxide semiconductor 230 in contact with the insulator 280c may be made to have a lower resistance. That is, a low-resistance region serving as a source region and a drain region can be formed relatively easily in the region of the oxide semiconductor 230 in contact with the insulator 280c and in its vicinity.

[0202] The thickness of the insulator 280a is preferably smaller than the thickness of the insulator 280b. In addition, the thickness of the insulator 280c is preferably smaller than the thickness of the insulator 280b. The thicknesses of the insulator 280a and the insulator 280c are preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, further preferably 3 nm or more and 7 nm or less, and even more preferably 3 nm or more and 5 nm or less. The thickness of the insulator 280b is preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 20 nm or less, and further preferably 7 nm or more and 15 nm or less.

[0203] Note that although Figure 2B and Figure 2C the thickness of the insulator 280c is substantially the same as the thickness of the insulator 280a in

[0204] In addition, although Figure 2B and Figure 2CThe structure in which the insulator 280c is provided on the planarized insulator 280b is shown, but the present invention is not limited thereto. For example, the insulator 280c may be deposited without performing the planarization process on the insulator 280b. By not performing the planarization process, the manufacturing cost can be reduced while the yield can be improved. In addition, the insulators 280a, 280b, and 280c can be continuously deposited without being exposed to the atmospheric environment. By performing the deposition without being exposed to the atmospheric environment, impurities or moisture from the atmospheric environment can be prevented from adhering to the insulators 280a to 280c, and thus the vicinity of the interface between the insulator 280a and the insulator 280b and the vicinity of the interface between the insulator 280b and the insulator 280c can be kept clean.

[0205] The insulator 283 preferably has a hydrogen barrier property, and particularly preferably has a high ability to suppress hydrogen diffusion. That is, the same insulating material as the insulator 252 can be used for the insulator 283. For example, silicon nitride can be used. In this case, the insulator 283 contains at least nitrogen and silicon. Thereby, hydrogen diffusion from the outside of the transistor into the oxide semiconductor 230 can be suppressed. Since the silicon nitride film and the silicon oxynitride film each have characteristics of less release of impurities (such as water and hydrogen) from themselves and oxygen and hydrogen being difficult to permeate, they can be applied to the insulator 283.

[0206] The insulator 283 may also have an oxygen barrier property. The insulator 283 is provided in contact with the conductor 260. Thereby, oxidation of the conductor 260 can be suppressed.

[0207] As the conductor 120, a single layer or a laminate of the conductors described in [Conductor] to be described later can be used. For example, as the conductor 120, a highly conductive material such as tungsten can be used.

[0208] Similar to the conductor 260, the conductor 120 is also preferably made of a conductive material that is not easily oxidized or has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen (such as titanium nitride or tantalum nitride) and a conductive material containing oxygen (such as ruthenium oxide, indium tin oxide doped with silicon, etc.). In addition, ruthenium can also be used for the conductor 120. By adopting such a structure, overoxidation of the conductor 240 due to the oxide semiconductor 230 or the like can be suppressed. Thereby, a decrease in the conductivity of the conductor 120 can be suppressed.

[0209] Although Figure 2B and Figure 2C show an example in which the conductor 120 is a single layer, the present invention is not limited thereto. The conductor 120 may also have a laminated structure. For example, as Figure 3As shown, the conductor 120 may also adopt a stacked structure of a conductor 120a, a conductor 120b on the conductor 120a, and a conductor 120c on the conductor 120b. At this time, for example, titanium nitride may be used as the conductor 120a and the conductor 120c, and tungsten may be used as the conductor 120b. By providing a layer containing tungsten in this way, the conductivity of the conductor 120 can be improved.

[0210] Although Figure 3 shows an example in which the conductor 120 adopts a stacked structure of three layers, namely, the conductor 120a to the conductor 120c, the present invention is not limited thereto. The conductor 120 may also adopt a stacked structure of two layers or a stacked structure of four or more layers. For example, in the case of adopting a two-layer structure, it may also be composed of only Figure 3 the conductor 120b and the conductor 120c in the structure of Figure 3 In addition, for example, it may also be composed of only

[0211] Here, by bringing the oxide semiconductor 230 into contact with the conductor 120, a metal compound or oxygen vacancies can be formed, and a low-resistance region can be formed in the oxide semiconductor 230. Thereby, the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced.

[0212] Note that although Figure 2B and Figure 2C show a structure in which the conductor 120 is formed in an island shape, the present invention is not limited thereto. For example, the conductor 120 may also be extended in the X direction or the Y direction according to the circuit design of the semiconductor device using the transistor 200 and used as a wiring.

[0213] Although Figure 2B and Figure 2C show a structure having a region where the top surface of the conductor 120 is in contact with the bottom surface of the oxide semiconductor 230, the present invention is not limited thereto. For example, a conductor may also be provided between the conductor 120 and the oxide semiconductor 230.

[0214] In addition, in order for the insulator 122 to function as an interlayer film, it is preferable that its relative dielectric constant is low. The insulator 122 may use an insulating material that can be used for the insulator 280b.

[0215] <Deformation Examples of Semiconductor Devices>

[0216] Next, deformation examples of the semiconductor device including the transistor 200 will be described with reference to FIGS. 4 to 9. Here, Figures 4A to 4E , Figures 5A to 5E and Figures 9A to 9D are a plan view and a cross-sectional view of the semiconductor device corresponding to Figures 2A to 2E .Figure 9D is a cross-sectional view along the XY plane of a layer including the conductor 205. Additionally, Figure 4E is a cross-sectional view along the XY plane of a layer including the conductor 240. Additionally, Figure 5E is a cross-sectional view along the XY plane of a layer including the insulator 280c. Additionally, Figures 6A to 8E is a cross-sectional view along the portion indicated by the dash-dot line A1 - A2.

[0217] In the semiconductor devices shown in FIGS. 4 to 9, the same structures as those of the semiconductor device shown in FIG. 2 are denoted by the same reference numerals, and for detailed information, reference can be made to the description according to Figures 1 to 3 thereof.

[0218] Although in the above structural example, an example is shown in which the side surface of the conductor 240 is in contact with the side surface of the insulator 252, and a part of the insulator 252 and a part of the insulator 254 are formed in the same layer as the conductor 240, the present invention is not limited thereto. As in Figures 4A to 4E the semiconductor device shown, a structure in which a part of the bottom surface of the conductor 240 can also be in contact with the upper end portions of the insulator 252 and the insulator 254 can also be adopted. In this case, as in Figure 4B and Figure 4C shown, the insulators 252 and 254 are formed below the conductor 240. Additionally, the side surface of the conductor 240 is in contact with the insulator 256.

[0219] In this modified example, as in Figure 4D shown, the layer including the insulator 280b is formed with the insulators 252, 254, 256, the oxide semiconductor 230, the insulator 250, and the conductor 260 in the opening 290. On the other hand, in this modified example, as in Figure 4E shown, the layer including the conductor 240 is formed with only the oxide semiconductor 230, the insulator 250, and the conductor 260 in the opening 290.

[0220] By adopting the above structure, a region where the conductor 240 is in contact with the oxide semiconductor 230 (that is, a low-resistance region) can be formed at a position closer to the center of the opening 290. As a result, the channel length of the transistor 200 becomes shorter, thereby improving the on-state current, field-effect mobility, and frequency characteristics of the semiconductor device.

[0221] Furthermore, as in Figures 5A to 5EAs shown in the semiconductor device, in addition to the conductor 240, an insulator 280c can also be formed on the insulators 252 and 254. In this case, a part of the bottom surface of the insulator 280c contacts the upper ends of the insulator 252 and the insulator 254. In addition, the side surface of the insulator 280c contacts the insulator 256. As Figure 5E shown, only the oxide semiconductor 230, the insulator 250, and the conductor 260 are formed in the opening 290 in the layer including the insulator 280c.

[0222] Although the above structural example shows an example in which the insulator 256 is provided and the insulator 254 is opposed to the oxide semiconductor 230 with the insulator 256 therebetween, the present invention is not limited thereto. As Figure 6A shown in the semiconductor device, a structure in which the insulator 256 is not provided and the side surface of the insulator 254 and a part of the insulator 252 are in contact with the oxide semiconductor 230 can also be adopted. Thereby, the process of forming the insulator 256 can be omitted and the productivity of the semiconductor device can be improved.

[0223] In addition, as Figure 6B shown, Figures 4A to 4E the semiconductor device shown can also adopt a structure in which the insulator 256 is not provided. In addition, as Figure 6C shown, Figures 5A to 5E the semiconductor device shown can also adopt a structure in which the insulator 256 is not provided. In Figure 6B and Figure 6C the structures shown, in order to bring the side surface of the conductor 240 into contact with the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductor 240 can be increased. Thereby, the on-state current, the field-effect mobility, and the frequency characteristics of the semiconductor device can be improved.

[0224] Although Figures 4A to 4E the semiconductor device shown shows an example in which the side surface of the conductor 240 contacts the side surface of the insulator 256 and a part of the insulator 256 and the conductor 240 are formed in the same layer, the present invention is not limited thereto. As Figure 7A shown in the semiconductor device, a structure in which a part of the bottom surface of the conductor 240 contacts the upper ends of the insulator 252, the insulator 254, and the insulator 256 can also be adopted. In this case, as Figure 7A shown, the insulators 252, 254, and 256 are formed below the conductor 240. Here, since the side surface of the conductor 240 contacts the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductor 240 can be increased. Thereby, the on-state current, the field-effect mobility, and the frequency characteristics of the semiconductor device can be improved.

[0225] Furthermore, as shown in the semiconductor device of Figure 7B , in addition to the conductor 240, an insulator 280c can also be formed on the insulator 256. In this case, a part of the bottom surface of the insulator 280c contacts the upper end portion of the insulator 252, the upper end portions of the insulator 254 and the insulator 256. In addition, the side surface of the insulator 280c contacts the oxide semiconductor 230.

[0226] Although Figures 4A to 4E shows an example in which the inner side surface of the conductor 240 (which can also be referred to as the side surface on the side of the conductor 260) is aligned with the inner side surface of the insulator 254, the present invention is not limited thereto. As shown in the semiconductor device of Figure 7C , a structure in which the inner side surface of the conductor 240 is arranged outside the inner side surface of the insulator 254 can also be adopted. In this case, a part of the insulator 256 sometimes contacts the upper end portion of the insulator 254.

[0227] Furthermore, as shown in the semiconductor device of Figure 7D , the inner side surface of the insulator 280c can also be arranged outside the inner side surface of the insulator 254. Here, it is preferable that the inner side surface of the conductor 240 is arranged outside the inner side surface of the insulator 280c. In this case, a part of the insulator 256 sometimes contacts the upper end portion of the insulator 254 and the upper end portion of the insulator 280c.

[0228] In addition, although the above structural example shows an example in which the top surface of the conductor 120 is flat, the present invention is not limited thereto. For example, as shown in Figure 8A , a structure in which a concave portion overlapping the opening 290 is formed on the top surface of the conductor 120 can also be adopted. At least a part of the insulator 252, the insulator 254, the insulator 256, the oxide semiconductor 230, the insulator 250, and the conductor 260 is formed in such a way as to be embedded in the concave portion. By forming the oxide semiconductor 230, the insulator 250, and the conductor 260 in the concave portion, it is possible to easily apply the gate electric field of the conductor 260 to the vicinity of the conductor 120 of the oxide semiconductor 230.

[0229] In addition, although the above structural example shows an example in which the conductor 120 is embedded in the insulator 122, the present invention is not limited thereto. For example, as shown in Figure 8B , a structure in which an insulator 280a is provided to cover the conductor 120 can also be adopted. In this case, the insulator 280a contacts a part of the top surface and the side surface of the conductor. Thereby, the process of forming the insulator 122 can be omitted and the productivity of the semiconductor device can be improved.

[0230] In addition, although the example of the above-described structure shows that the insulator 252 is L-shaped when viewed in cross section, the present invention is not limited thereto. For example, as Figure 8C shown, a structure in which the insulator 252 does not overlap with the insulator 254 may also be employed. In this case, the lower end portion of the insulator 254 contacts the top surface of the conductor 120. In addition, the insulator 252 does not contact the insulator 256.

[0231] In addition, although the example of the above-described structure shows that the width D of the opening 290 is greater than the height H of the opening 290 when viewed in cross section, the present invention is not limited thereto. For example, as Figure 8D shown, a structure in which the width D of the opening 290 is less than the height H of the opening 290 may also be employed. The width D and the height H of the opening 290 can be appropriately set according to the electrical characteristics required for the transistor 200.

[0232] In addition, although the example of the above-described structure shows that the insulator 280 has a three-layer structure of the insulators 280a to 280c, the present invention is not limited thereto. For example, as Figure 8E shown, the insulator 280 may also have a single-layer structure. Here, the insulator 280 is preferably made of an insulating material (e.g., silicon nitride) having a high hydrogen diffusion suppressing ability that can be used for the insulators 280a and 280c. By adopting such a structure, hydrogen diffusion from the outside of the transistor into the oxide semiconductor 230 through the insulator 280 can be suppressed.

[0233] In addition, although the example of the above-described structure shows that the transistor 200 has a single-gate structure, the present invention is not limited thereto. For example, as Figures 9A to 9D shown, a structure in which a conductor 205 serving as a second gate (which may also be referred to as a back gate) is provided between the insulator 280a and the insulator 280c may also be employed.

[0234] The conductor 205 is provided so as to contact the top surface of the insulator 280a, the bottom surface of the insulator 280c, and the side surface of the insulator 254. The conductor 205 can be made of a conductive material that can be used for the conductor 260. Here, as Figure 9D shown, in the cross section including the conductor 205, an opening 290 is formed in the conductor 205, and the insulators 252, 254, 256, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically in the opening 290.

[0235] The conductor 205 serves as the second gate electrode, and the insulators 252, 254, and 256 serve as the second gate insulating layer. Additionally, a fixed potential or an arbitrary signal can be supplied to the conductor 205. For example, by independently changing the potential applied to the conductor 205 without linking it to the potential applied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Note that the structure is not limited to the above, and a structure in which the conductor 205 is electrically connected to any one of the conductors 260, 240, and 120 can also be adopted.

[0236] Note that although Figure 9B , Figure 9C and Figure 9D show a structure in which the conductor 205 is arranged in a planar shape, it is not limited thereto, and it can also be arranged to extend in the X direction or the Y direction. Additionally, an insulator identical to the insulator 280b can be provided on either or both of the spaces between the conductor 205 and the insulator 280a and between the conductor 205 and the insulator 280c.

[0237] Additionally, the structures shown in Figures 8A to 8E and Figures 9A to 9D can also be used for the semiconductor device shown in Figures 4A to 4E and the semiconductor device shown in Figures 5A to 5E .

[0238] <Constituent Materials of Semiconductor Devices>

[0239] Hereinafter, the constituent materials that can be used for semiconductor devices and storage devices will be described.

[0240] [Substrate]

[0241] As a substrate for forming the transistor 200 and the capacitor 100, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttrium-stabilized zirconia substrate), a resin substrate, etc. can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited. Further, a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can be cited. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can be cited. Or, a substrate having elements provided thereon can also be used. As the elements provided on the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0242] [Insulator]

[0243] As the insulator, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, metal nitrides, etc. having insulating properties.

[0244] For example, when miniaturizing and highly integrating the transistor, due to the thinning of the gate insulator, problems such as leakage current sometimes occur. By using a high-k material as the insulator used as the gate insulator, low voltage operation of the transistor can be achieved while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant as the insulator used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a high dielectric strength.

[0245] As materials with a high relative dielectric constant (high-k), for example, alumina, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be cited.

[0246] As materials with a low relative dielectric constant, examples include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic resin. In addition, as inorganic insulating materials with a low relative dielectric constant other than the above, examples include silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. In addition, silicon oxide having pores can be cited. Further, these silicon oxides may also contain nitrogen.

[0247] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc., and metal nitrides such as aluminum nitride, silicon oxynitride, silicon nitride, etc. can be used.

[0248] In addition, an insulator in contact with a semiconductor layer such as a gate insulator or an insulator provided near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen is in contact with a semiconductor layer, or when an insulator having a region containing excess oxygen is provided near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. As an insulator that easily forms a region containing excess oxygen, silicon oxide, silicon oxynitride, or silicon oxide having pores, etc. can be cited.

[0249] In addition, as an insulator having oxygen barrier properties, oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride, etc. can be cited. In addition, as oxides containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), etc. can be cited.

[0250] In addition, as an insulator having hydrogen barrier properties, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride, etc. can be cited.

[0251] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be insulators having barrier properties against one or both of oxygen and hydrogen.

[0252] In addition, as an insulator having a function of capturing or fixing hydrogen, oxides containing magnesium or oxides containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following property: oxygen atoms have dangling bonds and capture or fix hydrogen by these dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a part thereof may form a crystalline region.

[0253] In addition, silicon nitride or silicon oxynitride can be cited as an insulator having a high hydrogen diffusion suppression ability.

[0254] Note that, in this specification and the like, a barrier insulating film means an insulating film having barrier properties. In addition, the barrier property means a property of not easily diffusing a corresponding substance (also referred to as a property of not easily permeating a corresponding substance, a property of low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). In addition, the function of capturing or fixing (also referred to as gettering) a corresponding substance can be interchanged with the barrier property. In addition, the hydrogen as the corresponding substance, for example, means at least one of a hydrogen atom, a hydrogen molecule, a water molecule, and a substance hydrogen-bonded to OH - and the like. In addition, unless otherwise specified, the impurity as the corresponding substance means an impurity in the channel formation region or the semiconductor layer, and for example, means at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, etc.), a copper atom, and the like. In addition, the oxygen as the corresponding substance, for example, means at least one of an oxygen atom, an oxygen molecule, and the like. Specifically, the oxygen barrier property means a property of not easily diffusing at least one of an oxygen atom, an oxygen molecule, and the like.

[0255] [Conductor]

[0256] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As an alloy containing the above metal element as a component, a nitride or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, a semiconductor having a high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0257] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide, or lanthanum and nickel oxide, materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials having a function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Examples of the conductive material containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed by depositing a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0258] In addition, a conductive material mainly composed of tungsten, copper or aluminum has high conductivity, so it is preferred.

[0259] In addition, a plurality of conductive layers formed of the above materials may be laminated. For example, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen may be adopted. In addition, a laminated structure combining a material containing the above metal element and a conductive material containing nitrogen may be adopted. In addition, a laminated structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be adopted.

[0260] In addition, when a metal oxide is used for the channel formation region of a transistor, the conductor used as the gate electrode preferably adopts a laminated structure combining a material containing the above metal element and a conductive material containing oxygen. In this case, it is preferable to dispose the conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0261] In particular, as the conductor used as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen may also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using the above materials, it is sometimes possible to capture hydrogen contained in the metal oxide forming the channel. Or, it is sometimes possible to capture hydrogen mixed in from an external insulator or the like.

[0262] [Metal Oxide]

[0263] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, plane defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of generating lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities, etc.

[0264] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause generation or trapping of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferable that the lattice defects in the metal oxide used for the semiconductor layer of a transistor are few.

[0265] In a transistor using a metal oxide, in particular, if there are oxygen vacancies (V O ) and impurities in the channel formation region of the metal oxide, the electrical characteristics are likely to vary, and sometimes the reliability is reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes also denoted as V O H), and electrons that become carriers may be generated. Thus, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have normally-on characteristics. Thus, in the channel formation region of the metal oxide, it is preferable to minimize oxygen vacancies and impurities as much as possible. In other words, it is preferable that the carrier concentration in the channel formation region of the metal oxide is reduced and it is i-type (intrinsic) or substantially i-type.

[0266] The types and amounts of lattice defects that are likely to exist in a metal oxide vary depending on the structure of the metal oxide or the deposition method of the metal oxide, etc.

[0267] The structure of a metal oxide is classified into a single crystal structure and other structures (non-single crystal structures). As non-single crystal structures, for example, there are CAAC structures, polycrystalline structures, nc structures, amorphous-like (a-like) structures, and amorphous structures, etc. The a-like structure has a structure between the nc structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0268] In addition, voids or low-density regions exist in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxides of metal oxides having an a-like structure is higher than that of metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0269] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a single crystal structure. By using this metal oxide for the transistor, a transistor having good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0270] In addition, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. In order to increase the on-state current of the transistor, it is only necessary to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce the scattering factors that affect the transport of carriers. In addition, carriers flow from the source electrode to the drain electrode through the channel formation region. Therefore, by providing a channel formation region in which carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0271] Here, a metal oxide having a channel formation region preferably uses a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal, a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked. Metal oxides having such a crystal include, for example, single crystal oxide semiconductors, CAAC-OS, etc.

[0272] In addition, the c-axis of the above crystal is preferably oriented in the normal direction of the formation surface or film surface of the metal oxide. As a result, a plurality of layers are arranged in parallel or substantially parallel to the formation surface or film surface of the metal oxide. That is, a plurality of layers extend in the channel length direction.

[0273] For example, the above-described three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron with the metal contained in the first layer present at the center. In addition, the second layer has an atomic coordination structure of an oxygen trigonal bipyramid or a tetrahedron with the metal contained in the second layer present at the center. In addition, the third layer has an atomic coordination structure of an oxygen trigonal bipyramid or a tetrahedron with the metal contained in the third layer present at the center.

[0274] As the crystal structure of the above crystal, for example, there are YbFe2O4-type structures, Yb2Fe3O7-type structures, and their deformed structures.

[0275] Furthermore, it is preferable that the first to third layers are each composed of one metal element or multiple metal elements having the same valence and oxygen. Note that it is preferable that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferable that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0276] By adopting the above structure, the crystallinity of the metal oxide can be improved, and the mobility of the metal oxide can be increased. Thus, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.

[0277] Examples of the metal oxide according to one aspect of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one aspect of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a metalloid element having a high bonding energy with oxygen, for example, a metal element or a metalloid element having a higher bonding energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one aspect of the present invention preferably contains any one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification and the like sometimes include metalloid elements.

[0278] As a metal oxide semiconductor according to an aspect of the present invention, for example, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also denoted as GZO), aluminum zinc oxide (Al—Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In—Al—Zn oxide, also denoted as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also denoted as IGAZO or IAGZO), etc. may be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), etc. may be cited.

[0279] By increasing the atomic number ratio of indium to the total number of atomic numbers of all metal elements in the metal oxide, the field effect mobility of the transistor can be increased.

[0280] Note that the metal oxide may also contain one or more metal elements with a large period number instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in addition to indium. There is a tendency that the larger the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by containing a metal element with a large period number, the field effect mobility of the transistor can sometimes be increased. As the metal element with a large period number, metal elements belonging to the fifth period and metal elements belonging to the sixth period, etc. may be cited. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, etc. may be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0281] In addition, the metal oxide may also contain one or more non-metal elements. By the metal oxide containing a non-metal element, the field effect mobility of the transistor can sometimes be increased. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, hydrogen, etc. may be cited.

[0282] In addition, by increasing the atomic number ratio of zinc to the total number of atomic numbers of all metal elements in the metal oxide, the metal oxide can have high crystallinity, whereby the diffusion of impurities in the metal oxide can be suppressed. Therefore, the variation in the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0283] In addition, by increasing the atomic number ratio of element M with respect to the total number of atomic numbers of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and thus a transistor with a small off-state current can be realized. In addition, the variation in the electrical characteristics of the transistor is suppressed, and the reliability can be improved.

[0284] In addition, by increasing the atomic number ratio of In with respect to the total number of atomic numbers of all metal elements in the metal oxide, the transistor can have a large on-state current and high-frequency characteristics.

[0285] In the present embodiment, as the metal oxide, In-Ga-Zn oxide may be taken as an example for description.

[0286] In order to form a metal oxide having the above-described layered crystal structure, it is preferable to deposit atoms layer by layer. In the deposition method of the metal oxide according to one aspect of the present invention, since the ALD method is used, a metal oxide having the above-described layered crystal structure can be easily formed.

[0287] Examples of the ALD method include a thermal ALD (Thermal ALD) method in which a precursor and a reactant are reacted using only heat energy, and a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a reactant excited by plasma is used.

[0288] The ALD method can deposit atoms layer by layer, and thus has the following effects: it can deposit an extremely thin film; it can deposit on a structure with a high aspect ratio; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at a low temperature, etc. In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferable. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of these elements can be performed using XPS or SIMS. Note that, although the deposition method of the metal oxide according to one aspect of the present invention uses the ALD method, since one or both of the conditions of a high substrate temperature during deposition and an impurity removal treatment are adopted, the amount of carbon and chlorine contained in the film is sometimes less than that in the case where the ALD method is used without adopting the above conditions.

[0289] The ALD method is a film-forming method in which a film is formed by a reaction on the surface of a substrate to be processed, different from deposition methods in which particles released from a target or the like are deposited. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the substrate to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of openings with a high aspect ratio, etc. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as a sputtering method or a CVD method with a high deposition rate. For example, a method of depositing a first metal oxide by a sputtering method and depositing a second metal oxide on the first metal oxide by the ALD method can be cited. For example, when the first metal oxide has a crystalline part, the second metal oxide sometimes grows crystallographically with the crystalline part as a nucleus.

[0290] The composition of the obtained film can be controlled according to the introduction amount of the source gas in the ALD method. For example, when using the ALD method, a film with an arbitrary composition can be deposited by adjusting the introduction amount of the source gas, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time), etc. In addition, for example, when using the ALD method, a film with a continuously changing composition can be deposited by changing the source gas while depositing. When depositing while changing the source gas, since the time required for transferring or adjusting the pressure is not required, the deposition time can be shortened compared with the case of depositing using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0291] [Transistor including an oxide semiconductor]

[0292] Next, the case of using a metal oxide (oxide semiconductor) for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor in the semiconductor layer may sometimes be referred to as an OS transistor, and a transistor using silicon in the semiconductor layer may be referred to as a Si transistor.

[0293] By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with a high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

[0294] It is preferable to use an oxide semiconductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 or less, preferably 1×10 17 cm -3 or less, and more preferably 1×10 15 cm-3 Hereinafter, it is more preferably 1×10 13 cm -3 Hereinafter, it is more preferably 1×10 11 cm -3 Hereinafter, it is further preferably less than 1×10 10 cm -3 and is 1×10 -9 cm -3 or more. Note that, when aiming to reduce the carrier concentration of the oxide semiconductor film, it suffices to reduce the impurity concentration in the oxide semiconductor film to reduce the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as highly pure intrinsic or substantially highly pure intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0295] Since the density of defect states of a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film is low, the density of trap states is sometimes also low.

[0296] In addition, it takes a long time for the charge trapped in the trap states of the oxide semiconductor to disappear and sometimes behaves like a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states are sometimes unstable.

[0297] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of the impurity include hydrogen, carbon, nitrogen, etc. Note that the impurity in the oxide semiconductor refers to an element other than the main components constituting the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0298] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor whose band gap is larger than the band gap of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0299] In addition, in Si transistors, as the miniaturization of the transistors progresses, the short-channel effect (also referred to as Short Channel Effect: SCE) appears. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the occurrence of the short-channel effect can be cited as the small band gap of silicon. On the other hand, OS transistors use an oxide semiconductor as a semiconductor material with a large band gap, whereby the short-channel effect can be suppressed. In other words, OS transistors are transistors without the short-channel effect or with very little short-channel effect.

[0300] In addition, the short-channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction in channel length). Specific examples of the short-channel effect include a decrease in the threshold voltage, an increase in the subthreshold swing value (sometimes denoted as the S value), and an increase in the leakage current. Here, the S value refers to the change in the gate voltage in the subthreshold region where the drain current value changes by one order of magnitude with a fixed drain voltage.

[0301] In addition, as an index of the tolerance to the short-channel effect, the characteristic length is widely used. The characteristic length is an index of the curvature of the potential in the channel formation region. The smaller the characteristic length, the steeper the potential rise, and thus it can be said that the ability to resist the short-channel effect is high.

[0302] The OS transistor is an accumulation-type transistor, and the Si transistor is an inversion-type transistor. Therefore, compared with the Si transistor, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region of the OS transistor are smaller. Therefore, compared with the Si transistor, the OS transistor has a higher ability to resist the short-channel effect. That is to say, when manufacturing a transistor with a short channel length, the OS transistor is more preferable compared with the Si transistor.

[0303] When reducing the carrier concentration of the oxide semiconductor until the channel formation region becomes i-type or substantially i-type, in a short-channel transistor, due to the Conduction-Band-Lowering (CBL) effect, the lower end of the conduction band in the channel formation region drops, and thus the energy difference between the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Thereby, the OS transistor can also be regarded as an n - -type region where the channel formation region becomes an n + -type region and the source region and the drain region become n + / n - / n + accumulation-type junction-less transistor structure or an n + / n - / n + accumulation-type non-junction transistor structure.

[0304] With the OS transistor having the above structure, even when the semiconductor device is miniaturized or highly integrated, good electrical characteristics can be achieved. For example, even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. On the other hand, in the Si transistor, the short-channel effect occurs, and thus it is sometimes difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, compared with the Si transistor, the OS transistor can be applied to transistors with a short channel length. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region during transistor operation.

[0305] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cut-off frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cut-off frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0306] As described above, the OS transistor has better effects than the Si transistor, such as a small off-state current and the ability to fabricate transistors with a short channel length.

[0307] [Impurities in Metal Oxide]

[0308] Here, the effects of various impurities in the metal oxide (oxide semiconductor) are described.

[0309] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, even more preferably 3×10 18 atoms / cm 3 or less, and further preferably 1×10 18 atoms / cm 3 or less. In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3Hereinafter, preferably 5×10 19 atoms / cm 3 Hereinafter, more preferably 3×10 19 atoms / cm 3 Hereinafter, more preferably 1×10 19 atoms / cm 3 Hereinafter, more preferably 3×10 18 atoms / cm 3 Hereinafter, further preferably 1×10 18 atoms / cm 3 Hereinafter.

[0310] In addition, when the oxide semiconductor contains nitrogen, electrons are generated as carriers, increasing the carrier concentration and making it prone to n-type doping. As a result, using an oxide semiconductor containing nitrogen in a semiconductor transistor easily results in a normally-on characteristic. Or, when the oxide semiconductor contains nitrogen, trap states may be formed. As a result, the electrical characteristics of the transistor may sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Hereinafter, preferably 5×10 19 atoms / cm 3 Hereinafter, more preferably 1×10 19 atoms / cm 3 Hereinafter, more preferably 5×10 18 atoms / cm 3 Hereinafter, more preferably 1×10 18 atoms / cm 3 Hereinafter, further preferably 5×10 17 atoms / cm 3 Hereinafter.

[0311] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies may sometimes be formed. When hydrogen enters these oxygen vacancies, electrons may sometimes be generated as carriers. In addition, sometimes electrons are generated as carriers because a part of the hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Thus, it is preferable to minimize hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to be less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0312] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0313] By using an oxide semiconductor with sufficiently reduced impurities for the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0314] [Other semiconductor materials]

[0315] The oxide semiconductor 230 can be replaced with a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above metal oxides. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero-bandgap semiconductor) can also be used. For example, it is preferable to use a single-element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) for the semiconductor material.

[0316] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by a bond weaker than covalent bonds and ionic bonds such as van der Waals forces. The layered material has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0317] Examples of the single-element semiconductor that can be used for the semiconductor material include silicon and germanium. Examples of the silicon that can be used for the semiconductor layer include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As the polycrystalline silicon, for example, low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be mentioned.

[0318] Examples of compound semiconductors that can be used for semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably contains crystals having a cubic crystal structure.

[0319] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0320] As the semiconductor layer, for example, it is preferable to use transition metal chalcogenides used as semiconductors. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. By using the above transition metal chalcogenides for the semiconductor layer, a semiconductor device with a large on-state current can be provided.

[0321] <Examples of the manufacturing method of the semiconductor device>

[0322] Next, use Figures 10A to 19C to illustrate Figures 2A to 2E the manufacturing method of the semiconductor device according to one embodiment of the present invention as shown in etc.

[0323] A in each drawing is a plan view. In addition, B in each drawing is a cross-sectional view of a portion along the dotted line A1 - A2 in A of each drawing. C in each drawing is a cross-sectional view of a portion along the dotted line A3 - A4 in A of each drawing. Note that, for clarity, some constituent elements are omitted in the plan view of A in each drawing.

[0324] Hereinafter, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be appropriately deposited using sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition), ALD, etc.

[0325] In addition, as the sputtering method, there can be mentioned the RF sputtering method using a high-frequency power source as the sputtering power source, the DC sputtering method using a DC power source, and the pulsed DC sputtering method that changes the voltage applied to the electrode in a pulsed manner. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.

[0326] Note that the CVD method can be classified into the plasma CVD (PECVD) method using plasma, the thermal CVD (TCVD: Thermal CVD) method using heat, the photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into the metal CVD (MCVD: Metal CVD) method and the metal organic CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0327] By using the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object to be processed can be reduced. For example, wirings, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device sometimes generate charge accumulation (charge up) due to receiving charges from the plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged due to the accumulated charges. On the other hand, since the above plasma damage does not occur in the case of using the thermal CVD method that does not use plasma, the yield of the semiconductor device can be improved. In addition, since plasma damage during deposition does not occur in the case of using the thermal CVD method, a film with few defects can be obtained.

[0328] In addition, as the ALD method, there can be adopted the thermal ALD method that causes a precursor and a reactant to react only by using heat energy, the PEALD method that uses a reactant excited by plasma, etc.

[0329] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material, etc. are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of openings with a high aspect ratio, etc. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferably used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0330] In addition, when using the CVD method, a film of any composition can be deposited according to the flow rate ratio of the source gases. For example, when using the CVD method, a film with a continuously changing composition can be deposited by changing the flow rate ratio of the source gases while performing the deposition. When performing the deposition while changing the flow rate ratio of the source gases, since there is no need for the time required for transferring or adjusting the pressure, the deposition time can be shortened compared to the case of performing the deposition using multiple deposition chambers. Therefore, sometimes the productivity of the semiconductor device can be improved.

[0331] In addition, when using the ALD method, by introducing various different precursors, a film of any composition can be deposited. For example, when introducing various different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0332] In addition, when introducing various different precursors using the ALD method, the type of oxidant can also be changed according to each precursor. For example, when at least a first precursor and a second precursor are introduced, ozone (O3) can be used as the oxidant for the first precursor, and oxygen (O2) can be used as the oxidant for the second precursor.

[0333] In addition, a heat treatment can also be performed before depositing the film. This heat treatment can also be performed under reduced pressure, and the film can be continuously deposited in a manner that does not expose it to the atmosphere. By performing this treatment, moisture and hydrogen attached to the formation surface of the film can be removed, and the moisture concentration and hydrogen concentration in the structure that is the formation surface can be reduced. The temperature of the heat treatment is preferably 100 °C or higher and 400 °C or lower.

[0334] First, a substrate (not shown) is prepared, and an insulator 122 is formed on the substrate (refer to Figures 10A to 10C ). The deposition of the insulator 122 can be appropriately performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. For example, as the insulator 122, silicon oxide can be deposited using a sputtering method.

[0335] Next, an opening is formed in the insulator 122, and a conductor 120 is formed so as to be embedded in the opening (refer to Figures 10A to 10C ). A conductive film is formed so as to be embedded in the opening, and the conductive film is subjected to chemical mechanical polishing (CMP: Chemical Mechanical Polishing) treatment until the insulator 122 is exposed, whereby the conductor 120 can be formed. When depositing the conductive film, a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be appropriately used. For example, as the conductive film, a laminated film of titanium nitride, tungsten, and titanium nitride can be deposited in sequence using the CVD method.

[0336] Note that the conductor 120 does not have to be formed in a way that embeds the conductor 120. In this case, the transistor 200 shown in Figure 8B can be formed by forming an insulator 280a that covers the conductor 120. Figure 8B The transistor 200 shown.

[0337] Next, insulators 280a to 280c are formed on the insulator 122 and the conductor 120 (see Figures 10A to 10C ). The insulators 280a to 280c can appropriately use the above-mentioned insulating materials. The deposition of the insulators 280a to 280c can be appropriately carried out by using sputtering, CVD, MBE, PLD, ALD, etc. For example, as the insulators 280a and 280c, a silicon nitride film can be deposited by sputtering. In addition, for example, as the insulator 280b, a silicon oxide film can be deposited by sputtering. Note that it is preferable to perform CMP processing on the insulator 280 after deposition to flatten its top surface. By flattening the insulator 280, the conductor 240 used as a wiring can be formed well. Figures 10A to 10C

[0338] In addition, sometimes CMP processing is not required. In this case, the top surface of the insulator 280 has a curved shape that bulges upward. By not performing the flattening process, the manufacturing cost can be reduced and the yield can be increased at the same time.

[0339] Note that the flattening process is not limited to being performed after depositing the insulators 280a to 280c. For example, the flattening process can also be performed after depositing the insulators 280a and 280b, and then the insulator 280c is deposited.

[0340] In addition, by using a sputtering method in which the deposition gas does not need to contain hydrogen molecules in the deposition of the insulators 280a to 280c, the hydrogen concentration in the insulators 280a to 280c can be reduced. By depositing the substrate insulators 280a to 280c in this way, the hydrogen diffusion from the insulators 280a to 280c to the oxide semiconductor 230 can be reduced, thereby reducing the oxygen defects and VoH in the channel formation region.

[0341] Note that the insulator 280 does not have to have a stacked structure. For example, the insulator 280 can also be formed of a single layer of silicon nitride. In this case, the transistor 200 shown in Figure 8E can be formed. Figure 8E The transistor 200 shown.

[0342] Next, a conductive film 240A is deposited on the insulator 280c (see Figures 10A to 10C ). Figures 10A to 10C)。The conductive film 240A can appropriately use the above-mentioned conductive materials. The deposition of the conductive film 240A can be appropriately carried out by means of sputtering method, CVD method, MBE method, PLD method, ALD method, etc. For example, as the conductive film 240A, a laminated film of titanium nitride, tungsten, and titanium nitride can be deposited in sequence by the CVD method. In addition, for example, the conductive film 240A can also adopt a laminated film of an indium tin oxide film added with silicon deposited by the sputtering method and a ruthenium film deposited by the ALD method thereon.

[0343] Next, a part of the conductive film 240A and a part of the insulators 280a to 280c are processed to form an opening 290 reaching the conductor 120 (refer to Figures 11A to 11C ). The formation of the opening 290 can be carried out by photolithography. Note that, in Figure 11A , the shape of the opening 290 when viewed from the plane is circular, but it is not limited thereto. For example, the shape of the opening 290 when viewed from the plane can also be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are arc-shaped.

[0344] Note that, in photolithography, first, the resist is exposed through a mask. Next, the developed solution is used to remove or leave the exposed area to form a resist mask. Next, etching treatment is carried out through this resist mask to process conductors, semiconductors, insulators, etc. into desired shapes. For example, it is sufficient to expose the resist using a KrF excimer laser, an ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. to form a resist mask. In addition, the immersion technique in which exposure is carried out in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after performing dry etching treatment, or performing dry etching treatment after performing wet etching treatment.

[0345] Furthermore, a hard mask made of an insulator or a conductor can also be used under the resist mask. When using the hard mask, an insulating film or a conductive film that becomes the hard mask material can be formed on the insulator 280c, and a resist mask can be formed thereon. Then, the hard mask material is etched to form a hard mask having a desired shape. The etching of the insulator 280c and the like can be performed after removing the resist mask, or can be performed without removing the resist mask. In the latter case, the resist mask sometimes disappears during the etching. In addition, the hard mask can also be removed by etching after forming the opening 290. On the other hand, when the hard mask material does not affect the subsequent processes or can be used in the subsequent processes, it is not necessary to remove the hard mask.

[0346] In addition, an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film can also be deposited between the workpiece or the hard mask and the resist mask. By using the SOC film and the SOG film as masks, the adhesion between the workpiece and the resist mask can be improved, and the durability of the mask pattern can be enhanced. For example, an SOC film, an SOG film, and a resist mask can be sequentially deposited on the workpiece and lithography can be performed.

[0347] As described above, the sidewall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. By adopting such a structure, miniaturization or high integration of the semiconductor device can be achieved. However, not limited to the above structure, the sidewall of the opening 290 can also be conical. By making the sidewall of the opening 290 have a conical shape, the coverage of the oxide semiconductor film and the like that becomes the oxide semiconductor 230, which will be described later, can be improved, and thus defects such as voids can be reduced.

[0348] Here, as Figure 11A and Figure 11B shown, the width D of the opening 290 is preferably greater than the height H of the opening 290, and the width D of the opening 290 is more preferably 2 times or more the height H of the opening 290. The channel width of the transistor 200 depends on the width D of the opening 290, and the channel length of the transistor 200 depends on the height H of the opening 290. That is, by making the width D of the opening 290 long and the height H short, the channel width of the transistor 200 can be made long and the channel length can be made short. Thereby, the on-state current, field-effect mobility, and frequency characteristics of the semiconductor device can be improved. Note that since the height H of the opening 290 is the sum of the thicknesses of the insulators 280a to 280c and the thickness of the conductive film 240A, the thicknesses of the insulators 280a to 280c and the thickness of the conductive film 240A can be set according to the height H of the opening 290.

[0349] Furthermore, the width D of the opening 290 (the maximum diameter when the opening 290 is circular when viewed from the plane) is preferably small. For example, the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less and 1 nm or more or 5 nm or more. Thus, it is preferable to perform microfabrication on the width D of the opening 290 by photolithography using light with a short wavelength such as EUV light or an electron beam.

[0350] The opening 290 is preferably formed by anisotropic etching of a part of the conductive film 240A and a part of the insulators 280a to 280c. In particular, processing using a dry etching method is suitable for microfabrication and is therefore preferable. In addition, this processing can also be performed under different conditions. Here, by adopting a shape in which the height H of the opening 290 is shorter than the width D of the opening 290, the etching distance during anisotropic etching can be shortened, and thus the side wall of the opening 290 can be relatively easily formed into a shape closer to vertical.

[0351] In addition, as described above, by adopting a laminated structure of an indium tin oxide film doped with silicon and a ruthenium film as the conductive film 240A, in the anisotropic etching process, the thin ruthenium film can be used as a hard mask. Thereby, in the anisotropic etching, side etching of the indium tin oxide film doped with silicon can be reduced, and thus the side wall of the opening 290 can be relatively easily formed into a shape closer to vertical.

[0352] Note that depending on the materials of the conductive film 240A and the insulators 280a to 280c and the anisotropic etching conditions, the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may be different from each other.

[0353] In addition, as a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which different multiple high-frequency voltages are applied to one of the parallel plate electrodes can also be adopted. Alternatively, a structure in which high-frequency voltages with the same frequency are applied to each of the parallel plate electrodes can also be adopted. Alternatively, a structure in which high-frequency voltages with different frequencies are applied to each of the parallel plate electrodes can also be adopted. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0354] Note that it is not necessarily required to form the opening 290 in such a manner that the top surface of the conductor 120 is flat. At this time, by forming a concave portion overlapping the opening 290 on the top surface of the conductor 120, the Figure 8A transistor 200 shown can be formed.

[0355] In addition, it is not necessary to form the opening 290 in such a manner that the width D of the opening 290 is longer than the height H of the opening 290. In this case, the Figure 8D transistor 200 shown can be formed by forming the opening 290 in such a manner that the height H of the opening 290 is longer than the width D of the opening 290.

[0356] Next, heat treatment can also be performed. The heat treatment is carried out at 250°C or higher and 650°C or lower, preferably at 300°C or higher and 500°C or lower, more preferably at 320°C or higher and 450°C or lower. In addition, the heat treatment is carried out in an atmosphere of nitrogen gas or inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas can be set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can be carried out in an atmosphere of nitrogen gas or inert gas, and then the heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to fill the escaped oxygen. By performing the above heat treatment, impurities such as water contained in the insulator 280 and the like can be reduced before the deposition of the oxide semiconductor film that will be the oxide semiconductor 230 described later. Note that this heat treatment is preferably carried out under conditions that do not excessively oxidize the conductor 120 and the conductor 240.

[0357] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By carrying out the heat treatment using a highly purified gas, it is possible to prevent as much as possible moisture and the like from being absorbed by the insulator 280 and the like.

[0358] Next, an insulating film 252A that becomes the insulator 252 is deposited in such a manner as to contact at least a part of the bottom and side walls of the contact opening 290 and the top surface of the conductive film 240A. As the insulating film 252A, an insulating material that can be used for the above-described insulator 252 can be appropriately used. The deposition of the insulating film 252A can be appropriately carried out by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the insulating film 252A is preferably formed in such a manner as to contact the side wall of the opening 290. Therefore, it is preferable to use a deposition method with good coverage for the deposition of the insulating film 252A, and it is more preferable to use a CVD method or an ALD method or the like. For example, as the insulating film 252A, silicon nitride can be deposited by the PEALD method.

[0359] Next, an insulating film 254A that becomes the insulator 254 is deposited in contact with the insulating film 252A (see Figures 12A to 12C ). As the insulating film 254A, an insulating material that can be used for the above-described insulator 254 can be appropriately used. The deposition of the insulating film 254A can be appropriately carried out by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the insulating film 254A is preferably formed in such a manner as to contact the concave portion of the insulating film 252A deposited in a shape reflecting the shape of the opening 290. Therefore, it is preferable to use a deposition method with good coverage for the deposition of the insulating film 254A, and it is more preferable to use a CVD method or an ALD method or the like. For example, as the insulating film 254A, hafnium oxide can be deposited by the thermal ALD method.

[0360] In addition, the deposition of the insulating film 252A and the deposition of the insulating film 254A can be continuously carried out under conditions where they are not exposed to the atmosphere. For example, a multi-chamber deposition apparatus can be used to continuously carry out the process without exposure to the atmosphere.

[0361] Next, a part of the insulating film 252A and the insulating film 254A is removed by anisotropic etching, thereby forming the insulator 254 that contacts the insulator 252 contacting the side wall of the opening 290 (see Figures 13A to 13C ). As a result, the insulator 252 is formed in such a manner as to contact the side surfaces of the insulator 280a, the side surfaces of the insulator 280b, the side surfaces of the insulator 280c, the side surface of the conductive film 240A, and the top surface of the conductor 120. In addition, as shown in Figure 13A , when viewed from a plane, the insulator 252 and the insulator 254 are formed in a concentric circle shape, and the conductor 120 is exposed at the center of the opening 290.

[0362] In addition, as shown in Figure 13B and Figure 13CAs shown, a protrusion is formed in a portion of the insulator 252 that contacts the top surface of the conductor 120. The protrusion of the insulator 252 is shaped to protrude more toward the center of the opening 290 than other portions. That is, the insulator 252 has a so-called L shape when viewed from a cross-section in a direction perpendicular to the Z-axis (which can also be said to be a direction perpendicular to the channel length direction).

[0363] The insulator 254 is formed so as to be located inside the insulator 252. As Figure 13B and Figure 13C shown, the bottom surface of the insulator 254 contacts the top surface of the protrusion of the insulator 252, and one side surface of the insulator 254 contacts the side surface of the insulator 252. In addition, the other side surface of the insulator 254 is formed to be aligned with the end portion of the protrusion of the insulator 252. In addition, the insulator 254 does not contact the conductor 120.

[0364] As the anisotropic etching of the insulating film 252A and the insulating film 254A, it is preferable to use a dry etching method. Note that the dry etching method conditions and the dry etching apparatus can be referred to the above description. For example, when silicon nitride is used for the insulating film 252A, the etching process can be performed using an ICP etching apparatus and using CHF3 and O2 as etching gases. In addition, for example, when hafnium oxide is used for the insulating film 254A, the etching process can be performed using an ICP etching apparatus with BCl3 as the etching gas. However, when etching the insulating film 252A, it is preferable to make the etching selectivity of the insulating film 252A with respect to the conductive film 240A and the conductor 120 sufficiently high to ensure that the conductive film 240A and the conductor 120 are not etched.

[0365] In addition, ions generated during the etching of the insulating film 252A and the insulating film 254A sometimes collide with the corner portions at the edges of the openings of the insulator 252 and the insulator 254. As a result, the above corner portions are sometimes polished into a tapered shape. For example, by making the etching gas contain an easily ionizable gas such as argon or applying a bias voltage to the electrode on the substrate side, the above corner portions are easily removed.

[0366] Next, an insulating film 256A that becomes the insulator 256 is formed so as to contact at least a part of the top surface of the conductor 120, the protrusion and the upper end portion of the insulator 252, the side surface and the upper end portion of the insulator 254, and the top surface of the conductive film 240A (refer to Figures 14A to 14C)。The insulating film 256A can appropriately use the insulating materials that can be used for the above-mentioned insulator 256. The deposition of the insulating film 256A can be carried out by using sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Here, the insulating film 256A is preferably formed in contact with the protruding portion of the insulator 252 and the side surface of the insulator 254. Therefore, the deposition of the insulating film 256A is preferably carried out by using a deposition method with good coverage, and more preferably using CVD method or ALD method, etc. For example, as the insulating film 256A, silicon oxide can be deposited by PEALD method.

[0367] Next, it is also possible to perform a microwave treatment in an oxygen-containing atmosphere to reduce the impurity concentration in the insulating film 256A. As impurities, hydrogen and carbon can be particularly mentioned. By performing microwave treatment on the silicon oxide film in an oxygen-containing atmosphere, the hydrogen contained in the insulating film 256A can be released to the outside in the form of H2O. By releasing hydrogen from the insulator 256 located near the oxide semiconductor 230, a semiconductor device with high reliability can be provided.

[0368] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using high frequencies such as microwave or RF and the oxygen plasma can act. When the oxygen plasma acts on the insulating film 256A in this way, the insulating film 256A can contain excess oxygen. By forming an insulator 256 containing excess oxygen in contact with the oxide semiconductor 230, oxygen can be supplied from the insulator 256 to the channel formation region of the oxide semiconductor 230 by performing heat treatment, etc. Therefore, oxygen vacancies and V O H in the channel formation region of the oxide semiconductor 230 can be reduced. Thereby, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved. Note that the oxygen acting on the insulating film 256A can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having unpaired electrons, also known as O radicals). In addition, the oxygen acting on the insulating film 256A can be one or more of the above forms, and oxygen radicals are particularly preferred.

[0369] In addition, when heating the substrate during the above-mentioned microwave treatment in an oxygen-containing atmosphere, the impurity concentration in the insulating film 256A can be further reduced, so it is preferred. The heating of the above-mentioned substrate can be carried out at 100 °C or higher and 650 °C or lower, preferably at 200 °C or higher and 600 °C or lower, and more preferably at 300 °C or higher and 450 °C or lower.

[0370] Next, a part of the insulating film 256A is removed by anisotropic etching, thereby forming an insulator 256 (see Figures 15A to 15C ) in contact with the protruding portion of the insulator 252 and the side surface of the insulator 254. Thereby, as Figure 15AAs shown, when viewed from a plane, the insulators 252, 254, and 256 are formed in concentric circles, and the conductor 120 is exposed at the center of the opening 290.

[0371] Anisotropic etching of the insulating film 256A preferably uses a dry etching method. Note that the dry etching method conditions and the dry etching apparatus can be referred to the above description. For example, when silicon oxide is used for the insulating film 256A, an ICP etching apparatus can be used to perform an etching process using CHF3 and O2 as etching gases. However, when etching the insulating film 256A, it is preferable to make the etching selectivity of the insulating film 256A with respect to the conductive film 240A and the conductor 120 sufficiently high to ensure that the conductive film 240A and the conductor 120 are not etched.

[0372] In addition, ions generated during the etching of the insulating film 256A sometimes collide with the corners at the edges of the opening of the insulator 256. As a result, the above corners are sometimes polished to have a tapered shape. For example, by making the etching gas contain an easily ionizable gas such as argon or applying a bias voltage to the electrode on the substrate side, the above corners are easily removed.

[0373] Next, an oxide semiconductor film that becomes the oxide semiconductor 230 is deposited in contact with at least a part of the top surface of the conductor 120, the side surface and the upper end of the insulator 256, the upper end of the insulator 254, the upper end of the insulator 252, and the top surface of the conductive film 240A. As this oxide semiconductor film, the metal oxides that can be used for the oxide semiconductor 230 described above can be appropriately used. This oxide semiconductor film can be appropriately deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, this oxide semiconductor film is preferably formed in contact with the bottom of the top surface of the conductor 120 and the side surface of the insulator 256. Therefore, the deposition of this oxide semiconductor film preferably uses a deposition method with good coverage, and more preferably uses a CVD method or an ALD method. For example, In-Ga-Zn oxide can be deposited as this oxide semiconductor film by the ALD method. In addition, the deposition method of the metal oxide by the ALD method will be described in detail in the following embodiments.

[0374] Note that the deposition method of the oxide semiconductor film that becomes the oxide semiconductor 230 is not limited to the CVD method or the ALD method. For example, a sputtering method can also be used. In addition, it is preferable to perform microwave treatment on the oxide semiconductor film after depositing it by the sputtering method.

[0375] In addition, as Figure 3As shown, in the case where the oxide semiconductor 230 has a stacked structure, the deposition methods of the respective layers included in the oxide semiconductor 230 may be the same or different. For example, in the case where the oxide semiconductor 230 has a stacked structure of two layers, the lower layer of the oxide semiconductor film ( Figure 3 the oxide semiconductor 230a shown) may be deposited by a sputtering method and the upper layer of the oxide semiconductor film ( Figure 3 the oxide semiconductor 230b shown) may be deposited by an ALD method. The oxide semiconductor film deposited by the sputtering method easily has crystallinity. Thus, by providing the oxide semiconductor film having crystallinity as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. Thus, even if pinholes or disconnections are formed in the lower layer of the oxide semiconductor film deposited by the sputtering method, the upper layer of the oxide semiconductor film deposited by the ALD method having good coverage can block the portions overlapping with the above-mentioned pinholes or disconnections.

[0376] In addition, in the case where the oxide semiconductor 230a is deposited by the sputtering method and the oxide semiconductor 230b is deposited by the ALD method, between the oxide semiconductor 230a and the oxide semiconductor 230b, sometimes the ratio of the thickness of the portion where the top surface of the conductor 240 is the surface to be formed (hereinafter, referred to as the first thickness) to the thickness of the portion where the side surface of the conductor 240 and the side surface of the insulator 280 are the surfaces to be formed (hereinafter, referred to as the second thickness) is different. For example, in the oxide semiconductor 230b, the ratio of the second thickness to the first thickness may be 1 or a value near it. On the other hand, in the oxide semiconductor 230a, the ratio of the second thickness to the first thickness is sometimes less than 1, less than 0.8, or less than 0.5. In particular, there is a tendency that the closer the angle formed by the side surface of the insulator 280 and the top surface of the conductor 120 in the opening 290 is to 90 degrees, the smaller the ratio of the second thickness to the first thickness in the oxide semiconductor 230a.

[0377] In addition, the impurity concentration in the oxide semiconductor 230 may have a concentration gradient. For example, when the oxide semiconductor 230a is deposited by the sputtering method and the oxide semiconductor 230b is deposited by the ALD method, the impurity concentration in the oxide semiconductor 230a may be lower than that in the oxide semiconductor 230b. Therefore, the oxide semiconductor 230 may have a concentration gradient in which its impurities become lower from the side of the conductor 260 toward the side of the conductor 120. Examples of the impurities in the oxide semiconductor 230 include one or more selected from hydrogen, nitrogen, and carbon.

[0378] Here, the oxide semiconductor film that becomes the oxide semiconductor 230 is preferably formed in contact with the top surface of the conductor 120 in the opening 290, the side surface of the insulator 256 in the opening 290, and the top surface of the conductor 240. When forming the oxide semiconductor film in contact with the conductor 120, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200. In addition, when forming the oxide semiconductor film in contact with the conductor 240, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistor 200.

[0379] Next, a heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the above-mentioned oxide semiconductor film does not crystallize, and may be performed at 250 °C or higher and 650 °C or lower, preferably at 400 °C or higher and 600 °C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas may be set to about 20%. In addition, the heat treatment may be performed under a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to replenish the oxygen that has escaped.

[0380] In addition, the gas used in the above heat treatment is preferably purified to a high purity. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a purified gas, it is possible to prevent as much as possible moisture and the like from being absorbed by the above-mentioned oxide semiconductor film and the like.

[0381] Here, the above heat treatment is preferably performed in a state where the insulator 256 containing excess oxygen is provided in contact with the above oxide semiconductor film. By performing the heat treatment in this manner, the insulator 256 supplies oxygen to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and VoH. In addition, since the insulator 254 having the function of capturing or fixing hydrogen is formed in contact with the insulator 256, hydrogen in the oxide semiconductor 230 and the insulator 256 can be captured or fixed by the insulator 254. In addition, since the insulator 254, the insulator 280a, and the insulator 280c that are difficult for hydrogen to permeate are formed so as to surround the insulator 280b, hydrogen diffusion from the insulator 280b and the like to the insulator 254, the insulator 256, and the oxide semiconductor 230 can be reduced. As a result, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. As a result, oxygen vacancies and V in the oxide semiconductor 230 can be reduced. OH, thereby enabling the provision of a semiconductor device having good electrical characteristics and high reliability.

[0382] Note that the heat treatment is performed after depositing the above oxide semiconductor film, but the present invention is not limited thereto. Further, the heat treatment may also be performed in a subsequent process.

[0383] Next, the oxide semiconductor film that becomes the oxide semiconductor 230 is processed by photolithography to form the oxide semiconductor 230 (see Figures 16A to 16C ). Thus, a part of the oxide semiconductor 230 is formed in the opening 290. Here, the oxide semiconductor 230 contacts a part of the side surface and the top surface of the conductor 240. As the processing of the oxide semiconductor 230, a dry etching method or a wet etching method can be used. Processing using the dry etching method is suitable for microfabrication.

[0384] Next, the conductive film 240A is processed to form the conductor 240 (see Figures 17A to 17C ). The formation of the conductor 240 can be performed by photolithography. As the processing of the conductive film 240A, a dry etching method or a wet etching method can be used. Processing using the dry etching method is suitable for microfabrication.

[0385] In the processing of the conductive film 240A, an etching method having a high selectivity with respect to the insulator 280c (an etching method using the insulator 280c as a stop film) is preferably used. For example, it is preferable to increase the etching selectivity between the conductive film 240A and the insulator 280c. Alternatively, it is preferable to provide an insulator having a high etching selectivity with respect to the conductive film 240A between the conductive film 240A and the insulator 280c.

[0386] Next, an insulator 250 is deposited on the oxide semiconductor 230, the conductor 240, and the insulator 280 (see Figures 18A to 18C ). As the insulator 250, the above-mentioned insulating material can be appropriately used. When depositing the insulator 250, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. Here, the insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290. Therefore, when depositing the insulator 250, a deposition method having good coverage is preferably used, and a CVD method or an ALD method, etc. are more preferably used. For example, as the insulator 250, silicon oxide can be deposited using the PEALD method. Note that the deposition of the insulator 250 is not limited to the CVD method or the ALD method. For example, a sputtering method can also be used.

[0387] In addition, as Figure 3As shown, the insulator 250 may have a stacked structure of insulators 250a to 250d. For example, alumina may be deposited as the insulator 250a by thermal ALD. Additionally, for example, silicon oxide may be deposited as the insulator 250b by PEALD. Additionally, for example, hafnium oxide may be deposited as the insulator 250c by thermal ALD. Additionally, for example, silicon nitride may be deposited as the insulator 250d by PEALD.

[0388] By depositing the insulator 250 after forming the oxide semiconductor 230, the side ends of the oxide semiconductor 230 are covered by the insulator 250. Therefore, short - circuiting between the oxide semiconductor 230 and the conductor 260 can be prevented. Furthermore, by adopting the above - mentioned structure, the side ends of the conductor 240 are covered by the insulator 250. Therefore, short - circuiting between the conductor 240 and the conductor 260 can be prevented.

[0389] Additionally, microwave treatment may be performed after depositing the insulator 250. By performing microwave treatment on the insulator 250 in an oxygen - containing atmosphere, hydrogen in the insulator 250 can be released to the outside in the form of H2O. By releasing hydrogen from the silicon oxide film located near the metal oxide, a highly reliable semiconductor device can be provided.

[0390] Additionally, by performing microwave treatment, impurities such as carbon in the oxide semiconductor 230 can also be removed. By removing carbon, which is an impurity in the oxide semiconductor 230, the crystallinity of the oxide semiconductor 230 can be improved. Thus, the oxide semiconductor 230 can be formed into CAAC - OS. In particular, when the oxide semiconductor 230 is deposited by ALD, carbon in the precursor may sometimes be incorporated into the oxide semiconductor 230, so it is preferable to remove carbon by microwave treatment.

[0391] Note that when the insulator 250 has a stacked structure, the above - mentioned microwave treatment is not necessarily performed after depositing all the insulators included in the insulator 250. For example, in Figure 3 the structure shown, microwave treatment may also be performed after depositing the insulators 250a and 250b, and then the insulators 250c and 250d may be deposited. Additionally, for example, microwave treatment may be performed after depositing the insulators 250a and 250b, then microwave treatment may be performed after depositing the insulator 250c, and then the insulator 250d may be deposited. Thus, microwave treatment in an oxygen - containing atmosphere can be performed multiple times.

[0392] Next, a conductive film 260A is deposited in a manner of embedding the recesses of the insulator 250 (refer to Figures 18A to 18C)。As the conductive film 260A, the above-mentioned conductive materials can be appropriately used. When depositing the conductive film 260A, sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be appropriately utilized. Here, the conductive film 260A is preferably formed in contact with the insulator 250 provided in the opening 290. Therefore, when depositing the conductive film 260A, a deposition method with good coverage or embedding property is preferably used, and CVD method or ALD method, etc. are more preferably used. For example, as the conductive film 260A, titanium nitride can be deposited by CVD method or ALD method, and then tungsten can be deposited on the titanium nitride by CVD method.

[0393] In addition, in the above, the conductive film 260A is provided in a manner of being embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the central portion of the conductive film 260A. In addition, the concave portion can also be filled with an inorganic insulating material or the like.

[0394] Next, the conductive film 260A is processed to form a conductor 260 (refer to Figures 19A to 19C ). The formation of the conductor 260 can be carried out by photolithography. As the above processing, dry etching method or wet etching method can be used. Processing by dry etching method is suitable for microfabrication.

[0395] Through the above procedures, a transistor 200 including an insulator 252, an insulator 254, an insulator 256, a conductor 120, a conductor 240, an oxide semiconductor 230, an insulator 250, and a conductor 260 can be formed.

[0396] Next, an insulator 283 is deposited to cover the conductor 260 and the insulator 250. As the insulator 283, the above-mentioned insulating materials can be appropriately used. When depositing the insulator 283, sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be appropriately utilized.

[0397] Through the above procedures, a Figures 2A to 2E such as the transistor 200 shown can be manufactured.

[0398] The manufacturing method of the Figures 2A to 2E transistor 200 shown with reference to FIGS. 10 to 19 has been described above, Figures 4A to 4E The transistor 200 shown can also be manufactured by the same method. The manufacturing method of the Figures 20A to 20F transistor 200 shown will be described below with reference to Figures 4A to 4E .

[0399] First, the manufacturing up to the insulator 280c is carried out by the Figures 10A to 10C method shown. Next, by using the Figures 11A to 11CThe method shown forms openings 290 in insulators 280a to 280c (refer to Figure 20A ). That is, in the transistor 200 shown in Figures 4A to 4E , the openings 290 are formed before depositing the conductive film 240A.

[0400] Next, insulators 252 and 254 are formed using the method shown in Figures 12A to 13C (refer to Figure 20B ). Here, the height of the top surface of insulator 280c is the same as or substantially the same as the height of the upper end portion of insulator 252 and the height of the upper end portion of insulator 254.

[0401] Next, a conductive film 240A is deposited on insulator 280c, insulator 252, insulator 254, and conductor 120 using the method shown in Figures 10A to 10C (refer to Figure 20C ). Here, the openings 290 may also be filled with a filler (e.g., SOC film, etc.) before depositing the conductive film 240A.

[0402] Next, the conductive film 240A is processed by photolithography to form an opening overlapping the opening 290 (refer to Figure 20D ). Here, as shown in Figure 20D , the upper end portion of insulator 252 and the upper end portion of insulator 254 are in contact with the conductive film 240A. The processing of the conductive film 240A can use a dry etching method or a wet etching method. Processing using a dry etching method is suitable for microfabrication. In addition, in the case where the openings 290 are filled with a filler, the filler can be removed after processing the conductive film 240A.

[0403] Note that although the side surface of the conductive film 240A is aligned with the side surface of the insulator 254 in Figure 20D , the present invention is not limited thereto. For example, by making the opening of the conductive film 240A larger than the opening of the insulator 254, the processing margin can be widened. In this case, the transistor 200 shown in Figure 7C can be manufactured.

[0404] Next, an insulating film 256A can be deposited on the conductive film 240A, insulator 280c, insulator 252, insulator 254, and conductor 120 using the method shown in Figures 14A to 14C (refer to Figure 20E ).

[0405] Next, the insulating film 256A is processed using the method shown in Figures 15A to 15C to form an insulator 256 in the opening 290 (refer to Figure 20F ). Here, the side surface of the conductive film 240A is in contact with the insulator 256.

[0406] In addition, an insulator 256 is formed in the opening 290 through the process shown by Figure 20F , and then a conductive film 240A is deposited through the process shown by Figure 20C . Thereby, the transistor 200 shown by Figure 7A can be manufactured.

[0407] Hereinafter, the transistor 200 shown by Figures 16A to 19C can be manufactured by using the method shown by Figures 4A to 4E .

[0408] In addition, the transistor 200 shown by Figures 4A to 4E can also be manufactured by using the same method as that of the transistor 200 shown by Figures 5A to 5E . Hereinafter, with reference to Figures 21A to 21F , the manufacturing method of the transistor 200 shown by Figures 5A to 5E will be described.

[0409] First, the manufacturing up to the position of the insulator 280b is performed by using the method shown by Figures 10A to 10C . Next, an opening 290 is formed in the insulators 280a and 280b by using the method shown by Figures 11A to 11C (refer to Figure 21A ). That is, in the transistor 200 shown by Figures 5A to 5E , the opening 290 is formed before depositing the insulator 280c and the conductive film 240A.

[0410] Next, insulators 252 and 254 are formed by using the method shown by Figures 12A to 13C (refer to Figure 21B ). Here, the height of the top surface of the insulator 280b is the same as or substantially the same as the height of the upper end portion of the insulator 252 and the height of the upper end portion of the insulator 254.

[0411] Next, an insulator 280c is deposited on the insulator 280b, the insulators 252 and 254, and the conductor 120 by using the method shown by Figure 20C (refer to Figure 21C ).

[0412] Next, the insulator 280c is processed by using the method shown by Figure 20D to form an opening overlapping the opening 290 therein (refer to Figure 21D ). Here, as shown by Figure 21D , the upper end portions of the insulator 252 and the insulator 254 are in contact with the insulator 280c.

[0413] Next, by using Figure 20CThe method shown deposits a conductive film 240A on insulators 280b, 280c, 252, 254, and conductor 120. Then, using Figure 20D the method shown, the conductive film 240A is processed to form an opening overlapping the opening 290 (see Figure 21D ).

[0414] In addition, although Figure 21D in the side surface of the conductive film 240A is aligned with the side surface of the insulator 280c and the side surface of the insulator 254, the present invention is not limited thereto. For example, by making the opening of the conductive film 240A larger than the opening of the insulator 280c and making the opening of the insulator 280c larger than the opening of the insulator 254, the processing margin can be widened. In this case, a Figure 7D shown transistor 200 can be manufactured.

[0415] Then, using Figure 20A and Figure 20B the method shown, an insulator 256 is formed in the opening 290 (see Figure 21F ). Here, the side surface of the insulator 280c contacts the insulator 256.

[0416] In addition, by performing the process shown in Figure 21F to form the insulator 256 in the opening 290, and then depositing the conductive film 240A by the process shown in Figure 21C , a Figure 7B shown transistor 200 can be manufactured.

[0417] Hereinafter, a Figures 16A to 19C shown transistor 200 can be manufactured by using the method shown. Figures 5A to 5E shown transistor 200.

[0418] <Structural Example of Storage Device>

[0419] The structure of a storage device using the above transistor 200 will be described with reference to FIG. 22. Figures 22A to 22C are a plan view and a cross-sectional view of a storage device including the transistor 200 and the capacitor 100. Figure 22A is a plan view of this storage device. In addition, Figure 22B and Figure 22C are cross-sectional views of this storage device. Here, Figure 22B is a cross-sectional view of a portion along the dashed line A1 - A2 shown in Figure 22A . In addition, Figure 22C is a cross-sectional view of a portion along the dashed line A3 - A4 shown in Figure 22A . Note that in the plan view of Figure 22A , some components are omitted for clarity.

[0420] Figures 22A to 22C The storage device shown includes: an insulator 140 on a substrate (not shown); a conductor 110 on the insulator 140; a storage cell 150 on the conductor 110; an insulator 180 on the conductor 110; an insulator 122; an insulator 280; and an insulator 283 on the storage cell 150. The insulator 140, the insulator 180, the insulator 280, and the insulator 283 are used as interlayer films. The conductor 110 is used as a wiring.

[0421] The storage cell 150 includes a capacitor 100 on the conductor 110 and a transistor 200 on the capacitor 100.

[0422] The capacitor 100 includes a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130. The conductor 120 is used as one of a pair of electrodes (sometimes referred to as the upper electrode), the conductor 115 is used as the other of the pair of electrodes (sometimes referred to as the lower electrode), and the insulator 130 is used as a dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0423] As Figure 22B and Figure 22C shown, the insulator 180 is provided with an opening 190 reaching the conductor 110. At least a part of the conductor 115 is disposed in the opening 190. Note that the conductor 115 has a region in contact with the top surface of the conductor 110 in the opening 190, a region in contact with the side surface of the insulator 180 in the opening 190, and a region in contact with at least a part of the top surface of the insulator 180. The insulator 130 is disposed such that at least a part of it is located in the opening 190. The conductor 120 is disposed such that at least a part of it is located in the opening 190. Further, as Figure 22B and Figure 22C shown, the conductor 120 is preferably provided so as to be embedded in the opening 190.

[0424] The capacitor 100 has a structure in which the upper electrode and the lower electrode face each other with a dielectric interposed therebetween not only on the bottom surface but also on the side surface in the opening 190, and thus the electrostatic capacitance per unit area can be increased. Accordingly, the deeper the depth of the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of the capacitor 100, the read operation of the storage device can be made stable. In addition, miniaturization or high integration of the storage device can be advanced.

[0425] The side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. At this time, the opening 190 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved.

[0426] A conductor 115 and an insulator 130 are stacked along the side wall of the opening 190 and the top surface layer of the conductor 110. In addition, a conductor 120 is provided on the insulator 130 in a manner of being embedded in the opening 190. The capacitor 100 having such a structure can be referred to as a trench capacitor or a trench-type capacitor.

[0427] An insulator 122 is disposed on the capacitor 100. That is, the insulator 122 is disposed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is disposed under the insulator 122.

[0428] As Figures 22A to 22C shown, the transistor 200 overlaps the capacitor 100. In addition, an opening 290 of a part of the structure provided with the transistor 200 has an overlapping area with the opening 190 of a part of the structure provided with the capacitor 100. In particular, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200 and as the upper electrode of the capacitor 100, so the transistor 200 and the capacitor 100 share a part of the structure. By adopting such a structure, the transistor 200 and the capacitor 100 can be disposed in a manner of not significantly increasing the occupied area when viewed from the plane. As a result, the occupied area of the storage cell 150 can be reduced, so the storage cells 150 can be arranged in a high density to increase the storage capacity of the storage device. In other words, high integration of the storage device can be achieved.

[0429] Figure 22D The circuit diagram of the storage device shown in this embodiment is shown. As Figure 22D shown, Figures 22A to 22C the structure shown is used as the storage cell of the storage device. The storage cell includes a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to the transistor 200, and the capacitor C corresponds to the capacitor 100.

[0430] One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitor C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitor C is connected to the wiring PL.

[0431] Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 260, and the wiring PL corresponds to the conductor 110. As Figures 22A to 22CAs shown, preferably, the conductor 260 extends in the Y direction and the conductor 240 extends in the X direction. By adopting such a structure, the wiring BL and the wiring WL cross each other. In addition, in Figure 22A the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited thereto. For example, the wiring PL may also be parallel to the wiring WL (conductor 260) or the wiring BL (conductor 240).

[0432] The conductor 110 is provided on the insulator 140. The conductor 110 serves as the wiring PL and can be provided in a planar shape, for example. As the conductor 110, a single layer or a stack of conductors described in [Conductor] to be described later can be used. For example, as the conductor 110, a highly conductive material such as tungsten can be used. Thus, by using a highly conductive material, the conductivity of the conductor 110 can be improved, enabling it to fully function as the wiring PL.

[0433] In addition, as the conductor 110, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion, etc., in a single layer or a stack. For example, titanium nitride or indium tin oxide added with silicon can also be used. Or, for example, it may have a structure in which tantalum nitride is laminated on tungsten. Or, for example, it may have a structure in which first titanium nitride, tungsten, and second titanium nitride are laminated in sequence. By adopting such a structure, oxidation of the conductor 110 caused by the insulator 180 can be suppressed when an oxide insulator is used for the insulator 180.

[0434] As the conductor 115, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 115, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion, etc. For example, titanium nitride or tantalum nitride can be used. Or, for example, it may have a structure in which tantalum nitride is laminated on titanium nitride. By adopting such a structure, oxidation of the conductor 115 caused by the insulator 130 can be suppressed when an oxide insulator is used for the insulator 130. In addition, oxidation of the conductor 115 caused by the insulator 180 can be suppressed when an oxide insulator is used as the insulator 180.

[0435] The insulator 130 is provided on the conductor 115. The insulator 130 is provided in contact with the top surface and the side surface of the conductor 115. That is, the insulator 130 preferably covers the side end portion of the conductor 115. Thereby, short - circuit between the conductor 115 and the conductor 120 can be prevented.

[0436] In addition, a structure in which the side end portion of the insulator 130 coincides with the side end portion of the conductor 115 can also be adopted. By adopting such a structure, the insulator 130 and the conductor 115 can be formed using the same mask, thereby simplifying the manufacturing process of the storage device.

[0437] As the insulator 130, it is preferable to use a material with a high relative dielectric constant described in [Insulator] below, that is, a so-called high-k material. By using a high-k material for the insulator 130, the thickness of the insulator 130 can be increased to an extent that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0438] In addition, as the insulator 130, it is preferable to use a laminated structure of insulating layers made of a high-k material, and it is preferable to use a laminated structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the high-k material. For example, as the insulator 130, an insulating film laminated with zirconia, alumina, and zirconia in this order can be used. In addition, for example, an insulating film laminated with zirconia, alumina, zirconia, and alumina in this order can be used. In addition, for example, an insulating film laminated with hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina in this order can be used. By using a laminated structure with an insulator such as alumina having a relatively high dielectric strength, the dielectric strength can be increased and electrostatic breakdown of the capacitor 100 can be suppressed.

[0439] In addition, as the insulator 130, a material that can have ferroelectricity can also be used. Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide can be cited. Here, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be appropriately set. For example, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide can be cited, etc. In addition, the ratio of the number of zirconium atoms to the number of atoms of the element J2 can be appropriately set. For example, the ratio of the number of zirconium atoms to the number of atoms of the element J2 can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X )), strontium barium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics having a perovskite structure can also be used.

[0440] In addition, as a material that may have ferroelectricity, metal nitrides containing element M1, element M2, and nitrogen can be cited. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic ratio of element M1 to element M2 can be appropriately set. In addition, metal oxides containing element M1 and nitrogen sometimes have ferroelectricity even if they do not contain element M2. In addition, as a material that may have ferroelectricity, materials obtained by adding element M3 to the above metal nitrides can be cited. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set.

[0441] In addition, as materials that may have ferroelectricity, perovskite oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-aluminum oxide can be cited.

[0442] Note that in the above description, although examples of metal oxides and metal nitrides are shown, it is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitroxides obtained by adding oxygen to the above metal nitrides can also be used.

[0443] In addition, as materials that may have ferroelectricity, for example, mixtures or compounds composed of multiple materials selected from the above materials can be used. In addition, the insulator 130 can have a stacked structure composed of multiple materials selected from the above materials. Since the above materials and the like may change in crystal structure (characteristics) depending on deposition conditions and various processes, etc., the materials that exhibit ferroelectricity in this specification and the like are not only called ferroelectrics, but also called materials that may have ferroelectricity.

[0444] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when processed into a thin film of several nm, so they are preferred. Here, the thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and further preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). For example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device. In this specification and the like, a material that may have ferroelectricity formed in a layer shape is sometimes called a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification and the like, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes called a ferroelectric device.

[0445] In addition, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even when its area is small, so it is preferable. For example, the ferroelectric layer can have ferroelectricity even when the area (occupied area) when viewed from the plane is 100 μm 2 Hereinafter, 10 μm 2 Hereinafter, 1 μm 2 Hereinafter, or 0.1 μm 2 Hereinafter, it can also have ferroelectricity. In addition, sometimes the ferroelectric layer can have ferroelectricity even when the area (occupied area) when viewed from the plane is 10,000 nm 2 Hereinafter, or 1000 nm 2 Hereinafter. By making the area of the ferroelectric layer small, the occupied area of the capacitor 100 can be reduced.

[0446] A ferroelectric is an insulator that has the property of being polarized internally under the action of an externally applied electric field and maintaining the polarization even when the electric field is 0. Therefore, by using a capacitor that uses this material as a dielectric (hereinafter, sometimes referred to as a ferroelectric capacitor), a non-volatile storage element can be formed. A non-volatile storage element using a ferroelectric capacitor is sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as the capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0447] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen in the crystal contained in the ferroelectric layer is displaced by an external electric field. In addition, it is presumed that the manifestation of ferroelectricity depends on the structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain a crystal. In particular, the insulator 130 preferably contains a crystal having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. In addition, the crystal structure of the crystal contained in the insulator 130 can be any one or more selected from the cubic system, tetragonal system, orthorhombic system, monoclinic system, and hexagonal system. In addition, the insulator 130 can also have an amorphous structure. In this case, the insulator 130 can also have a composite structure of an amorphous structure and a crystal structure.

[0448] The conductor 120 is provided in contact with a part of the top surface of the insulator 130. The conductor 120 is the same as the conductor used in the transistor 200 described above.

[0449] The insulator 180 is used as an interlayer film, so its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulator 180, a single layer or a laminate of insulators containing a material with a low relative dielectric constant described in [Insulator] below can be used. Silicon oxide and silicon oxynitride have thermal stability, so they are preferred. At this time, the insulator 180 contains at least silicon and oxygen.

[0450] Note that although Figure 22B and Figure 22C show the case where the insulator 180 is a single layer, the present invention is not limited thereto. The insulator 180 can also have a laminated structure. When a laminated structure is adopted, it is preferable that one or more of the layers of the insulator 180 use the insulator having a hydrogen barrier property described in [Insulator] above. Thereby, the diffusion of hydrogen from below through the insulator 180 and the conductor 115 into the insulator 130 can be suppressed. Since silicon nitride and silicon oxynitride respectively have the characteristics of less release of impurities (for example, water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, they can be applied to the insulator 180.

[0451] In addition, as Figure 22B and Figure 22C shown, it is preferable to provide an insulator 185 between the conductor 115 and the insulator 180. In addition, the insulator 185 is preferably provided in such a manner as to contact the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115.

[0452] As the insulator 185, it is preferable to use the insulator having a hydrogen barrier property described in [Insulator] above. Thereby, the diffusion of hydrogen from the outside of the capacitor 100 through the insulator 180 into the insulator 130 located in the opening 190 can be suppressed. For example, silicon nitride or silicon oxynitride can be used as the insulator 185. At this time, the insulator 185 contains at least silicon and nitrogen.

[0453] Furthermore, as the insulator 185, it is preferable to use the insulator having the function of capturing or fixing hydrogen described in [Insulator] above. By adopting such a structure, the hydrogen in the insulator 130 can be captured or fixed to reduce the hydrogen concentration in the insulator 130. Magnesium oxide, aluminum oxide, hafnium oxide, etc. can be used as the insulator 185. For example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide can also be used as the insulator 185.

[0454] In addition, use Figure 23A and Figure 23B to illustrate an example of a storage device in which two storage units 150 (hereinafter, referred to as storage unit 150a and storage unit 150b) are connected to the same wiring. Figure 23Ais a plan view of a storage device. Additionally, Figure 23B is a cross-sectional view of a portion along the Figure 23A dashed line A1 - A2 in Figure 23A . For clarity, some constituent elements are omitted in the plan view of

[0455] . Here, Figure 23A and Figure 23B the storage cells 150a and 150b shown have the same structure as the storage cell 150. The storage cell 150a includes a capacitor 100a and a transistor 200a, and the storage cell 150b includes a capacitor 100b and a transistor 200b. Therefore, in the Figure 23A and Figure 23B storage devices shown, the constituent elements having the same functions as the constituent elements of the storage device shown in Fig. 22 are given the same reference numerals.

[0456] As Figure 23A and Figure 23B shown, the conductors 260 used as the wiring WL are respectively provided in the storage cells 150a and 150b. Additionally, the conductor 240 which is part of the wiring BL is commonly provided in the storage cells 150a and 150b. In other words, the conductor 240 is in contact with the oxide semiconductors 230 of the storage cell 150a and the oxide semiconductor 230 of the storage cell 150b.

[0457] Here, Figure 23A and Figure 23B the storage device shown includes conductors 245 and 246 which are electrically connected to the storage cells 150a and 150b and serve as plugs (which can also be referred to as connection electrodes). The conductor 245 is disposed within an opening formed in the insulators 180, 280, and 140 and is in contact with the bottom surface of the conductor 240. Additionally, the conductor 246 is disposed within an opening formed in the insulators 287, 283, and 250 and is in contact with the top surface of the conductor 240. Additionally, as the conductors 245 and 246, a conductive material that can be used for the conductor 240, etc., can be used.

[0458] The insulator 287 is provided on the insulator 283. Since the insulator 287 is used as an interlayer film, its relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 287, a single layer or a laminate of insulators containing a material with a low relative permittivity described in the above [Insulator] can be used.

[0459] In addition, the impurity concentrations of water, hydrogen, etc. in the insulator 287 are preferably reduced. Thereby, it is possible to suppress impurities such as water and hydrogen from mixing into the channel formation region of the oxide semiconductor 230.

[0460] The conductors 245 and 246 are used as electrical connections for circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals and the plugs or wirings of the memory cells 150a and 150b. For example, the following structure can be adopted: the conductor 245 is electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 23, and the conductor 246 is electrically connected to the same memory device (not shown) provided above the memory device shown in FIG. 23. In this case, the conductors 245 and 246 are used as part of the wiring BL. Thus, by providing a memory device or the like above or below the memory device shown in FIG. 23, the storage capacity per unit area can be increased.

[0461] In addition, the memory cells 150a and 150b are line-symmetric with respect to the perpendicular bisector of the dotted line A1 - A2. Therefore, the transistors 200a and 200b are also arranged symmetrically with the conductors 245 and 246 interposed therebetween. Here, the conductor 240 also serves as the other of the source electrode and the drain electrode of the transistor 200a and the other of the source electrode and the drain electrode of the transistor 200b. In addition, the transistors 200a and 200b commonly use the conductors 245 and 246 used as plugs. Thus, by adopting the above structure as the connection relationship between the two transistors and the plugs, a memory device that can achieve miniaturization or high integration can be provided.

[0462] In addition, the conductor 110 used as the wiring PL can be provided separately in the memory cells 150a and 150b, or can be provided commonly in the memory cells 150a and 150b. Note that, as Figure 23B shown, the conductor 110 is provided so as to be separated from the conductor 245 so as not to cause a short circuit between the conductor 110 and the conductor 245.

[0463] In addition, by arranging the memory cells 150 in a matrix and three-dimensional manner, a memory cell array can be formed. As an example of the memory cell array, Figure 24A and Figure 24B show an example of a memory device in which four × two × four memory cells 150 are arranged in the X direction, Y direction, and Z direction. Figure 24A is a plan view of the memory device. In addition, Figure 24B is a cross-sectional view of a portion along the Figure 24A dotted line A1 - A2. In addition, for clarity, some constituent elements are omitted in the Figure 24A plan view.

[0464] Here, Figure 24A and Figure 24B the memory cells 150a to 150d shown have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, the memory cell 150b includes a capacitor 100b and a transistor 200b, the memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes a capacitor 100d and a transistor 200d. Therefore, in Figure 24A and Figure 24B the memory device shown, the same reference numerals are attached to the components having the same functions as the components constituting the memory device shown in FIG. 22.

[0465] Hereinafter, the memory device constituted by the memory cells 150a to 150d will be referred to as a memory cell unit. Figure 24A and Figure 24B the memory device shown includes memory cell units 160[1,1] to 160[2,4]. In addition, hereinafter, the memory cell units 160[1,1] to 160[2,4] may sometimes be collectively referred to as the memory cell unit 160. The memory cell 160[1,2] is provided on the memory cell 160[1,1], the memory cell 160[1,3] is provided on the memory cell 160[1,2], and the memory cell 160[1,4] is provided on the memory cell 160[1,3]. The memory cell 160[2,1] is adjacent to the memory cell 160[1,1] in the Y direction. The memory cell 160[2,2] is provided on the memory cell 160[2,1], the memory cell 160[2,3] is provided on the memory cell 160[2,2], and the memory cell 160[2,4] is provided on the memory cell 160[2,3].

[0466] As Figure 24B shown, in the memory cell unit 160, the memory cell 150c is disposed outside the memory cell 150a with the conductor 245 as the center, and the memory cell 150d is disposed outside the memory cell 150b. In other words, it can also be said that it is a memory device in which the memory cell 150c is provided adjacent to the memory cell 150a and the memory cell 150d is provided adjacent to the memory cell 150b in the memory device shown in FIG. 23.

[0467] As Figure 24A and Figure 24BAs shown, the memory cells 150 adjacent in the Y direction commonly use the conductor 260 serving as the wiring WL. Additionally, the conductor 240 which is a part of the wiring BL is commonly used within the same memory cell. In other words, the conductor 240 contacts the oxide semiconductors 230 in each of the memory cells 150a to 150d.

[0468] The conductor 245 is disposed between the conductors 240 included in the memory cells adjacent in the Z direction. For example, as Figure 24B shown, the conductor 245 is disposed in a manner that contacts the top surface of the conductor 240 in the memory cell 160[1,1] and the bottom surface of the conductor 240 in the memory cell 160[1,2]. Thus, the wiring BL is formed by the conductors 240 and the conductor 245 disposed in each memory cell 160. The conductor 245 is electrically connected to a sense amplifier (not shown) provided under the storage device shown in FIG. 24. Thus, by stacking a plurality of memory cells in the storage device shown in FIG. 24, the storage capacity per unit area can be increased.

[0469] In addition, the memory cells 150a and 150c and the memory cells 150b and 150d are line-symmetric with respect to the perpendicular bisector of the dotted line A1 - A2. Therefore, the transistors 200a and 200c and the transistors 200b and 200d are also symmetrically arranged with the conductor 245 interposed therebetween. Here, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistors 200a to 200d. Additionally, the transistors 200a to 200d commonly use the conductor 245 serving as a plug. Thus, by adopting the above structure as the connection relationship between the four transistors and the plug, a storage device capable of miniaturization or high integration can be provided.

[0470] As Figure 24A and Figure 24B shown, by stacking a plurality of memory cells, the cells can be integrally arranged without increasing the occupied area of the memory cell array. That is to say, a 3D memory cell array can be constituted. Note that Figure 24A and Figure 24B show an example of a structure having a stack of four layers each including two memory cells, but the present invention is not limited thereto. In the storage device, it may include one layer having at least one memory cell 150, or two or more of the above layers may be stacked.

[0471] Figure 24A and Figure 24B show a structure in which the conductor 245 serving as a plug is disposed between the memory cells 150. In other words, Figure 24A and Figure 24BShows a structure in which the conductor 245 serving as a plug is disposed inside the memory cell 160. Note that the present invention is not limited thereto. The conductor 245 may be disposed outside the memory cell.

[0472] As an example of a memory cell array, Figure 25A and Figure 25B Shows an example of a storage device in which three × three × four memory cells 150 are arranged in the X direction, Y direction, and Z direction. Figure 25A Is a plan view of the storage device. In addition, Figure 25B Is along Figure 25A The cross-sectional view of the portion of the dotted line A1 - A2 in. In addition, for clarity, in Figure 25A Some constituent elements are omitted in the plan view.

[0473] Figure 25A and Figure 25B The storage device shown has a structure in which m (m is an integer of 2 or more) layers including the memory cells 150 are stacked. Here, in Figure 25B The above layer provided in the first layer (the bottommost) is denoted as layer 170[1], the above layer provided in the second layer is denoted as layer 170[2], the above layer provided in the (m - 1)th layer is denoted as layer 170[m - 1], and the above layer provided in the mth layer (the topmost) is denoted as layer 170[m]. That is, the storage device according to one aspect of the present invention may also include a plurality of layers including the memory cells 150 and may have a structure in which a plurality of layers are stacked.

[0474] As Figure 25A and Figure 25B Shown, the conductor 245 may also be provided outside the memory cell. In addition, the conductor 245 may be electrically connected to a wiring provided in the upper layer of the layer including the conductor 245. For example, the conductor 245 provided in layer 170[1] is electrically connected to the wiring provided in layer 170[2]. In addition, the wiring provided in layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in layer 170[2]. That is, the wiring may be formed by the same process as the conductor 110.

[0475] Note that although Figure 25A and Figure 25BA structure in which a conductor 245 is electrically connected to a wiring provided in an upper layer of the layer including the conductor 245 is shown, but the present invention is not limited thereto. For example, the conductor 245 may also be electrically connected to a wiring provided in the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] may also be electrically connected to a wiring provided in the layer 170[1]. In addition, the wiring provided in the layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of the storage unit 150 included in the layer 170[1]. That is to say, the wiring may be formed by the same process as the conductor 110.

[0476] In addition, a drive circuit may be provided below the above storage device. For example, Figure 26 A structure in which a layer serving as a drive circuit is provided below the Figure 24B storage device shown is shown. In this way, by adopting a structure in which a drive circuit is provided below the storage device, the area of the storage device and the storage capacity of the storage device can be increased.

[0477] Figure 26 A transistor 310 included in the drive circuit is shown. The transistor 310 is provided on a substrate 311 and includes a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and low-resistance regions 314a and 314b serving as source regions or drain regions. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single-crystalline silicon substrate may be used.

[0478] Here, in the Figure 26 transistor 310 shown, the semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. In addition, the conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. In addition, a material for adjusting the work function may also be used for the conductor 316. Because of the convex portion of the semiconductor substrate, this type of transistor 310 is also called a Fin-type transistor. In addition, an insulator of a mask for forming the convex portion may also be provided in contact with the top of the convex portion. In addition, although a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0479] Note that Figure 26 the structure of the transistor 310 shown is only an example and is not limited to the above structure, and an appropriate transistor may be used according to the circuit structure or the driving method.

[0480] A wiring layer including an interlayer film, wirings, plugs, etc. may also be provided between the storage device and the drive circuit. In addition, the wiring layer may be provided as multiple layers according to the design. Here, in a conductor having the function of a plug or a wiring, the same symbol is sometimes used to represent multiple structures. In addition, in this specification, etc., a wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.

[0481] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film on the transistor 310. In addition, conductors 328, etc. are embedded in the insulator 320 and the insulator 322. In addition, conductors 330, etc. are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0482] In addition, the insulator used as an interlayer film may also be used as a planarization film covering the uneven shape below it. For example, in order to improve the flatness of the top surface of the insulator 322, planarization may also be achieved by CMP processing.

[0483] In addition, although the storage cell 150 in the above storage device includes a capacitor 100 and a transistor 200 on the capacitor 100, the present invention is not limited thereto. For example, as shown in FIG. 27, the storage cell may also be two stacked transistors.

[0484] Figures 27A to 27C are a plan view and a cross-sectional view of a storage device including a transistor 200 and a transistor 400. Figure 27A is a plan view of this storage device. In addition, Figure 27B and Figure 27C are cross-sectional views of this storage device. Here, Figure 27B is a cross-sectional view of a portion along the dash-dot line A1 - A2 shown in Figure 27A . In addition, Figure 27C is a cross-sectional view of a portion along the dash-dot line A3 - A4 shown in Figure 27A . Note that, for the clarity of the figure, Figure 27A some components are omitted in the plan view of

[0485] The storage cell 500 includes a transistor 400 and a transistor 200 on the transistor 400. The structure of the transistor 400 and the structure in its vicinity are the same as the structure of the transistor 200 and the structure in its vicinity described above.

[0486] Therefore, insulator 422 corresponds to insulator 122, conductor 420 corresponds to conductor 120, insulator 480a corresponds to insulator 280a, insulator 480b corresponds to insulator 280b, insulator 480c corresponds to insulator 280c, oxide semiconductor 430 corresponds to oxide semiconductor 230, insulator 450 corresponds to insulator 250, conductor 440 corresponds to conductor 240, insulator 452 corresponds to insulator 252, insulator 454 corresponds to insulator 254, insulator 456 corresponds to insulator 256, and opening 490 corresponds to opening 290. The structure of transistor 400 and the structures in its vicinity can be referred to the structure of transistor 200 and the structures in its vicinity described above.

[0487] In addition, conductor 120 serves as one of the source and drain of transistor 200 and serves as the gate of transistor 400.

[0488] Figure 27D A circuit diagram showing the corresponding memory cell 500 is shown. Figure 27D The shown memory cell includes transistor WTr and transistor RTr. Here, transistor WTr corresponds to transistor WTr0, and transistor RTr corresponds to transistor RTr0.

[0489] As Figure 27D shown, in memory cell 500, the gate of transistor RTr is electrically connected to wiring WWL, one of the source and drain is electrically connected to wiring WBL, and the other of the source and drain is electrically connected to the gate of transistor WTr. One of the source and drain of transistor WTr is electrically connected to wiring RBL, and the other of the source and drain is electrically connected to wiring RWL. Wiring WWL serves as a write word line, wiring WBL serves as a write bit line, wiring RBL serves as a read bit line, and wiring RWL serves as a read word line.

[0490] Here, the gate capacitance of transistor WTr serves as a storage capacitor. That is to say, memory cell 500 can also be called a capacitorless memory cell. Therefore, it can also be said that memory cell 500 is a gain cell type memory cell (2Tr0C) composed of two transistors without including a capacitor. In addition, without being limited to this, a structure including a capacitor and two transistors (2Tr1C) can also be adopted and the capacitor can be electrically connected to the gate of transistor WTr. This capacitor can use the above-mentioned capacitor 100.

[0491] When an OS transistor is used as transistor RTr, by turning off transistor RTr, the charge of the node where one of the source and drain of transistor RTr is electrically connected to the gate of transistor WTr can be maintained for an extremely long time. Therefore, a memory cell or a non-volatile memory cell with an extremely long refresh interval can be realized.

[0492] According to one aspect of the present invention, a novel transistor, a novel semiconductor device, and a novel memory device can be provided. In addition, a memory device capable of miniaturization or high integration can be provided. In addition, a memory device with high reliability can be provided. In addition, a memory device with good frequency characteristics can be provided. In addition, a memory device with a high operating speed can be provided. In addition, a memory device with low power consumption can be provided. In addition, a memory device including a transistor with a large on-state current can be provided. In addition, a memory device with small non-uniformity of transistor characteristics can be provided. In addition, a memory device with good electrical characteristics can be provided.

[0493] The memory cell 150 including the transistor 200 and the capacitor 100 shown in this embodiment can be used as a memory cell of a memory device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Since the off-state current of the transistor 200 is small, the stored content can be retained for a long time by using it in a memory device. In other words, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced. In addition, since the frequency characteristics of the transistor 200 are high, high-speed reading and writing of the memory device can be performed.

[0494] As described above, at least a part of the structure, method, etc. shown in this embodiment can be appropriately combined with other embodiments described in this specification and implemented.

[0495] (Embodiment 2)

[0496] In this embodiment, the metal oxide (hereinafter sometimes referred to as an oxide semiconductor or an oxide) of the semiconductor layer of the transistor that can be used in the memory device shown in the above embodiment and its deposition method will be described with reference to FIGS. 28 to 31.

[0497] In a semiconductor device according to one aspect of the present invention, a metal oxide having a channel formation region is preferably a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked.

[0498] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. For example, an ALD (Atomic Layer Deposition) method can be used as a method for forming the metal oxide.

[0499] The ALD method can deposit atoms layer by layer, thus having effects such as being able to deposit extremely thinly, being able to deposit on structures with a high aspect ratio, being able to deposit in a manner with few defects such as pinholes, being able to deposit with good coverage, and being able to deposit at low temperatures. In addition, the ALD method includes a thermal ALD method using a thermal deposition method and a plasma ALD method using a plasma deposition method. By using plasma, deposition can be carried out at a lower temperature, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine compared to the film formed by other deposition methods. Note that the quantification of these elements can be carried out using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS).

[0500] Different from the deposition method in which particles released from a target or the like are deposited, the ALD method is a deposition method in which a film is formed due to the reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the mold deposited by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for cases where the surface of an opening with a high aspect ratio needs to be covered, etc.

[0501] <Deposition Method of Metal Oxide Using ALD Method>

[0502] Here, a deposition method of a metal oxide using the ALD method, which can be used in one embodiment of the present invention, will be described.

[0503] Here, use Figures 28A to 28E An example of a method for depositing a metal oxide having a three-layer layered crystal structure using the ALD method will be described. First, the precursor 611a is introduced into the chamber, and the precursor 611a is adsorbed onto the surface of the substrate 610 (see Figure 28A . Hereinafter, this step may sometimes be referred to as the first step). Here, as Figure 28A shown, since the precursor 611a is adsorbed onto the surface of the substrate 610, the self-limiting mechanism of the surface chemical reaction comes into play and the precursor 611a no longer adsorbs onto the layer of the precursor 611a on the substrate 610. Note that the appropriate range of the substrate temperature at which the self-limiting mechanism of the surface chemical reaction comes into play is also referred to as the ALD window (ALD Window). The ALD window is determined according to the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and is sometimes set to 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower.

[0504] Next, by introducing an inert gas (such as argon, helium, or nitrogen) into the chamber, the remaining precursor 611a, reaction products, etc. are exhausted from the chamber (hereinafter, this step may sometimes be referred to as the second step). Alternatively, instead of introducing an inert gas into the chamber, the remaining precursor and reaction products, etc. can be exhausted from the chamber by vacuum evacuation. The second step is also referred to as purging.

[0505] Next, a reactant 612a (for example, an oxidizing agent (ozone (O3), oxygen (O2), water (H2O), and their plasmas, radicals, ions, etc.)) is introduced into the chamber to react with the precursor 611a adsorbed on the surface of the substrate 610, and a part of the components in the precursor 611a is detached in a state where the constituent molecules of the precursor 611a are adsorbed on the substrate 610 (refer to Figure 28B . Hereinafter, this step may sometimes be referred to as the third step). Thereby, a layer of the oxide 613a formed by oxidizing a part of the precursor 611a is formed on the surface of the substrate 610.

[0506] Next, by introducing an inert gas or performing vacuum evacuation, the remaining reactant 612a, reaction products, etc. are exhausted from the chamber (hereinafter, this step may sometimes be referred to as the fourth step).

[0507] Next, a precursor 611b containing a metal element different from the precursor 611a is introduced, and the same process as the first step is performed to adsorb the precursor 611b on the surface of the layer of the oxide 613a (refer to Figure 28C ). Here, as Figure 28C shown, since the precursor 611b is adsorbed on the layer of the oxide 613a, the self-stopping mechanism of the surface chemical reaction comes into play and the precursor 611b is no longer adsorbed on the layer of the precursor 611b on the substrate 610.

[0508] Next, similar to the second step, by introducing an inert gas or performing vacuum evacuation, the remaining precursor 611b, reaction products, etc. are exhausted from the chamber.

[0509] Next, similar to the third step, a reactant 612b is introduced into the chamber. Here, the same or different reactant as the reactant 612a can be used as the reactant 612b (refer to Figure 28D ). Thereby, a layer of the oxide 613b formed by oxidizing a part of the precursor 611b is formed on the layer of the oxide 613a.

[0510] Next, similar to the fourth step, by introducing an inert gas or performing vacuum evacuation, the remaining reactant 612b, reaction products, etc. are exhausted from the chamber.

[0511] Also, by performing the first to fourth steps in the same manner, a layer of oxide 613c can be formed on the layer of oxide 613b. Thus, by repeatedly performing the process of forming oxides 613a to 613c, a metal oxide having a laminated crystal structure with repeated laminated structures of oxides 613a to 613c can be formed (refer to Figure 28E ). That is, a layer of oxide can be formed in a set of the first to fourth steps, and by repeatedly performing this set, a laminated crystal structure in which multiple layers of oxides are laminated can be formed.

[0512] In addition, the thickness of the metal oxide having a laminated crystal structure can be 1 nm or more and less than 100 nm, preferably 3 nm or more and less than 20 nm.

[0513] In addition, when forming a metal oxide having a laminated crystal structure, it is preferable to perform the process shown in FIG. 28 while heating the substrate. For example, the substrate temperature may be set to 200°C or more and 600°C or less, preferably 300°C or more and below the decomposition temperature of the precursor. Note that when using multiple different types of precursors and depositing by ALD method, it is preferable to set the substrate temperature below the decomposition temperature of the lowest precursor among the multiple precursors. Thereby, in the deposition using the ALD method, they can be adsorbed onto an object (e.g., a substrate, etc.) in a state where none of the multiple precursors used decompose.

[0514] By performing the above deposition while heating the substrate within the above temperature range, in each of the processes from step 1 to step 4, impurities such as hydrogen or carbon contained in the precursor and reactant, etc. can be removed from the metal oxide. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Also, while removing the above impurities, metal atoms and oxygen atoms are rearranged, so that the layers of each oxide can be arranged in a high order. Thereby, a metal oxide having a laminated crystal structure with high crystallinity can be formed.

[0515] In order to perform the deposition while heating the substrate within the above temperature range, the decomposition temperature of the precursor used for the above deposition is preferably high. For example, the decomposition temperature of the precursor is preferably 200°C or more and 700°C or less, more preferably 300°C or more and 600°C or less. As such a precursor having a high decomposition temperature, a precursor formed of an inorganic substance (hereinafter, referred to as an inorganic precursor) is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed of organic substances (hereinafter, referred to as organic precursors), and sometimes their ALD window is within the above temperature range. In addition, since inorganic precursors do not contain impurities such as hydrogen or carbon, an increase in the impurity concentration of hydrogen or carbon, etc. in the deposited metal oxide can be prevented.

[0516] Also, a heat treatment is preferably performed after the deposition of the above metal oxide. In particular, the heat treatment is preferably continuously performed in a manner not exposed to external air after the deposition by the above ALD method. The heat treatment is performed at 100°C or higher and 1200°C or lower, preferably at 200°C or higher and 1000°C or lower, more preferably at 250°C or higher and 650°C or lower, still more preferably at 300°C or higher and 600°C or lower, further preferably at 400°C or higher and 550°C or lower, and even more preferably at 420°C or higher and 480°C or lower. In addition, the heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to replenish the oxygen that has escaped.

[0517] By performing the heat treatment in this way, impurities such as hydrogen and carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Also, while removing the above impurities, the metal atoms and oxygen atoms are rearranged, so that the crystallinity can be improved. As a result, a metal oxide having a highly crystalline layered crystal structure can be formed.

[0518] In addition, preferably, after the deposition of the above metal oxide, a microwave treatment is performed in an oxygen-containing atmosphere to reduce the impurity concentration in the metal oxide. As impurities, hydrogen and carbon can be particularly mentioned. Note that the above shows an example of the structure in which a microwave treatment is performed on a metal oxide in an oxygen-containing atmosphere, but it is not limited thereto. For example, a microwave treatment may also be performed on an insulating film located near the metal oxide, specifically, a silicon oxide film, in an oxygen-containing atmosphere.

[0519] Note that in FIG. 28, the structure in which the stacked structures of oxides 613a to 613c are repeated is described, but the present invention is not limited thereto. For example, a metal oxide in which a single layer, two layers, or four or more layers of oxides are repeatedly formed may also be used.

[0520] In addition, in the description of this specification and the like, when ozone, oxygen, or water is used as a reactant or an oxidant without special description, they include not only the gas state or molecular state but also the plasma state, radical state, and ionic state. When depositing using an oxidant in the plasma state, radical state, or ionic state, a radical ALD apparatus or a plasma ALD apparatus described later may be used.

[0521] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to make the precursor react sufficiently with an oxidizing agent. For example, setting a longer pulse time for introducing the oxidizing agent suffices. Alternatively, introducing the oxidizing agent multiple times suffices. When introducing the oxidizing agent multiple times, either the same type of oxidizing agent or different types of oxidizing agents can be introduced. For example, it is also possible to perform vacuum evacuation after introducing water as the first oxidizing agent into the chamber, and then introduce ozone or oxygen not containing hydrogen as the second oxidizing agent into the chamber and perform vacuum evacuation.

[0522] Thus, by repeatedly introducing the oxidizing agent and the inert gas (or performing vacuum evacuation) multiple times within a short period in the chamber, it is possible to more surely remove remaining hydrogen atoms, carbon atoms, chlorine atoms, etc. adsorbed on the substrate surface and discharge them outside the chamber. In addition, by introducing two types of oxidizing agents, more remaining hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. Thus, by preventing hydrogen atoms from being introduced into the film during deposition, water, hydrogen, etc. contained in the formed film can be reduced.

[0523] The ALD method is a deposition method in which a precursor and a reactant are made to react using thermal energy. The temperature required for the reaction of the precursor and the reactant is determined according to its temperature characteristics, vapor pressure, decomposition temperature, etc., and is set to be 100°C or higher and 600°C or lower, preferably 200°C or higher and 600°C or lower, more preferably 300°C or higher and 600°C or lower.

[0524] Furthermore, the ALD method in which the above-mentioned reaction of the precursor and the reactant is performed and the reactant excited by plasma is introduced into the chamber as a third source gas for treatment is sometimes referred to as the plasma ALD method. At this time, a plasma generation device is provided at the introduction part of the third source gas. When generating plasma, inductively coupled plasma (ICP) can be used. On the other hand, the ALD method that uses thermal energy to perform the reaction of the precursor and the reactant is sometimes referred to as the thermal ALD method.

[0525] In the plasma ALD method, deposition is carried out by introducing reactants excited by plasma in the third step. Alternatively, deposition is carried out by repeatedly performing the first step to the fourth step while introducing reactants excited by plasma (second reactants). In this case, the reactants introduced in the third step are referred to as the first reactants. In the plasma ALD method, the second reactant for the third source gas can use the same materials as the above-mentioned oxidants. That is to say, ozone, oxygen, and water excited by plasma can be used as the second reactant. In addition, in addition to oxidants, nitriding agents can also be used as the second reactant. Nitrogen (N2) or ammonia (NH3) can be used as the nitriding agent. In addition, a mixed gas of nitrogen (N2) and hydrogen (H2) can be used as the nitriding agent. For example, a mixed gas of 5% nitrogen (N2) and 95% hydrogen (H2) can be used as the nitriding agent. By depositing while introducing nitrogen or ammonia excited by plasma, a nitride film such as a metal nitride film can be formed.

[0526] In addition, as the carrier gas for the second reactant, argon (Ar), helium (He), or nitrogen (N2) can also be used. By using a carrier gas such as argon, helium, or nitrogen, it is easy to discharge plasma to generate the second reactant excited by plasma, so it is preferred. Note that when forming an oxide film such as a metal oxide film by the plasma ALD method and using nitrogen as the carrier gas, sometimes nitrogen is mixed into the film and the desired film quality cannot be obtained. In this case, it is preferred to use argon or helium as the carrier gas.

[0527] By using the ALD method, an extremely thin film can be deposited with a uniform thickness. In addition, it has a high coverage rate for surfaces with unevenness.

[0528] Here, refer to Figures 29A to 29D Describe the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide. In Figure 29B and Figure 29D , atoms are represented by spheres (circles), and the bonds between metal atoms and oxygen atoms are represented by lines. In Figure 29B and Figure 29D , the c-axis direction in the crystal structure of In-M-Zn oxide is represented by the arrow (c-axis) in the drawing. In addition, the a-b plane direction in the crystal structure of In-M-Zn oxide is the direction perpendicular to the c-axis direction represented by the arrow in Figure 29B and Figure 29D .

[0529] Figure 29AFIG. is a view showing an oxide 660 containing In-M-Zn oxide formed on a structure 650. Here, the structure refers to the constituent elements of a semiconductor device such as a transistor. The structure 650 includes a substrate; conductors such as a gate electrode, a source electrode, and a drain electrode; insulators such as a gate insulating film, an interlayer insulating film, and a base insulating film; and semiconductors such as a metal oxide and silicon. Figure 29A FIG. shows a case where the deposition surface of the structure 650 is arranged parallel to the substrate (or base, not shown).

[0530] Figure 29B FIG. is a view showing Figure 29A an enlarged view of the atomic arrangement in the crystal of a region 653 of a part of the oxide 660. Here, Figure 29A and Figure 29B the composition of the oxide 660 shown is In:M:Zn = 1:1:1 [atomic ratio], and the crystal structure is a YbFe2O4-type structure. In addition, the element M is a +3 valence metal element.

[0531] As Figure 29B shown, the crystals included in the oxide 660 are sequentially and repeatedly stacked with a layer 621 containing indium (In) and oxygen, a layer 631 containing the element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen. The layer 621, the layer 631, and the layer 641 are arranged in a manner substantially parallel to the deposition surface of the structure 650. In other words, the a-b plane of the oxide 660 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposition surface of the structure 650.

[0532] As Figure 29B shown, since the layer 621, the layer 631, and the layer 641 included in the above crystals are all composed of one metal element and oxygen, they can be arranged with high crystallinity to improve the carrier mobility of the metal oxide.

[0533] Note that the structure of the In-M-Zn oxide with In:M:Zn = 1:1:1 [atomic ratio] is not limited to Figure 29B the structure shown. The stacking order of the layer 621, the layer 631, and the layer 641 can also be changed. For example, the layer 621, the layer 641, and the layer 631 can be sequentially and repeatedly stacked. Or, the layer 621, the layer 631, the layer 641, the layer 621, the layer 641, and the layer 631 can be sequentially and repeatedly stacked. In addition, a part of the element M in the layer 631 can be replaced with zinc, and a part of the zinc in the layer 641 can be replaced with the element M.

[0534] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] is shown, but the composition formula is In (1+α) M (1-α)O3(ZnO) m (where α is a real number greater than 0 and less than 1, and m is a positive number) The crystalline In-M-Zn oxide can also have a layered crystal structure. As an example, refer to Figure 29C and Figure 29D which shows an In-M-Zn oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio].

[0535] Figure 29C FIG. shows an oxide 662 containing In-M-Zn oxide formed on the structure 650. Figure 29D shows Figure 29C an enlarged view of the atomic arrangement in the crystal of a region 654 of a part of the oxide 662 shown.

[0536] As Figure 29D shown, the crystal included in the oxide 662 has a layer 622 containing indium (In), element M and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 631 containing element M and oxygen. In the oxide 662, as multiple layers, the layer 622, the layer 641, the layer 631, and the layer 641 are repeatedly stacked in sequence. The layer 622, the layer 631, and the layer 641 are arranged substantially parallel to the deposition surface of the structure 650. In other words, the a-b plane of the oxide 662 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is substantially parallel to the normal direction of the deposition surface of the structure 650.

[0537] Note that the structure of the In-M-Zn oxide with In:M:Zn = 1:3:4 [atomic ratio] is not limited to the Figure 29D structure shown, and the structure can also be changed within the range of maintaining In:M:Zn = 1:3:4 [atomic ratio]. For example, the stacking order of the layer 622, the layer 631, and the layer 641 can also be changed. In addition, a part of the element M in the layer 631 can be replaced with zinc, and a part of the zinc in the layer 641 can be replaced with the element M. In addition, the layer 621 or the layer 631 can be formed instead of the layer 622.

[0538] Next, refer to Figures 30A to 31C which shows Figure 29A and Figure 29B the detailed formation method of the oxide 660 containing In-M-Zn oxide shown.

[0539] First, a source gas including a precursor containing indium is introduced into the chamber to adsorb the precursor onto the surface of the structure 650 (refer to Figure 30A) Here, the source gas includes a carrier gas such as argon, helium, or nitrogen in addition to the precursor. As the precursor containing indium, trimethylindium, triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0540] In addition, as the precursor containing indium, an inorganic precursor not containing hydrocarbons can also be used. As the inorganic precursor containing indium, halogen indium compounds such as indium trichloride, indium tribromide, and indium triiodide can be used. The decomposition temperature of indium trichloride is about 500 °C or higher and 700 °C or lower. Therefore, by using indium trichloride, the substrate can be heated to about 400 °C or higher and 600 °C or lower, for example, at 500 °C, while deposition is carried out using the ALD method.

[0541] Next, the introduction of the above source gas is stopped, and the chamber is purged to discharge the remaining precursor and reaction products, etc. from the chamber.

[0542] Next, as a reactant, an oxidant is introduced into the chamber to react the oxidant with the adsorbed precursor, and components other than indium are removed in the state where indium is adsorbed on the substrate, thereby forming a layer 621 in which indium and oxygen are bonded (see Figure 30B ). As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the above oxidant is stopped, and the chamber is purged to discharge the remaining reactant and reaction products, etc. from the chamber.

[0543] Next, a source gas including a precursor containing element M is introduced into the chamber to adsorb the precursor onto the layer 621 (see Figure 30C ). The source gas includes a carrier gas such as argon, helium, or nitrogen in addition to the precursor. When gallium is used as element M, as the precursor containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, dimethylisopropoxygallium, etc. can be used.

[0544] In addition, as the precursor containing gallium, an inorganic precursor not containing hydrocarbons can also be used. As the inorganic precursor containing gallium, halogen gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide can be used. The decomposition temperature of gallium trichloride is about 550 °C or higher and 700 °C or lower. Therefore, by using gallium trichloride, the substrate can be heated to about 450 °C or higher and 650 °C or lower, for example, at 550 °C, while deposition is carried out using the ALD method.

[0545] Next, the introduction of the above source gas is stopped, and the chamber is purged to discharge the remaining precursor and reaction products, etc. from the chamber.

[0546] Next, an oxidizing agent is introduced into the chamber as a reactant, and the oxidizing agent reacts with the adsorbed precursor, causing the components other than element M to be removed while element M is adsorbed to the substrate, thereby forming a layer 631 in which element M and oxygen are bonded (see Figure 30D ). At this time, sometimes a part of the oxygen constituting the layer 641 is adsorbed onto the layer 631. Next, the introduction of the above-mentioned oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0547] Next, a source gas containing a zinc-containing precursor is introduced into the chamber to adsorb the precursor onto the layer 631 (see Figure 31A ). At this time, sometimes a part of the layer 641 in which zinc and oxygen are bonded is formed. The source gas includes a carrier gas such as argon, helium, or nitrogen in addition to the precursor. As the zinc-containing precursor, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc acetate, etc. can be used.

[0548] In addition, as the zinc-containing precursor, an inorganic precursor not containing hydrocarbons can also be used. As the zinc-containing inorganic precursor, zinc halide compounds such as zinc dichloride, zinc dibromide, and zinc diiodide can be used. The decomposition temperature of zinc dichloride is about 450 °C or higher and 700 °C or lower. Therefore, by using zinc dichloride, the substrate can be heated to 350 °C or higher and 550 °C or lower, for example, 450 °C, while deposition is carried out by ALD method.

[0549] Next, the introduction of the above-mentioned source gas is stopped, and the chamber is purged to discharge the remaining precursor and reaction products from the chamber.

[0550] Next, an oxidizing agent is introduced into the chamber as a reactant, and the oxidizing agent reacts with the adsorbed precursor, causing the components other than zinc to be removed while zinc is adsorbed to the substrate, thereby forming a layer 641 in which zinc and oxygen are bonded (see Figure 31B ). Next, the introduction of the above-mentioned oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0551] Next, the layer 621 is formed again on the layer 641 by the above method (see Figure 31C ). By repeating the above method, an oxide 660 can be formed on the substrate or the structure.

[0552] Note that the above-mentioned precursor sometimes contains one or both of carbon and chlorine in addition to the metal element. The film formed using a carbon-containing precursor sometimes contains carbon. In addition, the film formed using a precursor containing a halogen such as chlorine sometimes contains a halogen such as chlorine.

[0553] As described above, by forming the oxide 660 using the ALD method, a metal oxide can be formed in which the c-axis is oriented substantially parallel to the normal direction of the deposition surface. For example, in the oxide semiconductor 230 shown in Figure 2B and Figure 2C , a layered crystal can be formed substantially parallel to the side wall of the opening 290, particularly a layered crystal substantially parallel to the side surface of the insulator 280. By adopting such a structure, the layered crystal of the oxide semiconductor 230 is substantially parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.

[0554] It is preferable to perform the process shown in Figures 30A to 31C while heating the substrate. For example, the substrate temperature can be set to 200 °C or higher and 600 °C or lower, preferably 300 °C or higher and below the decomposition temperature of the precursor.

[0555] In order to perform the deposition while heating the substrate within the above temperature range, the decomposition temperature of the precursor used for the above deposition is preferably high. For example, the decomposition temperature of the precursor is preferably 200 °C or higher and 700 °C or lower, more preferably 300 °C or higher and 600 °C or lower. As such a precursor with a high decomposition temperature, an inorganic precursor is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even when performing the deposition while heating the substrate as described above, the precursor is not easily decomposed.

[0556] As the inorganic precursor, for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used. As described above, the decomposition temperatures of these precursors are around 350 °C or higher and 700 °C or lower, much higher than the decomposition temperatures of general organic precursors. However, as described above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. When using such a plurality of different types of precursors and performing deposition using the ALD method, it is preferable to set the substrate temperature below the lowest decomposition temperature among the decomposition temperatures of the plurality of precursors. In the above example, it is sufficient to set the substrate temperature within the range where zinc dichloride, which has the lowest decomposition temperature among the precursors, does not decompose. Thus, indium trichloride and gallium trichloride can be adsorbed onto the object (e.g., substrate, etc.) in a state where they do not decompose either.

[0557] Note that Figures 30A to 31CAn example is shown where layer 621 is formed as a layer containing indium, layer 631 is formed thereon as a layer containing element M, and layer 641 is formed thereon as a layer containing zinc. However, the present embodiment is not limited thereto. Further, either layer 631 or layer 641 may be formed, layer 621 may be formed thereon, and the other of layer 631 and layer 641 may be formed thereon. Alternatively, either layer 631 or layer 641 may be formed, the other of layer 631 and layer 641 may be formed thereon, and layer 621 may be formed thereon.

[0558] In addition, when forming a metal oxide having an atomic ratio different from In:M:Zn = 1:1:1 [atomic ratio], the above-described layers 621, 631, and 641 may be appropriately formed according to the atomic ratio. For example, by repeatedly forming layer 641 a plurality of times before and after the formation of layer 631 shown Figure 31A a stack of layer 631 and layer 641 having a desired atomic ratio, number of layers, and thickness can be formed between two layers 621.

[0559] (Embodiment 3)

[0560] In the present embodiment, an example of the structure of a storage device using the storage unit described in the above embodiment will be described. An example of the structure of a storage device will be described in the present embodiment, in which a layer including stacked storage units and a layer including a functional circuit capable of amplifying and holding a data potential held in the storage unit and outputting the same are provided.

[0561] [Example of the structure of a storage device]

[0562] Figure 32 FIG. is a block diagram showing an example of the structure of a storage device 300 according to one aspect of the present invention. Figure 32 The storage device 300 shown includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of storage units 10 and a functional layer 50 having a plurality of functional circuits 51.

[0563] Figure 32 An example is shown where the memory array 20 includes a plurality of storage units 10 arranged in a matrix configuration of m rows and n columns (m and n are integers of 2 or more). Further, as an example, a functional circuit 51 is provided for each wiring BL serving as a bit line. Figure 32 An example is shown including a plurality of functional circuits 51 provided corresponding to n wirings BL.

[0564] In Figure 32In this case, the memory cell 10 at the first row and the first column is represented as memory cell 10[1,1], and the memory cell 10 at the m-th row and the n-th column is represented as memory cell 10[m, n]. Additionally, in this embodiment and the like, an arbitrary row may be denoted as "the i-th row". Additionally, an arbitrary column may be denoted as "the j-th column". Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n. Additionally, in this embodiment and the like, the memory cell 10 at the i-th row and the j-th column is represented as memory cell 10[i, j]. Note that in this embodiment and the like, when expressed as "i + α" (α is a positive integer or a negative integer), "i + α" is not less than 1 and not greater than m. Similarly, when expressed as "j + α", "j + α" is not less than 1 and not greater than n.

[0565] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first (the first row) provided wiring WL is represented as wiring WL[1], and the m-th (the m-th row) provided wiring WL is represented as wiring WL[m]. Similarly, the first (the first row) provided wiring PL is represented as wiring PL[1], and the m-th (the m-th row) provided wiring PL is represented as wiring PL[m]. Similarly, the first (the first column) provided wiring BL is represented as wiring BL[1], and the n-th (the n-th column) provided wiring BL is represented as wiring BL[n].

[0566] The multiple memory cells 10 provided in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The multiple memory cells 10 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0567] The memory array 20 may use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, which refers to a memory in which the access transistor is a transistor including an oxide semiconductor in the channel formation region (hereinafter, also referred to as "OS transistor"). The OS transistor has an extremely small leakage current flowing between the source and the drain in the off state. In DOSRAM, by turning off the access transistor (making it in a non-conductive state), the charge according to the data held in the capacitor can be maintained for a long time. Therefore, compared with a DRAM constituted by using a transistor including silicon in the channel formation region (hereinafter, also referred to as "Si transistor"), the frequency of the refresh operation of DOSRAM can be lower. As a result, low power consumption can be achieved.

[0568] In addition, as described in Embodiment 1 and the like, the storage unit 10 can be stacked by stacking the OS transistors. For example, in Figure 32 the shown memory array 20, a plurality of memory arrays 20[1] to memory arrays 20[m] can be stacked. By arranging the memory arrays 20[1] to memory arrays 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided, the memory density of the storage unit 10 can be increased. In addition, the memory array 20 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.

[0569] The wiring BL is used as a bit line for writing and reading data. The wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of the access transistor used as a switch. The wiring PL has a function as a constant potential line connected to the capacitor.

[0570] The storage units 10 included in the memory arrays 20[1] to memory arrays 20[m] are respectively connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided. By arranging the wiring BL extending from the storage units 10 included in the memory arrays 20[1] to memory arrays 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be significantly reduced, the power consumption and signal delay can be reduced. In addition, even if the capacitance of the capacitor included in the storage unit 10 is reduced, the storage device can operate.

[0571] The functional circuit 51 has a function of amplifying the data potential held in the storage unit 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, the minute potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided in the same manner as the wiring BL. By arranging the wiring BL and the wiring GBL extending from the storage units 10 included in the memory arrays 20[1] to memory arrays 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, the power consumption and signal delay can be reduced.

[0572] In addition, the wiring BL is arranged in a manner that it contacts the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is arranged in a manner that it contacts the region of the semiconductor layer of the transistor included in the memory cell 10 that serves as a source or a drain. Alternatively, the wiring BL is arranged in a manner that it contacts a conductor that contacts the region of the semiconductor layer of the transistor included in the memory cell 10 that serves as a source or a drain. That is to say, the wiring BL can be said to be a wiring that electrically connects, in the vertical direction, one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51.

[0573] The memory array 20 can be arranged to overlap the drive circuit 21. By arranging the drive circuit 21 and the memory array 20 to overlap, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and a reduction in power consumption and signal delay can be achieved. In addition, miniaturization of the storage device 300 can be realized.

[0574] By configuring the functional circuit 51 with an OS transistor in the same way as the transistor included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors, etc., in the same way as the memory arrays 20[1] to 20[m], and thus integration can be easily performed. By adopting a structure in which the functional circuit 51 amplifies a signal, the circuits such as the readout amplifier 46 of the subsequent-stage circuit can be miniaturized, and thus miniaturization of the storage device 300 can be realized.

[0575] The drive circuit 21 includes a PSW22 (power switch), a PSW23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 (Control Circuit), and a voltage generation circuit 33.

[0576] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected or discarded as needed. Alternatively, other circuits or other signals can also be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0577] In addition, signal BW, signal CE, and signal GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are signals for power gating control. In addition, signals PON1 and PON2 can also be generated in control circuit 32.

[0578] Control circuit 32 is a logic circuit having a function of controlling the overall operation of storage device 300. For example, control circuit performs logical operations on signals CE, signal GW, and signal BW to determine the operation mode of storage device 300 (e.g., write operation, read operation). Alternatively, control circuit 32 generates control signals for peripheral circuit 41 to execute the above operation mode.

[0579] Voltage generation circuit 33 has a function of generating a negative voltage. Signal WAKE has a function of controlling the input of signal CLK to voltage generation circuit 33. For example, when a signal of H level is applied to signal WAKE, signal CLK is input to voltage generation circuit 33, and voltage generation circuit 33 generates a negative voltage.

[0580] Peripheral circuit 41 is a circuit for writing and reading data to / from memory cell 10. In addition, peripheral circuit 41 is a circuit that outputs various signals for controlling functional circuit 51. Peripheral circuit 41 includes a row decoder 42 (RowDecoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (ColumnDriver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (SenseAmplifier).

[0581] Row decoder 42 and column decoder 44 have a function of decoding signal ADDR. Row decoder 42 is a circuit for specifying the row to be accessed, and column decoder 44 is a circuit for specifying the column to be accessed. Row driver 43 has a function of selecting the wiring WL specified by row decoder 42. Column driver 45 has the following functions: a function of writing data to memory cell 10; a function of reading data from memory cell 10; a function of holding the read data, etc.

[0582] The input circuit 47 has the function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. In addition, the output circuit 48 has the function of outputting Dout to the outside of the storage device 300. The data output from the output circuit 48 is the signal RDA.

[0583] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply potential of the storage device 300 is VDD, and the low power supply potential is GND (ground potential). In addition, VHM is a high power supply potential used to make the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. In Figure 32 the number of power supply domains supplied with VDD in the peripheral circuit 31 is 1, but it can also be multiple. At this time, power switches can be set for each power supply domain.

[0584] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and the functional layer 50, and multiple layers of memory arrays 20 can be overlapped and provided on the driving circuit 21. By overlapping and providing multiple layers of memory arrays 20, the memory density of the memory cell 10 can be increased. Figure 33A is a perspective view of the storage device 300 showing the case where five layers (m = 5) of memory arrays 20[1] to 20[5] and the functional layer 50 are overlapped and provided on the driving circuit 21.

[0585] In Figure 33A the memory array 20 provided in the first layer is denoted as the memory array 20[1], the memory array 20 provided in the second layer is denoted as the memory array 20[2], and the memory array 20 provided in the fifth layer is denoted as the memory array 20[5]. In addition, Figure 33A shows the wiring WL and the wiring PL extending in the X direction and the wiring BL extending in the Z direction (the direction perpendicular to the substrate surface provided with the driving circuit). Note that, in order to make the drawings easier to understand, the description of a part of the wiring WL and the wiring PL included in each of the memory arrays 20 is omitted. Note that, Figure 33A shows the structure in which the wiring PL extends in the X direction, but the present invention is not limited thereto. For example, the wiring PL can extend in the Y direction, or can extend in the X direction and the Y direction. For example, the wiring PL can also be provided in a planar shape.

[0586] Figure 33B is an illustration Figure 33A of a schematic structural example of the functional circuit 51 connected to the wiring BL and the memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. In addition, Figure 33B the wiring GBL provided between the functional circuit 51 and the drive circuit 21 is shown. Additionally, a structure in which one wiring BL is electrically connected to a plurality of memory cells (memory cells 10) is also referred to as a "memory string". Note that in the drawings, for improved visibility, the wiring GBL is sometimes shown as a thick line.

[0587] Figure 33B An example of the circuit structure of the memory cell 10 connected to the wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. Regarding the transistor 11, the capacitor 12, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc.

[0588] In the memory cell 10, one of the source and drain of the transistor 11 is connected to the wiring BL. The other of the source and drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL.

[0589] For example, two memory cells 10 connected to the same wiring BL in the same layer may adopt the structure shown in FIG. 23 according to Embodiment 1.

[0590] Additionally, Figure 33B etc. show the structure in which two memory cells 10 are connected to the same wiring BL in the same layer, but the present invention is not limited thereto. For example, a structure in which 4 memory cells 10 are provided for the wiring BL shared in the same layer, or a structure in which 8 memory cells 10 are provided for the wiring BL shared in the same layer may be adopted.

[0591] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 12.

[0592] Figure 33B The shown wiring GBL is provided in such a manner as to electrically connect the drive circuit 21 and the functional layer 50. Figure 34A A schematic diagram of the storage device 300 with the functional circuit 51 and the memory arrays 20[1] to 20[m] as the repeating unit 70 is shown. Although Figure 34A one wiring GBL is shown in, the wiring GBL can be appropriately provided according to the number of functional circuits 51 in the functional layer 50.

[0593] In addition, the wiring GBL is provided in contact with the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with the region of the semiconductor layer of the transistor included in the functional circuit 51 that serves as a source or a drain. Alternatively, the wiring GBL is provided in contact with a conductor that contacts the region of the semiconductor layer of the transistor included in the functional circuit 51 that serves as a source or a drain. That is to say, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0594] In addition, it is also possible to have a structure in which a repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] is stacked. The storage device 300A according to one embodiment of the present invention is as Figure 34B shown and may include repeating units 70[1] to 70[p] (p is an integer of 2 or more). The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately set according to the number of functional circuits 51.

[0595] In one embodiment of the present invention, while the OS transistor is stacked, the wiring serving as the bit line is arranged in a direction perpendicular to the substrate surface on which the drive circuit 21 is provided. By arranging the wiring serving as the bit line extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the drive circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced.

[0596] In addition, one embodiment of the present invention includes a functional layer 50 in the layer where the memory array 20 is provided, and the functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the storage unit 10 and outputting it. By adopting this structure, when reading data, the minute potential difference of the wiring BL serving as the bit line can be amplified, and the sense amplifier 46 included in the drive circuit 21 can be driven. Since the circuit such as the sense amplifier can be miniaturized, the miniaturization of the storage device 300 can be achieved. In addition, it can operate even if the capacitance of the capacitor 12 included in the storage unit 10 is reduced.

[0597] [Structural examples of the memory array 20 and the functional circuit 51]

[0598] Refer to Figure 35 Description Figures 32 to 3 the structural example of the functional circuit 51 and the structural example of the sense amplifier 46 included in the memory array 20 and the drive circuit 21 described in FIG. 4. Figure 35The driving circuit 21 is shown, which is connected to the wirings GBL (GBL_A, GBL_B), the wirings GBL (GBL_A, GBL_B) are connected to the functional circuits 51 (51_A, 51_B), and the functional circuits 51 (51_A, 51_B) are connected to the memory cells 10 (10_A, 10_B) connected to different wirings BL (BL_A, BL_B). As Figure 35 the shown driving circuit 21, in addition to the sense amplifier 46, a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 are also shown.

[0599] As the functional circuits 51_A and 51_B, transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown. Figure 35 The shown transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are OS transistors in the same manner as the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be laminated and provided in the same manner as the memory arrays 20[1] to 20[m].

[0600] The wirings BL_A and BL_B are connected to the gates of the transistors 52_a and 52_b. The wirings GBL_A and GBL_B are connected to one of the source and drain of the transistors 53_a, 53_b, 54_a, and 54_b. Similar to the wirings BL_A and BL_B, the wirings GBL_A and GBL_B are provided in the vertical direction and are connected to the transistors included in the driving circuit 21. As Figure 35 shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with control signals WE, RE, and MUX.

[0601] Constitute Figure 35 The transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the shown sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B are made of Si tra...

Claims

1. A semiconductor device, comprising: A first conductor; A first insulator; A second conductor on the first insulator; An oxide semiconductor; A second insulator; A third conductor; A third insulator; And A fourth insulator, Wherein, an opening reaching the first conductor is provided in the first insulator and the second conductor, A part of the oxide semiconductor is disposed in the opening and in contact with the top surface of the first conductor, Another part of the oxide semiconductor is disposed above the opening and in contact with at least a part of the top surface of the second conductor, The second insulator is disposed on the oxide semiconductor such that at least a part of it is located in the opening, The third conductor is disposed on the second insulator such that at least a part of it is located in the opening, The third insulator is disposed between the side wall of the opening and the oxide semiconductor in a manner of being located in the opening, The fourth insulator is disposed between the side wall of the opening and the third insulator in a manner of being located in the opening, The third insulator contains a metal oxide, And the fourth insulator contains silicon nitride.

2. The semiconductor device according to claim 1, Wherein the first insulator includes a first layer, a second layer on the first layer, and a third layer on the second layer, Both the first layer and the third layer contain silicon nitride, And the second layer contains silicon oxide.

3. The semiconductor device according to claim 2, wherein a side surface of the second conductor is in contact with the fourth insulator.

4. The semiconductor device according to claim 2, wherein a part of the bottom surface of the second conductor is in contact with the upper end portions of the third insulator and the fourth insulator.

5. The semiconductor device according to claim 2, wherein a part of the bottom surface of the third layer is in contact with the upper end portions of the third insulator and the fourth insulator.

6. The semiconductor device according to any one of claims 1 to 5, wherein when viewed in cross section, the width of the opening is greater than the height of the opening.

7. The semiconductor device according to claim 6, further comprising a fifth insulator containing silicon oxide, Wherein the fifth insulator is disposed between the third insulator and the oxide semiconductor in a manner of being located in the opening.

8. The semiconductor device according to claim 7, Wherein a part of the fourth insulator is disposed below the third insulator, And a part of the fourth insulator is in contact with the lower end portion of the third insulator and the side surface of the fifth insulator.

9. The semiconductor device according to claim 6, wherein the metal oxide contains hafnium.

10. A semiconductor device, comprising: A first conductor; A second conductor; A third conductor; A fourth conductor; An oxide semiconductor; A first insulator; A second insulator; A third insulator; A fourth insulator; And A fifth insulator, Wherein, the second conductor is located on the first insulator, The second insulator is located on the second conductor, The third conductor is located on the second insulator, an opening reaching the first conductor is provided in the first insulator, the second conductor, the second insulator, and the third conductor, a part of the oxide semiconductor is disposed in the opening and in contact with the top surface of the first conductor, another part of the oxide semiconductor is in contact with at least a part of the top surface of the third conductor outside the opening, the third insulator is disposed on the oxide semiconductor such that at least a part thereof is located in the opening, the fourth conductor is disposed on the third insulator such that at least a part thereof is located in the opening, the fourth insulator is disposed between the second conductor and the oxide semiconductor so as to be located in the opening, the fifth insulator is disposed between the second conductor and the fourth insulator so as to be located in the opening, the fourth insulator contains a metal oxide, and the fifth insulator contains silicon nitride.

11. The semiconductor device according to claim 10, wherein both the first insulator and the second insulator contain silicon nitride.

12. The semiconductor device according to claim 10, wherein a side surface of the third conductor is in contact with the fifth insulator.

13. The semiconductor device according to claim 10, wherein a part of the bottom surface of the third conductor is in contact with an upper end portion of the fourth insulator and an upper end portion of the fifth insulator.

14. The semiconductor device according to claim 10, wherein a part of the bottom surface of the second insulator is in contact with an upper end portion of the fourth insulator and an upper end portion of the fifth insulator.

15. The semiconductor device according to any one of claims 10 to 14, wherein when viewed in cross section, a width of the opening is greater than a height of the opening.

16. The semiconductor device according to claim 15, further comprising a sixth insulator containing silicon oxide, the sixth insulator being disposed between the fourth insulator and the oxide semiconductor so as to be located in the opening.

17. The semiconductor device according to claim 16, wherein a part of the fifth insulator is disposed below the fourth insulator, and a part of the fifth insulator is in contact with a lower end portion of the fourth insulator and a side surface of the sixth insulator.

18. The semiconductor device according to claim 15, wherein the metal oxide contains hafnium.

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