Amorphous method of two-dimensional material indium selenide

Abstract

The invention relates to an amorphization method of a two-dimensional material indium selenide. The non-crystallization method comprises the following steps: S1, providing an electrical chip provided with a nano layered indium selenide sample; s2, pulse voltage is applied to the electrical chip, so that the indium selenide is amorphized. The method induces amorphization by applying the pulse voltage, has the advantages of rapidness, accuracy, energy conservation and the like, and is suitable for manufacturing high-performance electronic and photoelectric devices.

Description

Technical Field

[0001] This application belongs to the field of nanoscience and technology, and particularly relates to a method for amorphizing two-dimensional material indium selenide. Background Art

[0002] Two-dimensional materials are a special type of materials with strong covalent bonds within layers and weak van der Waals forces connecting layers. They include graphene, transition metal dichalcogenides (TMDS), two-dimensional oxides, group III-VI layered compounds, etc. Two-dimensional materials have characteristics such as good thermal conductivity, high electron mobility, and adjustable band gaps. Due to their unique electronic, optical, and mechanical properties, they are widely used in fields such as electronic devices, energy storage, and sensors. Indium selenide (In2Se3), as a member of the two-dimensional material family, is a group III-VI layered semiconductor compound that exhibits excellent electronic and structural properties. The polycrystals of indium selenide provide a rare material platform with both ferroelectricity and semiconductivity, and are potential candidate materials for phase change memory applications.

[0003] In two-dimensional materials, there are many interfaces, including crystal-amorphous heterojunction interfaces. The amorphization treatment of indium selenide can change its electronic structure and improve its electrical, optical, and thermal properties, enabling it to have wider applications in electronic devices, optoelectronic devices, and the energy field.

[0004] Currently, the amorphization treatment methods of indium selenide include ion beam irradiation, electron beam irradiation, chemical modification, mechanical treatment, heat treatment, laser treatment, plasma treatment, stress-induced amorphization, amorphization during chemical vapor deposition (CVD) growth, and electro-induced amorphization. Ion beam irradiation equipment has high costs and may introduce impurities or defects. The cooling rate of the rapid cooling method is difficult to precisely control and may lead to partial crystallization. The chemical vapor deposition method has a complex process and high costs. Mechanical treatment may introduce impurities and it is difficult to control the degree of amorphization.

[0005] Therefore, it is necessary to provide a rapid, precise, and energy-saving amorphization method. Summary of the Invention

[0006] To solve the problems in the prior art, this application provides a method for amorphizing two-dimensional material indium selenide. This application induces amorphization by applying a pulsed voltage, which has advantages such as rapidity, precision, and energy saving, and is suitable for the manufacture of high-performance electronic and optoelectronic devices.

[0007] Specifically, this application provides a method for amorphizing two-dimensional material indium selenide, which includes the following steps:

[0008] S1: Provide an electrical chip provided with a nanolayered indium selenide sample;

[0009] S2: Apply a pulsed voltage to the electrical chip to amorphize indium selenide.

[0010] Generally, the amorphization of two-dimensional materials involves rapid cooling of liquid melting, bypassing thermodynamically favorable crystallization. So far, only a few material systems have achieved amorphization through pulsed current, but most of these systems are based on the melt quenching process. In this application, the amorphization of samples, especially chip samples prepared by focused ion beam-electron beam dual-beam electron microscopy, is induced by applying a pulsed voltage, which can avoid the melting step and can achieve solid-state amorphization by electrification, with advantages such as fast speed, high precision, and energy saving, and is suitable for the manufacture of high-performance electronic and optoelectronic devices.

[0011] In some embodiments, the starting voltage of the pulsed voltage is 0.05 - 0.15 V, for example, 0.06 V, 0.07 V, 0.08 V, 0.09 V, 0.1 V, 0.11 V, 0.12 V, 0.13 V, 0.14 V, or any value between them. In some embodiments, the starting voltage of the pulsed voltage is 0.08 - 0.12 V.

[0012] In some embodiments, the pulsed voltage is applied sequentially starting from 0.1 V until the amorphization effect appears.

[0013] In some embodiments, the pulse amplitude of the pulsed voltage is 0.05 - 0.15 V, for example, 0.06 V, 0.07 V, 0.08 V, 0.09 V, 0.1 V, 0.11 V, 0.12 V, 0.13 V, 0.14 V, or any value between them. If the pulse amplitude is too large, it may cause the accumulation of Joule heat and thermal effects, resulting in damage to the material structure and the sample; if the pulse amplitude is too small, the ideal effect may not be achieved within the expected experimental time, and it may also lead to slow or unstable electrical responses.

[0014] In some embodiments, the pulse amplitude of the pulsed voltage is 0.08 - 0.12 V.

[0015] In some embodiments, a pulsed voltage is applied to the nanolayered indium selenide sample on the electrical chip. The pulsed voltage starts from 0.05 - 0.15 V, for example, 0.1 V, and increases by 0.05 - 0.15 V, for example, 0.1 V each time, until the sample is amorphized.

[0016] In some embodiments, when the pulsed voltage increases to 1.5 V - 5 V, for example, 1.7 V, 1.9 V, 2.0 V, 2.1 V, 2.3 V, 2.5 V, 2.7 V, 2.9 V, 3.0 V, 3.1 V, 3.3 V, 3.5 V, 3.7 V, 3.9 V, 4.0 V, 4.1 V, 4.3 V, 4.5 V, 4.7 V, or 4.9 V, the sample is amorphized.

[0017] In some embodiments, an electrical chip is disposed on an in-situ electrothermal rod, and the in-situ electrothermal rod is disposed in a spherical aberration corrected transmission electron microscope. In the spherical aberration corrected transmission electron microscope, after the electrical chip is powered on, a pulsed voltage is applied, and the change of the nanolayered indium selenide sample on the electrical chip is observed.

[0018] In some embodiments, the electrical chip is powered on at a scale of 2 ± 1 μm and a magnification of 1150 ± 500x.

[0019] In some embodiments, on the electrical chip, the aspect ratio of the energized nanolayered indium selenide sample is 0.5:1 - 7.5:1, such as 1:1, 1.5:1, 2:1, 2.3:1, 2.5:1, 2.7:1, 3:1, 3.3:1, 3.5:1, 3.7:1, 3:1, 4.3:1, 4.5:1, 4.7:1, 5:1, 5.5:1, 6:1, 6.5:1, 7:1 or any value therebetween.

[0020] In some embodiments, the aspect ratio of the energized nanolayered indium selenide sample is 1:1 - 5:1. In some embodiments, the aspect ratio of the energized nanolayered indium selenide sample is 2.5:1 - 4.5:1.

[0021] In some embodiments, the nanolayered indium selenide sample is observed by in-situ spherical aberration correction scanning transmission. The sample is a cross-sectional sample, and electron beam irradiation is performed along a direction perpendicular to the cross-section.

[0022] In some embodiments, the electron beam energy of the electron beam irradiation is 300 ± 5 kV.

[0023] In some embodiments, the screen current of the electron beam irradiation is 0.05 - 0.5 nA.

[0024] In some embodiments, the electron beam irradiation is performed by continuous scanning; the scanning mode of the electron beam irradiation is linear scanning; the scanning speed of the electron beam irradiation is 10 - 100 nm / s.

[0025] In some embodiments, in step S1, providing an electrical chip provided with a nanolayered indium selenide sample includes the following steps:

[0026] S11: Depositing and protecting the indium selenide sample by using a focused electron beam - ion beam dual-beam electron microscope to obtain an indium selenide sample with a deposition layer;

[0027] S12: Using the ion beam mode in the focused electron beam - ion beam dual-beam electron microscope to perform cratering and refinement on the indium selenide sample with a protective layer in step S11 to obtain a refined indium selenide sample;

[0028] S13: Place the refined indium selenide sample in step S12 on the electrical chip;

[0029] S14: Use the ion beam mode in the focused electron beam - ion beam dual - beam electron microscope to thin the indium selenide sample on the electrical chip, obtaining an electrical chip with a nano - layered indium selenide sample set thereon.

[0030] In some embodiments, in step S11, the thickness of the deposition layer is 1 - 4 μm, such as 1.3 μm, 1.5 μm, 1.7 μm, 2 μm, 2.3 μm, 2.5 μm, 2.7 μm, 3 μm, 3.3 μm, 3.5 μm, 3.7 μm or any value between them. In some embodiments, the thickness of the deposition layer is 2 - 3 μm.

[0031] In some embodiments, in step S11, the deposition protection includes a first deposition protection with carbon as the deposition material and a second deposition protection with tungsten as the deposition material. There are two reasons for the first deposition protection with carbon. The first is to protect the surface layer from ion beam irradiation, and the second is to co - focus to determine the position; while using tungsten as the second deposition protection is to ensure the integrity of the sample and protect the surface layer.

[0032] In some embodiments, for the first deposition protection using the electron beam mode, the thickness of the deposited carbon layer is 0.1 μm - 0.3 μm, such as 0.13 μm, 0.15 μm, 0.17 μm, 0.2 μm, 0.23 μm, 0.25 μm, 0.27 μm or any value between them. In some embodiments, the thickness of the deposited carbon layer is 0.2 μm.

[0033] In some embodiments, for the second deposition protection using the ion beam mode, the thickness of the deposited tungsten layer is 2 - 3 μm, such as 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm or any value between them.

[0034] In some embodiments, in step S12, after grooving and refining, the length of the indium selenide sample is 3 - 10 μm, such as 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm or any value between them.

[0035] In some embodiments, in step S12, after grooving and refining, the width of the indium selenide sample is 2 - 6 μm, such as 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm or any value between them.

[0036] In some embodiments, in step S12, after trenching and finishing, the width of the indium selenide sample is 0.8 - 1.5 μm, such as 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, or any value therebetween.

[0037] In some embodiments, in step S12, after trenching and finishing, the length of the indium selenide sample is 7 μm, the width is 4 μm, and the thickness is 1 μm.

[0038] In some embodiments, in step S13, the finished indium selenide sample is disposed on the electrical chip by tungsten deposition.

[0039] In some embodiments, in step S14, after thinning treatment, the thickness of the indium selenide sample is less than or equal to 100 nm, such as 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, or 95 nm. In some embodiments, after thinning treatment, the thickness of the indium selenide sample is 60 - 80 nm.

[0040] In some embodiments, after low-voltage cleaning of the electrical chip provided with the nanolayered indium selenide sample in an ion beam mode, it is then disposed on the in-situ heating rod.

[0041] In some embodiments, the voltage of the low-voltage cleaning is 1 - 3 kV, and the beam current is 20 - 30 pA.

[0042] In some embodiments, the layered indium selenide sample is 2Hα-In2Se3.

[0043] In some embodiments, the working voltage of the electron beam mode in the focused electron beam - ion beam dual-beam electron microscope is 2 - 30 kV, and the electron beam current is 1 - 25 cps.

[0044] In some embodiments, the voltage of the ion beam mode in the focused electron beam - ion beam dual-beam electron microscope is 2 - 30 kV, and the current is 5 pA - 20 nA.

[0045] In some embodiments, the ion beam in the focused electron beam - ion beam dual-beam electron microscope is preferably a gallium ion beam.

[0046] Compared with the prior art, the beneficial effects of the present application are as follows:

[0047] 1) The pulsed voltage can provide high energy in an extremely short time (nanosecond or microsecond level), prompting In2Se3 to transform from the crystalline state to the amorphous state, and the speed is far beyond that of the traditional thermal annealing method.

[0048] 2) The pulsed voltage can achieve local amorphization, avoiding thermal effects on other parts of the material, and is suitable for high-density integration and miniaturized devices.

[0049] 3) The action time of the pulsed voltage is short, and the generated heat is limited, reducing the influence of the thermal effect on the material, which is especially suitable for heat-sensitive materials.

[0050] 4) The amorphization process of In2Se3 is reversible, and the crystalline state can be restored through appropriate heat treatment or electrical pulses, facilitating the repeated programming and erasing of the device.

[0051] 5) The pulsed voltage is applied only for a short time, with low energy consumption, and is suitable for low-power application scenarios.

[0052] 6) The amorphization by pulsed voltage does not require complex equipment, has a simple process, and is easy to integrate into the existing manufacturing process. Description of the Drawings

[0053] Figure 1 It is the Raman diagram of the In2Se3 crystal in some embodiments.

[0054] Figure 2 It is the characterization diagram of the In2Se3 crystal in some embodiments, where (a) is the high-resolution diagram of the In2Se3 crystal, (b) is the electron diffraction diagram of the In2Se3 crystal, and (c) is the atomic model diagram of In2Se3.

[0055] Figure 3 It is the preparation flow chart of the nanoscale chip sample in Example 1, where (a) is the deposition diagram of the layered indium selenide sample, (b) is the chip diagram with a bulk indium selenide sample adhered, (c) is the chip sample diagram obtained after thinning the indium selenide sample, (d) is the chip sample after removing the protective layer and the sputtering layer, and (e) is the final sample after power-on.

[0056] Figure 4 It is the equipment required for power-on in some embodiments of the present application, where (a) is the external power supply device; (b) is the thermoelectric rod device; (c) is the electrical chip placed in the thermoelectric rod; (d) is the electrical chip model diagram; (e) is the atomic structure diagram of 2Hα-In2Se3.

[0057] Figure 5 It shows the process of forming a heterojunction interface of the chip sample in Example 1. Among them, (a) is the structure of the chip sample before power-on; (b) is the structure diagram of the chip sample after power-on; (c-d) are the heterojunction interfaces generated after power-on, where (c) is the high-resolution diagram of the 2Hβ-In2Se3 and amorphous heterojunction interface, (d) is the high-resolution diagram of the 2Hα-In2Se3 and amorphous heterojunction interface; (e) is the high-resolution diagram of 2Hβ-In2Se3; (f) is the high-resolution diagram of 2Hα-In2Se3; Figure (g) is the high-resolution diagram of the amorphous; Figure (h) is the electron diffraction diagram of 2Hβ-In2Se3; Figure (i) is the electron diffraction diagram of 2Hα-In2Se3; Figure (j) is the electron diffraction diagram of the amorphous.

[0058] Figure 6 In some embodiments of the present application, the model diagrams of the In2Se3 crystal before and after power-on are shown. The left diagram is the model diagram before power-on, and the right diagram is the model diagram after power-on. It can be seen from the model diagrams that the original crystal structure is damaged after power-on, and a part of the structure becomes amorphous.

[0059] Figure 7 Illustrates the process of forming a heterojunction interface for the chip sample in Example 2.

[0060] Figure 8 Illustrates the process of forming a heterojunction interface for the chip sample in Example 3.

[0061] Figure 9 Illustrates the process of forming a heterojunction interface for the chip sample in Example 4.

[0062] Figure 10 Illustrates the process of forming a heterojunction interface for the chip sample in Example 5.

[0063] Figure 11 Illustrates the process of forming a heterojunction interface for the chip sample in Example 6. Detailed implementation manners

[0064] To make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in combination with embodiments and the accompanying drawings. The specific embodiments described herein are only used to explain the present application and do not constitute any limitation to the present application. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessarily confusing the concepts of the present disclosure. Such structures and technologies are also described in many publications.

[0065] In some embodiments, the present application provides a method for amorphizing a two-dimensional material indium selenide, which includes the following steps, specifically including the following steps:

[0066] (1) Use a focused electron beam-ion beam dual-beam electron microscope to cut, pit, and extract an indium selenide sample, and the obtained indium selenide sample is adhered to the electrodes at both ends of the electrical chip.

[0067] (2) Use a focused electron beam-ion beam dual-beam electron microscope to perform overall thinning on the chip sample to obtain a nanolayered indium selenide sample;

[0068] Optionally, use a focused electron beam-ion beam dual-beam electron microscope to tilt the sample, and a small beam current ion beam can be used to cut off the protective layer and the lower sputtering layer of the nanolayered sample;

[0069] (3) Use a focused electron beam-ion beam dual-beam electron microscope to perform low-voltage cleaning on the prepared chip sample;

[0070] (4) Place the electrical chip containing nanolayered indium selenide into an in-situ thermoelectric sample rod that can be connected to an external power source. Place the in-situ thermoelectric rod into the aberration-corrected transmission electron microscope chamber and observe after the vacuum is pumped.

[0071] (5) Observe using an aberration-corrected transmission electron microscope, reduce the magnification, and observe the overall morphology at low magnification; start to apply electricity to the chip sample, connect the in-situ hot spot rod to an external power source, apply a pulsed voltage starting from 0.1 V, and retain the U-I data corresponding to the applied voltage each time. Increase the pulsed voltage by 0.1 V each time until a significant morphological change can be observed through the transmission electron microscope, then stop applying the pulsed voltage.

[0072] In some embodiments, the nanolayered indium selenide material before power-on is 2Hα-In2Se3, and its Raman diagram is as Figure 1 shown, and its high-resolution diagram, electron diffraction diagram, and atomic model diagram are as Figure 2 shown.

[0073] In some embodiments, before cutting, the present application preferably uses a focused electron beam-ion beam dual-beam electron microscope to deposit and protect the indium selenide sample to form a deposition protection layer.

[0074] In some embodiments, electron beam deposition needs to be carried out first, using C as the deposition material. The voltage for the deposition protection is preferably 5 kV, and the current for the deposition protection is 0.69 nA, depositing about 0.2 μm; then ion beam deposition is carried out, choosing W as the deposition material. The voltage for the deposition protection is preferably 30 kV, and the current for the deposition protection is 0.23 nA, depositing about 2 - 3 μm.

[0075] In some embodiments, the thickness of the protection layer of the indium selenide sample is finally 2 - 4 μm, which is convenient for subsequent thinning.

[0076] In some embodiments, the thickness of the indium selenide sample is preferably 4 - 5 μm. The present application uses a focused electron beam-ion beam dual-beam electron microscope to overall thin the sample. The final thinned thickness is less than 100 nm, about 60 - 100 nm, then the thinning is completed to obtain a nanolayered indium selenide sample.

[0077] In some embodiments, before the overall thinning, the present application preferably uses the mechanical probe of the focused electron beam-ion beam dual-beam electron microscope to transfer the indium selenide sample to the chip electrode, and adhesively bond the sample at both ends of the electrode through W deposition, with the electrical chip serving as the sample carrier.

[0078] In some embodiments, use the ion beam mode in the focused electron beam-ion beam dual-beam electron microscope to perform low-voltage cleaning on the prepared chip sample.

[0079] In some embodiments, the equipment required for powering up the application is as follows Figure 4 As shown, (a) is an external power supply device; (b) is a thermoelectric rod device; (c) is an electrical chip placed in the thermoelectric rod; (d) is a model diagram of the electrical chip; and (e) is a nano-scale layered sample obtained after power is applied.

[0080] In some embodiments, the present application utilizes the STEM mode in a spherical aberration-corrected transmission electron microscope to observe the presence of obvious contrast and morphological changes in samples at low magnification. Figure 6 As shown, after power is turned on, it can be observed that the contrast at both ends of the sample does not change much, while the contrast in the middle changes greatly. By zooming in on the middle position, a clear amorphous structure can be observed.

[0081] The present application is further described below through specific examples.

[0082] Example 1

[0083] Step (1) uses the electron beam mode and ion beam mode of a focused electron beam-ion beam dual beam electron microscope to deposit and protect 2Hα-In2Se3. First, the electron beam mode is used for deposition, the electron beam voltage is 5kV, the beam current is 0.69nA, the deposition material is carbon (C), and the first deposition protection layer is formed, and the thickness of the protective layer is 0.2μm. Then, the ion beam mode is used for deposition, wherein the ion beam voltage is 30kV, the beam current is 0.23nA, and the deposition material is tungsten (W), forming a second deposition protection layer, and the thickness of the protective layer is 2-3μm. Finally, the thickness of the protective layer is about 3μm (such as Figure 3 (as shown in Figure (a)).

[0084] The sample with the protective layer deposited above was pitted and refined using the ion beam mode to obtain a 7 μm × 4 μm × 1 μm bulk indium selenide sample (such as Figure 3 (b) The voltage selected for gouging is 30 kV and the beam current is 5 nA; the voltage selected for fine finishing is 30 kV and the beam current is 2.3 nA.

[0085] Step (2) rotating the sample stage, using the ion beam mode to perform a U-cut on the pitted and finely trimmed bulk iron sample; then using a mechanical probe to transfer the bulk indium selenide sample to the electrical chip, the transfer process is to use W deposition to stick the sample to the electrical chip electrode (such as Figure 3 (as shown in Figure (c)).

[0086] Step (3): Thinning of the sample on the electrode of the academic chip is carried out in ion beam mode. The voltage used is 30 kV, the initial thinning beam current is 430 pA. When the sample is thinned to 500 nm, the beam current is switched to 230 pA, and then it is further thinned to 300 nm, after which it is switched to a small beam current of 80 pA for continuous thinning until it becomes transparent. When the measured sample thickness is less than 100 nm, the thinning is completed (as Figure 3 shown in Figure (d) below). Subsequently, by rotating the sample stage, the protective layer and sputtering layer of the sample are removed by a low beam current. The chip sample is subsequently cleaned at a low voltage using the ion beam mode, with the selected voltage being 2 kV and the beam current being 23 pA.

[0087] Step (4): After 2 minutes of low-voltage cleaning, the sample is taken out of the dual-beam electron microscope chamber, and the electrical chip is carefully picked up with chip tweezers and placed in the thermoelectric rod. It is tightened with small screws to ensure that the chip does not fall off. Then the thermoelectric rod is inserted into the spherical aberration corrected transmission electron microscope and waited for stabilization before subsequent observation.

[0088] The STEM mode in the spherical aberration corrected transmission electron microscope is used to perform low-magnification and high-magnification observations on the nanoscale layered sample. The selected electron beam energy is 300 KV, and the screen current size is 0.100 nA. At low magnification, the overall morphology of the chip sample can be observed. The sample is a uniform crystal sample, and the presented contrast is uniform; when the magnification is increased to 1.8 Mx, at high magnification, the clear two-dimensional material 2Hα-In2Se3 atomic phase can be observed.

[0089] Step (5): An external power supply is connected to the in-situ thermoelectric rod, and the external power supply control software is used to energize the sample. Observation was carried out at a magnification of 1150x using in-situ spherical aberration corrected scanning transmission (CS-STEM); the sample was observed using in-situ spherical aberration corrected scanning transmission (CS-STEM) (as Figure 5 shown in Figure (a) below). This sample is a cross-sectional sample, and the electron beam is irradiated along the direction perpendicular to the cross-section, that is, the

[110] direction.

[0090] In the experiment, the length and width of the area available for energized observation are 4 μm and 1 μm respectively, and the aspect ratio is 4:1. The result of the phase change shown in the STEM image is an obvious contrast change; the sample is observed at a low magnification using in-situ spherical aberration corrected scanning transmission (CS-STEM), and a pulsed voltage is applied for energization. We use the energization software QuickIV to set the voltage, with the set parameter start being 0 V, stop being 0.1 V, and the energization increasing gradually from 0.1 V with an increment of 0.1 V. When the energization reaches about 3 V, it can be found that both the morphology and contrast of the sample change at low magnification (as Figure 5 shown in Figure (b) below), and the changed morphology is subsequently characterized.

[0091] After power-on, the region with insignificant contrast change on the chip sample was observed under magnification, and its structure remained unchanged, still being the 2Hα-In2Se3 atomic phase. Regular diffraction spots could be obtained through diffraction analysis; while when magnifying the intermediate region with more obvious contrast change, the corresponding diffraction pattern became annular, indicating that the intermediate region had changed from a crystal to an amorphous state, achieving the purpose of local amorphization of the material using a pulsed voltage.

[0092] From Figure 5 As can be seen from Fig. (c-j) in the middle, a new phase of β-In2Se3 was introduced during the amorphization process of In2Se3 by applying a pulsed voltage. This is also a characteristic of electro-induced amorphization different from traditional amorphization. After power-on, two different phases of In2Se3 were formed, one is α-In2Se3 and the other is β-In2Se3. Among them, β-In2Se3 is more stable at high temperatures and is suitable for applications in high-temperature environments; and β-In2Se3 has excellent mechanical properties, which can enhance the durability of the device. Introducing the new phase of β-In2Se3 can significantly improve the electrical, optical, and thermal stability of the device, and support multi-state storage and low-power operation, making it suitable for the manufacture of high-performance electronic and optoelectronic devices.

[0093] Example 2

[0094] Steps (1)-(4) are the same as in Example 1.

[0095] Step (5): The only difference from step (5) of Example 1 is that in the experiment, the length and width of the region available for power-on observation are 4.5 μm and 3.5 μm respectively; the aspect ratio is 1.3:1.

[0096] The sample was observed at low magnification using in-situ aberration-corrected scanning transmission (CS-STEM). A pulsed voltage was applied for power-on, and the voltage was set using the power-on software QuickIV. The parameter start was set to 0 V, stop was set to 0.1 V, and the power-on increased gradually from 0.1 V with an increment of 0.1 V. When the power-on reached about 4.6 V, it was found that both the morphology and contrast of the sample changed at low magnification (as shown in Figure 7 ), and the change in the sample morphology was more obvious. Through high-magnification observation, it was found that the regions with insignificant contrast change on both sides of the sample were still α-In2Se3, and the region with obvious contrast change in the middle was β-In2Se3. It was also found during the observation that applying a pulsed voltage could generate an amorphous state (i.e., the part circled by the yellow dotted line in Figure 7 ). And as can be seen from Figure 7 , at this time, the interface between α-In2Se3 and the amorphous state was obtained.

[0097] Compared with Example 1, only the interface between α-In2Se3 and the amorphous state was obtained in Example 2.

[0098] Example 3

[0099] Steps (1)-(4) are the same as those in Example 1.

[0100] Step (5): The only difference from step (5) of Example 1 is that in the experiment, the length and width of the area available for power-on observation are 4 μm and 2 μm respectively; the aspect ratio is 2:1.

[0101] The sample was observed at a magnification of 1150x using in-situ aberration-corrected scanning transmission (CS-STEM). Pulse voltage was applied for power-on. The voltage was set using the power-on software QuickIV, with the parameter start set to 0 V, stop set to 0.1 V, and the power-on increasing gradually from 0.1 V with an increment of 0.1 V. When the power-on reached about 3.3 V, it was found that the morphology and contrast of the sample changed at low magnification (as shown in Figure 8 ). When the power-on increased gradually from 0.1 V to 3.3 V, amorphous could appear. As can be seen from Figure 8 , an α-In2Se3 / amorphous interface was obtained at this time.

[0102] The power-on results of Example 3 and Example 2 are similar, and only an α-In2Se3 / amorphous interface was obtained. However, the morphological change of the sample with an aspect ratio of 2:1 in Example 3 was not damaged after power-on, while in Example 1, the sample was damaged after applying the pulse voltage.

[0103] Example 4

[0104] Steps (1)-(4) are the same as those in Example 1.

[0105] Step (5): The only difference from step (5) of Example 1 is that in the experiment, the length and width of the area available for power-on observation are 5.1 μm and 1.7 μm respectively; the aspect ratio is 3:1.

[0106] The sample was observed at a magnification of 1150x using in-situ aberration-corrected scanning transmission (CS-STEM). Pulse voltage was applied for power-on. The voltage was set using the power-on software QuickIV, with the parameter start set to 0 V, stop set to 0.1 V, and the power-on increasing gradually from 0.1 V with an increment of 0.1 V. When the power-on reached about 1.9 V, it was found that the morphology and contrast of the sample changed at low magnification (as shown in Figure 9 ). At this time, the morphological change of the sample was relatively large. The sample fracture could be observed at low magnification, and the contrast change around the fracture area was relatively obvious. After high-magnification observation, it was found that there was some amorphous at the fracture edge. Looking to both sides, β-In2Se3 was around, and α-In2Se3 was at the two ends of the sample where the contrast did not change. Therefore, as can be seen from Figure 9 , a β-In2Se3 / amorphous interface was obtained at this time.

[0107] The energization results of Example 4 and Examples 2 and 3 are quite obvious in comparison. In Examples 2 and 3, the contrast of the sample changed after applying the pulsed voltage, but the sample did not break, and the α-In2Se3 and amorphous interfaces were obtained on both sides of the sample. However, in Example 4, the sample broke after applying the voltage, and there was amorphous at the fracture surface, so the β-In2Se3 and amorphous interface was obtained.

[0108] Example 5

[0109] Steps (1)-(4) are the same as those in Example 1.

[0110] Step (5): The only difference from step (5) of Example 1 is that the length and width of the energization observation area available in the experiment are 4.1 μm and 1.1 μm respectively; the aspect ratio is 4:1.

[0111] The sample was observed at a magnification of 1150x using in-situ aberration-corrected scanning transmission (CS-STEM), pulsed voltage was applied for energization, and the voltage was set using the energization software QuickIV. The parameter start was set to 0 V, stop was set to 0.1 V, and the energization increased gradually from 0.1 V with an increment of 0.1 V. When the energization reached about 3.2 V, it was found that the morphology and contrast of the sample changed at low magnification (as shown in Figure 10 . When the energization increased gradually from 0.1 V to 3.2 V, the morphology change of the sample was more obvious. At low magnification, it was observed that the sample broke, and the contrast change around the fracture area was more obvious. After high-magnification observation, it was found that there was some amorphous at the fracture edge. Looking at both sides, the surrounding was β-In2Se3, and the α-In2Se3 was at the two ends of the sample where the contrast did not change. Therefore, it can be seen from Figure 10 that the β-In2Se3 and amorphous interface was obtained at this time.

[0112] The energization results of Example 5 and Example 4 are similar, and only the β-In2Se3 and amorphous interface are obtained. After applying the pulsed voltage in Examples 4 and 5, the sample will break, and there will be amorphous at the fracture surface. Therefore, in this case, the β-In2Se3 and amorphous interface will be obtained.

[0113] Example 6

[0114] Steps (1)-(4) are the same as those in Example 1.

[0115] Step (5): The only difference from step (5) of Example 1 is that the length and width of the energization observation area available in the experiment are 5 μm and 1 μm respectively; the aspect ratio is 5:1.

[0116] The sample was observed at a magnification of 1150x using in-situ aberration-corrected scanning transmission electron microscopy (CS-STEM). Pulsed voltage was applied, and the voltage was set using the power-on software QuickIV. The parameter start was set to 0 V, stop was set to 0.1 V, and the power-on voltage gradually increased in increments of 0.1 V. When the voltage was applied up to about 3.5 V, it was found that the morphology and contrast of the sample changed at low magnification (as shown in Figure 11 ). Observation at high magnification revealed that the region with contrast change was β-In2Se3. Next, the pulsed voltage was continuously applied, and when the voltage reached 4.4 V, it was found that the sample broke. It was observed that there was a lot of amorphous material at the fracture surface. Looking at both sides in turn, it was found to be β-In2Se3 and α-In2Se3. Therefore, a β-In2Se3 and amorphous interface was obtained by applying a pulsed voltage to a chip sample with an aspect ratio of 5:1.

[0117] The power-on results of Example 6 were similar to those of Example 5 and Example 4, and only a β-In2Se3 and amorphous interface was obtained. Because the sample was relatively slender at this time, the sample would break after power-on. At this time, there was amorphous material at the fracture surface. Since β-In2Se3 was more resistant to high-temperature environments than α-In2Se3, a β-In2Se3 and amorphous interface was obtained.

[0118] From the comparison of the above examples, it can be seen that the amorphous regions generated by chip samples with different aspect ratios are different after applying pulsed voltage. If the aspect ratio is 2:1 or less than 2:1, an α-In2Se3 and amorphous interface will be obtained after power-on; if the aspect ratio is greater than 2:1, such as 3:1, 4:1, 5:1, the sample will break after applying pulsed voltage, generating a β-In2Se3 and amorphous interface.

[0119] The preferred embodiments of the present application have been described in detail above. However, the present application is not limited thereto. Within the scope of the technical concept of the present application, various simple modifications can be made to the technical solutions of the present application, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed in the present application and fall within the protection scope of the present application.

Claims

1. An amorphization method for two-dimensional indium selenide material, comprising the following steps: S1: Provide an electrical chip provided with a nanolayered indium selenide sample; S2: Apply a pulsed voltage to the electrical chip to amorphize indium selenide.

2. The amorphization method according to claim 1, characterized in that, The starting voltage for applying the pulsed voltage is 0.05 - 0.15 V, preferably 0.08 - 0.12 V, and the pulse amplitude is 0.05 - 0.15 V, preferably 0.08 - 0.12 V.

3. The amorphization method according to claim 1 or 2, characterized in that, Place the electrical chip on an in-situ heating rod, place the in-situ heating rod in a spherical aberration corrected transmission electron microscope. In the spherical aberration corrected transmission electron microscope, after powering on the electrical chip, apply a pulsed voltage and observe the change of the nanolayered indium selenide sample on the sample electrical chip; Preferably, power on the electrical chip at a scale of 2 ± 1 μm and a magnification of 1150 ± 500x.

4. The amorphization method according to claim 3, characterized in that, On the electrical chip, the aspect ratio of the powered nanolayered indium selenide sample is 0.5:1 - 7.5:1, preferably 1:1 - 5:1, more preferably 2.5:1 - 4.5:

1.

5. The amorphization method according to claim 3 or 4, characterized in that, Use in-situ spherical aberration correction scanning transmission to observe the nanolayered indium selenide sample. The sample is a cross-sectional sample, and electron beam irradiation is performed along a direction perpendicular to the cross-section; Preferably, the electron beam energy of the electron beam irradiation is 300 ± 5 kV; Preferably, the screen current of the electron beam irradiation is 0.05 - 0.5 nA.

6. The amorphization method according to any one of claims 1-5, characterized in that, In step S1, providing an electrical chip provided with a nanolayered indium selenide sample includes the following steps: S11: Deposit and protect the indium selenide sample using a focused electron beam - ion beam dual beam electron microscope to obtain a layered indium selenide sample with a deposited layer; S12: Use the ion beam mode in the focused electron beam - ion beam dual beam electron microscope to pit and refine the indium selenide sample with a protective layer in step S11 to obtain a refined indium selenide sample; S13: Place the refined indium selenide sample in step S12 on the electrical chip; S14: Use the ion beam mode in the focused electron beam - ion beam dual beam electron microscope to thin the indium selenide sample on the electrical chip to obtain an electrical chip provided with a nanolayered indium selenide sample.

7. The amorphization method according to claim 6, wherein, In step S11, the thickness of the deposited layer is 1 - 4 μm, preferably 2 - 3 μm; and / or The deposition protection includes a first deposition protection with carbon as the deposition material and a second deposition protection with tungsten as the deposition material, Preferably, the first deposition protection is carried out in the electron beam mode, and the thickness of the deposited carbon layer is 0.1 - 0.3 μm; Preferably, the second deposition protection is carried out in the ion beam mode, and the thickness of the deposited tungsten layer is 2 - 3 μm; and / or In step S12, after pitting and refining, the length of the layered indium selenide sample is 3 - 10 μm, the width is 2 - 6 μm, and the thickness is 0.8 - 1.5 μm; and / or In step S13, the refined layered indium selenide sample is placed on the electrical chip by tungsten deposition; and / or In step S14, after thinning treatment, the thickness of the indium selenide sample is less than or equal to 100 nm, preferably 60 - 80 nm.

8. The amorphization method according to claim 7, wherein After low-voltage cleaning of the electrical chip provided with a nanolayered indium selenide sample using the ion beam mode, then place it on the in-situ heating rod; Preferably, the voltage for low-voltage cleaning is 1 - 3 kV, and the beam current is 20 - 30 pA.

9. The amorphization method according to any one of claims 1-8, characterized in that, The indium selenide sample is 2Hα-In2Se3.

10. The amorphization method according to any one of claims 1-8, characterized in that, In the focused electron beam-ion beam dual-beam electron microscope, the operating voltage of the electron beam mode is 2 - 30 kV, and the electron beam current is 1 - 25 cps; and / or In the focused electron beam-ion beam dual-beam electron microscope, the voltage of the ion beam mode is 2 - 30 kV, and the current is 5 pA - 20 nA.

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