Hybrid quenching circuit for realizing gating quenching and rapid active quenching and working method

Abstract

The invention discloses a mixed quenching circuit for realizing gating quenching and rapid active quenching and a working method, and relates to the technical field of weak light detection, the mixed quenching circuit comprises a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier and a balance denoising network, the in-phase input end of the first high-speed comparator is connected with the anode of an APD, and the in-phase input end of the second high-speed comparator is connected with the cathode of the APD; the inverted input end is connected with the adjustable discriminating level and the anode of the APD, and the inverted output end is connected with the latch enabling inverted input end of the APD; the in-phase output end is connected with the input end of the quenching transistor, and the output end of the quenching transistor is connected with the anode of the APD; the output end of the high-speed operational amplifier is connected with the output end of the quenching transistor; the inverting output end and the latch enabling inverting input end of the first high-speed comparator are connected with the inverting input end of the second high-speed comparator; and the in-phase input end of the second high-speed comparator is connected with an adjustable discriminating level. According to the invention, the working modes of gating and free operation can be compatible, and the minimum circuit complexity and dual-mode detection performance are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of weak light detection, and in particular to a hybrid quenching circuit and a working method for realizing gated quenching and fast active quenching. Background Art

[0002] Single-photon detectors are currently key devices in the fields of quantum information, lidar, and biomedicine. They have extremely high response sensitivity and can achieve the capture and conversion of energy at the single-photon level. Common single-photon detectors mainly include photomultiplier tubes (PMTs), superconducting nanowires (SNSPDs), and semiconductor avalanche photodiode detectors (APDs). APDs are more practical due to their low cooling requirements, fast response speed, small size, and easy coupling between optical fibers and devices.

[0003] The principle of a single-photon detector using an avalanche photodiode (APD) is as follows: A reverse bias voltage is applied to the APD, and this voltage is higher than its breakdown voltage. This operating voltage region is called the "Geiger region", and at this time, the APD operates in the single-photon detection mode, also known as the Geiger mode. The APD operates in the Geiger mode to obtain a sufficiently high gain. When a single photon is detected and incident, an avalanche current will be generated in the APD and spontaneously continue. Being in the avalanche state for a long time will affect the device life and stability of the APD. Therefore, after the avalanche current is detected, it is necessary to immediately reduce its bias voltage below the breakdown voltage by an active or passive method to quench the avalanche current, and the required peripheral circuit is called a quenching circuit. Common quenching circuits are divided into active quenching circuits and passive quenching circuits. The passive quenching circuit uses a relatively large-value resistor connected in series with the APD to quench the avalanche using the voltage drop generated by it; the active quenching circuit actively reduces the voltage difference across the APD through a bias voltage control circuit to achieve quenching.

[0004] Single-photon detectors usually operate in two modes: The first is the free-running mode, that is, the APD can operate in a state where the bias voltage is higher than the breakdown voltage and can detect photons except during the dead time; the second is the gated mode, that is, the bias voltage of the APD is only higher than the breakdown voltage when the gate is open and stops detecting when the gate is closed through an external gating signal. Both the free-running mode and the gated mode need to be combined with a quenching circuit to work properly. However, when the gate width is narrow enough, the gating signal itself can achieve avalanche quenching, and such a circuit is also called a gated quenching circuit.

[0005] The working mode requirements of detectors vary greatly for different practical applications. For systems where the arrival time of photons is predictable, such as quantum communication systems, single-photon detectors usually operate in the gated mode to achieve a high detection signal-to-noise ratio; for systems where the arrival time of photons is random, such as lidar systems, single-photon detectors are usually required to operate in the free-running mode or a mode with a relatively large gate width, but the afterpulse effect is relatively severe. Therefore, a hybrid quenching circuit with gated quenching and fast active quenching capabilities is of great practical significance for single-photon detectors applicable to applications that combine free-running requirements and gated requirements, such as free-space optical communication. Summary of the Invention

[0006] In order to overcome the above problems existing in the prior art, the present invention proposes a hybrid quenching circuit and working method for achieving gated quenching and fast active quenching.

[0007] The technical solution adopted by the present invention to solve its technical problems is: a hybrid quenching circuit for achieving gated quenching and fast active quenching, including an APD, a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier, and a balanced noise cancellation network. The anode of the APD is connected to an adjustable bias voltage source. The non-inverting input terminal of the first high-speed comparator is connected to the anode of the APD through an AC coupling capacitor. The inverting input terminal of the first high-speed comparator is connected to an adjustable discrimination level. The inverting output terminal of the first high-speed comparator is connected to the latch enable inverting input terminal of the first high-speed comparator. The non-inverting output terminal of the first high-speed comparator is connected to the input terminal of the quenching transistor. The output terminal of the quenching transistor is connected to the anode of the APD. The anode of the APD is connected to the inverting input terminal of the first high-speed comparator through a balanced noise cancellation network. The output circuit of the high-speed operational amplifier is connected to the output terminal of the quenching transistor. The inverting output terminal and the latch enable inverting input terminal of the first high-speed comparator are connected to the inverting input terminal of the second high-speed comparator. The non-inverting input terminal of the second high-speed comparator is connected to the adjustable discrimination level.

[0008] For the above hybrid quenching circuit for achieving gated quenching and fast active quenching, a T-network is provided between the non-inverting output terminal of the first high-speed comparator and the input terminal of the quenching transistor. The T-network includes a second resistor, a third resistor, and a third capacitor. The third capacitor is used to accelerate the conduction of the quenching transistor.

[0009] For the above hybrid quenching circuit for achieving gated quenching and fast active quenching, the balanced noise cancellation network includes a first resistor, a first capacitor, and a second capacitor.

[0010] For the above hybrid quenching circuit for achieving gated quenching and fast active quenching, an AC coupling capacitor is provided between the anode of the APD and the non-inverting input terminal of the first high-speed comparator.

[0011] In the hybrid quenching circuit for realizing gated quenching and fast active quenching, the high-speed operational amplifier is controlled by an FPGA, and the FPGA has a built-in serializer / deserializer to generate a gating signal, which is amplified and outputted by a common-mode amplifier circuit composed of a high-speed operational amplifier U3.

[0012] The invention discloses a working method of a hybrid quenching circuit for realizing gated quenching and fast active quenching. Based on the above hybrid quenching circuit for realizing gated quenching and fast active quenching, in free running or wide gated mode, when there is no avalanche signal, the reset lock signal is in a high impedance state, the first high-speed comparator is in a normal comparison state, and the quenching transistor is in an off state; when the APD detects a photon, the avalanche pulse generated is higher than the identification level of the inverting input terminal of the first high-speed comparator, the avalanche is identified, and the output level of the first high-speed comparator is inverted; the in-phase output terminal of the first high-speed comparator is inverted, driving the quenching transistor The output is reversed, the APD cathode voltage is reduced, and the avalanche is quenched; at the same time, the inverting output of the first high-speed comparator latches the quenching state through the latch enable inverting input; after the avalanche is quenched, the high-speed operational amplifier controlled by the FPGA cuts off the bias of the quenching transistor to achieve the lowest power consumption; at the same time, the reset lock signal is pulled low, and the latch state of the first high-speed comparator is released through the latch enable non-inverting input, restoring its comparison function; after the set dead time, or when the gate open signal arrives, the FPGA controls the high-speed operational amplifier to restore the quenching transistor bias, and the APD resumes work; In the narrow gating mode, the reset lock signal remains normally low, so that the first high-speed comparator cannot enter the latched state; at the same time, the reset lock signal is pulled low through the T-type network so that the base potential of the quenching transistor is always low, and the quenching transistor cannot be turned on. After the first high-speed comparator identifies the avalanche, it no longer has a quenching effect. The quenching and recovery of the APD are only completed by the narrow gating signal itself; at the same time, the inverting output end of the first high-speed comparator is normally output to the inverting input end of the second high-speed comparator, and is input into the FPGA after being buffered by the second high-speed comparator, so that the avalanches can be counted normally.

[0013] The beneficial effect of the present invention is that the hybrid quenching circuit for the gated / free-running dual-mode single-photon detector of the present invention flexibly utilizes the latch enable function of the comparator, controls the logic of the reset lock signal through the FPGA, and adds a T-type network in the feedback loop formed between the comparator in-phase output and the latch enable in-phase input terminal, so that the hybrid quenching circuit can be compatible with the gated and free-running working modes, while avoiding the influence of the quenching and recovery of the quenching transistor on the high-speed operation of the narrow gated signal. Compared with the prior art, the minimum circuit complexity and good dual-mode detection performance are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1This is the circuit structure block diagram of the hybrid quenching circuit of the present invention. Detailed implementation mode

[0015] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific implementation modes.

[0016] As Figure 1 shown, this embodiment discloses a hybrid quenching circuit for a single-photon detector compatible with gated and free-running dual modes, which can achieve gated quenching and fast active quenching. Specifically, it includes APD D1, the first high-speed comparator U1, the second high-speed comparator U2, the quenching transistor Q1, the high-speed operational amplifier U3, and the C-RC balanced noise cancellation network, where the C-RC balanced noise cancellation network includes the first resistor R1, the first capacitor C1, and the second capacitor C2.

[0017] The anode of APD D1 is connected to the adjustable bias voltage source through the resistor R d ; the anode of APD D1 is connected to the non-inverting input terminal of the first high-speed comparator U1 through the AC coupling capacitor C C ; the inverting input terminal of the first high-speed comparator U1 is connected to the adjustable discrimination level through the resistor R N ; the inverting output terminal of the first high-speed comparator U1 is connected to the latch enable inverting input terminal of the first high-speed comparator U1; the non-inverting output terminal of the first high-speed comparator U1 is connected to the input terminal of the quenching transistor Q1 through a T-network, and the T-network is composed of the second resistor R2, the third resistor R3, and the third capacitor C3; the output terminal of the quenching transistor Q1 is connected to the anode of the APD; the anode of the APD is connected to the inverting input terminal of the first high-speed comparator U1 through the balanced noise cancellation network; The FPGA built-in serializer / deserializer (Serializer-Deserializer, SerDes) generates a gating signal, which is amplified by the non-inverting amplifier circuit composed of the high-speed operational amplifier U3 and then output, and the output circuit of the high-speed operational amplifier U3 is connected to the output terminal of the quenching transistor Q1; The inverting output terminal and the latch enable inverting input terminal of the first high-speed comparator U1 are connected to the inverting input terminal of the second high-speed comparator U2; the non-inverting input terminal of the second high-speed comparator U2 is connected to the adjustable discrimination level; the second high-speed comparator U2 is used to realize the conversion of single-ended to differential level signals with higher sensitivity.

[0018] Based on the above hybrid quenching circuit, this embodiment also discloses a working method of the hybrid quenching circuit, which specifically includes: when the single-photon detector operates in the free-running or wide-gated mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, and the first high-speed comparator U1 is in a normal comparison state. At this time, the quenching transistor Q1 is in the off state.

[0019] When a photon is detected, the avalanche pulse generated by APD D1 is higher than the discrimination level at the inverting input terminal of the first high-speed comparator U1, and the avalanche is discriminated. The output level of the first high-speed comparator U1 is inverted, the non-inverting output terminal of the first high-speed comparator U1 is inverted, driving the output of the quenching transistor Q1 to invert. The third capacitor C3 is used to accelerate the conduction of the quenching transistor, the cathode voltage of the APD decreases, and the avalanche is quenched. After the avalanche is quenched, it enters the quenching state holding time, and the inverting output terminal of the first high-speed comparator U1 latches this quenching state through the latch enable inverting input terminal. After the avalanche is quenched, the high-speed operational amplifier U3 controlled by the FPGA cuts off the bias of the quenching transistor Q1 to achieve the lowest power consumption; at the same time, the reset lock signal is pulled low, and the latch state of the first high-speed comparator U1 is released through the latch enable non-inverting input terminal, restoring its comparison function. After the set dead time has passed, or when the gate control "on" signal arrives, the FPGA controls the high-speed operational amplifier U3 to restore the bias of the quenching transistor Q1, and at this time the APD resumes operation.

[0020] In the narrow gate control mode, the reset lock signal remains constantly low, making it impossible for the first high-speed comparator U1 to enter the latch state; at the same time, the reset lock signal being pulled low makes the base potential of the quenching transistor Q1 always low through the T-network, and the quenching transistor Q1 cannot conduct. After the first high-speed comparator U1 discriminates the avalanche, it no longer has a quenching effect, and the quenching and recovery of the APD are only completed by the narrow gate control signal itself. At the same time, the inverting output terminal of the first high-speed comparator U1 is normally output to the inverting input terminal of the second high-speed comparator U2. After being buffered by the second high-speed comparator U2 and input to the FPGA, the avalanche can be normally counted.

[0021] The above embodiments are only exemplary embodiments of the present invention and are not used to limit the present invention. Those skilled in the art can make various modifications or equivalent replacements to the present invention within the essence and protection scope of the present invention, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of the present invention.

Claims

1. A hybrid quenching circuit that implements gated quenching and fast active quenching, characterized in that It includes an APD, a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier, and a balanced noise cancellation network. The anode of the APD is connected to an adjustable bias voltage source. The non-inverting input terminal of the first high-speed comparator is connected to the anode of the APD. The inverting input terminal of the first high-speed comparator is connected to an adjustable discrimination level. The inverting output terminal of the first high-speed comparator is connected to the latch enable inverting input terminal of the first high-speed comparator. The non-inverting output terminal of the first high-speed comparator is connected to the input terminal of the quenching transistor. The output terminal of the quenching transistor is connected to the anode of the APD. The anode of the APD is connected to the inverting input terminal of the first high-speed comparator through the balanced noise cancellation network. The output circuit of the high-speed operational amplifier is connected to the output terminal of the quenching transistor. The inverting output terminal and the latch enable inverting input terminal of the first high-speed comparator are connected to the inverting input terminal of the second high-speed comparator. The non-inverting input terminal of the second high-speed comparator is connected to the adjustable discrimination level.

2. The hybrid quenching circuit for implementing gated quenching and fast active quenching according to claim 1, wherein A T-network is provided between the non-inverting output terminal of the first high-speed comparator and the input terminal of the quenching transistor. The T-network includes a second resistor, a third resistor, and a third capacitor. The third capacitor is used to accelerate the conduction of the quenching transistor.

3. The hybrid quenching circuit for implementing gated quenching and fast active quenching according to claim 1, wherein The balanced noise cancellation network includes a first resistor, a first capacitor, and a second capacitor.

4. The hybrid quenching circuit for implementing gated quenching and fast active quenching according to claim 1, wherein An AC coupling capacitor is provided between the anode of the APD and the non-inverting input terminal of the first high-speed comparator.

5. The hybrid quenching circuit for implementing gated quenching and fast active quenching according to claim 1, wherein The high-speed operational amplifier is controlled by an FPGA. The FPGA internally has a serializer / deserializer to generate a gating signal, which is amplified and output after passing through a non-inverting amplification circuit composed of the high-speed operational amplifier U3.

6. A working method of a hybrid quenching circuit that implements gated quenching and fast active quenching, characterized in that, Based on the hybrid quenching circuit for gated quenching and fast active quenching according to any one of claims 1-5, in the free-running or wide-gated mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, the first high-speed comparator is in a normal comparison state, and the quenching transistor is in an off state. When the APD detects a photon and the generated avalanche pulse is higher than the discrimination level of the inverting input terminal of the first high-speed comparator, the avalanche is discriminated, and the output level of the first high-speed comparator is inverted. The non-inverting output terminal of the first high-speed comparator is inverted, driving the output of the quenching transistor to invert, reducing the voltage of the cathode of the APD, and quenching the avalanche. At the same time, the inverting output terminal of the first high-speed comparator latches this quenching state through the latch enable inverting input terminal. After the avalanche is quenched, the high-speed operational amplifier controlled by the FPGA cuts off the bias of the quenching transistor to achieve the lowest power consumption. At the same time, the reset lock signal is pulled low, and the latch state of the first high-speed comparator is released through the latch enable non-inverting input terminal to restore its comparison function. After the set dead time has passed, or when the gated on signal arrives, the FPGA controls the high-speed operational amplifier to restore the bias of the quenching transistor, and at this time the APD resumes operation. In the narrow gate mode, the reset lock signal remains constantly low, preventing the first high-speed comparator from entering the latch state. At the same time, the reset lock signal being pulled low makes the base potential of the quenching transistor always low through the T-network, preventing the quenching transistor from conducting. After the first high-speed comparator detects an avalanche, there is no longer any quenching effect. The quenching and recovery of the APD are solely accomplished by the narrow gate signal itself. At the same time, the inverting output terminal of the first high-speed comparator is normally output to the inverting input terminal of the second high-speed comparator, buffered by the second high-speed comparator and then input to the FPGA, enabling normal counting of the avalanche.

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