Mask layout and obtaining method thereof, and semiconductor structure forming method

Abstract

The invention discloses a mask layout and an acquisition method thereof, and a semiconductor structure forming method, the layout acquisition method comprises the following steps: providing an initial layout which comprises a plurality of first-class graphs and a plurality of second-class graphs which are parallel to a first direction, and the second-class graphs penetrate through the first-class graphs along a second direction; distributing a plurality of first-class graphs to the first layout and the second layout, wherein the first-class graphs comprise first graphs located in the first layout and second graphs located in the second layout; a plurality of second-class graphs are distributed to the third layout and the fourth layout, the second-class graphs comprise the third graphs and the fourth graphs, the third graphs are the second-class graphs penetrating through the first graphs, and the fourth graphs are the second-class graphs penetrating through the second graphs; if a third graph on the third layout meets the first preset rule, first auxiliary graphs are generated on the two sides of the third graph in the second direction; and if a fourth graph on the fourth layout meets a second preset rule, generating second auxiliary graphs on two sides of the fourth graph along the second direction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a mask layout, a method for obtaining the same, and a method for forming a semiconductor structure. Background Art

[0002] With the development of semiconductor technology and the reduction of critical dimensions, the number and density of patterns on the design layout have increased sharply. During the lithography process, it has gradually become impossible to expose all patterns onto the wafer at once. The MP (Multi-Patterning) technology has begun to become a necessary means to enable the exposed patterns to meet the process requirements of each node. The MP technology splits the patterns on the design layout into multiple masks and realizes that all patterns on the design layout can be transferred onto the wafer with good quality through multiple exposures.

[0003] However, for high nodes, as the device size becomes smaller and smaller, the number of mask splits will increase. For some product patterns, there are higher process precision requirements, more stringent MTT (mean to target) tolerance ranges, and higher requirements for critical dimension uniformity (CDU) during production and research. Therefore, it is particularly important to improve its process window, and how to make the sizes of the split patterns evenly distributed and reasonable and friendly to the process has always been the pursuit of optical proximity effect correction. Therefore, a more flexible balancing method is needed in the application of the MP technology. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a mask layout, a method for obtaining the same, and a method for forming a semiconductor structure to improve the process of applying the MP technology, enhance the process window, and make the sizes of the split patterns evenly distributed and reasonable.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for obtaining a mask layout, including: providing an initial layout, the initial layout includes a plurality of first-type graphics and a plurality of second-type graphics, the first-type graphics are parallel to the first direction, the second-type graphics penetrate the first-type graphics along the second direction, and the second direction is perpendicular to the first direction; according to the graphic splitting rule, distributing a plurality of the first-type graphics to a first layout and a second layout, a plurality of the first-type graphics include a first graphic located in the first layout and a second graphic located in the second layout; distributing a plurality of the second-type graphics to a third layout and a fourth layout, a plurality of the second-type graphics include a third graphic and a fourth graphic, the third graphic is a second-type graphic that penetrates the first graphic, and the fourth graphic is a second-type graphic that penetrates the second graphic; determining whether the third graphic on the third layout satisfies a first preset rule; if the third graphic satisfies the first preset rule, generating first auxiliary graphics on both sides of the third graphic along the second direction; determining whether the fourth graphic on the fourth layout satisfies a second preset rule; if the fourth graphic satisfies the second preset rule, generating second auxiliary graphics on both sides of the fourth graphic along the second direction.

[0006] Optionally, the first preset rule includes: the spacing between adjacent third graphics in the first direction is greater than or equal to a preset value.

[0007] Optionally, the second preset rule includes: the spacing between adjacent fourth graphics in the first direction is greater than or equal to a preset value.

[0008] Optionally, it further includes: if the third graphic does not satisfy the first preset rule, splitting the third graphic into a fifth layout until the third graphics on each layout satisfy the preset rule.

[0009] Optionally, it further includes: if the fourth graphic does not satisfy the second preset rule, splitting the fourth graphic into a sixth layout until the fourth graphics on each layout satisfy the preset rule.

[0010] Optionally, the size of the first auxiliary graphic in the second direction includes: 1 / 2 of the minimum lithography pitch.

[0011] Optionally, the size of the second auxiliary graphic in the second direction includes: 1 / 2 of the minimum lithography pitch.

[0012] Optionally, adjacent first auxiliary graphics are merged together in the second direction.

[0013] Optionally, adjacent second auxiliary graphics are merged together in the second direction.

[0014] Accordingly, the technical solution of the present invention further provides a photomask layout, including: a first layout, the first layout includes a plurality of first patterns, and the first patterns are parallel to a first direction; a second layout, the second layout includes a plurality of second patterns, and the second patterns are parallel to the first direction; a third layout, the third layout includes a plurality of third patterns and a plurality of first auxiliary patterns, the third patterns are parallel to a second direction, the third patterns correspond to the first patterns, the third patterns penetrate the first patterns along the second direction, the second direction is perpendicular to the first direction, and the first auxiliary patterns are located on both sides of the third patterns along the second direction; a fourth layout, the fourth layout includes a plurality of fourth patterns and a plurality of second auxiliary patterns, the fourth patterns are parallel to the second direction, the fourth patterns correspond to the second patterns, the fourth patterns penetrate the second patterns along the second direction, and the second auxiliary patterns are located on both sides of the fourth patterns along the second direction.

[0015] Optionally, the spacing between adjacent third patterns in the first direction is greater than or equal to a preset value; the spacing between adjacent fourth patterns in the first direction is greater than or equal to a preset value.

[0016] Optionally, it further includes: a fifth layout, the fifth layout includes a plurality of third patterns, the third patterns correspond to the first patterns, and the spacing between adjacent third patterns in the first direction is greater than or equal to a preset value.

[0017] Optionally, it further includes: a sixth layout, the sixth layout includes a plurality of fourth patterns, the fourth patterns correspond to the second patterns, and the spacing between adjacent fourth patterns in the first direction is greater than or equal to a preset value.

[0018] Optionally, the dimension of the first auxiliary pattern in the second direction includes: 1 / 2 of the minimum lithography pitch; the dimension of the second auxiliary pattern in the second direction includes: 1 / 2 of the minimum lithography pitch.

[0019] Optionally, adjacent first auxiliary patterns are combined together in the second direction.

[0020] Optionally, adjacent second auxiliary patterns are combined together in the second direction.

[0021] Accordingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a plurality of mask plates formed based on the mask plate layout obtained by the above method, the plurality of mask plates including a first type of mask plate and a second type of mask plate, the first type of mask plate including a first mask plate and a second mask plate, the first mask plate being formed based on a first layout, the second mask plate being formed based on a second layout, the second type of mask plate including a third mask plate and a fourth mask plate, the third mask plate being formed based on a third layout, the fourth mask plate being formed based on a fourth layout, the third mask plate corresponding to the first mask plate, and the fourth mask plate corresponding to the second mask plate; providing an etching layer to be etched; sequentially transferring the patterns of the second type of mask plate and the first type of mask plate with corresponding relationships to the etching layer to be etched, including: transferring the pattern of the third mask plate corresponding to the first mask plate to the etching layer to be etched, and then transferring the pattern of the first mask plate to the etching layer to be etched to form a first groove in the etching layer to be etched, the first groove being parallel to a first direction, and the first direction being parallel to the surface of the etching layer to be etched; transferring the pattern of the fourth mask plate corresponding to the second mask plate to the etching layer to be etched, and then transferring the pattern of the second mask plate to the etching layer to be etched to form a second groove in the etching layer to be etched, the second groove being parallel to the first direction; forming a first metal layer in the first groove; and forming a second metal layer in the second groove.

[0022] Optionally, the etching layer to be etched includes a substrate and a dielectric layer located on the substrate.

[0023] Optionally, transferring the pattern of the third mask plate corresponding to the first mask plate to the etching layer to be etched includes: forming a first sacrificial layer on the etching layer to be etched; using the third mask plate to form a first mask structure on the first sacrificial layer, the first mask structure exposing a part of the surface of the first sacrificial layer; performing a modification treatment on the first sacrificial layer exposed by the first mask structure to form a plurality of first modified layers on the etching layer to be etched, the first modified layers being parallel to a second direction, the second direction being parallel to the surface of the etching layer to be etched, and the first direction being perpendicular to the second direction.

[0024] Optionally, the first mask structure includes: a first cushion layer, a first anti-reflection layer located on the first cushion layer, and a first photoresist layer located on the first anti-reflection layer. The method for forming the first mask structure includes: forming a first cushion layer, a first anti-reflection layer located on the first cushion layer, and an initial photoresist layer located on the first anti-reflection layer on the first sacrificial layer; using the third mask plate to expose the initial photoresist layer, and then developing to form a first photoresist layer, the first photoresist layer exposing a part of the surface of the first anti-reflection layer; using the first photoresist layer as a mask to etch the first anti-reflection layer and the first cushion layer until the surface of the first sacrificial layer is exposed to form the first mask structure.

[0025] Optionally, the process of modifying the exposed first sacrificial layer of the first mask structure includes: an ion implantation process; after forming a plurality of first modification layers, it further includes: removing the first mask structure.

[0026] Optionally, transferring the pattern of the first mask to the layer to be etched to form a first groove in the layer to be etched includes: forming a second mask structure on the first modification layer and the first sacrificial layer using the first mask, the second mask structure exposing a part of the surface of the first sacrificial layer and a part of the surface of the first modification layer; etching the exposed first sacrificial layer using the second mask structure as a mask to form a plurality of third grooves in the first sacrificial layer, the extending direction of the third grooves being parallel to the first direction, and the first modification layer penetrating through the third grooves along the second direction; etching the dielectric layer using the first modification layer and the third grooves as masks, and the pattern of the third grooves being transferred downward to form a first groove in the dielectric layer, the extending direction of the first groove being parallel to the first direction, and the pattern of the first modification layer being transferred downward to form a first isolation layer penetrating through the first groove.

[0027] Optionally, the second mask structure includes: a second cushion layer, a second anti-reflection layer located on the second cushion layer, and a second photoresist layer located on the second anti-reflection layer. The method for forming the second mask structure includes: forming a second cushion layer, a second anti-reflection layer located on the second cushion layer, and an initial photoresist layer located on the second anti-reflection layer on the first sacrificial layer and the first modification layer; exposing the initial photoresist layer using the first mask, and then developing to form a second photoresist layer, the second photoresist layer exposing a part of the surface of the second anti-reflection layer; etching the second anti-reflection layer and the second cushion layer using the second photoresist layer as a mask until the surface of the first sacrificial layer is exposed to form the second mask structure.

[0028] Optionally, the etching rate of the exposed first sacrificial layer using the second mask structure as a mask is greater than the etching rate of the first modification layer.

[0029] Optionally, transferring the pattern of the fourth mask corresponding to the second mask to the layer to be etched includes: forming a second sacrificial layer on the layer to be etched; forming a third mask structure on the second sacrificial layer using the fourth mask, the third mask structure exposing a part of the surface of the second sacrificial layer; modifying the exposed second sacrificial layer of the third mask structure to form a plurality of second modification layers on the layer to be etched, the second modification layers being parallel to the second direction.

[0030] Optionally, transferring the pattern of the second mask to the layer to be etched to form a second groove in the layer to be etched, including: forming a fourth mask structure on the second modification layer and the second sacrificial layer using the second mask, the fourth mask structure exposing a part of the surface of the second sacrificial layer and a part of the surface of the second modification layer; etching the exposed second sacrificial layer using the fourth mask structure as a mask to form a plurality of fourth grooves in the second sacrificial layer, the extending direction of the fourth grooves being parallel to the first direction, and the second modification layer penetrating through the fourth grooves along the second direction; etching the dielectric layer using the second modification layer and the fourth grooves as masks, the pattern of the fourth grooves being transferred downward to form a second groove in the dielectric layer, the extending direction of the second groove being parallel to the first direction, and the pattern of the second modification layer being transferred downward to form a second isolation layer penetrating through the second groove.

[0031] Optionally, forming the first groove first and then forming the second groove; before forming the second groove, further including: forming a first filling layer in the first groove.

[0032] Optionally, forming the second groove first and then forming the first groove; before forming the first groove, further including: forming a second filling layer in the second groove.

[0033] Optionally, the second type of mask further includes a fifth mask, the fifth mask being formed based on a fifth layout, and the fifth mask corresponding to the first mask; before transferring the pattern of the first mask to the layer to be etched, further including: transferring the pattern of the fifth mask to the layer to be etched.

[0034] Optionally, the second type of mask further includes a sixth mask, the sixth mask being formed based on a sixth layout, and the sixth mask corresponding to the second mask; before transferring the pattern of the second mask to the layer to be etched, further including: transferring the pattern of the sixth mask to the layer to be etched.

[0035] Optionally, the substrate includes: a substrate; a device layer located on the substrate, the device layer including isolation structures and device structures located within the isolation structures, the device structures including transistors, diodes, triodes, capacitors, inductors, or conductive structures.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] The method for obtaining the layout of the mask plate of the present invention generates first auxiliary patterns on both sides of the third pattern along the second direction, and generates second auxiliary patterns on both sides of the fourth pattern along the second direction. On the one hand, it can avoid the head-to-head phenomenon of adjacent third patterns and adjacent fourth patterns on a single photomask, thereby improving the process window. On the other hand, the first auxiliary patterns are located on both sides of the third pattern along the second direction, and the second auxiliary patterns are located on both sides of the fourth pattern along the second direction, thereby increasing the size of the third pattern and the fourth pattern along the second direction, making the contact position between the second type of pattern and the first type of pattern smoother. When forming a semiconductor structure using the layout of the mask plate subsequently, the size of the semiconductor structure with strict size requirements is more accurate. On the other hand, there is no need to split the patterns with the head-to-head phenomenon anymore, saving the number of photomasks and reducing costs.

[0038] Furthermore, adjacent first auxiliary patterns are merged together in the second direction, and adjacent second auxiliary patterns are merged together in the second direction. On the one hand, when splitting the patterns, there is no need to consider the size requirements in the second direction, simplifying the splitting steps and reducing the running time. On the other hand, the merged first auxiliary patterns and the third pattern approach a one-dimensional pattern, and the merged second auxiliary patterns and the fourth pattern approach a one-dimensional pattern, making the pattern sizes on a single photomask more uniformly distributed and the two-dimensional effect greatly weakened, improving the size uniformity and being more friendly to the actual production process.

[0039] The method for forming a semiconductor structure of the present invention transfers the patterns of the second type of mask plate and the first type of mask plate with corresponding relationships to the layer to be etched in sequence, transfers the patterns of the third mask plate corresponding to the first mask plate to the layer to be etched, then transfers the patterns of the first mask plate to the layer to be etched, transfers the patterns of the fourth mask plate corresponding to the second mask plate to the layer to be etched, and then transfers the patterns of the second mask plate to the layer to be etched. On the one hand, the first auxiliary patterns and the second auxiliary patterns inserted during the formation of the second type of mask plate improve the process window, make the size more accurate, and improve the size uniformity of the isolation layer formed by the second type of pattern. On the other hand, the second type of pattern and the first type of pattern are alternately transferred to the layer to be etched, enabling the isolation layer formed by the second type of pattern to selectively isolate the metal layer formed by the first type of pattern, improving the flexibility of the process. Description of the Drawings

[0040] Figures 1 to 3 is a schematic diagram of the process for obtaining the layout of the mask plate in an embodiment;

[0041] Figure 4 and Figure 5 is a scanning electron microscope schematic diagram of a semiconductor structure in an embodiment;

[0042] Figure 6 It is a flowchart of a method for obtaining a mask layout in an embodiment of the present invention;

[0043] Figures 7 to 16 It is a schematic diagram of the process of obtaining a mask layout in an embodiment of the present invention;

[0044] Figures 17 to 45 It is a schematic diagram of the process of forming a semiconductor structure in an embodiment of the present invention. Detailed implementation manners

[0045] As described in the background art, it is still necessary to improve the process of applying the MP technology to improve the process window and make the pattern sizes after splitting evenly and reasonably distributed. The following will analyze and explain with specific embodiments.

[0046] Figures 1 to 3 It is a schematic diagram of the process of obtaining a mask layout in an embodiment; Figure 4 and Figure 5 It is a scanning electron microscope schematic diagram of a semiconductor structure in an embodiment.

[0047] Please refer to Figure 1 , an initial layout 100 is provided. The initial layout 100 includes a first type of graphics and a second type of graphics. The first type of graphics is parallel to the first direction X, and the second type of graphics penetrates the first type of graphics along the second direction Y. The second direction Y is perpendicular to the first direction X. The first type of graphics includes a first graphic 101 and a second graphic 102, and the second type of graphics includes 103, 104, and 105.

[0048] The first type of graphics is used to form a mask in the subsequent process, and transfer the graphics of the mask to the semiconductor structure to form a metal layer. The second type of graphics is used to form a mask in the subsequent process, and transfer the graphics of the mask to the semiconductor structure to form a barrier layer that separates the metal layers.

[0049] Please refer to Figure 2 and Figure 3 , according to the graphic splitting rule, a number of the first type of graphics are allocated to a first layout 110 and a second layout 120. A number of the first layout 110 and the second layout 120 are allocated. The first layout 110 includes a first graphic 101 and a second type of graphic labeled 103 that penetrates the first graphic 101. The second layout 120 includes a second graphic 102 and second type of graphics labeled 104 and 105 that penetrate the second graphic 102.

[0050] The size of the second type of pattern is small. In the first layout diagram 110, adjacent second type of patterns marked as 103 form a head-to-head (HTH) shape due to the small spacing. In the second layout diagram 120, adjacent second type of patterns marked as 104 and 105 form a head-to-head shape due to the small spacing. Subsequently, when transferring the second type of pattern onto the semiconductor layer, the second type of pattern with a head-to-head shape will be shrunk during the exposure process, resulting in a reduction in the size of the pattern actually transferred onto the semiconductor layer (as shown in region A of Figure 4 ). Subsequently, when forming the metal layer based on the transferred pattern, it will cause the formed isolation layer to be unable to effectively cut off the metal layer (as shown in region B of Figure 5 ), resulting in a short circuit of the metal layer.

[0051] Regarding the above problems, on the one hand, through traditional optical proximity effect techniques, such as adjusting the correction model, correction recipe, etching bias, and inserting auxiliary patterns, etc., it is difficult to completely solve. If additional masks are added through MP technology and the small-sized pattern parts stuck in the head-to-head situation are assigned to an additional mask, thus avoiding the head-to-head stuck situation, the disadvantage is an increase in mask cost. On the other hand, by continuously optimizing the process manufacturing flow, such as adjusting the minimum size critical dimension (CD) of lithography exposure during lithography, or adjusting the etching bias during etching or ion implantation to adjust the small-sized pattern stuck in the head-to-head situation in place, etc., although to a certain extent, the process window of the small-sized pattern can be increased, but it does not cure the root cause. Forcefully adjusting each process step to make the overall process friendly to the small-sized pattern stuck in the head-to-head situation will inevitably sacrifice other types of patterns, consuming time and increasing R & D costs. For advanced nodes using DUV lithography machines, on key layers such as M0C, defects will still appear on the wafer and the electrical performance of the sacrificed chips will be affected.

[0052] To solve the above problems, the technical solution of the present invention provides a mask layout diagram, a method for obtaining the same, and a method for forming a semiconductor structure. By generating first auxiliary patterns on both sides of the third pattern along the second direction and generating second auxiliary patterns on both sides of the fourth pattern along the second direction, on the one hand, it can avoid the head-to-head phenomenon of adjacent third patterns and adjacent fourth patterns in one mask, thereby improving the process window; on the other hand, the first auxiliary patterns are located on both sides of the third pattern along the second direction, and the second auxiliary patterns are located on both sides of the fourth pattern along the second direction, thereby increasing the size of the third pattern and the fourth pattern along the second direction, making the contact position between the second type of pattern and the first type of pattern smoother. Subsequently, when forming a semiconductor structure using the mask layout diagram, the size of the semiconductor structure with strict size requirements is more accurate; on the further hand, there is no need to split the patterns with the head-to-head phenomenon anymore, saving the number of masks and reducing costs.

[0053] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following provides a detailed description of specific embodiments of the present invention with reference to the accompanying drawings.

[0054] Figure 6 It is a flowchart of a method for obtaining a mask layout in an embodiment of the present invention.

[0055] Please refer to Figure 6 , the method for obtaining a mask layout includes:

[0056] Step S10: Provide an initial layout, where the initial layout includes a plurality of first-type graphics and a plurality of second-type graphics. The first-type graphics are parallel to the first direction, and the second-type graphics penetrate the first-type graphics along the second direction, and the second direction is perpendicular to the first direction;

[0057] Step S20: According to the graphic splitting rule, allocate a plurality of the first-type graphics to a first layout and a second layout. The plurality of the first-type graphics include a first graphic located in the first layout and a second graphic located in the second layout;

[0058] Step S30: Allocate a plurality of the second-type graphics to a third layout and a fourth layout. The plurality of the second-type graphics include a third graphic and a fourth graphic. The third graphic is a second-type graphic that penetrates the first graphic, and the fourth graphic is a second-type graphic that penetrates the second graphic;

[0059] Step S40: Determine whether the third graphic on the third layout meets a first preset rule;

[0060] Step S50: If the third graphic meets the first preset rule, generate first auxiliary graphics on both sides of the third graphic along the second direction;

[0061] Step S60: Determine whether the fourth graphic on the fourth layout meets a second preset rule;

[0062] Step S70: If the fourth graphic meets the second preset rule, generate second auxiliary graphics on both sides of the fourth graphic along the second direction.

[0063] The method for obtaining the mask layout can generate first auxiliary patterns on both sides of the third pattern along the second direction, and generate second auxiliary patterns on both sides of the fourth pattern along the second direction. On the one hand, it can avoid the head-to-head phenomenon of adjacent third patterns and adjacent fourth patterns on a single photomask, thereby improving the process window. On the other hand, the first auxiliary patterns are located on both sides of the third pattern along the second direction, and the second auxiliary patterns are located on both sides of the fourth pattern along the second direction, thereby increasing the size of the third pattern and the fourth pattern along the second direction, making the contact position between the second type of pattern and the first type of pattern smoother. When forming a semiconductor structure using the mask layout subsequently, the size of the semiconductor structure with strict size requirements is more accurate. On the other hand, there is no need to split the patterns with the head-to-head phenomenon anymore, saving the number of photomasks and reducing costs.

[0064] Next, in combination with Figures 7 to 16 each step will be analyzed and described. Figures 7 to 16 is a schematic diagram of the process for obtaining the mask layout in an embodiment of the present invention.

[0065] Please combine Figure 7 and continue to refer to Figure 6 , referring to step S10: Provide an initial layout 200, where the initial layout 200 includes a plurality of first-type patterns and a plurality of second-type patterns. The first-type patterns are parallel to the first direction X, and the second-type patterns penetrate the first-type patterns along the second direction Y, and the second direction Y is perpendicular to the first direction X.

[0066] In this embodiment, the second-type patterns schematically shown in the initial layout 200 include patterns marked as 203, 204, 205, and 206.

[0067] In this embodiment, the first-type patterns are used for the patterns of the mask for forming the metal layer in the semiconductor structure subsequently; the second-type patterns are used for the patterns for cutting the metal layer in the semiconductor structure subsequently.

[0068] Please combine Figure 8 and Figure 9 and continue to refer to Figure 6 , referring to step S20: According to the pattern splitting rule, allocate a plurality of the first-type patterns to a first layout 210 (refer to Figure 8 ) and a second layout 220 (refer to Figure 9 ), and a plurality of the first-type patterns include a first pattern 201 located in the first layout 210 and a second pattern 202 located in the second layout 220.

[0069] In this embodiment, the first layout 210 includes a plurality of first patterns 201, and the first patterns 201 are parallel to the first direction X. Figure 8Also shown are a number of second - type figures, which are only used to illustrate the corresponding positional relationship between a number of second - type figures 203 and 206 and the first figure 201 for the convenience of understanding this allocation and subsequent allocations, that is, the second - type figures 203 and 206 penetrate through the first figure 201 along the second direction Y. Figure 8 In the first layout 210, the second - type figures are not included, and the first - type figures and the second - type figures are allocated in different layouts.

[0070] In this embodiment, the second layout 220 includes a number of second figures 202, and the second figures 202 are parallel to the first direction X. Figure 9 Also shown are a number of second - type figures, which are only used to illustrate the corresponding positional relationship between a number of second - type figures 204 and 205 and the second figure 202 for the convenience of understanding this allocation and subsequent allocations, that is, the second - type figures 204 and 205 penetrate through the second figure 202 along the second direction Y. Figure 8 In the second layout 220, the second - type figures are not included, and the first - type figures and the second - type figures are allocated in different layouts.

[0071] Please refer to Figure 10 and Figure 11 and continue to refer to Figure 6 , refer to step S30: Allocate a number of the second - type figures to the third layout 230 (refer to Figure 10 ) and the fourth layout 240 (refer to Figure 11 ). A number of the second - type figures include a third figure and a fourth figure. The third figure is a second - type figure that penetrates through the first figure 201, and the fourth figure is a second - type figure that penetrates through the second figure 202.

[0072] In this embodiment, the third layout 230 includes a number of third figures. Figure 10 The third figures shown include 203 and 206. The third figures 203 and 206 are second - type figures that penetrate through the first figure 201 (refer to Figure 8 ); the fourth layout 240 includes a number of fourth figures. Figure 11 The fourth figures shown include 204 and 205. The fourth figures 204 and 205 are second - type figures that penetrate through the second figure 202 (refer to Figure 9 ).

[0073] Please refer to Figure 10 and continue to refer to Figure 6 , refer to step S40: Determine whether the third figures on the third layout 230 meet the first preset rule.

[0074] The first preset rule includes: The spacing between adjacent third figures in the first direction X is greater than or equal to a preset value.

[0075] In this embodiment, it is necessary to determine whether the spacing of the third graphics marked as 203 and 206 in the first direction X is greater than or equal to a preset value.

[0076] Please combine Figure 12 Continue to refer to Figure 6 , refer to step S50: If the third graphic meets the first preset rule, generate first auxiliary graphics on both sides of the third graphic along the second direction Y; if the third graphic does not meet the first preset rule, split the third graphic into the fifth layout until the third graphics on each layout meet the preset rule.

[0077] In this embodiment, since the third graphic meets the first preset rule, first auxiliary graphics 208 are generated on both sides of the third graphic along the second direction Y.

[0078] The size of the first auxiliary graphic 208 in the second direction Y includes: 1 / 2 of the minimum lithography pitch. The minimum lithography pitch (pitch) is the minimum size of the semiconductor structure that can be formed under the current exposure conditions. First auxiliary graphics 208 are generated on both sides of the third graphic along the second direction Y, and the size of the first auxiliary graphic 208 in the second direction Y includes: 1 / 2 of the minimum lithography pitch. Thus, the sizes of the two first auxiliary graphics 208 on both sides of the third graphic in the second direction Y are the minimum lithography pitch. Therefore, they can be exposed under the current exposure conditions while not occupying too much area.

[0079] In this embodiment, adjacent first auxiliary graphics 208 are merged in the second direction Y and merged with the third graphic into a one-dimensional graphic, that is, the third graphic is stretched along the second direction Y. On the one hand, it makes the size uniformity of the graphic better, can improve the process window and the electrical performance of the semiconductor structure, and can also reduce the 2D effect of the graphic; on the other hand, when the subsequent graphic is transferred, the flatness of the contact position between the third graphic and the first graphic is better. When the metal layer formed by the first graphic is cut off by the structure formed by the third graphic, the cutting position will be more accurate.

[0080] Adjacent first auxiliary graphics 208 are merged together in the second direction Y. On the one hand, when splitting the graphic, there is no need to consider the size requirements in the second direction Y, the splitting steps are simplified, and the running time will be reduced; on the other hand, the merged first auxiliary graphic 208 and the third graphic approach a one-dimensional graphic, making the graphic sizes on a single reticle more uniformly distributed, greatly weakening the influence of the two-dimensional effect, improving the size uniformity, and being more friendly to the actual production process.

[0081] In other embodiments, adjacent first auxiliary graphics may not be merged in the second direction.

[0082] In another embodiment, if the third pattern does not meet the first preset rule, the third pattern is split into the fifth layout until the third patterns on each layout meet the preset rule; first auxiliary patterns are generated on both sides of the third pattern that meets the preset rule along the second direction.

[0083] Please refer to Figure 11 and continue to refer to Figure 6 , and refer to step S60: Determine whether the fourth pattern on the fourth layout 240 meets the second preset rule.

[0084] The second preset rule includes: the spacing between adjacent fourth patterns in the first direction X is greater than or equal to a preset value.

[0085] In this embodiment, it is necessary to determine whether the spacing between the fourth patterns marked as 204 and 205 in the first direction X is greater than or equal to the preset value.

[0086] Please continue to refer to Figure 6 , and refer to step S70: If the fourth pattern meets the second preset rule, second auxiliary patterns are generated on both sides of the fourth pattern along the second direction; if the fourth pattern does not meet the second preset rule, the fourth pattern is split into the sixth layout until the fourth patterns on each layout meet the preset rule.

[0087] Please refer to Figure 13 and Figure 14 , in this embodiment, the fourth pattern does not meet the second preset rule, so the fourth pattern is split into the sixth layout 250 until the fourth patterns on each layout meet the preset rule.

[0088] In this embodiment, the fourth pattern is continuously split. Pattern 204 is split into the fourth layout 240, and pattern 205 is split into the sixth layout 250.

[0089] Continue to determine whether the pattern 204 on the fourth layout 240 meets the second preset rule; continue to determine whether the pattern 205 on the sixth layout 250 meets the second preset rule.

[0090] In this embodiment, the pattern 204 on the fourth layout 240 meets the second preset rule; the pattern 205 on the sixth layout 250 meets the second preset rule.

[0091] Please refer to Figure 15 , the pattern 204 on the fourth layout 240 meets the second preset rule, so second auxiliary patterns 209 are generated on both sides of the fourth pattern along the second direction Y.

[0092] The size of the second auxiliary pattern 209 in the second direction Y includes: 1 / 2 of the minimum lithography pitch. The minimum lithography pitch is the minimum size that can be exposed and formed in the semiconductor structure.

[0093] In other embodiments, adjacent second auxiliary patterns can be combined in the second direction.

[0094] Please refer to Figure 16 , if the pattern 205 on the sixth layout diagram 250 meets the second preset rule, then third auxiliary patterns 207 are generated on both sides of the fourth pattern along the second direction Y.

[0095] In other embodiments, adjacent second auxiliary patterns can be combined in the second direction.

[0096] Correspondingly, an embodiment of the present invention further provides a mask layout, and the mask layout includes:

[0097] As Figure 8 shown, the first layout diagram 210, the first layout diagram 210 includes a plurality of first patterns 201, and the first patterns 201 are parallel to the first direction X;

[0098] As Figure 9 shown, the second layout diagram 220, the second layout diagram 220 includes a plurality of second patterns 202, and the second patterns 202 are parallel to the first direction X;

[0099] As Figure 12 shown, the third layout diagram 230, the third layout diagram 230 includes a plurality of third patterns and a plurality of first auxiliary patterns 208, the third patterns are labeled 203 and 206, the third patterns are parallel to the second direction Y, the third patterns correspond to the first patterns 201, the third patterns penetrate through the first patterns 201 along the second direction Y, the second direction Y is perpendicular to the first direction X, and the first auxiliary patterns 208 are located on both sides of the third patterns along the second direction Y.

[0100] As Figure 15 shown, the fourth layout diagram 240, the fourth layout diagram 240 includes a plurality of fourth patterns and a plurality of second auxiliary patterns 209, the fourth patterns are labeled 204, the fourth patterns are parallel to the second direction Y, the fourth patterns correspond to the second patterns 202, the fourth patterns penetrate through the second patterns 202 along the second direction Y, and the second auxiliary patterns 209 are located on both sides of the fourth patterns along the second direction Y.

[0101] In this embodiment, the pitch between adjacent third patterns in the first direction X is greater than or equal to a preset value; the pitch between adjacent fourth patterns in the first direction X is greater than or equal to a preset value.

[0102] In another embodiment, it further includes: a fifth layout diagram, which includes a plurality of third patterns, the third patterns corresponding to the first patterns, and the distance between adjacent third patterns in the first direction X being greater than or equal to a preset value.

[0103] In this embodiment, it further includes: as Figure 16 shown in the sixth layout diagram 250, the sixth layout diagram 250 includes a plurality of fourth patterns and a plurality of third auxiliary patterns 207, the fourth patterns being labeled as 205, the fourth patterns corresponding to the second patterns 202, the distance between adjacent fourth patterns in the first direction X being greater than or equal to a preset value, and the third auxiliary patterns 207 being located on both sides of the fourth patterns along the second direction Y.

[0104] In this embodiment, the size of the first auxiliary pattern in the second direction includes: 1 / 2 of the minimum lithography pitch; the size of the second auxiliary pattern in the second direction includes: 1 / 2 of the minimum lithography pitch.

[0105] In this embodiment, adjacent first auxiliary patterns 208 are merged together in the second direction Y.

[0106] In another embodiment, adjacent second auxiliary patterns are merged together in the second direction.

[0107] Figures 17 to 45 is a schematic diagram of the process of forming a semiconductor structure in an embodiment of the present invention.

[0108] Provided are a plurality of mask layouts formed based on the mask layout obtained by the method as Figures 7 to 16 described.

[0109] A plurality of the mask layouts include a first type of mask layout and a second type of mask layout. The first type of mask layout includes a first mask layout and a second mask layout. The first mask layout is formed based on a first layout 210 (refer to Figure 8 ), the first layout 210 including a first pattern 201; the second mask layout is formed based on a second layout 220 (refer to Figure 9 ), the second layout 220 including a second pattern 202.

[0110] The second type of mask layout includes a third mask layout and a fourth mask layout.

[0111] In this embodiment, the third mask layout is formed based on a third layout 230 (refer to Figure 12 ), the third layout 230 including second type patterns 203 and 206 and first auxiliary patterns 208 located on both sides of the second type patterns 203 and 206, and the third mask layout corresponding to the first mask layout.

[0112] In this embodiment, the fourth mask is formed based on the fourth layout diagram 240 (refer to Figure 15 ), the fourth layout diagram 240 includes a second type of pattern 204 and second auxiliary patterns 209 located on both sides of the second type of pattern 204, and the fourth mask corresponds to the second mask.

[0113] In this embodiment, the second type of mask further includes a sixth mask, the sixth mask is formed based on the sixth layout diagram 250 (refer to Figure 16 ), the sixth layout diagram 250 includes a second type of pattern 205 and second auxiliary patterns 207 located on both sides of the second type of pattern 205, and the sixth mask corresponds to the second mask.

[0114] In another embodiment, the second type of mask further includes a fifth mask, the fifth mask is formed based on the fifth layout diagram, and the fifth mask corresponds to the first mask.

[0115] Please refer to Figure 17 to provide the layer to be etched.

[0116] The layer to be etched includes a substrate 300 and a dielectric layer 301 located on the substrate 300.

[0117] The substrate 300 includes: a substrate (not shown); a device layer located on the substrate, the device layer includes an isolation structure (not shown) and device structures (not shown) located within the isolation structure, and the device structures include transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0118] Next, transfer the patterns of the second type of mask and the first type of mask with corresponding relationships to the layer to be etched in sequence, including: transfer the pattern of the third mask with a corresponding relationship to the first mask to the layer to be etched, and then transfer the pattern of the first mask to the layer to be etched to form a first groove in the layer to be etched, the first groove being parallel to the first direction; transfer the pattern of the fourth mask with a corresponding relationship to the second mask to the layer to be etched, and then transfer the pattern of the second mask to the layer to be etched to form a second groove in the layer to be etched, the second groove being parallel to the first direction.

[0119] Transfer the pattern of the third mask with a corresponding relationship to the first mask to the layer to be etched, and then transfer the pattern of the first mask to the layer to be etched to form a first groove in the layer to be etched, the first groove being parallel to the first direction. For the specific process, please refer to Figures 17 to 29 .

[0120] Please continue to refer to Figure 17 and Figure 18, a first sacrificial layer 302 is formed on the layer to be etched; a first mask structure is formed on the first sacrificial layer 302 by using a third mask, and the first mask structure includes: a first cushion layer 303, a first anti-reflection layer 304 located on the first cushion layer 303, and a first photoresist layer 305 located on the first anti-reflection layer 304.

[0121] The forming method of the first mask structure includes: forming a first cushion layer 303 on the first sacrificial layer 302, a first anti-reflection layer 304 located on the first cushion layer 303, and an initial photoresist layer (not shown) located on the first anti-reflection layer 304; exposing the initial photoresist layer by using the third mask, and then forming a first photoresist layer 305 after development, and the first photoresist layer 305 exposes a part of the surface of the first anti-reflection layer 304; etching the first anti-reflection layer 304 and the first cushion layer 303 by using the first photoresist layer 305 as a mask until the surface of the first sacrificial layer 302 is exposed, so as to form the first mask structure.

[0122] Figure 18 In, during the process of etching the first anti-reflection layer 304 and the first cushion layer 303 by using the first photoresist layer 305 as a mask until the surface of the first sacrificial layer 302 is exposed, the first photoresist layer 305 is naturally consumed.

[0123] The material of the first cushion layer 303 includes amorphous materials, and the amorphous materials include amorphous silicon or amorphous carbon; the first anti-reflection layer 304 includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0124] In this embodiment, the material of the first sacrificial layer 302 includes amorphous silicon (α-si).

[0125] Please continue to refer to Figure 18 , a modification treatment is performed on the first sacrificial layer 302 exposed by the first mask structure, and a plurality of first modification layers 306 are formed on the layer to be etched, and the first modification layers 306 are parallel to the second direction Y, and the second direction Y is parallel to the surface of the layer to be etched.

[0126] The process of performing a modification treatment on the first sacrificial layer exposed by the first mask structure includes: an ion implantation process. The implanted ions of the ion implantation process include fluorine ions, carbon ions or nitrogen ions, and the material of the first modification layer 306 has a large etching selectivity ratio with the material of the first sacrificial layer 302 and can be selectively removed in subsequent process steps.

[0127] Please refer to Figure 19And Figure 20 , Figure 19 is Figure 20 a schematic cross-sectional structure diagram along the direction of section line AA1, Figure 20 is Figure 19 a top view of , after forming a plurality of first modified layers 306, the first mask structure is removed.

[0128] Please refer to Figures 21 to 23 , Figure 22 is Figure 21 a schematic diagram based on , Figure 22 is Figure 23 a schematic cross-sectional structure diagram along the direction of section line AA1, Figure 23 is Figure 22 a top view of , a second mask structure is formed on the first modified layer 306 and the first sacrificial layer 302 by using a first mask plate, and the second mask structure exposes a part of the surface of the first sacrificial layer 302 and a part of the surface of the first modified layer 306.

[0129] The second mask structure includes: a second cushion layer 307, a second anti-reflection layer 308 located on the second cushion layer 307, and a second photoresist layer 309 located on the second anti-reflection layer 308.

[0130] The forming method of the second mask structure includes: forming a second cushion layer 307 on the first sacrificial layer 302 and the first modified layer 306, a second anti-reflection layer 308 located on the second cushion layer 307, and an initial photoresist layer (not shown) located on the second anti-reflection layer 308; exposing the initial photoresist layer by using the first mask plate, and then forming a second photoresist layer 309 after development, and the second photoresist layer 309 exposes a part of the surface of the second anti-reflection layer 308; etching the second anti-reflection layer 308 and the second cushion layer 307 by using the second photoresist layer 309 as a mask until the surface of the first sacrificial layer 302 is exposed to form the second mask structure.

[0131] Figure 22 In , during the process of etching the second anti-reflection layer 308 and the second cushion layer 307 by using the second photoresist layer 309 as a mask until the surface of the first sacrificial layer 302 is exposed, the second photoresist layer 309 is naturally consumed.

[0132] The material of the second cushion layer 307 includes amorphous materials, and the amorphous materials include amorphous silicon or amorphous carbon; the second anti-reflection layer 308 includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0133] Please refer toFigures 24 to 26 , Figure 24 is Figure 26 a schematic cross-sectional structure diagram along the direction of the section line AA1, Figure 25 is Figure 26 a schematic cross-sectional structure diagram along the direction of the section line BB1, Figure 26 is Figure 24 and Figure 25 a top view of , with the exposed first sacrificial layer 302 etched using the second mask structure as a mask, a plurality of third grooves 330 are formed in the first sacrificial layer 302, the extending direction of the third grooves 330 is parallel to the first direction X, the first modified layer 306 penetrates the third grooves along the second direction Y, the first direction X is parallel to the surface of the layer to be etched, and the first direction X is perpendicular to the second direction Y.

[0134] In this embodiment, the etching rate of the first sacrificial layer 302 by the process of etching the exposed first sacrificial layer 302 using the second mask structure as a mask is greater than the etching rate of the first modified layer 306.

[0135] Please refer to Figures 27 to 29 , Figure 27 is Figure 29 a schematic cross-sectional structure diagram along the direction of the section line BB1, Figure 28 is Figure 29 a schematic cross-sectional structure diagram along the direction of the section line CC1, Figure 29 is Figure 27 and Figure 28 a top view of and , with the dielectric layer 301 etched using the first modified layer 306 and the third grooves 330 as masks, the pattern of the third groove 309 and the third grooves 330 is transferred downward to form a first groove 311 in the dielectric layer 301, the extending direction of the first groove 311 is parallel to the first direction X, and the pattern of the first modified layer 306 is transferred downward to form a first isolation layer 310 penetrating the first groove 311.

[0136] In another embodiment, the second type of mask also includes a fifth mask, the fifth mask is formed based on a fifth layout, and the fifth mask corresponds to the first mask. Before transferring the pattern of the first mask to the layer to be etched, it further includes: transferring the pattern of the fifth mask to the layer to be etched.

[0137] After forming the first groove 311 and the first isolation layer 310, it further includes: removing the first modified layer 306 and the first sacrificial layer 302.

[0138] Please refer to Figure 30 and Figure 31 , Figure 30 is a schematic diagram based on Figure 27Figure 31 is a schematic diagram based on Figure 27 , a first filling layer 312 is formed in the first groove 311.

[0139] The method for forming the first filling layer 312 in the first groove 311 includes: forming a filling material layer (not shown) in the first groove 311 and on the dielectric layer 301; planarizing the filling material layer to form the first filling layer 312 in the first groove 311.

[0140] In this embodiment, the material of the first filling layer 312 includes amorphous carbon.

[0141] Transfer the pattern of the fourth mask plate corresponding to the second mask plate to the layer to be etched, and then transfer the pattern of the second mask plate to the layer to be etched to form a second groove in the layer to be etched. Please refer to Figures 32 to 42 .

[0142] Please refer to Figure 32 and Figure 33 , Figure 32 is a schematic diagram based on Figure 31 . Figure 33 is a schematic diagram based on Figure 32 , a second sacrificial layer 320 is formed on the dielectric layer 301, on the first filling layer 312 and on the first isolation layer 310; a third mask structure is formed on the second sacrificial layer 320 by using the fourth mask plate, and the third mask structure exposes a part of the surface of the second sacrificial layer 320.

[0143] The third mask structure includes: a third cushion layer 321, a third anti-reflection layer 322 located on the third cushion layer 321, and a third photoresist layer 323 located on the third anti-reflection layer 322.

[0144] The method for forming the third mask structure includes: forming a third cushion layer 321 on the second sacrificial layer 320, a third anti-reflection layer 322 located on the third cushion layer 321, and an initial photoresist layer (not shown) located on the third anti-reflection layer 322; exposing the initial photoresist layer by using the fourth mask plate, and then developing to form the third photoresist layer 323, the third photoresist layer 323 exposes a part of the surface of the third anti-reflection layer 322; etching the third anti-reflection layer 322 and the third cushion layer 321 by using the third photoresist layer 323 as a mask until the surface of the second sacrificial layer 320 is exposed to form the third mask structure.

[0145] Figure 33During the process of etching the third anti-reflection layer 322 and the third cushion layer 321 with the third photoresist layer 323 as a mask until the surface of the second sacrificial layer 320 is exposed, the third photoresist layer 323 is naturally consumed.

[0146] The material of the third cushion layer 321 includes amorphous materials, and the amorphous materials include amorphous silicon or amorphous carbon; the third anti-reflection layer 322 includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0147] In this embodiment, the material of the second sacrificial layer 320 includes amorphous silicon (α-si).

[0148] Please continue to refer to Figure 33 and perform a modification process on the second sacrificial layer 320 exposed by the third mask structure to form a plurality of second modified layers 324 on the layer to be etched, and the second modified layers 324 are parallel to the second direction Y.

[0149] The process of performing a modification process on the second sacrificial layer 320 exposed by the third mask structure includes: an ion implantation process. The implanted ions of the ion implantation process include fluoride ions, carbon ions, or nitrogen ions, and the material of the second modified layer 324 has a large etching selectivity ratio with the material of the second sacrificial layer 320 and can be selectively removed in subsequent process steps.

[0150] After forming the second modified layer 324, remove the third mask structure.

[0151] Please refer to Figures 34 to 36 and Figure 35 is a schematic diagram based on Figure 34 and Figure 35 is Figure 36 a schematic cross-sectional structure diagram along the section line CC1 direction, Figure 36 is Figure 35 a top view of, and a fourth mask structure is formed on the second modified layer 324 and the second sacrificial layer 320 by using a second mask plate, and the fourth mask structure exposes a part of the surface of the second sacrificial layer 320 and a part of the surface of the second modified layer 324.

[0152] The fourth mask structure includes: a fourth cushion layer 325, a fourth anti-reflection layer 326 located on the fourth cushion layer 325, and a fourth photoresist layer 327 located on the fourth anti-reflection layer 326.

[0153] The method for forming the fourth mask structure includes: forming a fourth cushion layer 325 on the second sacrificial layer 320, a fourth anti-reflection layer 326 on the fourth cushion layer 325, and an initial photoresist layer (not shown) on the fourth anti-reflection layer 326; exposing the initial photoresist layer using the fourth mask plate, and then developing to form a fourth photoresist layer 327, where the fourth photoresist layer 327 exposes a part of the surface of the fourth anti-reflection layer 326; etching the fourth anti-reflection layer 326 and the fourth cushion layer 325 using the fourth photoresist layer 327 as a mask until the surface of the second sacrificial layer 320 is exposed, thereby forming the fourth mask structure.

[0154] Figure 35 During the process of etching the fourth anti-reflection layer 326 and the fourth cushion layer 325 using the fourth photoresist layer 327 as a mask until the surface of the second sacrificial layer 320 is exposed, the fourth photoresist layer 327 is naturally consumed.

[0155] The material of the fourth cushion layer 325 includes amorphous materials, and the amorphous materials include amorphous silicon or amorphous carbon; the fourth anti-reflection layer 326 includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0156] In this embodiment, the second type of mask plate further includes a sixth mask plate, and further includes: transferring the pattern of the sixth mask plate to the layer to be etched. For the process of transferring the pattern of the sixth mask plate to the layer to be etched, please refer to Figures 34 to 36 and details will not be elaborated here.

[0157] Please refer to Figures 37 to 39 , Figure 37 is Figure 39 a schematic cross-sectional structure diagram along the sectional line CC1 direction, Figure 38 is Figure 39 a schematic cross-sectional structure diagram along the sectional line DD1 direction. Using the fourth mask structure as a mask to etch the exposed second sacrificial layer 320, a plurality of fourth grooves 325 are formed in the second sacrificial layer 320. The extending direction of the fourth grooves 325 is parallel to the first direction X, and the second modified layer 324 penetrates through the fourth grooves 325 along the second direction Y.

[0158] In this embodiment, the etching process of etching the exposed second sacrificial layer 320 using the fourth mask structure as a mask has an etching rate for the second sacrificial layer 320 greater than the etching rate for the second modified layer 324.

[0159] After forming the fourth grooves 325, the fourth mask structure is removed.

[0160] Please refer to Figures 40 to 42 , Figure 40 which is Figure 42 a schematic cross-sectional structure diagram along the direction of section line DD1. Figure 41 which is Figure 42 a schematic cross-sectional structure diagram along the direction of section line EE1. Using the second modified layer 324 and the fourth groove 325 as masks to etch the dielectric layer 301, the pattern of the fourth groove 325 is transferred downward to form a second groove 327 in the dielectric layer 301. The extending direction of the second groove 327 is parallel to the first direction X, and the pattern of the second modified layer 324 is transferred downward to form a second isolation layer 326 penetrating through the second groove 327.

[0161] After forming the second groove 327 and the second isolation layer 326, it further includes: removing the second modified layer 324, the second sacrificial layer 320, and the first filling layer 312.

[0162] In this embodiment, the first groove 311 is formed first, and then the second groove 327 is formed; before forming the second groove 327, a first filling layer 312 is further formed in the first groove 311.

[0163] In another embodiment, the second groove is formed first, and then the first groove is formed; before forming the first groove, it further includes: forming a second filling layer in the second groove.

[0164] Please refer to Figures 43 to 45 , Figure 43 which is Figure 45 a schematic cross-sectional structure diagram along the direction of section line EE1. Figure 44 which is Figure 45 a schematic cross-sectional structure diagram along the direction of section line DD1. A first metal layer 328 is formed in the first groove 311, and a second metal layer 329 is formed in the second groove 327.

[0165] The first metal layer 328 and the second metal layer 329 are formed simultaneously.

[0166] The forming method of the first metal layer 328 and the second metal layer 329 includes: forming a metal material layer (not shown) in the first groove 311, the second groove 327, and on the dielectric layer 301; planarizing the metal material layer until the surface of the dielectric layer 301 is exposed, and forming a plurality of first metal layers 328 and second metal layers 329 parallel to the first direction X in the dielectric layer 301. The first isolation layer 310 penetrates through the first metal layer 328 along the second direction Y, and the second isolation layer 326 penetrates through the second metal layer 329 along the second direction Y.

[0167] The first metal layer 328 is electrically connected to the device structure in the substrate, and the second metal layer 329 is electrically connected to the device structure in the substrate.

[0168] For the method of forming the semiconductor structure, the patterns of the second type of mask and the first type of mask with corresponding relationships are sequentially transferred to the layer to be etched, the pattern of the third mask with a corresponding relationship to the first mask is transferred to the layer to be etched, then the pattern of the first mask is transferred to the layer to be etched, the pattern of the fourth mask with a corresponding relationship to the second mask is transferred to the layer to be etched, and then the pattern of the second mask is transferred to the layer to be etched. On the one hand, the first auxiliary pattern and the second auxiliary pattern inserted during the formation of the second type of mask improve the process window, make the size more accurate, and the size uniformity better for the isolation layer formed by the second type of pattern; on the other hand, the second type of pattern and the first type of pattern are alternately transferred to the layer to be etched, so that the isolation layer formed by the second type of pattern can selectively isolate the metal layer formed by the first type of pattern, improving the flexibility of the process.

[0169] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for obtaining a mask layout, characterized in that, Comprising: Providing an initial layout, the initial layout including a plurality of first - type graphics and a plurality of second - type graphics, the first - type graphics being parallel to a first direction, the second - type graphics penetrating the first - type graphics along a second direction, the second direction being perpendicular to the first direction; According to the graphic splitting rule, allocating a plurality of the first - type graphics to a first layout and a second layout, the plurality of the first - type graphics including a first graphic located in the first layout and a second graphic located in the second layout; Allocating a plurality of the second - type graphics to a third layout and a fourth layout, the plurality of the second - type graphics including a third graphic and a fourth graphic, the third graphic being a second - type graphic penetrating the first graphic, the fourth graphic being a second - type graphic penetrating the second graphic; Judging whether the third graphic on the third layout satisfies a first preset rule; If the third graphic satisfies the first preset rule, generating first auxiliary graphics on both sides of the third graphic along the second direction; Judging whether the fourth graphic on the fourth layout satisfies a second preset rule; If the fourth graphic satisfies the second preset rule, generating second auxiliary graphics on both sides of the fourth graphic along the second direction.

2. The method for obtaining a mask layout according to claim 1, wherein The first preset rule includes: the distance between adjacent third graphics in the first direction is greater than or equal to a preset value.

3. The method for obtaining a mask layout according to claim 1, wherein The second preset rule includes: the distance between adjacent fourth graphics in the first direction is greater than or equal to a preset value.

4. The method for obtaining a mask layout according to claim 1, wherein Also comprising: If the third graphic does not satisfy the first preset rule, splitting the third graphic to a fifth layout until the third graphics on each layout satisfy the preset rule.

5. The method for obtaining a photomask layout according to claim 1, wherein Also comprising: If the fourth graphic does not satisfy the second preset rule, splitting the fourth graphic to a sixth layout until the fourth graphics on each layout satisfy the preset rule.

6. The method for obtaining a mask layout according to claim 1, wherein The size of the first auxiliary graphic in the second direction includes: 1 / 2 of the minimum lithography pitch.

7. The method for obtaining a photomask layout according to claim 1, wherein The size of the second auxiliary graphic in the second direction includes: 1 / 2 of the minimum lithography pitch.

8. The mask layout acquisition method according to claim 1, wherein Adjacent first auxiliary graphics are merged together in the second direction.

9. The method for obtaining a mask layout according to claim 1, wherein Adjacent second auxiliary graphics are merged together in the second direction.

10. A photomask layout, characterized in that, Comprising: A first layout, the first layout including a plurality of first graphics, the first graphics being parallel to the first direction; A second layout, the second layout including a plurality of second graphics, the second graphics being parallel to the first direction; A third layout, the third layout including a plurality of third graphics and a plurality of first auxiliary graphics, the third graphics being parallel to the second direction, the third graphics corresponding to the first graphics, the third graphics penetrating the first graphics along the second direction, the second direction being perpendicular to the first direction, the first auxiliary graphics being located on both sides of the third graphics along the second direction; A fourth layout, the fourth layout including a plurality of fourth graphics and a plurality of second auxiliary graphics, the fourth graphics being parallel to the second direction, the fourth graphics corresponding to the second graphics, the fourth graphics penetrating the second graphics along the second direction, the second auxiliary graphics being located on both sides of the fourth graphics along the second direction.

11. The photomask layout according to claim 10, wherein, The spacing between adjacent ones of the third figures in the first direction is greater than or equal to a preset value; the spacing between adjacent ones of the fourth figures in the first direction is greater than or equal to a preset value.

12. The photomask layout according to claim 10, wherein, Further comprising: A fifth layout diagram, the fifth layout diagram includes a plurality of third figures, the third figures correspond to the first figures, and the spacing between adjacent ones of the third figures in the first direction is greater than or equal to a preset value.

13. The mask layout according to claim 10, wherein Further comprising: A sixth layout diagram, the sixth layout diagram includes a plurality of fourth figures, the fourth figures correspond to the second figures, and the spacing between adjacent ones of the fourth figures in the first direction is greater than or equal to a preset value.

14. The mask layout according to claim 10, wherein The size of the first auxiliary figure in the second direction includes: 1 / 2 of the minimum lithography pitch; the size of the second auxiliary figure in the second direction includes: 1 / 2 of the minimum lithography pitch.

15. The mask layout according to claim 10, wherein Adjacent ones of the first auxiliary figures are merged together in the second direction.

16. The mask layout according to claim 10, wherein Adjacent ones of the second auxiliary figures are merged together in the second direction.

17. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a plurality of mask layouts formed based on the mask layout diagram obtained by the method according to any one of claims 10 to 16, the plurality of mask layouts include a first type of mask layout and a second type of mask layout, the first type of mask layout includes a first mask layout and a second mask layout, the first mask layout is formed based on a first layout diagram, the second mask layout is formed based on a second layout diagram, the second type of mask layout includes a third mask layout and a fourth mask layout, the third mask layout is formed based on a third layout diagram, the fourth mask layout is formed based on a fourth layout diagram, the third mask layout corresponds to the first mask layout, and the fourth mask layout corresponds to the second mask layout; Providing a layer to be etched; Transferring the figures of the second type of mask template and the first type of mask layout with corresponding relationships to the layer to be etched in sequence, including: transferring the figure of the third mask layout corresponding to the first mask layout to the layer to be etched, then transferring the figure of the first mask layout to the layer to be etched, and forming a first groove in the layer to be etched, the first groove is parallel to the first direction, and the first direction is parallel to the surface of the layer to be etched; Transferring the figure of the fourth mask layout corresponding to the second mask layout to the layer to be etched, then transferring the figure of the second mask layout to the layer to be etched, and forming a second groove in the layer to be etched, the second groove is parallel to the first direction; Forming a first metal layer in the first groove; Forming a second metal layer in the second groove.

18. The method for forming a semiconductor structure according to claim 17, wherein The layer to be etched includes a substrate and a dielectric layer located on the substrate.

19. The method for forming a semiconductor structure according to claim 18, wherein, Transferring the figure of the third mask layout corresponding to the first mask layout to the layer to be etched, including: forming a first sacrificial layer on the layer to be etched; using the third mask layout to form a first mask structure on the first sacrificial layer, the first mask structure exposes a part of the surface of the first sacrificial layer; performing a modification treatment on the first sacrificial layer exposed by the first mask structure, and forming a plurality of first modified layers on the layer to be etched, the first modified layers are parallel to the second direction, the second direction is parallel to the surface of the layer to be etched, and the first direction is perpendicular to the second direction.

20. The method for forming a semiconductor structure according to claim 19, wherein, The first masking structure includes: a first cushion layer, a first anti-reflection layer located on the first cushion layer, and a first photoresist layer located on the first anti-reflection layer. The forming method of the first masking structure includes: forming a first cushion layer, a first anti-reflection layer located on the first cushion layer, and an initial photoresist layer located on the first anti-reflection layer on the first sacrificial layer; exposing the initial photoresist layer using the third mask plate, and then forming a first photoresist layer after development, the first photoresist layer exposing a part of the surface of the first anti-reflection layer; etching the first anti-reflection layer and the first cushion layer using the first photoresist layer as a mask until the surface of the first sacrificial layer is exposed, forming the first masking structure.

21. The method for forming a semiconductor structure according to claim 19, wherein, The process for modifying the first sacrificial layer exposed by the first masking structure includes: an ion implantation process; After forming a plurality of first modified layers, it further includes: removing the first masking structure.

22. The method for forming a semiconductor structure according to claim 19, wherein, Transferring the pattern of the first mask plate to the layer to be etched to form a first groove in the layer to be etched includes: forming a second masking structure on the first modified layer and the first sacrificial layer using the first mask plate, the second masking structure exposing a part of the surface of the first sacrificial layer and a part of the surface of the first modified layer; etching the exposed first sacrificial layer using the second masking structure as a mask to form a plurality of third grooves in the first sacrificial layer, the extending direction of the third grooves being parallel to the first direction, and the first modified layer penetrating the third grooves along the second direction; etching the dielectric layer using the first modified layer and the third grooves as a mask, the pattern of the third grooves being transferred downward to form a first groove in the dielectric layer, the extending direction of the first groove being parallel to the first direction, and the pattern of the first modified layer being transferred downward to form a first isolation layer penetrating the first groove.

23. The method for forming a semiconductor structure according to claim 22, wherein, The second masking structure includes: a second cushion layer, a second anti-reflection layer located on the second cushion layer, and a second photoresist layer located on the second anti-reflection layer. The forming method of the second masking structure includes: forming a second cushion layer, a second anti-reflection layer located on the second cushion layer, and an initial photoresist layer located on the second anti-reflection layer on the first sacrificial layer and the first modified layer; exposing the initial photoresist layer using the first mask plate, and then forming a second photoresist layer after development, the second photoresist layer exposing a part of the surface of the second anti-reflection layer; etching the second anti-reflection layer and the second cushion layer using the second photoresist layer as a mask until the surface of the first sacrificial layer is exposed, forming the second masking structure.

24. The method for forming a semiconductor structure according to claim 22, wherein The etching rate of the first sacrificial layer in the process of etching the exposed first sacrificial layer using the second masking structure as a mask is greater than the etching rate of the first modified layer.

25. The method for forming a semiconductor structure according to claim 18, wherein Transfer the pattern of the fourth mask corresponding to the second mask to the layer to be etched, including: forming a second sacrificial layer on the layer to be etched; using the fourth mask to form a third mask structure on the second sacrificial layer, and the third mask structure exposes part of the surface of the second sacrificial layer; performing a modification treatment on the second sacrificial layer exposed by the third mask structure to form a plurality of second modification layers on the layer to be etched, and the second modification layers are parallel to the second direction.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, Transfer the pattern of the second mask to the layer to be etched and form a second groove in the layer to be etched, including: using the second mask to form a fourth mask structure on the second modification layer and the second sacrificial layer, and the fourth mask structure exposes part of the surface of the second sacrificial layer and part of the surface of the second modification layer; etching the exposed second sacrificial layer with the fourth mask structure as a mask to form a plurality of fourth grooves in the second sacrificial layer, the extending direction of the fourth grooves is parallel to the first direction, and the second modification layer penetrates through the fourth grooves along the second direction; etching the dielectric layer with the second modification layer and the fourth grooves as masks, and the pattern of the fourth grooves is transferred downward to form a second groove in the dielectric layer, the extending direction of the second groove is parallel to the first direction, and the pattern of the second modification layer is transferred downward to form a second isolation layer penetrating through the second groove.

27. The method for forming a semiconductor structure according to claim 17, wherein, Form the first groove first, and then form the second groove; before forming the second groove, it further includes: forming a first filling layer in the first groove.

28. The method for forming a semiconductor structure according to claim 17, wherein, Form the second groove first, and then form the first groove; before forming the first groove, it further includes: forming a second filling layer in the second groove.

29. The method for forming a semiconductor structure according to claim 17, wherein, The second type of mask further includes a fifth mask, the fifth mask is formed based on a fifth layout pattern, and the fifth mask corresponds to the first mask; Before transferring the pattern of the first mask to the layer to be etched, it further includes: transferring the pattern of the fifth mask to the layer to be etched.

30. The method for forming a semiconductor structure according to claim 17, wherein, The second type of mask further includes a sixth mask, the sixth mask is formed based on a sixth layout pattern, and the sixth mask corresponds to the second mask; Before transferring the pattern of the second mask to the layer to be etched, it further includes: transferring the pattern of the sixth mask to the layer to be etched.

31. The method for forming a semiconductor structure according to claim 18, wherein The substrate includes: a substrate; a device layer located on the substrate, the device layer includes an isolation structure and a device structure located in the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

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