Frequency regulation method, power management controller and storage medium

Abstract

The invention provides a frequency adjustment method, a power management controller and a storage medium. The method comprises the following steps: acquiring a first working state and a core working frequency of a processor chip through a DVFS monitoring program every preset monitoring period; the method comprises the following steps: when a DVFS monitoring program represents a busy state in a first working state of a processor chip and the core working frequency of the processor chip is lower than a set frequency, increasing the core working frequency of the processor chip, and configuring a DVFS activation signal of a DVFS system to be at a first value; when the processor chip monitors that the task is triggered, the DVFS system is triggered, so that the DVFS system obtains a second working state of the processor chip and a DVFS activation signal; wherein the monitoring period is smaller than a triggering period of the processor chip monitoring task. Therefore, the probability of monitoring that the processor chip is in the busy working state can be increased, and the core working frequency of the processor chip can be improved in time.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a frequency adjustment method, a power management controller, and a storage medium. Background Art

[0002] The DVFS (Dynamic Voltage and Frequency Scaling) system is a technology that dynamically adjusts the operating voltage and frequency of a processor chip according to the workload of the processor chip to reduce power consumption while meeting performance requirements.

[0003] Currently, the DVFS system is usually mounted in the processor chip monitoring task of the power management control firmware. Among them, the power management control firmware is configured in the power management controller, and the processor chip monitoring task is used to obtain the power consumption and temperature of the processor chip. When the power management control firmware executes the processor chip monitoring task, that is, when the power management control firmware obtains the power consumption and temperature of the processor chip, the DVFS system will adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained by the power management control firmware.

[0004] However, since the power management control firmware executes the processor chip monitoring task according to a preset trigger period. Although the trigger period of the processor chip monitoring task is very short. However, for some special applications, such as applications with extremely short running times, or pulsed applications, the running of the special application may have ended before the trigger period of the processor chip monitoring task is reached. This makes it possible that during the running time of the special application, the DVFS system may not be activated in time to increase the frequency of the processor chip, resulting in a relatively low operating frequency of the processor chip and affecting the normal operation of the application. Summary of the Invention

[0005] The purpose of the embodiments of this application is to provide a frequency adjustment method, a power management controller, and a storage medium to solve the problem in the related art that the DVFS system cannot be activated in time to increase the frequency of the processor chip, thus affecting the normal operation of the application.

[0006] The embodiments of this application provide a frequency adjustment method applied to a power management controller. The power management controller is configured with power management control firmware, and the DVFS system is mounted in the processor chip monitoring task of the power management control firmware. A preset DVFS monitoring program is also mounted in the power management control firmware. The processor chip monitoring task is used to obtain the power consumption and temperature of the processor chip. The method includes:

[0007] Obtain the first working state and core working frequency of the processor chip through the DVFS monitoring program at every preset monitoring period;

[0008] When the first working state of the processor chip characterized by the DVFS monitoring program is a busy state and the core working frequency of the processor chip is lower than the set frequency, increase the core working frequency of the processor chip and configure the DVFS activation signal of the DVFS system to be at the first value;

[0009] When the monitoring task of the processor chip is triggered, trigger the DVFS system so that the DVFS system obtains the second working state of the processor chip and the DVFS activation signal;

[0010] Control the DVFS system to adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the monitoring task of the processor chip when the second working state of the processor chip is a busy state and the DVFS activation signal is at the first value; wherein, the monitoring period is less than the trigger period of the monitoring task of the processor chip.

[0011] In the above implementation process, by mounting the DVFS monitoring program in the power management control firmware, since the monitoring period of the DVFS monitoring program is less than the trigger period of the monitoring task of the processor chip, therefore, obtain the first working state and core working frequency of the processor chip through the DVFS monitoring program at every preset monitoring period. Compared with triggering the DVFS system when the monitoring task of the processor chip is triggered so that the DVFS system obtains the second working state of the processor chip and the DVFS activation signal, the working state of the processor chip characterized by a busy state can be monitored more timely. At the same time, since the DVFS monitoring program will increase the core working frequency of the processor chip when the first working state of the processor chip is a busy state and the core working frequency of the processor chip is lower than the set frequency, in this way, through the DVFS monitoring program, not only can the probability of monitoring the working state of the processor chip in a busy state be increased, but also the core working frequency of the processor chip can be increased when the processor chip is monitored to be in a busy state, thereby reducing the probability of not being able to increase the core working frequency of the processor chip in time.

[0012] Furthermore, the processor chip includes a plurality of hardware components. Obtaining the first working state of the processor chip through the DVFS monitoring program at every preset monitoring period includes:

[0013] The working status of each of the hardware components is obtained every other monitoring period through the DVFS monitoring program; the working status corresponding to the hardware component characterizes the first working status of the processor chip;

[0014] Correspondingly, when the first working status of the processor chip characterizes a busy state and the core working frequency of the processor chip is lower than the set frequency, increasing the core working frequency of the processor chip includes:

[0015] When the working status corresponding to any one of the hardware components characterizes a busy state and the core working frequency of the processor chip is lower than the set frequency, increasing the core working frequency of the processor chip.

[0016] In the above implementation process, by obtaining the working status of each hardware component in the processor chip, and when the working status corresponding to any one of the hardware components characterizes a busy state and the core working frequency of the processor chip is lower than the set frequency, the core working frequency of the processor chip is adjusted according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task. Since the hardware components exist in the processor chip, the working status of the processor chip actually depends on the working status of the hardware components. Therefore, by obtaining the working status of the hardware components to determine the working status of the processor chip can be more representative, and then the working status of the processor chip can be obtained more accurately, and it can be more accurately determined whether the core working frequency of the processor chip needs to be increased.

[0017] Further, the processor chip monitoring task is triggered by a timer; the monitoring period is determined according to the time unit used by the timer.

[0018] In the above implementation process, by using a timer to trigger the processor chip monitoring task, it can be ensured that the processor chip monitoring task is executed at a specified time point. Since the DVFS system is mounted in the processor chip monitoring task, when the processor chip monitoring task is triggered, the DVFS system will also be triggered. Therefore, this can also ensure that the DVFS system is carried out at a specified time point and ensure the controllability of the DVFS system.

[0019] Further, increasing the core working frequency of the processor chip through the DVFS monitoring program includes:

[0020] The core working frequency of the processor chip is increased to the set frequency through the DVFS monitoring program.

[0021] In the above implementation process, the core operating frequency of the processor chip is increased to the set frequency through the DVFS monitoring program. Since the DVFS monitoring program represents a busy state in the first operating state of the processor chip, and the core operating frequency of the processor chip is lower than the set frequency, the core operating frequency of the processor chip is increased to the set frequency. In this way, when the processor chip is in a busy state, the core operating frequency of the processor chip can be directly increased to the set frequency, thereby improving the performance of the processor chip to better ensure the operation of the application.

[0022] Further, increasing the core operating frequency of the processor chip through the DVFS monitoring program includes:

[0023] Judging, by the DVFS monitoring program, whether the sum of the core operating frequency and the preset increment exceeds a preset threshold;

[0024] If not, increasing the core operating frequency by the preset increment through the DVFS monitoring program;

[0025] If it exceeds, adjusting the core operating frequency to the preset threshold through the DVFS monitoring program.

[0026] In the above implementation process, by using the DVFS monitoring program to judge whether the sum of the core operating frequency and the preset increment exceeds the preset threshold, and directly adjusting the core operating frequency to the preset threshold when the sum of the core operating frequency and the preset increment exceeds the preset threshold. In this way, it can be ensured that the core operating frequency of the processor chip does not exceed the preset threshold. This can not only improve the working performance of the processor chip, but also reduce the breakdown phenomenon caused by a large instantaneous power consumption in the subsequent case of adjusting the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task by the DVFS system.

[0027] In addition, when the sum of the core operating frequency and the preset increment does not exceed the preset threshold, directly increasing the preset increment to the core operating frequency can improve the performance of the processor chip to better ensure the operation of the application.

[0028] Further, the preset threshold is the set frequency.

[0029] In the above implementation process, by setting the set frequency as the preset threshold, it can be ensured that the core operating frequency of the processor chip does not exceed the set frequency when increasing the core operating frequency of the processor chip through the DVFS monitoring program.

[0030] Further, when controlling the DVFS system to characterize the second working state of the processor chip as a busy state and the DVFS activation signal is in the first value, after adjusting the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task, the method further includes:

[0031] When controlling the DVFS system to characterize the second working state of the processor chip as an idle state every time the DVFS system obtains it within a preset duration, configure the DVFS activation signal to be in the second value; when the DVFS activation signal is in the second value, the DVFS system does not adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task.

[0032] In the above implementation process, when controlling the DVFS system to characterize the second working state of the processor chip as a busy state and the DVFS activation signal is in the first value, after adjusting the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task, when controlling the DVFS system to characterize the second working state of the processor chip as an idle state every time the DVFS system obtains it within a preset duration, configure the DVFS activation signal to be in the second value. Since when the DVFS system characterizes the second working state of the processor chip as an idle state every time the DVFS system obtains it within a preset duration, it means that there is no need to control the DVFS system to adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task. At this time, configuring the DVFS activation signal to be in the second value can control the DVFS system not to adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task, thereby reducing waste of resources.

[0033] In a second aspect, an embodiment of the present application further provides a power management controller, which is configured to be connected to a processor chip, and the power management controller includes a storage unit and an execution unit; a power management control firmware, a DVFS system, and a DVFS monitoring program are stored in the storage unit; when the power management control firmware is read and executed by the execution unit, it will execute multiple tasks including a processor chip monitoring task, the DVFS system is mounted in the processor chip monitoring task, and the execution unit is further configured to read and execute the DVFS system and the DVFS monitoring program to implement the frequency adjustment method as described above.

[0034] In a third aspect, an embodiment of the present application further provides a storage medium storing a power management control firmware, a DVFS system, and a DVFS monitoring program. The DVFS system is mounted in the processor chip monitoring task of the power management control firmware. When the power management control firmware is executed, it will execute multiple tasks including the processor chip monitoring task. When the DVFS system and the DVFS monitoring program are executed, they implement the frequency adjustment method as described above. Description of the Drawings

[0035] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0036] Figure 1 It is a schematic structural diagram of a power management control firmware provided by an embodiment of the present application;

[0037] Figure 2 It is a schematic structural diagram of a power management controller provided by an embodiment of the present application;

[0038] Figure 3 It is a schematic flowchart of a frequency adjustment method provided by an embodiment of the present application;

[0039] Figure 4 It is a schematic structural diagram of a DVFS system provided by an embodiment of the present application;

[0040] Figure 5 It is a graph showing the change curve of the core working frequency over time and the change curve of the running state of the application over time provided by an embodiment of the present application;

[0041] Figure 6 It is a graph showing the change curve of the core working frequency over time and the change curve of the running state of the application over time provided by an embodiment of the present application. Detailed Embodiments

[0042] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application.

[0043] In the embodiment of the present application, the DVFS system is mounted in the processor chip monitoring task of the power management control firmware. The power management control firmware is configured in the power management controller.

[0044] Combined with Figure 1As shown, the power management control firmware 203 may include multiple tasks. Tasks in the power management control firmware include, for example, interrupt signal reception, mailbox request reception, performance monitoring tasks, voltage and temperature monitoring tasks, etc. Among them, interrupt signal reception is used to receive the interrupt signals generated by the processor chip. Mailbox request processing is used to receive mailbox requests. Mailbox requests are used to achieve asynchronous communication between different hardware components. Performance monitoring tasks may include storage firmware monitoring tasks and processor chip monitoring tasks, etc. The storage firmware monitoring task is used to obtain the operating voltage and power consumption of the storage system, etc. The processor chip monitoring task is used to obtain the power consumption and core temperature of the processor chip. The processor chip monitoring task can also be used to obtain the power consumption of the board. The voltage and temperature monitoring task is used to obtain the operating voltage and core temperature of the processor chip.

[0045] Exemplarily, there may be multiple processor chips on the board. In the case of multiple processor chips, the processor chip monitoring task is used to obtain the power consumption and core temperature of each processor chip. In the case where there is only one processor chip on the board, the processor chip monitoring task is used to obtain the power consumption and core temperature of the processor chip. And the power consumption of this processor chip is the power consumption of the board.

[0046] Moreover, a corresponding trigger period can be set for each task, and the trigger period of each task can be implemented by a trigger. That is, when the trigger period corresponding to each task is reached, the corresponding task will be triggered to execute. Since in the power management control firmware, not all tasks need to be executed at all times, for tasks that are executed periodically, a corresponding trigger period can be set to disperse the execution time of multiple tasks. That is, at a certain time point, only one or more tasks are executed, rather than all tasks, thereby ensuring the efficient execution of tasks.

[0047] In some embodiments, the periodically executed task can be the storage firmware monitoring task, and the trigger period corresponding to the storage firmware monitoring task can be Time1. The periodically executed task can be the processor chip monitoring task, and the trigger period corresponding to the processor chip monitoring task can be Time2.

[0048] Since the processor chip monitoring task is triggered only when the corresponding trigger period is reached, and the DVFS system is mounted in the processor chip monitoring task, the execution period of the DVFS system is essentially the same as the trigger period of the processor chip monitoring task. Although the trigger period of the processor chip monitoring task is very short, for some special applications, such as applications with extremely short running times, that is, the execution duration of the application may last for several milliseconds; or pulse-type applications, that is, the application returns to a long-term static state after running for several milliseconds and repeats this process. Therefore, during the operation of the characteristic application, the trigger period of the processor chip monitoring task may not be reached. This may prevent the DVFS system from being activated in a timely manner to increase the frequency of the processor chip during the operation of the special application, resulting in a relatively low operating frequency of the processor chip and affecting the normal operation of the application.

[0049] To solve the above problem that the DVFS system cannot be activated in a timely manner to increase the frequency of the processor chip, thus affecting the normal operation of the application, the embodiment of the present application provides a frequency adjustment method applied to a power management controller. Combined with Figure 2 as shown in Figure 2 FIG. is a schematic structural diagram of a power management controller provided by an embodiment of the present application. The power management controller 200 is configured to be connected to a processor chip. And the power management controller includes a storage unit 201 and an execution unit 202. The storage unit 201 stores power management control firmware 203, a DVFS monitoring program 204, and a DVFS system 400. When the power management control firmware is read and executed by the execution unit, it will execute multiple tasks including the processor chip monitoring task, and the DVFS system is mounted in the processor chip monitoring task. The execution unit is further configured to read and execute the DVFS system and the DVFS monitoring program to implement the frequency adjustment method provided by the embodiment of the present application.

[0050] The execution unit can be other circuits in the power management controller that can be programmed and run. And the storage unit can be a hardware register, a non-volatile memory, or a volatile memory.

[0051] In the power management controller provided by the embodiment of the present application, since the monitoring period of the DVFS monitoring program is shorter than the trigger period of the processor chip monitoring task, when the execution unit executes the DVFS monitoring program, the probability of monitoring that the processor chip is in a busy working state can be increased, and the core working frequency of the processor chip can be timely increased, thereby reducing the probability of not being able to timely increase the core working frequency of the processor chip.

[0052] Embodiment 1

[0053] Combined with Figure 3As shown in the figure, an embodiment of the present application provides a frequency adjustment method, which is applied to a power management controller such as Figure 1 and Figure 3 is a schematic flowchart of the frequency adjustment method provided in the embodiment of the present application, including:

[0054] Step S301, the DVFS monitoring program obtains the first working state and the core working frequency of the processor chip at every preset monitoring period.

[0055] In an alternative implementation manner of the embodiment of the present application, the working states of each hardware component can be obtained by the DVFS monitoring program at every monitoring period; the working state corresponding to the hardware component represents the first working state of the processor chip.

[0056] Exemplarily, the DVFS monitoring program can send a first state acquisition instruction to each hardware component at every monitoring period to trigger each hardware component to feedback the working state. Since the hardware components exist in the processor chip, the working state of the processor chip actually depends on the working state of the hardware components.

[0057] And when the working state of the hardware component represents a busy state, it can be considered that the processor chip is called, that is, the processor chip is also in a busy state. In some embodiments, the processor chip can be a GPU (Graphics Processing Unit). Therefore, by obtaining the working state of the hardware component to determine the working state of the processor chip can be more representative, and thus the working state of the processor chip can be obtained more accurately.

[0058] The core working frequency of the processor chip is the frequency of the internal clock signal of the processor chip, which is used to represent the number of operations that the processor chip can execute per second. And. The performance of the processor chip is proportional to the core working frequency of the processor chip. Correspondingly, when the core working frequency of the processor chip is larger, the number of operations that the processor chip can execute per second is more, and the performance of the processor chip is better. When there are multiple processor chips, the core working frequencies of each processor chip can be obtained by the DVFS monitoring program.

[0059] Step S302, when the first working state of the processor chip represents a busy state and the core working frequency of the processor chip is lower than the set frequency, the DVFS monitoring program increases the core working frequency of the processor chip and configures the DVFS activation signal of the DVFS system to be in the first value.

[0060] Correspondingly, in the case where the operating state of the hardware component represents the first operating state of the processor chip, if the operating state of any hardware component represents a busy state, it can be determined that the processor chip is in a busy state. And, when the core operating frequency of the processor chip is lower than the set frequency, the core operating frequency of the processor chip can be increased.

[0061] In addition, if there are multiple processor chips, based on obtaining the core operating frequency of each processor chip, the core operating frequency of the processor chips with a core operating frequency lower than the set frequency can be increased.

[0062] In an alternative implementation manner of the embodiment of the present application, the core operating frequency of the processor chip can be increased to the set frequency through the DVFS monitoring program. Since the DVFS monitoring program increases the core operating frequency of the processor chip to the set frequency only when the first operating state of the processor chip represents a busy state and the core operating frequency of the processor chip is lower than the set frequency. In this way, when the processor chip is in a busy state, the core operating frequency of the processor chip can be directly increased to the set frequency, thereby improving the performance of the processor chip to better ensure the operation of the applications loaded on the processor chip.

[0063] In an alternative implementation manner of the embodiment of the present application, the DVFS monitoring program can increase the core operating frequency by a preset increment when the sum of the core operating frequency and the preset increment does not exceed the preset threshold.

[0064] Since the DVFS monitoring program determines whether the sum of the core operating frequency and the preset increment exceeds the preset threshold only when the first operating state of the processor chip represents a busy state and the core operating frequency of the processor chip is lower than the set frequency, and increases the core operating frequency by the preset increment only when the sum of the core operating frequency and the preset increment does not exceed the preset threshold. In this way, when it is detected that the processor chip is in a busy state, increasing the core operating frequency of the processor chip can achieve the effect of improving the performance of the processor chip. And, since the monitoring period of the DVFS monitoring program is less than the triggering period of the processor chip monitoring task, by obtaining the first operating state of the processor chip through the DVFS monitoring program, the operating state of the processor chip representing a busy state can be monitored more timely. Thus, the core operating frequency of the processor chip can be increased more timely, and the performance of the processor chip can be improved more timely to better meet the performance requirements of the applications loaded on the processor chip for the processor chip.

[0065] In an alternative implementation of the embodiment of the present application, when the sum of the core operating frequency and the preset increment exceeds the preset threshold through the DVFS monitoring program, the core operating frequency can be adjusted to the preset threshold. When the sum of the core operating frequency and the preset increment exceeds the preset threshold through the DVFS monitoring program, the core operating frequency can be directly adjusted to the preset threshold. In this way, it can be ensured that the core operating frequency of the processor chip does not exceed the preset threshold, which can not only improve the working performance of the processor chip, but also reduce the breakdown phenomenon caused by large instantaneous power consumption when the core operating frequency of the processor chip is adjusted according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task by the DVFS system subsequently.

[0066] In this embodiment, the preset threshold can be a set frequency. When the preset threshold is a set frequency, when increasing the core operating frequency of the processor chip through the DVFS monitoring program, it can be ensured that the core operating frequency of the processor chip does not exceed the set frequency.

[0067] Alternatively, the difference between the preset threshold and the set frequency can be within a preset range. When the difference between the preset threshold and the set frequency is within the preset range, when increasing the core operating frequency of the processor chip through the DVFS monitoring program, it can be ensured that the difference between the maximum core operating frequency of the processor chip and the set frequency is within the preset range. Thus, the purpose of controlling the core operating frequency of the processor chip can be achieved.

[0068] Exemplarily, when the core operating frequency of the processor chip is equal to the set frequency, in all the applications loaded on the processor chip, the power consumption of more than a preset proportion of the applications is less than the power consumption wall, while the power consumption of the remaining applications exceeds the power consumption wall, and the difference between the power consumption of all applications and the power consumption wall is within a preset power consumption range. The preset proportion is, for example, 80%. Therefore, increasing the core operating frequency of the processor chip to the set frequency through the DVFS monitoring program can not only improve the performance of the processor chip, but also reduce the power-off phenomenon caused by large instantaneous power consumption when the core operating frequency of the processor chip is adjusted according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task by the DVFS system subsequently.

[0069] Step S303, when the processor chip monitoring task is triggered, trigger the DVFS system so that the DVFS system obtains the second working state and the DVFS activation signal of the processor chip.

[0070] The DVFS system is triggered when the processor chip monitoring task is triggered. Therefore, the cycle for the DVFS system to obtain the second working state and the DVFS activation signal of the processor chip is essentially the trigger cycle of the processor chip monitoring task.

[0071] The first working state and the second working state of the processor chip are both the working states of the processor chip. The first working state is the working state of the processor chip obtained by the DVFS monitoring program. The second working state is the working state of the processor chip obtained by the DVFS system. If the DVFS monitoring program and the DVFS system obtain the working state of the processor chip at the same moment, the first working state and the second working state are the same.

[0072] Exemplarily, the processor chip monitoring task is triggered by a timer. In some embodiments, the trigger period of the processor chip monitoring task is, for example, 4 milliseconds. When the timing duration of the timer is equal to 4 milliseconds, the processor chip monitoring task is triggered to obtain the power consumption and temperature of the processor chip. And, the timing duration of the timer will be reset to zero to start timing again. So that when the next timing duration is equal to 4 milliseconds, the processor chip monitoring task is triggered again, thereby realizing the periodic operation of the processor chip monitoring task.

[0073] The monitoring period is determined according to the timing unit used by the timer. Exemplarily, the monitoring period can be equal to the unit timing duration of the timer. Or, the monitoring period can also be any value within a preset duration range. Wherein, the lower limit of the value range of the preset duration range is the unit timing duration of the timer, and the upper limit of the value range of the preset duration range is the trigger period of the processor chip monitoring task. In this way, the monitoring period can be less than the trigger period of the processor chip monitoring task.

[0074] Step S304, control the DVFS system to adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task when the second working state of the processor chip represents a busy state and the DVFS activation signal is at the first value. Wherein, the monitoring period is less than the trigger period of the processor chip monitoring task.

[0075] Step S305, control the DVFS system to configure the DVFS activation signal to be at the second value when the second working state of the processor chip obtained each time within a preset duration represents an idle state. When the DVFS activation signal is at the second value, the DVFS system does not adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task.

[0076] In an alternative implementation manner of the embodiment of the present application, the above step S305 can be replaced by: controlling the DVFS system to configure the DVFS activation signal to be at the second value when the second working state of the processor chip obtained within a continuous preset number of times represents an idle state.

[0077] The frequency adjustment method provided by the embodiments of the present application mounts a DVFS monitoring program in the power management control firmware. Since the monitoring period of the DVFS monitoring program is less than the triggering period of the processor chip monitoring task, the DVFS monitoring program obtains the first working state and the core working frequency of the processor chip every preset monitoring period. Compared with triggering the DVFS system when the processor chip monitoring task is triggered to enable the DVFS system to obtain the second working state and the DVFS activation signal of the processor chip, it can more timely monitor the working state indicating the busy state of the processor chip. At the same time, since the DVFS monitoring program increases the core working frequency of the processor chip when the first working state of the processor chip indicates a busy state and the core working frequency of the processor chip is lower than the set frequency, in this way, the DVFS monitoring program can not only increase the probability of monitoring the working state of the processor chip in a busy state, but also increase the core working frequency of the processor chip when it is monitored that the processor chip is in a busy state, thereby reducing the probability of not being able to increase the core working frequency of the processor chip in time.

[0078] Embodiment 2

[0079] On the basis of Embodiment 1, the embodiments of the present application provide a DVFS system. Combining Figure 4 with the structural schematic diagram of the DVFS system shown. The DVFS system 400 includes an activation monitoring unit 401, an information processing unit 402, a logic processing unit 403, and a frequency and voltage processing unit 404.

[0080] Among them, the activation monitoring unit 401 is configured to obtain the second working state and the DVFS activation signal of the processor chip.

[0081] Exemplarily, when the processor chip monitoring task is triggered, the activation monitoring unit is triggered to send a second state acquisition instruction to each hardware component in the processor chip, triggering each hardware component to feedback the working state. The working state fed back by each hardware component upon receiving the second state acquisition instruction is the second working state of the processor chip.

[0082] The information processing unit 402 is configured to obtain target parameters, where the target parameters are the power consumption and temperature of the processor chip obtained in the processor chip monitoring task.

[0083] The logic processing unit 403 is configured to determine the target working frequency of the processor chip according to the target parameters and send the target working frequency to the frequency and voltage processing unit.

[0084] The logic processing unit 403 can also be configured to determine the target voltage of the processor chip according to the target parameters and send the target voltage to the frequency and voltage processing unit.

[0085] Exemplarily, the logic processing unit 403 may perform a matching operation using the target parameter in the correspondence relationship between the preset target parameter, target voltage, and target operating frequency to obtain the target voltage and target operating frequency.

[0086] Optionally, the logic processing unit 403 may perform a matching operation using the target parameter in the correspondence relationship between the preset target parameter and voltage - frequency level to obtain the target voltage - frequency level. The logic processing unit 403 may further perform a matching operation using the target voltage - frequency level in the association relationship between the preset voltage - frequency level, target voltage, and target operating frequency to obtain the target voltage and target operating frequency.

[0087] Alternatively, the logic processing unit 403 may directly send the target voltage - frequency level to the frequency - voltage processing unit 404.

[0088] The frequency - voltage processing unit 404 is configured to adjust the core operating frequency of the processor chip according to the target operating frequency.

[0089] Correspondingly, the frequency - voltage processing unit 404 may also be configured to adjust the operating voltage of the processor chip according to the target voltage.

[0090] In this embodiment, if the frequency - voltage processing unit 404 receives the target voltage and target operating frequency, the frequency - voltage processing unit 404 may adjust the operating voltage and core operating frequency of the processor chip according to the target voltage and target operating frequency respectively.

[0091] If the frequency - voltage processing unit 404 receives the target voltage - frequency level, before the frequency - voltage processing unit 404 adjusts the operating voltage and core operating frequency of the processor chip according to the target voltage and target operating frequency respectively, the frequency - voltage processing unit 404 may perform a matching operation using the target voltage - frequency level in the association relationship between the preset voltage - frequency level, target voltage, and target operating frequency to obtain the target voltage and target operating frequency.

[0092] Embodiment III

[0093] Based on the above - mentioned embodiment, this embodiment further gives an illustrative example of the present application.

[0094] Exemplarily, in combination with Figure 5 the curve of the core operating frequency changing with time and the curve of the running state of the application changing with time as shown, where the processor chip is, for example, Chip A. In Chip A, Application B is loaded, and the running duration of Application B is 8 milliseconds. Figure 5 The line a in

[0095] In the power management control firmware, the trigger period of the processor chip monitoring task is, for example, 4 milliseconds. The monitoring period is, for example, 1 millisecond.

[0096] When the processor chip control task is triggered, the DVFS system will obtain the operating state of Chip A. If Application B enters the running state when the processor chip monitoring task ends. Then the DVFS system will obtain that Chip A is busy only when Application B has been running for 4 milliseconds, and will adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task, so as to increase the core operating frequency of the processor chip to the first frequency Fmax. Figure 5 Line b in [description] is the curve of the core operating frequency of the processor chip changing with time when the operating frequency of the processor chip is adjusted by the DVFS system. Since the DVFS system is mounted in the processor chip monitoring task of the power management control firmware. Therefore, the trigger of the DVFS system is triggered according to the trigger of the processor chip monitoring task. If Application B enters the running state when the processor chip monitoring task ends. Since the trigger period of the processor chip monitoring task is 4 milliseconds. Then when Application B enters the running state, the processor chip monitoring task will not be triggered again until 4 milliseconds later. Correspondingly, the DVFS system will also not be triggered until 4 milliseconds later. Then the DVFS system will obtain that Chip A is busy only when Application B has been running for 4 milliseconds. It can be seen that the DVFS system cannot be activated in time at the start of the running of Application B and increase the core operating frequency of Chip A.

[0097] When the core operating frequency of Chip A is adjusted according to the frequency adjustment method provided in the embodiments of the present application. The DVFS monitoring program will obtain the operating state of Chip A every 1 millisecond of the monitoring period. If Application B starts running when the previous monitoring period ends, then the DVFS monitoring program will obtain that Chip A is busy when Application B has been running for 1 millisecond. And increase the core operating frequency of Chip A to the set frequency Fbase, and at the same time configure the DVFS activation signal of the DVFS system to be at the first value. It can be seen that Application B has only been running for 1 millisecond before the core operating frequency of the processor chip increases. Thus, the effect of quickly increasing the core operating frequency of the processor chip can be achieved.

[0098] In addition, in the frequency adjustment method provided in the embodiments of the present application, when the DVFS system has been running Application B for 4 milliseconds, it obtains that Chip A is in a busy state and the DVFS activation signal is at a first value. The DVFS system can adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task, so as to increase the core operating frequency of the processor chip to a first frequency Fmax. Thus, the curve shown by line c in Figure 5 is obtained. Among them, line c represents the curve of the change of the core operating frequency of the processor chip over time obtained according to the frequency adjustment method provided in the embodiments of the present application.

[0099] Exemplarily, in combination with Figure 6 the curve of the change of the core operating frequency over time and the curve of the change of the running state of the application over time are shown. Among them, the processor chip is, for example, Chip A. In Chip A, Application C is loaded, and the running duration of Application C is 3 milliseconds. Figure 6 Line a in

[0100] represents the curve of the change of the running state of Application C over time.

[0101] In the power management control firmware, the trigger period of the processor chip monitoring task is, for example, 4 milliseconds. The monitoring period is, for example, 1 millisecond.

[0101] When the processor chip control task is triggered, the DVFS system will obtain the working state of Chip A. If Application C enters the running state when the processor chip monitoring task is triggered and ends. Then the DVFS system will obtain the working state of Chip A only when Application C runs to the end. Since Application C has been running, at this time, the working state of Chip A represents an idle state. The DVFS system will not adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task, so the core operating frequency of the processor chip has been at a second frequency, that is, Fidle. Figure 6The line C in [description] is the curve of the core operating frequency of the processor chip changing with time under the condition of adjusting the operating frequency of the processor chip using the existing DVFS system. Since the DVFS system is mounted in the processor chip monitoring task of the power management control firmware, the triggering of the DVFS system is triggered according to the triggering of the processor chip monitoring task. If the C application enters the running state when the triggering of the processor chip monitoring task ends. Since the triggering period of the processor chip monitoring task is 4 milliseconds. Then when the C application enters the running state, the processor chip monitoring task will not be triggered again until 4 milliseconds later. Correspondingly, the DVFS system will also not be triggered until 4 milliseconds later. And the running duration of the C application is only 3 milliseconds. Therefore, the DVFS system will only obtain the working state of chip A again when the C application finishes running. It can be seen that the existing DVFS system cannot monitor the working state of chip A when the C application is running, resulting in the failure to increase the core operating frequency of chip A during the running process of the C application. The core operating frequency of chip A is the first frequency Fidle, that is, as Figure 6 shown by the curve of the core operating frequency changing with time in [description].

[0102] When adjusting the core operating frequency of chip A according to the frequency adjustment method provided in the embodiments of the present application. Although the DVFS system still obtains the working state of chip A only when the C application has finished running, and obtains that the DVFS activation signal is at the first value. Similarly, the DVFS system will not adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task.

[0103] However, since the DVFS monitoring program obtains the working state of chip A every 1 millisecond of the monitoring period. If the C application starts running at the end of the previous monitoring period, then the DVFS monitoring program will obtain that chip A is in the busy state when the C application has run for 1 millisecond. And increase the core operating frequency of chip A from the first frequency Fidle to the set frequency Fbase, and at the same time configure the DVFS activation signal of the DVFS system to be at the first value. Thus obtaining the curve shown in Figure 6 [description]. The line c represents the curve of the core operating frequency of the processor chip changing with time obtained according to the frequency adjustment method provided in the embodiments of the present application. It can be seen that the C application has only run for 1 millisecond before the core operating frequency of the processor chip increases. Thus, it is possible to timely increase the core operating frequency of the processor chip during the running process of the C application, so as to meet the performance requirements of the C application for chip A.

[0104] Based on the same inventive concept, this embodiment also provides a storage medium, such as a floppy disk, an optical disc, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc. In this storage medium, there are stored a power management control firmware, a DVFS system, and a DVFS monitoring program. The DVFS system is mounted in the processor chip monitoring task of the power management control firmware. When the power management control firmware is executed, it will execute multiple tasks including the processor chip monitoring task. When the DVFS system and the DVFS monitoring program are executed, they are used to implement the above frequency adjustment method. Details are not described herein again.

[0105] In the embodiments provided in this application, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0106] In addition, the units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] Furthermore, in each embodiment of this application, the various functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0108] In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0109] In this article, "a plurality of" means two or more.

[0110] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A frequency adjustment method, characterized in that, Applied to a power management controller, a power management control firmware is configured in the power management controller, a DVFS system is mounted in the processor chip monitoring task of the power management control firmware, and a preset DVFS monitoring program is also mounted in the power management control firmware. The processor chip monitoring task is used to obtain the power consumption and temperature of the processor chip. The method includes: Obtaining, by the DVFS monitoring program, the first working state and the core working frequency of the processor chip at intervals of a preset monitoring period; When the first working state of the processor chip characterized by the DVFS monitoring program is a busy state and the core working frequency of the processor chip is lower than the set frequency, increasing the core working frequency of the processor chip and configuring the DVFS activation signal of the DVFS system to be at a first value; When the processor chip monitoring task is triggered, triggering the DVFS system so that the DVFS system obtains the second working state of the processor chip and the DVFS activation signal; Controlling the DVFS system to adjust the core working frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task when the second working state of the processor chip characterized by the DVFS system is a busy state and the DVFS activation signal is at the first value; wherein, the monitoring period is less than the trigger period of the processor chip monitoring task.

2. The method according to claim 1, characterized in that The processor chip includes a plurality of hardware components. Obtaining, by the DVFS monitoring program, the first working state of the processor chip at intervals of a preset monitoring period includes: Obtaining, by the DVFS monitoring program, the working states of the respective hardware components at intervals of the monitoring period; the working state corresponding to the hardware component characterizes the first working state of the processor chip; Correspondingly, when the first working state of the processor chip characterized by the DVFS monitoring program is a busy state and the core working frequency of the processor chip is lower than the set frequency, increasing the core working frequency of the processor chip includes: When the working state corresponding to any one of the hardware components is a busy state and the core working frequency of the processor chip is lower than the set frequency, increasing the core working frequency of the processor chip.

3. The method according to claim 1, characterized in that, The processor chip monitoring task is triggered by a timer; the monitoring period is determined according to the timing unit used by the timer.

4. The method according to claim 3, wherein The monitoring period is equal to the unit timing duration of the timer.

5. The method according to any one of claims 1 to 4, characterized in that, Increasing the core working frequency of the processor chip by the DVFS monitoring program includes: Increasing the core working frequency of the processor chip to the set frequency by the DVFS monitoring program.

6. The method according to any one of claims 1 to 4, characterized in that Increasing the core working frequency of the processor chip by the DVFS monitoring program includes: Judging, by the DVFS monitoring program, whether the sum of the core working frequency and a preset increment exceeds a preset threshold; If not, increasing the core working frequency by the preset increment by the DVFS monitoring program; If it exceeds, the core operating frequency is adjusted to the preset threshold by the DVFS monitoring program.

7. The method according to claim 6, characterized in that, The preset threshold is the set frequency.

8. The method according to any one of claims 1 to 4, characterized in that, After controlling the DVFS system to adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task when the second operating state of the processor chip represented by the DVFS system is in a busy state and the DVFS activation signal is at a first value, the method further includes: Controlling the DVFS system to configure the DVFS activation signal to be at a second value when the second operating state of the processor chip obtained each time within a preset duration is in an idle state; when the DVFS activation signal is at the second value, the DVFS system does not adjust the core operating frequency of the processor chip according to the power consumption and temperature of the processor chip obtained in the processor chip monitoring task.

9. A power management controller, characterized in that, The power management controller is configured to be connected to the processor chip, and the power management controller includes a storage unit and an execution unit; the storage unit stores power management control firmware, a DVFS system, and a DVFS monitoring program; the power management control firmware, when read and executed by the execution unit, executes multiple tasks including the processor chip monitoring task, the DVFS system is mounted in the processor chip monitoring task, and the execution unit is further configured to read and execute the DVFS system and the DVFS monitoring program to implement the frequency adjustment method according to any one of claims 1 to 8.

10. A storage medium, characterized in that, Stores power management control firmware, a DVFS system, and a DVFS monitoring program. The DVFS system is mounted in the processor chip monitoring task of the power management control firmware. When the power management control firmware is executed, it executes multiple tasks including the processor chip monitoring task. When the DVFS system and the DVFS monitoring program are executed, they implement the frequency adjustment method according to any one of claims 1 to 8.

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