Memory management method, memory storage device and memory control circuit unit

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the steps that according to first data, multi-stage programming is executed on a plurality of entity units in a rewritable nonvolatile memory module, and the multi-stage programming comprises first-stage programming and second-stage programming; before the execution of the multi-stage programming is started and the completion of the second-stage programming, storing second data, the second data being generated by encoding the first data; and adjusting the reading operation or the programming operation of at least one of the plurality of entity units according to the second data. Therefore, the working performance of the memory storage device can be improved.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a memory management method, a memory storage device, and a memory control circuit unit. Background Art

[0002] In recent years, the growth of portable electronic devices such as mobile phones and notebook computers has been very rapid, which has led to a rapid increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (e.g., flash memory) have the characteristics of data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable electronic devices exemplified above.

[0003] Generally speaking, in order to avoid the loss of incompletely stored data due to accidental power-off during the data writing period of a memory storage device, the memory storage device will back up the to-be-stored data that has not been completely stored. Once an accidental power-off occurs during the data writing period, after the memory storage device is powered on again, this backup data can be used to re-execute the writing operation for the original to-be-stored data. However, as the amount of data written in each write operation becomes larger and larger, the amount of data that needs to be backed up also becomes larger, resulting in excessive occupation of system resources. Summary of the Invention

[0004] The present invention provides a memory management method, a memory storage device, and a memory control circuit unit, which can improve the above problems.

[0005] An embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module. The memory management method includes: performing multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, where the multi-stage programming includes first-stage programming and second-stage programming; saving second data before starting to execute the multi-stage programming and before the second-stage programming is completed, where the second data is generated by encoding the first data; and adjusting a read operation or a programming operation of at least one of the plurality of physical units according to the second data.

[0006] In an exemplary embodiment of the present invention, the plurality of physical units belong to the same word line.

[0007] In an exemplary embodiment of the present invention, the plurality of physical units at least include an upper physical programming unit and a lower physical programming unit.

[0008] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0009] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: detecting an abnormal power-off event before the completion of the second-stage programming after the completion of the first-stage programming; and after the abnormal power-off event is restored, adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0010] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result.

[0011] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result includes: adjusting a first parameter for the read operation or the programming operation according to a first threshold voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; and adjusting a second parameter for the read operation or the programming operation according to a second threshold voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

[0012] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: adjusting at least one of a read voltage level, a programming voltage level, and a decoding parameter corresponding to at least one of the plurality of physical units according to the second data.

[0013] In an exemplary embodiment of the present invention, the memory management method further includes: generating the second data in response to an abnormal power-off event before the completion of the second-stage programming.

[0014] In an exemplary embodiment of the present invention, the memory management method further includes: correcting third data read from at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0015] In an exemplary embodiment of the present invention, the memory management method further includes: not saving the second data for the plurality of physical units that have completed the second-stage programming.

[0016] In an exemplary embodiment of the present invention, in the multi-stage programming performed on the plurality of physical units, the programming voltage level for the first-stage programming is different from the programming voltage level for the second-stage programming.

[0017] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, where the multi-stage programming includes a first-stage programming and a second-stage programming; save second data before starting to perform the multi-stage programming and before the completion of the second-stage programming, where the second data is generated by encoding the first data; and adjust a read operation or a programming operation of at least one of the plurality of physical units according to the second data.

[0018] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0019] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: detecting an abnormal power-off event before the completion of the second-stage programming after the completion of the first-stage programming; and after the abnormal power-off event is restored, adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0020] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result.

[0021] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result includes: adjusting a first parameter for the read operation or the programming operation according to a first threshold voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; and adjusting a second parameter for the read operation or the programming operation according to a second threshold voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

[0022] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: adjusting at least one of a read voltage level, a programming voltage level, and a decoding parameter corresponding to at least one of the plurality of physical units according to the second data.

[0023] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: generate the second data in response to an abnormal power-off event before the completion of the second-stage programming.

[0024] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: correct third data read from at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0025] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: not save the second data for the plurality of physical units that have completed the second-stage programming.

[0026] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, where the multi-stage programming includes first-stage programming and second-stage programming; save second data before starting to perform the multi-stage programming and before the second-stage programming is completed, where the second data is generated by encoding the first data; and adjust a read operation or a programming operation of at least one of the plurality of physical units according to the second data.

[0027] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0028] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: detecting an abnormal power-off event before the second-stage programming is completed after the first-stage programming is completed; and after the abnormal power-off event is restored, adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0029] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result.

[0030] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result includes: adjusting a first parameter for the read operation or the programming operation according to a first threshold voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; and adjusting a second parameter for the read operation or the programming operation according to a second threshold voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

[0031] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: adjusting at least one of a read voltage level, a programming voltage level, and a decoding parameter corresponding to at least one of the plurality of physical units according to the second data.

[0032] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: generate the second data in response to an abnormal power-off event before the completion of the second-stage programming.

[0033] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: correct third data read from at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

[0034] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: not save the second data for the plurality of physical units that have completed the second-stage programming.

[0035] Based on the above, according to the first data, multi-stage programming can be performed on a plurality of physical cells in a rewritable non-volatile memory module. In particular, before starting to perform the multi-stage programming and before the second-stage programming in the multi-stage programming is completed, the second data generated by encoding the first data can be saved. Thereafter, a read operation or a programming operation on at least one of the plurality of physical cells can be adjusted based on the second data. Thus, compared with the conventional method that requires a complete backup of the first data until the corresponding programming operation is completed, the present invention can achieve the same or better data management and / or data recovery performance by saving the second data generated by encoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0037] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0039] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0040] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

[0041] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module shown according to an exemplary embodiment of the present invention;

[0042] Figure 7A is a schematic diagram of performing multi-stage programming on physical cells in a rewritable non-volatile memory module to store data shown according to an exemplary embodiment of the present invention;

[0043] Figure 7B is a schematic diagram of reading data from programmed physical cells shown according to an exemplary embodiment of the present invention;

[0044] Figure 8 is a schematic diagram of encoding first data to generate second data shown according to an exemplary embodiment of the present invention;

[0045] Figure 9AIt is a schematic diagram of the threshold voltage distribution of a memory cell after the first-stage programming as shown in an exemplary embodiment of the present invention;

[0046] Figure 9B It is a schematic diagram of the threshold voltage distribution of grouped memory cells as shown in an exemplary embodiment of the present invention;

[0047] Figure 10 It is a schematic diagram of adjusting the read voltage level as shown in an exemplary embodiment of the present invention;

[0048] Figure 11 It is a schematic diagram of adjusting decoding parameters as shown in an exemplary embodiment of the present invention;

[0049] Figure 12 It is a schematic diagram of correcting error bits according to second data as shown in an exemplary embodiment of the present invention;

[0050] Figure 13 It is a schematic diagram of performing interleaved programming on memory cells on multiple word lines as shown in an exemplary embodiment of the present invention;

[0051] Figure 14 It is a flowchart of a memory management method as shown in an exemplary embodiment of the present invention;

[0052] Figure 15 It is a flowchart of a memory management method as shown in an exemplary embodiment of the present invention. Detailed Description of the Invention

[0053] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0054] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0055] Figure 1 It is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device as shown in an exemplary embodiment of the present invention. Figure 2 It is a schematic diagram of a host system, a memory storage device, and an I / O device as shown in an exemplary embodiment of the present invention.

[0056] Please refer to Figure 1 andFigure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0057] In an exemplary embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0058] In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 in a wired or wireless manner.

[0059] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0060] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 a memory storage device 30 and a host system 31.

[0061] Figure 3 is a schematic diagram of a host system and a memory storage device shown in an exemplary embodiment of the present invention. Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342 that directly connect a memory module to the substrate of the host system.

[0062] Figure 4 is a schematic diagram of the memory storage device shown in an exemplary embodiment of the present invention. Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0063] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip including the memory control circuit unit 42.

[0064] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware form or firmware form and perform operations such as data writing, reading, and erasing in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0065] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which 1 bit can be stored in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which 2 bits can be stored in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which 3 bits can be stored in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which 4 bits can be stored in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0066] Each storage cell in the rewritable non-volatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also referred to as "writing data to the storage cell" or "programming the storage cell". With the change in the threshold voltage, each storage cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, and thus one or more bits stored in this storage cell can be obtained.

[0067] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may form a plurality of physical programming units, and these physical programming units may form a plurality of physical erasure units. Specifically, the memory cells on the same word line may form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0068] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit for erasure. That is, each physical erasure unit contains the smallest number of memory cells to be erased together. For example, the physical erasure unit is a physical block.

[0069] Figure 5 It is a schematic diagram of a memory control circuit unit shown in an exemplary embodiment of the present invention. Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0070] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions will be executed to perform operations such as data writing, reading, and erasing. When describing the operation of the memory management circuit 51 below, it is equivalent to describing the operation of the memory control circuit unit 42.

[0071] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions will be executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0072] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of the rewritable non-volatile memory module 43 in the form of program code (for example, the system area in the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit will execute these control instructions to perform operations such as data writing, reading, and erasing.

[0073] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0074] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 is used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0075] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are generated by the memory management circuit 51, for example, and are transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code and the memory address will be included.

[0076] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correcting circuit 54, a buffer memory 55, and a power management circuit 56.

[0077] The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 will generate a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 will write the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. After that, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it will simultaneously read the error correcting code and / or error detecting code corresponding to this data, and the error checking and correcting circuit 54 will perform error checking and correcting operations on the read data based on this error correcting code and / or error detecting code.

[0078] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0079] In an exemplary embodiment, Figure 4 the rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 the memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 the memory management circuit 51 may include a flash memory management circuit.

[0080] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to Figure 6 , the memory management circuit 51 may logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602.

[0081] In an exemplary embodiment, a physical unit refers to a physical programming unit. In an exemplary embodiment, a physical unit may also refer to multiple physical programming units.

[0082] The physical units 610(0) to 610(A) in the storage area 601 are used to store user data (such as user data from Figure 1 the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 may store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the spare area 602 do not store data (such as valid data). For example, if a certain physical unit does not store valid data, this physical unit may be associated (or added) to the spare area 602. In addition, the physical units in the spare area 602 (or physical units that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store this new data. In an exemplary embodiment, the spare area 602 is also referred to as a free pool.

[0083] The memory management circuit 51 may configure the logical units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0084] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data stored in this physical unit currently includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it means that the data stored in this physical unit is invalid data.

[0085] The memory management circuit 51 can record management data (also called logical-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logical-to-physical mapping table.

[0086] Figure 7A FIG. is a schematic diagram of performing multi-stage programming on physical units in a rewritable non-volatile memory module to store data according to an exemplary embodiment of the present invention. Please refer to Figure 7A In the figure, the horizontal axis represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells having a specific threshold voltage. In addition, Figure 7A Multi-stage programming based on the quad-level cell (QLC) mode is taken as an example for illustration, but the present invention is not limited thereto. In an exemplary embodiment, the multi-stage programming can also be performed based on the single-level cell (SLC) mode, the multi-level cell (MLC) mode, the triple-level cell (TLC) mode, or other modes, and the present invention does not limit this.

[0087] In an exemplary embodiment, it is assumed that before performing multi-stage programming on multiple physical units (also called the first physical units) located on a certain word line (also called the first word line) to store data, the threshold voltage distribution of multiple memory cells belonging to the first physical units may only include state 700. State 700 is also called the erased state. For example, after performing an erase operation on multiple memory cells belonging to the first physical units, the threshold voltage distribution of these memory cells may only include state 700.

[0088] In an exemplary embodiment, the memory management circuit 51 can send at least one write instruction sequence (also called the first write instruction sequence) to the rewritable non-volatile memory module 43 according to specific data (also called the first data). For example, the first data can be the data to be stored from the host system 11 and / or the valid data collected from the rewritable non-volatile memory module 43 through a garbage collection (GC) operation. The first write instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to perform a programming operation on the first physical units to store the first data.

[0089] In an exemplary embodiment, according to a first write instruction sequence, the rewritable non-volatile memory module 43 can perform a programming operation on the first physical unit through multi-stage programming to store the first data. For Figure 7A example, according to the first write instruction sequence, the rewritable non-volatile memory module 43 can first perform the first programming (also referred to as the first-stage programming) in the multi-stage programming on the first physical unit to roughly disperse the threshold voltages of multiple memory cells belonging to the first physical unit within the voltage range corresponding to states 701 to 716. It should be noted that even after the first-stage programming, the programming operation (i.e., multi-stage programming) for the first physical unit is still not completed (i.e., the first data has not been completely stored in the first physical unit).

[0090] After the first programming (i.e., the first-stage programming), the rewritable non-volatile memory module 43 can perform the second programming (also referred to as the second-stage programming) in the multi-stage programming on the first physical unit to more precisely control the threshold voltages of the multiple memory cells in states 701 to 716 within the voltage range corresponding to states 721 to 736. In particular, after the second-stage programming, it can be regarded that the programming operation (i.e., multi-stage programming) for the first physical unit has been completed (i.e., the first data has been completely stored in the first physical unit). In an exemplary embodiment, if the aforementioned programming operation (i.e., multi-stage programming) for the first physical unit has been completed (i.e., the first data has been completely stored in the first physical unit), the first data cached in the rewritable non-volatile memory module 43 and / or the buffer memory 55 can be removed.

[0091] In an exemplary embodiment, in the multi-stage programming performed on the first physical unit, the programming voltage level for the first-stage programming is different from the programming voltage level for the second-stage programming. For Figure 7A example, the programming voltage level for the first-stage programming is used to raise the threshold voltage of each memory cell to the voltage position corresponding to states 701 to 716. However, the programming voltage level for the second-stage programming is used to further raise or correct the threshold voltage of each memory cell to the voltage position corresponding to states 721 to 736.

[0092] It should be noted that Figure 7A the exemplary embodiment described above takes the 16:16 multi-stage programming mode as an example for illustration. However, in another exemplary embodiment, the aforementioned multi-stage programming can also be an 8:16 or other types of multi-stage programming modes, and the present invention is not limited thereto.

[0093] In an exemplary embodiment, states 721 to 736 respectively correspond to different bit combinations in a quad-level cell (QLC) mode, namely, "1111", "1110", "1100", "1101", "1001", "0001", "0101", "0100", "0110", "0010", "0000", "1000", "1010", "1011", "0011", and "0111". For example, assume that the threshold voltage of a certain memory cell belonging to the first physical cell is within the voltage range corresponding to state 722, indicating that the data stored in this memory cell is "1110". Or, assume that the threshold voltage of another memory cell belonging to the first physical cell is within the voltage range corresponding to state 734, indicating that the data stored in this memory cell is "1011", and so on. However, the bit combination corresponding to each of the states 721 to 736 can also be adjusted according to practical requirements, and the present invention does not limit this.

[0094] In an exemplary embodiment, among the above 16 bit combinations, the different bits in each bit combination respectively belong to different physical cells in the first physical cell. For example, among the above 16 bit combinations, the first to fourth bits in each bit combination can respectively belong to physical cell (L), physical cell (M), physical cell (U), and physical cell (T) in the first physical cell, as Figure 7A shown.

[0095] In an exemplary embodiment, two of physical cell (L), physical cell (M), physical cell (U), and physical cell (T) can be regarded as the upper physical programming unit and the lower physical programming unit. According to the memory management specification adopted, the names of physical cell (L), physical cell (M), physical cell (U), and physical cell (T) can be determined or adjusted respectively.

[0096] In other words, in Figure 7A the exemplary embodiment, it is assumed that multiple memory cells located on the first word line can form the multiple first physical cells (i.e., physical cell (L), physical cell (M), physical cell (U), and physical cell (T)). After performing the first-stage programming and the second-stage programming on these memory cells successively, the first data can be completely written into the multiple first physical cells.

[0097] Figure 7B is a schematic diagram of reading data from the programmed physical cell shown in the exemplary embodiment of the present invention. Please refer to Figure 7B and continue with Figure 7AIn an exemplary embodiment, for the first physical unit that has undergone second-stage programming, the memory management circuit 51 may send at least one read instruction sequence (also referred to as the first read instruction sequence) to the rewritable non-volatile memory module 43. The first read instruction sequence is used to instruct the rewritable non-volatile memory module 43 to read data (i.e., first data) from the plurality of first physical units (i.e., physical unit (L), physical unit (M), physical unit (U), and physical unit (T)).

[0098] In an exemplary embodiment, according to the first read instruction sequence, the rewritable non-volatile memory module 43 may read data (i.e., first data) from the plurality of first physical units based on a set of read voltages. For example, this set of read voltages may include read voltage levels L(1) to L(3), M(1) to M(4), U(1) to U(4), and T(1) to T(4).

[0099] The read voltage levels L(1) to L(3) are used to read data (also referred to as first sub-data) belonging to the physical unit (L). For example, by applying the read voltage levels L(1) to L(3) to the plurality of memory cells belonging to the first physical unit, the data (i.e., first sub-data) belonging to the physical unit (L) can be obtained. The read voltage levels M(1) to M(4) are used to read data (also referred to as second sub-data) belonging to the physical unit (M). For example, by applying the read voltage levels M(1) to M(4) to the plurality of memory cells belonging to the first physical unit, the data (i.e., second sub-data) belonging to the physical unit (M) can be obtained. The read voltage levels U(1) to U(4) are used to read data (also referred to as third sub-data) belonging to the physical unit (U). For example, by applying the read voltage levels U(1) to U(4) to the plurality of memory cells belonging to the first physical unit, the data (i.e., third sub-data) belonging to the physical unit (U) can be obtained. In addition, the read voltage levels T(1) to T(4) are used to read data (also referred to as fourth sub-data) belonging to the physical unit (T). For example, by applying the read voltage levels T(1) to T(4) to the plurality of memory cells belonging to the first physical unit, the data (i.e., fourth sub-data) belonging to the physical unit (T) can be obtained.

[0100] In an exemplary embodiment, if the programming operation (i.e., multi-stage programming) for the first physical unit is not completed (for example, only the first-stage programming is performed on the first physical unit and the second-stage programming has not been performed), then there is a high probability that the data (i.e., first data) stored in the first physical unit cannot be correctly read out subsequently. For Figure 7A example, if only the first-stage programming is performed, then there will be a large area of overlap between the states 701 to 716 in the threshold voltage distribution of the plurality of memory cells belonging to the first physical unit. In this case, if directly using Figure 7BIf the read voltage set is used to read these memory cells, it is very easy to cause data read failure due to reading too many error bits.

[0101] In an exemplary embodiment, from the start of performing the foregoing programming operation (i.e., multi-stage programming) on the first physical cell until the completion of this programming operation, the memory management circuit 51 may save specific data (also referred to as second data). For example, the second data may be generated by encoding the first data. In particular, the data volume of the second data may be smaller than the total data volume of the first data. For example, the memory management circuit 51 may encode the data stored in different physical cells in the first data (such as the foregoing first sub-data, second sub-data, third sub-data, and fourth sub-data) to generate the second data. For example, this encoding may include exclusive OR (XOR) encoding or other types of encoding algorithms, which are not limited in the present invention.

[0102] Figure 8 is a schematic diagram of encoding the first data to generate the second data shown in the exemplary embodiment of the present invention. Please refer to Figure 8 , in the first-stage programming, according to the first data, the threshold voltage distribution of multiple memory cells belonging to the first physical cell is roughly dispersed from state 800 to states 801-816. For example, states 801-816 may be the same as or similar to Figure 7A states 701-716. In this case, the threshold voltage distribution (i.e., states 801-816) of these memory cells that have only undergone the first-stage programming can roughly reflect the data storage states of the corresponding multiple first physical cells (i.e., physical cell (L), physical cell (M), physical cell (U), and physical cell (T)). However, before actually performing the second-stage programming on these memory cells, there may be a large area of overlap between states 801-816.

[0103] In an exemplary embodiment, before performing the second-stage programming on the memory cells in states 801 to 816, the memory management circuit 51 may encode the first data (i.e., the aforementioned first sub-data, second sub-data, third sub-data, and fourth sub-data) scattered in the first physical unit to obtain the data EB (i.e., the second data). For example, if the data (i.e., bit combination) stored in a certain memory cell is one of "1111", "1100", "1001", "0101", "0110", "0000", "1010", and "0011", then by performing XOR encoding on the sub-data (i.e., the first sub-data, second sub-data, third sub-data, and fourth sub-data) respectively belonging to the physical unit (L), physical unit (M), physical unit (U), and physical unit (T) stored in this memory cell, the data in the data EB corresponding to this memory cell (also called the fifth sub-data) can be encoded as "0". Or, if the data (i.e., bit combination) stored in a certain memory cell is one of "1110", "1101", "0001", "0100", "0010", "1000", "1011", and "0111", then by performing XOR encoding on the sub-data (i.e., the first sub-data, second sub-data, third sub-data, and fourth sub-data) respectively belonging to the physical unit (L), physical unit (M), physical unit (U), and physical unit (T) stored in this memory cell, the data in the data EB corresponding to this memory cell can be encoded as "1".

[0104] Or, from another perspective, after the first-stage programming, if the threshold voltage of a certain memory cell is within the voltage range corresponding to one of the states 801, 803, 805, 807, 809, 811, 813, and 815, then the data in the data EB corresponding to this memory cell can be encoded as "0". In addition, after the first-stage programming, if the threshold voltage of a certain memory cell is within the voltage range corresponding to one of the states 802, 804, 806, 808, 810, 812, 814, and 816, then the data in the data EB corresponding to this memory cell can be encoded as "1".

[0105] In an exemplary embodiment, according to data EB (i.e., the second data), the memory management circuit 51 can determine the state to which each memory cell belonging to the first physical cell belongs among states 801 to 816. For example, assuming that the data corresponding to a certain memory cell in data EB is "0", the memory management circuit 51 can infer that the state to which this memory cell belongs among states 801 to 816 is one of states 801, 803, 805, 807, 809, 811, 813, and 815. Or, assuming that the data corresponding to a certain memory cell in data EB is "1", the memory management circuit 51 can infer that the state to which this memory cell belongs among states 801 to 816 is one of states 802, 804, 806, 808, 810, 812, 814, and 816.

[0106] In an exemplary embodiment, according to data EB (i.e., the second data), the memory management circuit 51 can determine the actual data (i.e., bit combination) stored in each memory cell belonging to the first physical cell. For example, assuming that the data corresponding to a certain memory cell in data EB is "0", the memory management circuit 51 can infer that the data stored in this memory cell is one of "1111", "1100", "1001", "0101", "0110", "0000", "1010", and "0011". Or, assuming that the data corresponding to a certain memory cell in data EB is "1", the memory management circuit 51 can infer that the data stored in this memory cell is one of "1110", "1101", "0001", "0100", "0010", "1000", "1011", and "0111".

[0107] In an exemplary embodiment, the memory management circuit 51 can save data EB (i.e., the second data) based on the single-level cell (SLC) mode. For example, after obtaining data EB, the memory management circuit 51 can send a write instruction sequence (also referred to as the second write instruction sequence) to the rewritable non-volatile memory module 43. The second write instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to store data EB into a certain physical cell (also referred to as the second physical cell) in the rewritable non-volatile memory module 43. According to the second write instruction sequence, the rewritable non-volatile memory module 43 can store data EB into the second physical cell based on the single-level cell (SLC) mode. In an exemplary embodiment, the memory management circuit 51 can also save data EB based on other operation modes, which are not limited in the present invention.

[0108] In an exemplary embodiment, before the programming operation for the first physical unit (i.e., multi-stage programming) is completed (for example, only the first stage of programming is performed on the first physical unit and the second stage of programming has not been performed yet), the memory management circuit 51 can adjust the subsequent reading (i.e., read operation) and / or writing (i.e., programming operation) of at least one of the plurality of first physical units according to the data EB (i.e., the second data). For example, the memory management circuit 51 can adjust at least one of the subsequent read voltage levels, programming voltage levels, and decoding parameters corresponding to at least one of the plurality of first physical units according to the data EB (i.e., the second data). The read voltage level is used to read data from at least one of the plurality of first physical units. The programming voltage level is used to perform a second programming or a complete programming operation on the plurality of first physical units. The decoding parameters are used to decode the data read from at least one of the plurality of first physical units. In addition, more different operation behaviors and / or at least one parameter corresponding to a certain operation behavior can also be adjusted based on the data EC (i.e., the second data), which is not limited in the present invention.

[0109] In an exemplary embodiment, the decoding parameter can include a Log Likelihood Ratio (LLR). For example, the error checking and correcting circuit 54 can decode data based on a Low-density parity-check code (LDPC code) or other decoding algorithms in combination with this Log Likelihood Ratio. In an exemplary embodiment, the decoding parameter can include other types of decoding parameters as long as the decoding performance can be improved.

[0110] In an exemplary embodiment, the memory management circuit 51 can detect an abnormal power-off event before the programming operation for the first physical unit is completed (for example, only the first stage of programming is performed on the first physical unit and the second stage of programming has not been performed yet). This abnormal power-off event causes the second stage of programming that is expected to be performed on the first physical unit to be unable to be performed after the first stage of programming is performed on the first physical unit. For example, after the first stage of programming is performed on the first physical unit, if this abnormal power-off event causes the memory storage device 10 to power off, then in the power-off state, the second stage of programming that is expected to be performed on the first physical unit will not be able to be performed.

[0111] In an exemplary embodiment, after the recovery of the aforementioned abnormal power-off event (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can adjust the subsequent reading (i.e., read operation) and / or writing (i.e., programming operation) for at least one of the plurality of first physical units according to the saved data EB (i.e., the second data). Thus, after the recovery of the abnormal power-off event, the memory storage device 10 can be quickly restored to the normal state.

[0112] In an exemplary embodiment, the memory management circuit 51 can group a plurality of memory cells belonging to the plurality of first physical units in the rewritable non-volatile memory module 43 according to the saved data EB (i.e., the second data). Then, according to the grouping result, the memory management circuit 51 can adjust the subsequent reading and / or writing for at least one of the plurality of first physical units.

[0113] In an exemplary embodiment, the grouping result can reflect that a part of the memory cells (also called the first memory cells) in the first physical unit belong to a certain group (also called the first group), and another part of the memory cells (also called the second memory cells) in the first physical unit belong to another group (also called the second group). For Figure 8 example, if the data corresponding to a certain memory cell in the data EB is "0", the memory management circuit 51 can group this memory cell (i.e., the first memory cell) into the first group. Or, if the data corresponding to a certain memory cell in the data EB is "1", the memory management circuit 51 can group this memory cell (i.e., the second memory cell) into the second group.

[0114] In an exemplary embodiment, after obtaining the grouping result, the memory management circuit 51 can adjust at least one parameter (also called the first parameter) for the aforementioned reading or writing according to the threshold voltage distribution of the first memory cells (also called the first threshold voltage distribution). In addition, the memory management circuit 51 can adjust at least one parameter (also called the second parameter) for the aforementioned reading or writing according to the threshold voltage distribution of the second memory cells (also called the second threshold voltage distribution). The first parameter and the second parameter can be the same parameter or different parameters. For example, the first parameter and the second parameter can include at least one of the aforementioned reading voltage level, programming voltage level, and decoding parameter. Then, the memory management circuit 51 can access the first physical unit according to the adjusted parameters (e.g., the first parameter and / or the second parameter). For example, the memory management circuit 51 can perform a read operation or a programming operation on the first physical unit according to the adjusted parameters (e.g., the first parameter and / or the second parameter). Or, the memory management circuit 51 can also perform other management operations on the first physical unit according to the adjusted parameters (e.g., the first parameter and / or the second parameter).

[0115] Figure 9A It is a schematic diagram of the threshold voltage distribution of a memory cell after the first-stage programming as shown in an exemplary embodiment of the present invention. Please refer to Figure 9A , following the Figure 8 exemplary embodiment, assuming that after the first-stage programming is performed on a plurality of memory cells belonging to the first physical cell, the threshold voltage distributions of these memory cells include states 801 to 816. The read voltage level L(1) is between the voltage ranges corresponding to states 805 and 806 respectively. The read voltage level L(2) is between the voltage ranges corresponding to states 811 and 812 respectively. The read voltage level L(3) is between the voltage ranges corresponding to states 814 and 815 respectively.

[0116] It should be noted that in the Figure 9A exemplary embodiment, since the second-stage programming has not been performed on these memory cells, there are large areas of overlap between adjacent states 805 and 806, states 811 and 812, and states 814 and 815. In this case, if the aforementioned abnormal power-off event occurs, after the abnormal power-off event is restored (for example, the memory storage device 10 is powered on again), using the read voltage levels L(1) to L(3) to attempt to read the data (i.e., the first sub-data) stored in the physical cell (L) from these memory cells, there will be a high probability of read failure (because too many error bits are read). At this time, in general, unless there is a backup data that completely stores the first data, the first data will be permanently lost. However, if there is a backup data that completely stores the first data, this backup data will occupy a lot of storage space, resulting in a reduction in the available storage space of the system.

[0117] Figure 9B It is a schematic diagram of the threshold voltage distribution of the grouped memory cells as shown in an exemplary embodiment of the present invention. Please refer to Figure 9B , following the Figure 9AIn an exemplary embodiment, after the recovery of an abnormal power-off event (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can group multiple memory cells belonging to the first physical unit according to the data EB (i.e., the second data) saved before or at the time of the abnormal power-off event. For example, according to the data "0" in the data EB, the memory cells corresponding to the states 801, 803, 805, 807, 809, 811, 813, and 815 among these memory cells (i.e., the first memory cells) can be grouped into the first group. For example, the critical voltage distribution (i.e., the first critical voltage distribution) of the first memory cells belonging to the first group may include the states 801, 803, 805, 807, 809, 811, 813, and 815. In addition, according to the data "1" in the data EB, the memory cells corresponding to the states 802, 804, 806, 808, 810, 812, 814, and 816 among these memory cells can be grouped into the second group. For example, the critical voltage distribution (i.e., the second critical voltage distribution) of the second memory cells belonging to the second group may include the states 802, 804, 806, 808, 810, 812, 814, and 816.

[0118] In an exemplary embodiment, the memory management circuit 51 can adjust the parameters for accessing the first physical unit according to the first critical voltage distribution and / or the second critical voltage distribution. Thus, after the recovery of an abnormal power-off event (e.g., the memory storage device 10 is powered on again), using the adjusted parameters to access the first physical unit can effectively reduce the number of error bits read.

[0119] In an exemplary embodiment, the memory management circuit 51 can adjust at least one of the read voltage levels L(1) to L(3) according to the first critical voltage distribution and / or the second critical voltage distribution. Hereinafter, taking the adjustment of the read voltage level L(1) as an example for illustration.

[0120] Figure 10 is a schematic diagram of adjusting the read voltage level shown in the exemplary embodiment of the present invention. Please refer to Figure 10 , following Figure 9A and Figure 9B , in an exemplary embodiment, according to the first critical voltage distribution (including the states 805 and 807), the memory management circuit 51 can add an adjustment value ΔV(1) to the read voltage level L(1) to obtain the read voltage level L(1)'. For example, the voltage position of the read voltage level L(1)' can be at the bottom of the V-shaped or U-shaped valley between the states 805 and 807. Regarding how to determine the adjustment value ΔV(1) and / or how to find the bottom of the V-shaped or U-shaped valley between any two states belongs to the prior art. For example, it can be achieved by analyzing the critical voltage distribution state of the memory cells within a specific voltage range, and will not be elaborated here.

[0121] After an abnormal power-off event recovery (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can use the read voltage level L(1)' to read partial data of the first physical unit belonging to the physical unit (L) (including determining which memory cells belong to the state 805), so as to improve the correctness of the read data. For Figure 10 example, compared with the read voltage level L(1), using the read voltage level L(1)' to read partial data of the first physical unit belonging to the physical unit (L) can change the memory cells in the diagonal area on the right side of the original read voltage level L(1) in the state 805 from belonging to the state 806 to belonging to the state 805. Thus, the number of error bits read can be effectively reduced.

[0122] On the other hand, according to the second critical voltage distribution (including the states 804 and 806), the memory management circuit 51 can subtract an adjustment value ΔV(2) from the read voltage level L(1) to obtain the read voltage level L(1)". For example, the voltage position of the read voltage level L(1)" can be at the bottom of the V-shaped or U-shaped valley between the states 804 and 806.

[0123] After an abnormal power-off event recovery (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can use the read voltage level L(1)" to read partial data of the physical unit (L) (including determining which memory cells belong to the state 806), so as to improve the correctness of the read data. For Figure 10 example, compared with the read voltage level L(1), using the read voltage level L(1)" to read partial data of the first physical unit belonging to the physical unit (L) can change the memory cells in the diagonal area on the left side of the original read voltage level L(1) in the state 806 from belonging to the state 805 to belonging to the state 806, thereby effectively reducing the number of error bits read. It should be noted that Figure 10 the adjustment mechanism of the read voltage level presented in the exemplary embodiment of can be applied to the adjustment of the remaining read voltage levels, which will not be repeated here.

[0124] In an exemplary embodiment, the memory management circuit 51 can adjust the decoding parameters (such as LLR) used in conjunction with at least one of the read voltage levels L(1) to L(3) according to the first critical voltage distribution and / or the second critical voltage distribution. The following will take the adjustment of the decoding parameters used in conjunction with the read voltage level L(1) as an example for illustration.

[0125] Figure 11 is a schematic diagram of adjusting the decoding parameters shown in the exemplary embodiment of the present invention. Please refer to Figure 11 , following Figure 9A, Figure 9B and Figure 10 In an exemplary embodiment, after the recovery of an abnormal power-off event (e.g., the memory storage device 10 is powered on again), it is assumed that a plurality of voltage intervals are divided based on the original read voltage level L(1) and decoding parameters corresponding to each voltage interval are given (e.g., LLR(1) to LLR(6)). For example, these voltage intervals have the same or similar voltage gaps between each other. In the case where states 805 and 806 overlap significantly, even when using LLR(1) to LLR(6) in combination with the LDPC decoding algorithm, there is still a high probability that the data read cannot be successfully decoded.

[0126] In an exemplary embodiment, according to the first critical voltage distribution (including states 805 and 807), the memory management circuit 51 can divide a plurality of voltage intervals based on the adjusted read voltage level L(1)' and give decoding parameters corresponding to each voltage interval (e.g., LLR(1)' to LLR(6)'). For example, these voltage intervals have the same or similar voltage gaps between each other. Then, the error checking and correcting circuit 54 can decode the data read based on the read voltage level L(1)' according to LLR(1)' to LLR(6)' in combination with the LDPC decoding algorithm. Compared with using the original decoding parameters (e.g., LLR(1) to LLR(6)) to decode the data read based on the read voltage level L(1), using the new decoding parameters (e.g., LLR(1)' to LLR(6)') to decode the data read based on the read voltage level L(1)' can effectively improve the decoding success rate.

[0127] On the other hand, according to the second critical voltage distribution (including states 804 and 806), the memory management circuit 51 can divide a plurality of voltage intervals based on the read voltage level L(1)'' and give decoding parameters corresponding to each voltage interval (e.g., LLR(1)'' to LLR(6)''). For example, these voltage intervals have the same or similar voltage gaps between each other. Then, the error checking and correcting circuit 54 can decode the data read based on the read voltage level L(1)'' according to LLR(1)'' to LLR(6)'' in combination with the LDPC decoding algorithm. Compared with using the original decoding parameters (e.g., LLR(1) to LLR(6)) to decode the data read based on the read voltage level L(1), using the new decoding parameters (e.g., LLR(1)'' to LLR(6)'' ) to decode the data read based on the read voltage level L(1)'' can effectively improve the decoding success rate.

[0128] In an exemplary embodiment, the memory management circuit 51 may also correct the data (also referred to as the third data) read from the first physical unit that has not been fully programmed (i.e., the physical unit that has undergone the first-stage programming and has not undergone the second-stage programming) according to the data EB (i.e., the second data) saved before or at the time of the abnormal power-off event.

[0129] Figure 12 FIG. is a schematic diagram of correcting an error bit according to the second data shown in the exemplary embodiment of the present invention. Please refer to Figure 12 , following the Figure 9A exemplary embodiment, after the abnormal power-off event is restored (e.g., the memory storage device 10 is powered on again), when using the read voltage level L(1) to attempt to read the data (i.e., the first sub-data) stored in the physical unit (L) from these memory cells, it may be misjudged that these memory cells belong to state 806 because the threshold voltages of some memory cells belonging to state 805 are higher than the read voltage level L(1). Or, it may also be misjudged that some memory cells belonging to state 806 belong to state 805 because the threshold voltages of these memory cells are lower than the read voltage level L(1).

[0130] In an exemplary embodiment, for the memory cells that actually belong to state 805 but are misjudged to belong to state 806 (also referred to as the first target memory cells), the memory management circuit 51 may, according to the data (i.e., the fifth sub-data) in the data EB (i.e., the second data) corresponding to the first target memory cells, in combination with the remaining sub-data (such as the second sub-data, the third sub-data, and the fourth sub-data) read from the first target memory cells, update the misjudged first sub-data in the first target memory cells from "0" (belonging to state 806) to "1" (belonging to state 805). It should be noted that this data correction process only involves the logical operation (such as XOR operation) between the multiple sub-data (i.e., the first sub-data to the fourth sub-data) read from the same memory cell (i.e., the first target memory cell) and the data (i.e., the fifth sub-data) in the data EB corresponding to the first target memory cell, and may not involve the LDPC or other types of decoding algorithms used by the error checking and correcting circuit 54.

[0131] Similarly, for a memory cell that actually belongs to state 806 but is misjudged as belonging to state 805 (also known as the second target memory cell), the memory management circuit 51 can, according to the data in data EB (i.e., the second data) corresponding to the second target memory cell (i.e., the fifth sub-data), combined with the remaining sub-data read from the second target memory cell (such as the second sub-data, the third sub-data, and the fourth sub-data), update the misjudged first sub-data in the second target memory cell from "1" (belonging to state 805) to "0" (belonging to state 806). It should be noted that this data correction process only involves logical operations (such as XOR operations) between multiple sub-data (i.e., the first sub-data to the fourth sub-data) read from the same memory cell (i.e., the second target memory cell) and the data in data EB corresponding to the second target memory cell (i.e., the fifth sub-data), and may not involve LDPC or other types of decoding algorithms used by the error checking and correction circuit 54.

[0132] In an exemplary embodiment, after an abnormal power-off event recovery (such as the memory storage device 10 being powered on again), the memory management circuit 51 can determine or adjust the programmed voltage levels corresponding to these first physical units according to the data actually stored in each memory cell belonging to the first physical unit (i.e., the first data). How to obtain the data actually stored in each memory cell belonging to the first physical unit (i.e., the first data) has been described in detail above and will not be repeated here. Then, the memory management circuit 51 can perform the unfinished programming operation (such as the second-stage programming) on the first physical unit according to the determined or adjusted programmed voltage levels. Alternatively, in an exemplary embodiment, the memory management circuit 51 can also choose to re-store the first data in other physical units, which is not limited in the present invention.

[0133] Thus, without the need to additionally store backup data of the first data or re-obtain the first data from the host system 11, after an abnormal power-off event recovery (such as the memory storage device 10 being powered on again), the memory management circuit 51 can continue to complete the previously unfinished programming operation, thereby improving the working efficiency of the memory storage device 10.

[0134] In an exemplary embodiment, data EB (i.e., the second data) can also be automatically generated in response to the detected abnormal power-off event before the programming operation (i.e., multi-stage programming) for the first physical unit is completed. That is, in an exemplary embodiment, if no abnormal power-off event is detected before the programming operation (i.e., multi-stage programming) for the first physical unit is completed, data EB (i.e., the second data) may not be generated either.

[0135] In an exemplary embodiment, the memory management circuit 51 only needs to save the data EB (i.e., the second data) until the programming operation for the first physical unit (e.g., the second-stage programming in the aforementioned multi-stage programming) is completed. If the programming operation for the first physical unit (e.g., the second-stage programming in the aforementioned multi-stage programming) is completed, the memory management circuit 51 can remove the data EB (i.e., the second data). For example, removing the data EB may mean marking the physical unit storing the data EB as storing invalid data.

[0136] In an exemplary embodiment, the memory management circuit 51 only generates and saves the data EC (i.e., the second data) corresponding to a physical unit (or the memory cells belonging to this physical unit) for the physical units that have performed the first-stage programming and have not performed the second-stage programming. In an exemplary embodiment, the memory management circuit 51 does not generate and / or save the data EC (i.e., the second data) corresponding to a physical unit (or the memory cells belonging to this physical unit) for the physical units that have performed or completed the second-stage programming.

[0137] Figure 13 is a schematic diagram of interleaved programming for memory cells on multiple word lines as shown in the exemplary embodiment of the present invention. Please refer to Figure 13 , in an exemplary embodiment, it is assumed that the rewritable non-volatile memory module 43 includes at least word lines (1) to (3), and each word line includes strings (1) to (5). In addition, each string includes a plurality of memory cells. It should be noted that the total number of word lines included in the rewritable non-volatile memory module 43 and the total number of strings included in each word line can both be adjusted according to practical requirements.

[0138] In an exemplary embodiment, in the rewritable non-volatile memory module 43 that supports the aforementioned multi-stage programming, the rewritable non-volatile memory module 43 performs interleaved programming on multiple strings on multiple word lines to store data into the corresponding physical units. Taking Figure 13 as an example, when writing data, the rewritable non-volatile memory module 43 can, according to Figure 13 the numbers (indicating the programming order), first sequentially perform the first-stage programming in the multi-stage programming on strings (1) to (5) on word line (1) respectively (corresponding to Figure 13 the numbers 1 to 5 in

[0139] After performing the first-stage programming on string (5) on word line (1) (corresponding to Figure 13 the number 5 in Figure 13the number 6) in, perform a second-stage programming on the string (1) on the word line (1) (corresponding to Figure 13 the number 7) in, perform a first-stage programming on the string (2) on the word line (2) (corresponding to Figure 13 the number 8) in, and perform a second-stage programming on the string (2) on the word line (1) (corresponding to Figure 13 the number 9) in, and so on. Only after the first-stage programming and the second-stage programming are completely executed for a certain string, this string (or the memory cells on the string) will be regarded as having been completely programmed. It should be noted that Figure 13 the programming sequence is only an example and is not used to limit the present invention.

[0140] Traditionally, before the second-stage programming of some memory cells is completed, if an abnormal power-off event occurs, then after the abnormal power-off event is restored, the memory management circuit 51 may have to obtain the previously incompletely stored data from the host system 11 again and re-execute the write operation corresponding to this data, resulting in waste of the bandwidth between the host system 11 and the memory storage device 10. Or, before the second-stage programming of some memory cells is completed, the memory management circuit 51 can retain backup data of the data to be stored corresponding to these memory cells. If an abnormal power-off event occurs, then after the abnormal power-off event is restored, the memory management circuit 51 can re-execute the data write according to this backup data. However, if the Figure 13 data writing mechanism is adopted, then before the programming operation for each word line is completed, the memory management circuit 51 needs to retain at least the backup data belonging to 6 strings, resulting in rapid consumption of the storage resources of the system.

[0141] However, in the foregoing exemplary embodiment, by saving the second data to replace the traditional saving of the backup data corresponding to the first data, the storage resources of the system can be effectively saved. In addition, the second data can also be used to adjust the read operation and / or write operation for a specific physical unit to improve the operation efficiency and operation stability of the memory storage device 10.

[0142] Figure 14 is a flowchart of a memory management method shown according to an exemplary embodiment of the present invention. Please refer to Figure 14 , in step S1401, according to the first data, perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module, where the multi-stage programming includes a first-stage programming and a second-stage programming. In step S1402, before starting to execute the multi-stage programming and before the second-stage programming is completed, save the second data, where the second data is generated by encoding the first data. In step S1403, according to the second data, adjust the read operation or the programming operation of at least one of the plurality of physical units.

[0143] Figure 15 is a flowchart of a memory management method shown in an exemplary embodiment of the present invention. Please refer to Figure 15 , in step S1501, a programming operation is performed on a plurality of physical cells in a rewritable non-volatile memory module according to first data. In step S1502, the first data is encoded to generate second data. In step S1503, the second data is saved. In step S1504, it is determined whether the programming operation for the plurality of physical cells has been completed. If the programming operation has been completed, in step S1505, the second data is removed.

[0144] If the programming operation has not been completed, then in step S1506, it is detected whether an abnormal power-off event has occurred. If an abnormal power-off event has occurred, in step S1507, after the abnormal power-off event is restored, according to the second data, the read operation or the programming operation of at least one of the plurality of physical cells is adjusted. If no abnormal power-off event has occurred, it can return to step S1504.

[0145] However, Figure 14 and Figure 15 The steps in have been described in detail above and will not be elaborated here. It should be noted that, Figure 14 and Figure 15 The steps in can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 14 and Figure 15 The method of can be used in conjunction with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0146] In summary, the memory management method, memory storage device, and memory control circuit unit proposed by the present invention can temporarily store corresponding encoded data (i.e., second data) before the multi-stage programming for a plurality of physical cells is actually completed. Thus, if an abnormal power-off event occurs during the execution of the multi-stage programming, subsequent recovery operations or related settings can be quickly performed according to this encoded data, thereby improving the working efficiency of the memory storage device.

[0147] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a rewritable non-volatile memory module, the memory management method includes: Performing multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes first-stage programming and second-stage programming; Before starting to execute the multi-stage programming and before the second-stage programming is completed, saving second data, wherein the second data is generated by encoding the first data; and Adjusting a read operation or a programming operation of at least one of the plurality of physical units according to the second data.

2. The memory management method according to claim 1, wherein the plurality of physical units belong to the same word line.

3. The memory management method according to claim 2, wherein the plurality of physical units at least include an upper physical programming unit and a lower physical programming unit.

4. The memory management method according to claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

5. The memory management method according to claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: After the first-stage programming is completed, detecting an abnormal power-off event before the second-stage programming is completed; And After the abnormal power-off event is restored, adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

6. The memory management method according to claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; And Adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result.

7. The memory management method according to claim 6, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result includes: Adjusting a first parameter for the read operation or the programming operation according to a first threshold voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; And Adjust a second parameter for the read operation or the programming operation according to a second threshold voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

8. The memory management method according to claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of physical cells according to the second data comprises: Adjust at least one of a read voltage level, a programming voltage level, and a decoding parameter corresponding to at least one of the plurality of physical cells according to the second data.

9. The memory management method according to claim 1, further comprising: Generating the second data in response to an abnormal power-off event before completion of the second-phase programming.

10. The memory management method according to claim 1, further comprising: Correcting third data read from at least one of the plurality of physical cells that have completed the first-phase programming and have not completed the second-phase programming according to the second data.

11. The memory management method according to claim 1, further comprising: Not saving the second data for the plurality of physical cells that have completed the second-phase programming.

12. The memory management method according to claim 1, wherein in the multi-phase programming performed on the plurality of physical cells, a programming voltage level for the first-phase programming is different from a programming voltage level for the second-phase programming.

13. A memory storage device, characterized in that, Comprising: A connection interface unit for connecting to a host system; A rewritable non-volatile memory module; And A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, Wherein the memory control circuit unit is configured to: Perform multi-phase programming on a plurality of physical cells in the rewritable non-volatile memory module according to first data, wherein the multi-phase programming comprises first-phase programming and second-phase programming; Save second data before starting to perform the multi-phase programming and before completion of the second-phase programming, wherein the second data is generated by encoding the first data; and Adjust a read operation or a programming operation of at least one of the plurality of physical cells according to the second data.

14. The memory storage device according to claim 13, wherein the plurality of physical cells belong to the same word line.

15. The memory storage device according to claim 14, wherein the plurality of physical cells at least comprise an upper physical programming cell and a lower physical programming cell.

16. The memory storage device according to claim 13, wherein the operation of the memory control circuit unit adjusting the read operation or the programming operation of at least one of the plurality of physical cells according to the second data comprises: Adjust the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

17. The memory storage device according to claim 13, wherein the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: After the first-stage programming is completed, detect an abnormal power-off event before the second-stage programming is completed; And After the abnormal power-off event is restored, adjust the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

18. The memory storage device according to claim 13, wherein the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Group a plurality of storage units corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; And Adjust the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result.

19. The memory storage device according to claim 18, wherein the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result includes: Adjust a first parameter for the read operation or the programming operation according to a first threshold voltage distribution of a plurality of first storage units belonging to a first group among the plurality of storage units; And Adjust a second parameter for the read operation or the programming operation according to a second threshold voltage distribution of a plurality of second storage units belonging to a second group among the plurality of storage units.

20. The memory storage device according to claim 13, wherein the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Adjust at least one of a read voltage level, a programming voltage level, and a decoding parameter corresponding to at least one of the plurality of physical units according to the second data.

21. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Generate the second data in response to an abnormal power-off event before the second-stage programming is completed.

22. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Correct third data read from at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

23. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Not save the second data for the plurality of physical units that have completed the second-stage programming.

24. The memory storage device according to claim 13, wherein in the multi-stage programming performed on the plurality of physical units, the programming voltage level for the first-stage programming is different from the programming voltage level for the second-stage programming.

25. A memory control circuit unit, characterized in that, For controlling a rewritable non-volatile memory module, the memory control circuit unit includes: A host interface for connecting to a host system; A memory interface for connecting to the rewritable non-volatile memory module; and A memory management circuit connected to the host interface and the memory interface, wherein the memory management circuit is configured to: Perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; Save second data before starting to perform the multi-stage programming and before the second-stage programming is completed, wherein the second data is generated by encoding the first data; and Adjust a read operation or a programming operation of at least one of the plurality of physical units according to the second data.

26. The memory control circuit unit according to claim 25, wherein the plurality of physical units belong to the same word line.

27. The memory control circuit unit according to claim 26, wherein the plurality of physical units at least include an upper physical programming unit and a lower physical programming unit.

28. The memory control circuit unit according to claim 25, wherein the operation of the memory management circuit adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

29. The memory control circuit unit according to claim 25, wherein the operation of the memory management circuit adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Detecting an abnormal power-off event before the second-stage programming is completed after the first-stage programming is completed; And After the abnormal power-off event is restored, adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

30. The memory control circuit unit according to claim 25, wherein the operation of the memory management circuit for adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; And Adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result.

31. The memory control circuit unit according to claim 30, wherein the operation of the memory management circuit for adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the grouping result includes: Adjusting a first parameter for the read operation or the programming operation according to a first threshold voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; And Adjusting a second parameter for the read operation or the programming operation according to a second threshold voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

32. The memory control circuit unit according to claim 25, wherein the operation of the memory management circuit for adjusting the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: Adjusting at least one of a read voltage level, a programming voltage level, and a decoding parameter corresponding to at least one of the plurality of physical units according to the second data.

33. The memory control circuit unit according to claim 25, wherein the memory management circuit is further configured to: Generate the second data in response to an abnormal power-off event before the completion of the second-stage programming.

34. The memory control circuit unit according to claim 25, wherein the memory management circuit is further configured to: Correct third data read from at least one of the plurality of physical units that have completed the first-stage programming and have not completed the second-stage programming according to the second data.

35. The memory control circuit unit according to claim 25, wherein the memory management circuit is further configured to: Not save the second data for the plurality of physical units that have completed the second-stage programming.

36. The memory control circuit unit according to claim 25, wherein in the multi-stage programming performed on the plurality of physical units, the programming voltage level for the first-stage programming is different from the programming voltage level for the second-stage programming.

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