A flexible FPGA lookup table-based optimized random number generation method
By using a flexible lookup table V-LUT random number generation method, the resource waste and quality problems of existing FPGA random number generation algorithms are solved, achieving efficient and optimized random number generation, which is suitable for simulating nuclear radiation events in nuclear signal generators.
Patent Information
- Application Number
- CN202510756401.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-09
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2045-06-09
AI Technical Summary
Existing FPGA-based random number generation algorithms suffer from problems such as low random number quality, wasted LUT resources, and uncertainty in the maximum period.
A flexible lookup table (V-LUT) random number generation method is adopted. By obtaining parameters, generating a state transition matrix, converting it into Verilog code, and configuring the FPGA circuit, the resource usage of the random number generator is optimized, and quality testing is performed.
It improves the efficiency and quality of random number generation, reduces FPGA resource consumption, and is suitable for simulating the randomness and noise of nuclear radiation events in nuclear signal generators.
Smart Images
Figure CN120276707B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of random number hardware generation technology, and particularly relates to a flexible optimized random number generation method based on FPGA lookup tables. Background Technology
[0002] Random number generation algorithms can be based on both software and hardware methods. Because software-based methods are less efficient, many random number generators originally designed for software architectures are now being ported to FPGAs to accelerate computation. For example, the combined Tausworthe software random number generator uses word-level shifts, XOR, and AND operations to construct simple recursions with different periods, and then combines these recursions through XOR operations to generate a random number generator with a longer period. The Mason rotator uses the same word-level operators as the combined Tausworthe, combined with a RAM-based queue, to create a software random number generator with a fairly good uniform distribution and an extremely long period. All these software random number generators are designed with word-level instructions in mind, and therefore are often inefficient in terms of resources consumed per bit generated. In contrast, FPGA-optimized random number generation algorithms are more resource-efficient than software-based ones because they can utilize bitwise operations and FPGA-specific features to simplify computation.
[0003] Currently, random number generation algorithms based on FPGA lookup tables mainly include Lookup Table Optimized Random Number Generation Algorithm (LUT-OPT), Lookup Table First-In-First-Out Queue Generation Algorithm (LUT-FIFO), and Lookup Table Shift Register Generation Algorithm (LUT-SR). However, these FPGA lookup table generation algorithms have problems such as low random number quality, wasted LUT resources, and uncertain maximum period. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention proposes a flexible optimized random number generation method based on FPGA lookup tables.
[0005] The method is based on a hardware FPGA to implement a flexible lookup table (V-LUT) random number generator, specifically including:
[0006] Step S1: Obtain the parameters of the V-LUT random number generator, which are used to determine the period length and resource usage of the random number generator;
[0007] Step S2: Use the Flexible Lookup Table (V-LUT) state transition matrix generator to create the state transition matrix;
[0008] Step S3: Convert the state transition matrix into Verilog code to implement the corresponding FPGA circuit;
[0009] Step S4: Configure the FPGA circuit by optimizing the parameters of the flexible look-up table V-LUT random number generator.
[0010] Step S5: Perform quality testing on the random numbers generated by the flexible look-up table V-LUT random number generator.
[0011] In step S1, the parameters include the matrix dimension d, the shift register length k, the random bit number r, and the maximum input number t of the look-up table.
[0012] In step S2, based on the parameters, the flexible look-up table V-LUT state transition matrix generation program randomly generates several matrices, and selects a primitive matrix T that meets the requirements as the state transition matrix.
[0013] In step S3, for a flexible look-up table V-LUT random number generator with a random bit number r and a matrix dimension d, its state transition matrix is divided into: I, A1, A2 and other parts; I represents an identity matrix with a size of d-r, A1 and A2 are sub-matrices used to determine specific bits connected to the FPGA multi-bit XOR gate, the dimension of A1 is r×r, the dimension of A2 is r×k, and other parts are all 0.
[0014] In step S3:
[0015] For the sub-matrices A1 and A2 in the state transition matrix, each 1 indicates a connection is needed, and each 0 in the matrix indicates no connection is needed. Each row corresponds to the input configuration of an XOR gate, and the 1 in the row indicates that this bit needs to be connected to the corresponding XOR gate.
[0016] For the sub-matrix A1, it controls the output feedback of the first r-bit registers to the XOR gate to further determine the connection mode in the feedback path.
[0017] For the sub-matrix A2, it controls the output of the last k-bit registers to be connected to the XOR gate to further increase randomness and cycle length.
[0018] In step S4:
[0019] Set the value of r and define the number of XOR gates required by the FPGA circuit as r.
[0020] When the cycle length of the random number generator is the first length, set r < d and k = d-r.
[0021] When the cycle length of the random number generator is the second length and the required number of random numbers is lower than the number threshold, set 0 < k < d-r.
[0022] Where the first length is less than the second length.
[0023] In step S5, the quality test includes:
[0024] Quality testing was performed using the NIST randomness test suite;
[0025] Check the linearity of the Campbell value;
[0026] Analyze the spacing distribution between adjacent pulses.
[0027] In the method: registers in the FPGA circuit that do not participate in the XOR gate operation are configured as shift registers based on flexible lookup tables (V-LUTs) to reduce the resource usage of the random number generator. The shift registers based on flexible lookup tables (V-LUTs) are mapped to LUT-SRL structures to further reduce the number of flip-flops required.
[0028] In the method, a flexible lookup table (V-LUT) random number generator is applied to a nuclear-simulated signal generator, which is used to simulate the output signal of a nuclear reactor detector, wherein random numbers generated by the V-LUT random number generator are used to simulate the randomness of nuclear radiation events.
[0029] In the method:
[0030] The nuclear signal generator uses random numbers generated by a flexible lookup table (V-LUT) random number generator to generate pulse sequences, thereby simulating nuclear radiation events that conform to a Poisson distribution.
[0031] The nuclear-simulated signal generator uses random numbers generated by a flexible lookup table (V-LUT) random number generator to generate white noise in order to simulate the noise in the detector output signal.
[0032] The nuclear-simulated signal generator uses random numbers generated by a flexible lookup table (V-LUT) random number generator to set the output pulse amplitude spectrum in order to simulate radiation events at different energy levels.
[0033] This invention describes a flexible FPGA-based lookup table random number generation method using a general model, which can be customized and optimized for various applications; namely, the Versatile LUT (V-LUT) random number generation algorithm. This method first determines the structure of the random number generator, and then determines whether the polynomial representation of its output sequence is a primitive polynomial. This method allows the random number generator to better utilize the hardware characteristics of the FPGA, thereby improving the efficiency of random number generation. The V-LUT random number generator requires a corresponding algorithm to ensure that it can traverse all 2^ ... n-1 There are several states. Attached Figure Description
[0034] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0035] Figure 1 This is a flowchart illustrating a flexible, optimized random number generation method based on FPGA lookup tables.
[0036] Figure 2 This is a schematic diagram of the state transition matrix. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0038] This invention proposes a flexible, optimized random number generation method based on FPGA lookup tables. The method implements a flexible lookup table (V-LUT) random number generator using a hardware FPGA, specifically including (e.g.) Figure 1 (As shown): Step S1, obtain the parameters of the Flexible Lookup Table (V-LUT) random number generator, which are used to determine the period length and resource usage of the random number generator; Step S2, use the V-LUT state transition matrix generation program to create a state transition matrix; Step S3, convert the state transition matrix into Verilog code to implement the corresponding FPGA circuit; Step S4, configure the FPGA circuit by optimizing the parameters of the V-LUT random number generator; Step S5, perform quality testing on the random numbers generated by the V-LUT random number generator.
[0039] First embodiment
[0040] The main steps of generating random numbers using the V-LUT random number generator include:
[0041] Step 1: Determine the necessary parameters
[0042] Four key parameters need to be determined: d - matrix dimension; k - length of shift register; r - number of random bits; t - maximum number of LUT inputs; these parameters will affect the cycle length and resource usage of the random number generator.
[0043] Step 2: Generate the state transition matrix
[0044] Use the automatic V-LUT state transition matrix generation program to create the matrix: Input the parameters (d, k, r, t) determined in the first step; the program will randomly generate a large number of matrices; screen out the primitive matrices that meet the requirements; arbitrarily select a primitive matrix T from them.
[0045] Step 3: Implement the FPGA circuit
[0046] Convert the generated state transition matrix into Verilog code: Use some functions of the matrix screening algorithm; convert the primitive matrix T into Verilog code; implement this code in the FPGA.
[0047] For a V-LUT random number generator that shifts r bits by d bits, its state transition matrix can be divided into four parts: I, A1, A2 and other parts, as Figure 2 shown, matrix I represents the identity matrix of size (d - r); A1 and A2 are matrices that determine which bit is connected to a multi-bit XOR gate.
[0048] Step 4: Configuration and optimization
[0049] To save FPGA resources, it is recommended to use a smaller r value. Implementing a V-LUT on the FPGA requires r XOR gates. When a shorter period is required, set r < d and k = d - r; when a longer period is required but fewer random numbers are needed per period, 0 < k < d - r can be set.
[0050] Step 5: Test the random number quality
[0051] The quality of the generated random numbers can be tested by the following methods: Use the NIST randomness test suite for testing; check the linearity of the Campbell value; analyze the interval distribution between adjacent pulses.
[0052] Among them, the V-LUT algorithm is suitable for implementation in the FPGA and is more resource-efficient than traditional pseudo-random number generators; when using a larger d value (such as d = 128), the probability of finding a primitive matrix will be significantly reduced; the FPGA supports 6-input LUTs, which is beneficial to implementing more complex V-LUT structures.
[0053] Among them, the LUT is the basic hardware resource: The LUT is the most basic logic resource in the FPGA and can be used to implement various combinational logic functions; in the FPGA, the LUT can be configured as any multi-input 1-output logic function; XOR is a logical operation used to implement the state transition in a pseudo-random number generator; in linear feedback shift registers LFSR and other pseudo-random number generators, the XOR operation is a key component.
[0054] Among them, LUT is configured as a shift register: In FPGA design, LUT (Look-Up Table) can be configured as a shift register; In addition to implementing ordinary combinational logic functions, LUT in FPGA can be specially configured in many modern FPGA architectures (such as Xilinx Virtex series) as a mode called SRL (Shift Register LUT).
[0055] In Xilinx FPGAs, a LUT can be configured as a shift register of up to 16-32 bits (depending on the FPGA series); this special configuration utilizes the internal structure of the LUT, enabling a single LUT to replace multiple traditional flip-flops.
[0056] Of all the registers, dr-k+1 are not involved in the XOR operation, and therefore can be configured as LUT-based shift registers, which can further reduce FPGA resource usage. Specific application procedures include:
[0057] (1) Identify non-feedback paths: In the V-LUT structure, identify those registers that do not participate in the XOR feedback calculation; these registers only perform simple shift operations.
[0058] (2) Optimize the mapping: map these simple shift registers to the LUT-SRL structure. One LUT can implement the shift function of multiple bits, reducing the number of flip-flops required.
[0059] (3) Resource reduction: For example, when d=10, r=4, k=3, there will be dr-k+1=4 registers that can be mapped to LUT shift registers; this can significantly reduce the number of flip-flops and LUTs required for the design.
[0060] In a V-LUT pseudorandom number generator, A1 and A2 are key parts of the state transition matrix. They determine which bits are connected to the XOR gate, thus affecting the quality and characteristics of the generated random numbers.
[0061] The state transition matrix of a V-LUT random number generator can be divided into four parts:
[0062] Matrix I - represents the identity matrix of size dr;
[0063] Matrix A1 - A matrix of dimension r×r;
[0064] Matrix A2 - A matrix of dimension r×k, where k≤dr;
[0065] All other parts - are zero.
[0066] The matrix structure and connection relationships of A1 and A2:
[0067] (1) Meaning of matrix elements: Each 1 in the matrix represents a connection that is needed. Each 0 in the matrix represents a connection that is not needed.
[0068] (2) Relationship between matrix rows and XOR gates: Each row of the matrix corresponds to the input configuration of an XOR gate. The 1 in the row indicates that the bit needs to be connected to the corresponding XOR gate.
[0069] The purpose of the A1 matrix:
[0070] Size: r×r matrix;
[0071] Function: Controls how the output of the first r bits of the register is fed back to the XOR gate;
[0072] Impact: Determines the connection pattern in the feedback path.
[0073] The purpose of the A2 matrix:
[0074] Size: r×k matrix, where k≤dr;
[0075] Function: Controls how the output of the following k-bit register is connected to the XOR gate;
[0076] Impact: Increased randomness and period length.
[0077] Practical connection example: Based on d=8, r=4, k=4 (n is d, representing the matrix dimension):
[0078]
[0079] The first four rows of the state transition matrix T contain matrices A1 (4×4) and A2 (4×4). For example, the first row [1 0 1 0| 1 0 0 0] indicates that the first XOR gate is connected to the outputs of the 1st, 3rd, and 5th bit registers. The last four rows are the identity matrix I (4×4), representing simple shift operations.
[0080] Second embodiment
[0081] Application of V-LUT PRNG in Nuclear Simulation Signal Generators: Nuclear simulation signal generators are devices used to simulate the output signals of nuclear reactor detectors, requiring high-quality random numbers to accurately simulate the randomness of nuclear radiation events. V-LUT PRNGs, as pseudo-random number generators optimized for FPGAs, have important applications in nuclear simulation signal generators.
[0082] The random numbers in the nuclear simulation signal generator are mainly used for the following purposes: pulse sequence generation: simulating nuclear radiation events that conform to the Poisson distribution; white noise generation: simulating noise in the detector output signal; output pulse amplitude spectrum setting: simulating radiation events at different energy levels.
[0083] Pulse sequence generation specifically involves using a V-LUT PRNG to generate the number of pulses per cycle to simulate the arrival of a nuclear radiation event. The implementation method involves using an inverse transform sampling algorithm to convert the uniformly distributed random numbers generated by the V-LUT into the number of pulses per cycle conforming to a Poisson distribution. The advantages are: the efficient implementation of V-LUT reduces FPGA resource consumption while maintaining good randomness.
[0084] Third Embodiment
[0085] For a V-LUT random number generator, its state transition matrix is divided into four parts: I, A1, A2, and others. Matrix I represents an identity matrix of size nr, and A1 and A2 are matrices that determine which bit is connected to the multi-bit XOR gate. The dimensions of these matrices are respectively... and ,in All parts except I, A1, and A2 are zero. To save FPGA resources, it is recommended to use a smaller r, because implementing a V-LUT on an FPGA requires r XOR gates.
[0086] Here are a few simple examples with different combinations of (r, n), where n is d:
[0087] When r=n, a V-LUT random number generator becomes a LUT-OPT random number generator.
[0088]
[0089] When certain applications require a longer period and a smaller number of random numbers per period... It is a more reasonable choice.
[0090]
[0091] When better random number quality, i.e., a longer period length, can be set... For example, when hour:
[0092]
[0093] At this point, nr-k+1 registers are not involved in the XOR operation, so they can be configured as LUT-based shift registers, which can further reduce the amount of FPGA resources used.
[0094] First, a large number of matrices conforming to the V-LUT pseudo-random generator structure are randomly generated, and then verified to select qualified matrices. To reduce computation time, this invention proposes a custom matrix characteristic polynomial algorithm optimized for specific matrices. Each 1 value in each row of the matrix represents an XOR operation requiring one input, which is then performed by a lookup table. Ideally, for resource efficiency, the number of inputs should not exceed the number of inputs to a single LUT slice.
[0095] Compared to previous work, the V-LUT method offers a wider search range. Therefore, more alternative random number generators can be implemented, while using a minimal polynomial-based approach avoids the problem of computational precision.
[0096] The FPGA code generation process for V-LUT mainly includes three steps:
[0097] Step 1: Randomly generate a large number of matrices based on user-defined parameters (d, k, r, t).
[0098] Step 2: Locate all the original matrices generated in Part 1. Step 2 has two sub-processes.
[0099] Process 1: The matrix characteristic polynomial algorithm. Obtain the first d+1 vectors generated by T, and calculate the minimal polynomial P(z) of the sequence. First, eliminate some obviously reducible P(z). For example, if the degree of P(z) is less than d, the current matrix T is rejected. Then, factorize all the polynomials that have passed the initial screening. If there are two or more irreducible factors, reject the matrix.
[0100] Process 2: All polynomials P(z) passed through Process 1 are irreducible. Traversal All prime factors of f, if any prime factor f satisfies If the matrix fails to pass through process 2, it is rejected. All matrices that pass through process 2 are considered primitive.
[0101] Step 3: Convert the original matrix T into Verilog code.
[0102] Step 3: Integrating with Xorshift, LUT-OPT, LUT-SR, Versatile LUTs, and other LUT-based technologies. It is compatible with any other possible linear recursive random number generator structure. The probability that the random polynomial is an nth-degree primitive polynomial can be described as follows: ,in This refers to Euler's totient function. Most randomly generated matrices are non-invertible, with only a few being primitive. Here's an example illustrating the implementation of this invention in an FPGA with d=128, k=10, and r=16. First, the LUT in the FPGA can be configured as a 6-input XOR gate or a 32-bit shift register. In this case, the V-LUT uses 16 XOR gates to generate random bits. Of the 128-bit register, dk-r+1=103 bits can be used as LUT-based shift registers. This not only reduces resource usage but also lowers the timing constraints in the FPGA. If Xorshift were implemented directly in the FPGA, 128 LUTs and 128 registers would be needed, which places higher demands on both resources and timing constraints. Using V-LUTs requires 20 LUTs and 26 registers, representing 15% and 20% of the Xorshift algorithm's requirements, respectively.
[0103] In summary, when the number of random numbers required per cycle is small and the random number cycle requirement is long, using V-LUT can significantly reduce FPGA resource consumption and the difficulty of implementing pseudo-random number generators.
[0104] Please note that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be pointed out that for those skilled in the art, several modifications and improvements can be made without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A flexible, optimized random number generation method based on FPGA lookup tables, characterized in that, The method is implemented based on the hardware FPGA to realize the flexible lookup table V-LUT random number generator, specifically including: Step S1, obtaining the parameters of the flexible lookup table V-LUT random number generator, where the parameters are used to determine the cycle length and resource usage of the random number generator; In step S1, the parameters include the matrix dimension d, the shift register length k, the random bit number r, and the maximum input number t of the lookup table; Step S2, using the flexible lookup table V-LUT state transition matrix generation program to create the state transition matrix; In step S2, based on the parameters, the flexible lookup table V-LUT state transition matrix generation program randomly generates several matrices, and selects a primitive matrix T that meets the requirements as the state transition matrix; Step S3, converting the state transition matrix into Verilog code to implement the corresponding FPGA circuit; In step S3, for a flexible lookup table V-LUT random number generator with a random bit number r and a matrix dimension d, its state transition matrix is divided into: I, A1, A2 and other parts; I represents the identity matrix with a size of d-r, A1 and A2 are sub-matrices used to determine the specific bits connected to the FPGA multi-bit XOR gate, the dimension of A1 is r×r, the dimension of A2 is r×k, and other parts are all 0; In step S3: For the sub-matrices A1 and A2 in the state transition matrix, each 1 indicates that a connection is required, each 0 in the matrix indicates that no connection is required, each row corresponds to the input configuration of an XOR gate, and the 1 in the row indicates that this bit needs to be connected to the corresponding XOR gate; For the sub-matrix A1, it controls the output feedback of the first r-bit registers to the XOR gate to further determine the connection mode in the feedback path; For the sub-matrix A2, it controls the output connection of the last k-bit registers to the XOR gate to further increase the randomness and cycle length; Step S4, configuring the FPGA circuit by optimizing the parameters of the flexible lookup table V-LUT random number generator; Step S5, performing quality testing on the random numbers generated by the flexible lookup table V-LUT random number generator.
2. The flexible FPGA lookup table-based optimized random number generation method according to claim 1, characterized in that, In step S4: Set the value of r, and define the number of XOR gates required by the FPGA circuit as r; When the cycle length of the random number generator is the first length, set r < d and k = d-r; When the cycle length of the random number generator is the second length and the required number of random numbers is lower than the number threshold, set 0 < k < d-r; Where the first length is less than the second length.
3. The flexible FPGA lookup table-based optimized random number generation method according to claim 2, characterized in that, In step S5, the quality testing includes: Performing quality testing using the NIST randomness test suite; Checking the linearity of the Campbell value; Analyzing the interval distribution between adjacent pulses.
4. The flexible FPGA lookup table-based optimized random number generation method according to claim 3, characterized in that, In the method: Configure the registers not participating in the XOR gate operation in the FPGA circuit as shift registers based on the flexible lookup table V-LUT to reduce the resource usage of the random number generator, and map the shift registers based on the flexible lookup table V-LUT to the LUT-SRL structure to further reduce the required number of flip-flops.
5. The flexible FPGA lookup table-based optimized random number generation method according to claim 1, characterized in that, In the method, a flexible lookup table (V-LUT) random number generator is applied to a nuclear-simulated signal generator, which is used to simulate the output signal of a nuclear reactor detector. The random numbers generated by the V-LUT random number generator are used to simulate the randomness of nuclear radiation events.
6. The flexible FPGA lookup table-based optimized random number generation method according to claim 5, characterized in that, In the method: The nuclear signal generator uses random numbers generated by a flexible lookup table (V-LUT) random number generator to generate pulse sequences, thereby simulating nuclear radiation events that conform to a Poisson distribution. The nuclear-simulated signal generator uses random numbers generated by a flexible lookup table (V-LUT) random number generator to generate white noise in order to simulate the noise in the detector output signal. The nuclear-simulated signal generator uses random numbers generated by a flexible lookup table (V-LUT) random number generator to set the output pulse amplitude spectrum in order to simulate radiation events at different energy levels.