Mutual exclusion lock device based on hardware implementation and control method thereof

Abstract

The invention discloses a hardware-based mutual exclusion lock device and a control method thereof, and belongs to the technical field of data processing, the hardware-based mutual exclusion lock device comprises hardware and software, and the hardware is connected with the software; the hardware comprises a first register, a second register and a first counter, and the first register is connected with the first counter; the software comprises a locking interface and a release locking interface, the locking interface is connected with the release locking interface, the first register and the second register, and the release locking interface is connected with the second register. According to the mutual exclusion lock device realized based on hardware, a high-speed mutual exclusion scheme for verifying mutual exclusion in current different address spaces in an operating system is not needed, and the mutual exclusion requirements of different address spaces in current high-performance application scenes such as a high-speed data forwarding plane and the like are met.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a hardware-implemented mutex device and its control method. Background Art

[0002] Mutex technology is mainly used for mutual exclusion between different contexts, such as protecting shared resources accessed between multiple processes and multiple threads. Generally speaking, when multiple processes and multiple threads need to work together, they need to access one or more shared resources. When accessing shared resources, not all threads / processes can access the resources simultaneously. Simultaneous access will result in errors and the cooperation result will not meet the expectations. At this time, a mutex mechanism is needed to ensure that only one thread / process can access the shared resource at the same time. In the operating system implementation technology, the existing critical section mutex technologies mainly include semaphores and spin locks. The basic principle is that the shared resource accessor first competes for the semaphore / spin lock. At the same time, only one competitor can compete for the semaphore / spin lock. The person who successfully competes for the semaphore / spin lock can be considered to have obtained the lock successfully, and the shared resource is locked. After successfully obtaining the lock, other competitors cannot lock successfully again until the competitor who obtained the lock successfully releases the lock, and then other competitors have the opportunity to obtain the lock successfully again. The competitor who successfully locks can safely access the shared resource. After the access is completed, the lock is released, and then other competitors lock and access the shared resource after locking. Thus, the purpose of mutual exclusion access to shared resources by multiple competitors is achieved.

[0003] The above-mentioned semaphore / spin lock implementation is commonly used in the same address space. For example, different threads in the same process or kernel are in the same address space. However, different processes, between the user space and the kernel space belong to different address spaces, and cannot directly access each other. The mutex lock needs to be placed in the kernel space. The user space process competes for the semaphore / spin lock through system calls such as ioctl to enter the kernel space to complete the locking, so as to achieve the purpose of mutual exclusion in different address spaces.

[0004] In today's high-concurrency and high-speed data processing scenarios, the network interface has a high rate, the CPU core processes a large number of packets, and high performance is pursued. The traditional technology of mutual exclusion between different address spaces by means of the kernel space has low performance due to system calls involving kernel entry, exit, and context switching, and cannot meet the requirements of high-speed data processing and forwarding. The technology of mutual exclusion between different address spaces by means of the kernel space needs to enter the kernel through the system call interface to compete for the lock. The system call interface involves kernel entry, exit, and context switching. There is no problem in traditional low-speed application scenarios, but it can no longer meet the high-speed requirements of today's data processing and forwarding plane. Summary of the Invention

[0005] The purpose of this application is to overcome the defects of the prior art and provide a hardware - based mutex device and its control method to meet the high - speed mutex competition requirements in different address spaces.

[0006] In a first aspect, this application provides a hardware - based mutex device, including: hardware and software, where the hardware is connected to the software; The hardware includes: a first register, a second register, and a first counter, where the first register is connected to the first counter; The software includes: a lock interface and a release lock interface, where the lock interface is connected to the release lock interface, the first register, and the second register, and the release lock interface is connected to the second register.

[0007] Optionally, the first register is a read - only register, and the second register is a readable and writable register.

[0008] Optionally, the first register includes a first sequence number, which is used to represent the queuing sequence number when the software competes for the lock.

[0009] Optionally, the first register atomically obtains the current value of the first counter and increments the current value of the first counter by one; the two tasks of obtaining the current value of the first counter and returning it to the software and incrementing the current value of the first counter by one are completed by the hardware logic in the implementation of the software reading the first register. For the software, these two tasks are atomic.

[0010] Optionally, the second register includes a second sequence number, which is used to represent the sequence number that is currently allowed to obtain the lock.

[0011] Optionally, the lock interface reads the first sequence number of the first register and the second sequence number of the second register, judges the first sequence number and the second sequence number, and completes the locking; the release lock interface obtains the first sequence number from the lock interface, increments the first sequence number by one, sends a write request to the second register, and writes the incremented first sequence number into the second register.

[0012] Optionally, the software further includes an address mapping interface, which is respectively connected to the release lock interface and the release lock interface, and is used to map the physical addresses of the first register and the second register to the address space where the software runs.

[0013] In a second aspect, this application also provides a control method for a hardware - based mutex device, which is used to control the hardware - based mutex device described in any item of the first aspect, and includes the following steps: Initialize the first register, the second register, and the first counter; Map the physical addresses of the first register and the second register to the address mapping interface of the software; When acquiring a lock, the software sends a read request to the first register through the locking interface to obtain the first sequence number of the first register; the locking interface sends a read request to the second register to obtain the second sequence number of the second register, and judges the first sequence number and the second sequence number to complete the locking; When releasing a lock, the release locking interface obtains the first sequence number from the locking interface, increments the obtained first sequence number by one, and sends a write request to the second register; the second register receives the write request and performs a write operation to complete the lock release.

[0014] Optionally, when acquiring a lock, the software sends a read request to the first register through the locking interface to obtain the first sequence number of the first register; the locking interface sends a read request to the second register to obtain the second sequence number of the second register, and judges the first sequence number and the second sequence number to complete the locking, including: Send a read request to the first register through the locking interface; The first register receives the read request, obtains the value of the first counter, and increments the value of the first counter by one; The first register uses the obtained value of the first counter as the first sequence number and returns the first sequence number to the locking interface; The locking interface sends a read request to the second register to obtain the second sequence number of the second register; Compare the first sequence number with the second sequence number. If the first sequence number is the same as the second sequence number, the locking is completed; if the first sequence number is different from the second sequence number, wait and repeat reading the second sequence number until the obtained second sequence number is equal to the first sequence number to complete the locking.

[0015] Optionally, when releasing a lock, the release locking interface obtains the first sequence number from the locking interface, increments the obtained first sequence number by one, and sends a write request to the second register; the second register receives the write request and performs a write operation to complete the lock release, including: The release locking interface obtains the first sequence number, increments the obtained first sequence number by one, and sends a write request to the second register; The second register receives the write request and judges whether the written value is equal to the current value of the second register plus one. If not, discard the current write request and keep the current value of the second register unchanged; if the written value is equal to the current value of the second register plus one, perform a write operation to update the value of the second register; After the second register completes the write operation, the release lock interface returns a status code indicating successful lock release, implementing lock release.

[0016] This application provides a hardware-implemented mutex device and its control method. By setting two registers and arranging them for queued access, interference is avoided and a fast mutex is achieved. By setting a first sequence number and a second sequence number, the uniqueness and orderliness of the sequence numbers during multi-threaded competition are ensured. By directly mapping the physical addresses of the registers to different software spaces, software running in different address spaces can directly access the registers, eliminating the need to enter the kernel through system calls to complete locking and unlocking. This reduces the overhead caused by saving and reloading the context during context switching, reduces the performance impact caused by cache invalidation due to context switching, and reduces the performance jitter during CPU operation, providing a low-latency and highly reliable mutex solution for high-speed data processing and multi-process high-performance scenarios.

[0017] To make the above features and advantages of the invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 It is a schematic structural diagram of a hardware-implemented mutex device provided in an embodiment of this application.

[0020] Figure 2 It is a flowchart of the control method of a hardware-implemented mutex device provided in another embodiment of this application.

[0021] Figure 3 It is a flowchart of step S3 in the control method of a hardware-implemented mutex device provided in another embodiment of this application.

[0022] Figure 4 It is a flowchart of the read operation of the sequence number request register in step S32 of the control method of a hardware-implemented mutex device provided in another embodiment of this application.

[0023] Figure 5 It is a flowchart of step S4 in the control method of a hardware-implemented mutex device provided in another embodiment of this application.

[0024] Figure 6This is the flowchart of the write operation of the sequence number confirmation register for step S42 in the control method of the mutex device implemented based on hardware provided in another embodiment of this application. Detailed implementation manners

[0025] To make the objectives and technical solutions of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of this application without creative efforts shall fall within the scope of protection of this application.

[0026] In one embodiment, please refer to Figure 1 , this application provides a mutex device implemented based on hardware, which may include: hardware 1 and software 2, where hardware 1 is connected to software 2; hardware 1 includes a sequence number request register (Token - Require register) 11, a sequence number confirmation register (Token - Current register) 12, and a sequence number counter (sequence counter) 13, and the sequence number request register 11 is connected to the sequence number counter 13; software 2 includes a lock interface 21 and a release lock interface 22, the lock interface 21 is connected to the release lock interface 22, the sequence number request register 11, and the sequence number confirmation register 12, and the release lock interface 22 is connected to the sequence number confirmation register 12.

[0027] As an example, the sequence number request register 11 may be a read - only register to limit the operation authority of software 2 on the sequence number request register 11 and be able to resist the tampering of malicious software on the sequence number request register 11.

[0028] As an example, the sequence number request register 11 includes a first queuing sequence number Require - ID, which is used to represent the sequence number when software competes for the lock. The first queuing sequence number Require - ID may be unique and incrementing.

[0029] As an example, the sequence number request register 11 is used to obtain the current value of the sequence number counter 13, use the current value of the sequence number counter 13 as the first queuing sequence number Require - ID of the sequence number request register 11, and output the first queuing sequence number Require - ID to software 2.

[0030] As an example, when software 2 acquires a lock, it reads the sequence number request register 11. The sequence number request register 11 obtains the current value of the sequence number counter 13 and increments the value of the sequence number counter 13 by one. The sequence number request register 11 returns the current value of the sequence number counter 13 read as the first queuing sequence number Require-ID to software 2. The first queuing sequence number Require-ID is unique. Software 2 obtains the unique value of the first queuing sequence number Require-ID by reading the sequence number request register 11, without directly operating on the sequence number counter 13, ensuring the atomicity and efficiency of the reading mechanism, and simplifying the development complexity of software 2 at the same time.

[0031] As an example, the sequence number request register 11 obtains the current value of the sequence number counter 13 and increments the value of the sequence number counter 13 by one. These two tasks are completed by the hardware logic in the implementation of software 2 reading the sequence number request register 11. For software 2, these two tasks are atomic, that is, these two operations are inseparable. After the sequence number request register 11 obtains the current value of the sequence number counter 13 each time, it will immediately increment the value of the sequence number counter 13 to ensure the uniqueness and orderliness of the generation of the first queuing sequence number Require-ID. Software 2 can only obtain the value of the first queuing sequence number Require-ID through a read operation, and the increment of the sequence number counter 13 is automatically completed by the sequence number request register 11 without the intervention of software 2. Even in a multi-processor / multi-thread concurrent request scenario, the sequence number request register 11 will ensure that each read operation returns a unique and incrementing first queuing sequence number Require-ID, avoiding duplication or race conditions of the first queuing sequence number Require-ID.

[0032] As an example, the sequence number confirmation register 12 can be a readable and writable register to achieve the correct locking and unlocking of the lock, enabling software 2 to directly operate on the sequence number confirmation register 12 without relying on the operating system kernel, avoiding context switching caused by system calls, enabling the mutex mechanism to adapt to high-speed data processing scenarios, and improving the overall performance of the system in application scenarios with high-performance requirements for multi-processes.

[0033] As an example, the sequence number confirmation register 12 is used to store the value of the second queuing sequence number Current-ID that is currently allowed to acquire the lock. The value of the second queuing sequence number Current-ID is the value of the sequence number confirmation register 12. The second queuing sequence number Current-ID is used to represent the queuing sequence number currently allowed to acquire the lock.

[0034] As an example, the sequence number confirmation register 12 inputs the value written by software 2 when releasing the lock and outputs the currently stored value of the second queuing sequence number Current-ID.

[0035] As an example, when a write operation is performed on the sequence number confirmation register 12, the sequence number confirmation register 12 needs to determine whether the written value is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register 12 plus one. If the written value is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register 12 plus one, the write operation is executed, and the value of the sequence number confirmation register 12 is updated to the written value, that is, updated to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register 12 plus one; if the written value is other values, the current write request is discarded, and the value of the second queuing sequence number Current-ID of the sequence number confirmation register 12 remains unchanged. In this way, to a certain extent, it can prevent the sequence number confirmation register 12 from being maliciously rewritten.

[0036] As an example, when the software 2 releases the lock, the software 2 writes the value obtained from the first queuing sequence number Require-ID in the sequence number request register 11 plus one into the sequence number confirmation register 12. The sequence number confirmation register 12 checks the written value. If the written value is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register 12 plus one, the value of the second queuing sequence number Current-ID is updated to obtain a new value of the second queuing sequence number Current-ID. The new value of the second queuing sequence number Current-ID is equal to the value of the first queuing sequence number Require-ID plus one, that is, the original second queuing sequence number Current-ID plus one.

[0037] As an example, the access speeds of the sequence number request register 11 and the sequence number confirmation register 12 are very fast, much faster than memory access, making it faster than the semaphore spin lock access implemented by relying on memory variables.

[0038] As an example, the sequence number counter 13 is bound to the sequence number request register 11 and is used to provide a unique first queuing sequence number Require-ID value for the sequence number request register 11, ensuring the mutual exclusion access order, guaranteeing the orderliness of lock requests, the fairness of lock competition, the correctness of lock release, and guaranteeing the orderliness of lock competition.

[0039] As an example, when the sequence number counter 13 receives a read request from the sequence number request register 11, it outputs the current value of the sequence number counter 13 to the sequence number request register 11, and after the read operation is completed, the current value of the sequence number counter 13 is automatically incremented by one to achieve automatic update. In this way, it is ensured that each read operation can obtain a unique and incrementing value, thereby guaranteeing the orderliness and uniqueness of the first queuing sequence number Require-ID value.

[0040] As an example, the hardware 1 can be a chip.

[0041] As an example, the access requests to the sequence number request register 11 and the sequence number confirmation register 12 are always queued serially. The access requests are not discarded or concurrent within the hardware 1 to ensure the accuracy and orderliness of the data access to the sequence number request register 11 and the sequence number confirmation register 12.

[0042] As an example, the initial values of the sequence number request register 11, the sequence number confirmation register 12, and the sequence number counter 13 are all zero.

[0043] As an example, the locking interface 21 is used to read the first queued sequence number Require-ID value of the sequence number request register 11 and the second queued sequence number Current-ID value of the sequence number confirmation register 12. By judging the first queued sequence number Require-ID value and the second queued sequence number Current-ID value, the locking is completed and the status of "locking successful" is returned.

[0044] As an example, the locking interface 21 reads the first queued sequence number Require-ID value of the sequence number request register 11 atomically, and the locking interface 21 reads the first queued sequence number Require-ID of the sequence number request register 11 cyclically. Specifically, the locking interface 21 reads the first queued sequence number Require-ID value of the sequence number request register 11 and the second queued sequence number Current-ID value of the sequence number confirmation register 12, and compares the first queued sequence number Require-ID value with the second queued sequence number Current-ID value. If the first queued sequence number Require-ID value is the same as the second queued sequence number Current-ID value, the locking is completed; if the first queued sequence number Require-ID value is different from the second queued sequence number Current-ID value, wait and repeat reading the second queued sequence number Current-ID value until the obtained second queued sequence number Current-ID value is equal to the first queued sequence number Require-ID value, and the locking is completed.

[0045] As an example, the locking interface 21 can also be used to send the first queued sequence number Require-ID value to the lock release interface 22, so that the release operation does not depend on re-reading the sequence number request register 11, but directly uses the sequence number saved during locking, ensuring consistency with the operation logic of the registers in the hardware, ensuring that the acquisition and release of the lock are completed by the same entity, avoiding accidental release, and also being able to reduce one hardware interaction and reduce latency.

[0046] As an example, the lock release interface 22 is used to atomically update the sequence number confirmation register 12, release the acquired lock resource, and release the lock resource efficiently and safely, ensuring concurrent correctness and performance optimization.

[0047] As an example, the unlock interface 22 obtains the first queuing serial number Require-ID value from the lock interface 21, sends a write request to the serial number confirmation register 12 after incrementing the first queuing serial number Require-ID value by one, and writes the value obtained by incrementing the first queuing serial number Require-ID value by one into the serial number confirmation register 12. When the serial number confirmation register 12 receives the write request, it determines whether the value obtained by incrementing the first queuing serial number Require-ID value by one is equal to the value obtained by incrementing the current second queuing serial number Current-ID value of the serial number confirmation register 12 by one. If they are equal, the current value of the second queuing serial number Current-ID of the serial number confirmation register 12 is updated to the value obtained by incrementing the written first queuing serial number Require-ID value by one, obtaining a new second queuing serial number Current-ID value, completing the lock release and returning; if they are not equal, the current write request is discarded, and the second queuing serial number Current-ID value of the serial number confirmation register 12 remains unchanged.

[0048] As an example, the lock interface 21 and the unlock interface 22 can be implemented by code.

[0049] As an example, the software 2 may further include an address mapping interface (not shown). The address mapping interface is connected to the standard interface of the operating system, the unlock interface, and the unlock interface, and is used to map the physical addresses of the serial number request register 11 and the serial number confirmation register 12 to the address space where the software runs. Specifically, the physical addresses of the serial number request register 11 and the serial number confirmation register 12 are mapped to the address space where the software runs through the address mapping interface of the software 2 via the standard interface of the operating system, enabling the software 2 to directly access the hardware 1 through pointers without going through the kernel for transfer, providing a high-speed and kernel-free mutual exclusion capability for different address spaces with mutual exclusion requirements.

[0050] As an example, an address space with mutual exclusion requirements refers to an independent virtual memory space that needs to mutually access shared resources, and may include: the user space of different processes, the user space and the kernel space, different core spaces of a multi-core processor, etc. By mapping the registers in the hardware 1 to these address spaces with mutual exclusion requirements through the operating system, the software 2 can directly operate the registers to achieve high-speed mutual exclusion, avoiding the performance bottleneck caused by traditional kernel transfer.

[0051] As an example, the standard interfaces and parameter settings of different operating systems are different, and can be selected according to the actual situation. For example: the mmap function of the Linux system, the CreateFile, DeviceIoControl or MapPhysicalMemory, ioremap function of the Windows system, etc.

[0052] The above mutex device implemented based on hardware is simple to implement. A fast mutex is achieved by setting two registers for queued access; the unique first queuing serial number Require-ID is generated by atomically reading and incrementing the serial number counter through the serial number request register, ensuring the uniqueness and orderliness of the serial numbers during multi-threaded competition; the write operation is verified through the serial number confirmation register, and only legal writes that increment the current value by one are allowed, which can ensure the correctness of lock release and resist malicious tampering; the physical addresses of the registers are directly mapped to the address spaces of different software through the address mapping interface, and the registers can be directly accessed in the address space without the need to enter the kernel through system calls to complete locking and unlocking, reducing the overhead caused by the saving and reloading of context during context switching, reducing the performance impact caused by cache invalidation due to context switching, and reducing the performance jitter during CPU operation, providing a low-latency and highly reliable mutex solution for high-speed data processing and multi-process high-performance scenarios.

[0053] In another embodiment, please refer to Figure 2 , this application also provides a control method for a mutex device implemented based on hardware, which may include the following steps: Step S1 to Step S4.

[0054] Step S1: Initialize the serial number request register, the serial number confirmation register, and the serial number counter.

[0055] Step S2: Map the physical addresses of the serial number request register and the serial number confirmation register to the address space where the software runs through the address mapping interface.

[0056] Step S3: When acquiring the lock, the software sends a read request to the serial number request register through the locking interface to obtain the value of the first queuing serial number Require-ID of the serial number request register; the locking interface sends a read request to the serial number confirmation register to obtain the value of the second queuing serial number Current-ID of the serial number confirmation register, and judges the value of the first queuing serial number Require-ID and the value of the second queuing serial number Current-ID to complete the locking.

[0057] Step S4: When releasing the lock, the release locking interface obtains the value of the first queuing serial number Require-ID from the locking interface, increments the obtained value of the first queuing serial number Require-ID by one, and sends a write request to the serial number confirmation register; the serial number confirmation register receives the write request and performs the write operation to complete the lock release.

[0058] In the control method of the hardware-implemented mutex device of the present application, through initialization operations, the consistency and reliability of the initial state of the mutex are ensured, providing an orderly starting point for subsequent operations; through the address mapping interface, the physical addresses of the registers are mapped to the address space of the software, enabling the software to directly access the hardware registers, avoiding the context switching overhead of kernel system calls, and laying the foundation for high-speed mutual exclusion access; through the lock interface, a unique first queuing serial number Require-ID value is obtained from the serial number request register, ensuring the uniqueness and orderliness of the lock request serial numbers during multi-threaded competition; through the release lock interface, the second queuing serial number Current-ID value of the serial number confirmation register is updated to release the lock, ensuring the security of the release operation. The method of the present application realizes high-speed mutual exclusion without kernel transfer, can reduce the latency of lock acquisition and release, improve the concurrency efficiency in scenarios of multiple processes and multiple address spaces, and effectively meet the requirements of high-speed data processing for a low-latency mutual exclusion mechanism.

[0059] In step S1, refer to Figure 2 step S1 in, initialize the serial number request register, the serial number confirmation register, and the serial number counter.

[0060] As an example, initialize the serial number request register, the serial number confirmation register, and the serial number counter, and set the initial values of the serial number request register, the serial number confirmation register, and the serial number counter to zero, that is, the initial values of the first queuing serial number Require-ID and the second serial number Current-ID are both zero, providing a reliable initial condition for subsequent lock acquisition and release operations, and ensuring the correctness and stability of the mutex mechanism.

[0061] In step S2, refer to Figure 2 step S2 in, map the physical addresses of the serial number request register and the serial number confirmation register to the address space where the software runs through the address mapping interface.

[0062] As an example, map the physical addresses of the serial number request register and the serial number confirmation register to the address space in the software by operating the address mapping interface to establish a direct communication channel between the software and the registers in the hardware, enabling the software to directly access the registers in the hardware through pointers without kernel transfer, improving the interaction efficiency between the software and the hardware, reducing the call overhead and the time of context switching, and providing high-speed, kernel-free mutual exclusion capabilities for different address spaces with mutual exclusion requirements.

[0063] As an example, the address mapping interface can adopt the standard interface of the system, and the standard interfaces and parameter settings of different operating systems are different, which can be selected according to the actual situation.

[0064] In step S3, refer to Figure 2In step S3, when acquiring the lock, the software sends a read request to the sequence number request register through the locking interface to obtain the value of the first queuing sequence number Require-ID of the sequence number request register; the locking interface sends a read request to the sequence number confirmation register to obtain the value of the second queuing sequence number Current-ID of the sequence number confirmation register, and judges the value of the first queuing sequence number Require-ID and the value of the second queuing sequence number Current-ID to complete the locking.

[0065] For example, please refer to Figure 3 , step S3 may include the following steps: step S31 to step S35.

[0066] Step S31: Send a read request to the sequence number request register through the locking interface.

[0067] Step S32: After receiving the read request, the sequence number request register obtains the value of the sequence number counter and increments the value of the sequence number counter by one.

[0068] Step S33: The sequence number request register uses the obtained value of the sequence number counter as the value of the first queuing sequence number Require-ID and returns the value of the first queuing sequence number Require-ID to the locking interface.

[0069] Step S34: The locking interface sends a read request to the sequence number confirmation register to obtain the value of the second queuing sequence number Current-ID of the sequence number confirmation register.

[0070] Step S35: Compare the value of the first queuing sequence number Require-ID with the value of the second queuing sequence number Current-ID. If the value of the first queuing sequence number Require-ID is the same as the value of the second queuing sequence number Current-ID, the locking is completed; if the value of the first queuing sequence number Require-ID is different from the value of the second queuing sequence number Current-ID, wait and repeatedly read the value of the second queuing sequence number Current-ID until the obtained value of the second queuing sequence number Current-ID is equal to the value of the first queuing sequence number Require-ID, and the locking is completed.

[0071] For example, in step S31, when acquiring the lock, the software calls the locking interface and sends a read request to the sequence number request register in the hardware through the locking interface to obtain a unique sequence number for subsequent lock competition judgment.

[0072] For example, please refer to Figure 4 , in step S32, the sequence number request register receives the read request from the locking interface, initiates a read operation on the sequence number counter, obtains the current value of the sequence number counter, and increments the current value of the sequence number counter by one to realize the automatic update of the sequence number counter.

[0073] As an example, the sequence number request register obtains the current value of the sequence number counter, increments the value of the sequence number counter by one, and is atomic to ensure the uniqueness and orderliness of the generation of the first queuing sequence number Require-ID value.

[0074] As an example, in step S33, the current value of the sequence number counter is saved to the sequence number request register as the first queuing sequence number Require-ID value, that is, the obtained value of the sequence number counter is used to update the first queuing sequence number Require-ID value, and the sequence number request register returns the first queuing sequence number Require-ID value to the lock interface.

[0075] As an example, the value of the sequence number counter is always 1 greater than the first queuing sequence number Require-ID value of the sequence number request register.

[0076] As an example, in step S34, the software sends a read request to the sequence number confirmation register through the lock interface to obtain the sequence number currently allowed to acquire the lock stored in the sequence number confirmation register, that is, to obtain the second queuing sequence number Current-ID value.

[0077] As an example, in step S35, the lock interface compares the first queuing sequence number Require-ID value with the second queuing sequence number Current-ID value. If the first queuing sequence number Require-ID value is the same as the second queuing sequence number Current-ID value, the right to use the lock is obtained and the lock is successfully acquired; if the first queuing sequence number Require-ID value is different from the second queuing sequence number Current-ID value, the lock is held by other software, enters the spin-wait state, and the lock interface continuously sends a read request to the sequence number confirmation register to obtain the latest second queuing sequence number Current-ID value, and immediately compares the new second queuing sequence number Current-ID value with the first queuing sequence number Require-ID value after each read until the obtained second queuing sequence number Current-ID value is equal to the first queuing sequence number Require-ID value, and the lock is successfully acquired.

[0078] Further, after the lock is successfully acquired, the lock interface can return a non-zero value indicating successful acquisition of the lock.

[0079] As an example, after the software returns a non-zero value from the lock interface, it means that the software has successfully competed for the lock and can initiate access to the critical section and perform read and write operations on the shared resources.

[0080] As an example, the lock interface can return 1 to indicate completion of locking.

[0081] As an example, during the spin-wait process, the thread will not be suspended, that is, no kernel scheduling is required, but continuously sends a read request to the sequence number confirmation register to ensure a low-latency response to the lock release event.

[0082] In step S4, refer to Figure 2 step S4 therein. When releasing the lock, the release lock interface obtains the value of the first queuing sequence number Require-ID from the lock interface, increments the obtained value of the first queuing sequence number Require-ID by one, and sends a write request to the sequence number confirmation register; the sequence number confirmation register receives the write request, performs a write operation, and completes the lock release.

[0083] As an example, refer to Figure 5 , step S4 may include the following steps: step S41 to step S43.

[0084] Step S41: The release lock interface obtains the value of the first queuing sequence number Require-ID, increments the obtained value of the first queuing sequence number Require-ID by one, and sends a write request to the sequence number confirmation register.

[0085] Step S42: After receiving the write request, the sequence number confirmation register determines whether the written value is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register plus one. If not, the current write request is discarded, and the current value of the second queuing sequence number Current-ID of the sequence number confirmation register remains unchanged; if the written value is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register plus one, a write operation is performed to update the value of the second queuing sequence number Current-ID of the sequence number confirmation register.

[0086] Step S43: After the sequence number confirmation register completes the write operation, the release lock interface returns the status code of successfully releasing the lock to implement the lock release.

[0087] As an example, in step S41, after the software accesses the critical section, it needs to release the lock to give other software the opportunity to continue to lock the critical section. The software obtains the currently held value of the first queuing sequence number Require-ID from the lock interface through the release lock interface, increments the obtained value of the first queuing sequence number Require-ID by one to obtain a new value of the first queuing sequence number Require-ID, and sends a write request to the sequence number confirmation register to write the new value of the first queuing sequence number Require-ID into the sequence number confirmation register.

[0088] As an example, refer to Figure 6, in step S42, the sequence number confirmation register receives a write request and determines whether the first queuing sequence number Require-ID to be written is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register plus one. If the value of the first queuing sequence number Require-ID to be written is not equal to the current value of the second queuing sequence number Current-ID plus one, the sequence number confirmation register rejects the write operation, discards the current write request, keeps the current second queuing sequence number Current-ID unchanged, and returns an error status code to the software; if the value of the first queuing sequence number Require-ID to be written is equal to the current value of the second queuing sequence number Current-ID of the sequence number confirmation register plus one, then the write operation is executed, the value of the first queuing sequence number Require-ID is written into the sequence number confirmation register, and the current value of the second queuing sequence number Current-ID of the current sequence number confirmation register is updated.

[0089] As an example, the sequence number confirmation register's rejection of the write operation can indicate an illegal release, that is, a non-lock holder attempts to release the lock; it can indicate a duplicate release, that is, the lock holder releases the same lock multiple times; it may also indicate a concurrent conflict, that is, multiple threads attempt to release the lock simultaneously.

[0090] As an example, when the software performs a write operation on the sequence number confirmation register, the value written and the value after the current value of the first queuing sequence number Require-ID of the sequence number confirmation register plus one must be equal because the locking condition is that the value of the first queuing sequence number Require-ID is equal to the value of the second queuing sequence number Current-ID.

[0091] As an example, in step S43, after the sequence number confirmation register successfully updates the value, it sends a write completion signal to the release lock interface, indicating that the write operation has been atomically completed. The release lock interface returns a status code to the caller, that is, the release lock interface returns a status code indicating successful lock release to the software, implementing lock release.

[0092] As an example, when the sequence number confirmation register completes the write operation, if there is a spin-waiting lock interface in step S35, then the lock interface will end the spin wait and successfully acquire the lock.

[0093] As an example, since the first queuing sequence number Require-ID value of the sequence number request register returns the current value of the sequence number counter and increments the sequence number counter by 1 when read by software, other competitors (i.e., other software) will definitely increment the queuing sequence number value by 1 in sequence when they read. After the software that successfully locks this time releases the lock, the second queuing sequence number Current-ID value of the sequence number confirmation register will also be updated to the original second queuing sequence number Current-ID value plus 1. Then, after releasing the lock, it will definitely allow the next competitor whose first queuing sequence number Require-ID value is 1 greater than that of the competitor (i.e., the software that successfully locks this time) that successfully locks this time to complete the lock. By analogy, mutual exclusion services can be continuously implemented.

[0094] In one example, it can be analogized to the operation of a restaurant with only one food pickup window. Each competitor who comes to obtain a lock is equivalent to getting a queuing number at the food pickup window, and this queuing number increases by 1. The queuing numbers obtained by different competitors must be different. The sequence number request register and the sequence number counter together achieve the purpose of assigning a different queuing number to each competitor. After the queuing number is obtained, it comes to the calling number link. The food pickup window will call the numbers in sequence. Only the competitor whose number is called can pick up food from the window, and the competitors whose numbers are not called can only wait first. In this way, the purpose of providing orderly service to all competitors is achieved. The purpose of calling the number is completed through the sequence number confirmation register. The initial values of the sequence number request register and the sequence number confirmation register are 0. Then, for the first competitor who comes to get the number, both the first queuing number Require-ID value and the second queuing number Current-ID value are 0. It will successfully lock and then can safely access the critical section. For the second competitor who comes to get the number, the first queuing number Require-ID value will be 1. Before the first competitor releases the lock, the second competitor who comes to get the number always reads the second queuing number Current-ID value as 0. Then, the second competitor can only spin and wait and repeatedly read the sequence number confirmation register until the first competitor releases the lock. When the first competitor releases the lock, it will write the value obtained by adding 1 to its first queuing number Require-ID value into the sequence number confirmation register. The judgment logic of the sequence number confirmation register will judge the write operation, and the write can succeed only when it meets the write conditions of the sequence number confirmation register. After the write succeeds, the second queuing number Current-ID value of the sequence number confirmation register will become 1. At this time, when the second competitor repeatedly reads the sequence number confirmation register, it will read the second queuing number Current-ID value as 1, and its first queuing number Require-ID value is also 1. At this time, it will complete the lock and can safely access the critical section. Other competitors who get other first queuing number Require-ID values will queue up and wait in the same way until the first queuing number Require-ID value is equal to the second queuing number Current-ID value to obtain the lock, and can access the critical section only after obtaining the lock.

[0095] In the control method of the hardware-implemented mutex device of the present application, by directly mapping the physical address of the register to the address space of the software, the register can be directly accessed locally, and there is no longer a need to enter the kernel through a system call to complete locking and unlocking. This reduces the overhead caused by the saving and refilling of the context during frequent context switches, reduces the performance impact caused by cache invalidation due to frequent context switches, reduces the performance jitter during the operation of the CPU, and constructs a high-speed mutual exclusion access channel; by obtaining the unique first queuing sequence number Require-ID from the sequence number request register through the lock interface, the uniqueness and orderliness of the lock request sequence numbers during multi-threaded competition are ensured; by releasing the lock interface to update the second queuing sequence number Current-ID of the sequence number confirmation register to release the lock, problems such as illegal release and repeated release are effectively prevented, ensuring the security of the release operation. The method of the present application realizes high-speed mutual exclusion without kernel transfer, can greatly reduce the latency of lock acquisition and release, significantly improve the concurrency efficiency in multi-process and multi-address space scenarios, and effectively meet the stringent requirements of high-speed data processing for a low-latency mutual exclusion mechanism.

[0096] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0097] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0098] Although the present application has been disclosed as above with embodiments, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field to which the present application pertains can make some modifications and refinements without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to that defined by the appended patent application scope.

Claims

1. A hardware-implemented mutex device, characterized in that, Comprising: Hardware and software, the hardware being connected to the software; The hardware includes: a first register, a second register, and a first counter, the first register being connected to the first counter; The software includes: a lock interface and a release lock interface, the lock interface being connected to the release lock interface, the first register, and the second register, and the release lock interface being connected to the second register.

2. The hardware-implemented mutex device according to claim 1, wherein The first register is a read-only register, and the second register is a read-write register.

3. The hardware-implemented mutex device according to claim 2, wherein The first register includes a first serial number, and the first serial number is used to represent the queuing serial number when the software competes for the lock.

4. The hardware-implemented mutex device according to claim 3, wherein The first register atomically obtains the current value of the first counter and increments the current value of the first counter by one.

5. The hardware-implemented mutex device according to claim 4, wherein The second register includes a second serial number, and the second serial number is used to represent the queuing serial number currently allowed to obtain the lock.

6. The hardware-implemented mutex device according to claim 5, characterized in that The lock interface reads the first serial number of the first register and the second serial number of the second register, judges the first serial number and the second serial number, and completes the locking; the release lock interface obtains the first serial number from the lock interface, increments the first serial number by one, sends a write request to the second register, and writes the incremented first serial number into the second register.

7. The hardware-implemented mutex device according to claim 1, characterized in that, The software further includes an address mapping interface, the address mapping interface being respectively connected to the release lock interface and the release lock interface, and being used to map the physical addresses of the first register and the second register to the address space where the software runs.

8. A control method for a hardware-implemented mutex device, characterized in that, For controlling the hardware-implemented mutex device according to any one of claims 1 to 7, comprising the following steps: Initializing the first register, the second register, and the first counter; Mapping the physical addresses of the first register and the second register to the address space where the software runs through the address mapping interface; When obtaining the lock, the software sends a read request to the first register through the lock interface to obtain the first serial number of the first register; the lock interface sends a read request to the second register to obtain the second serial number of the second register, judges the first serial number and the second serial number, and completes the locking; When releasing the lock, the release lock interface obtains the first serial number from the lock interface, increments the obtained first serial number by one, and sends a write request to the second register; the second register receives the write request and performs a write operation to complete the lock release.

9. The control method of the hardware-implemented mutex device according to claim 8, characterized in that, When obtaining the lock, the software sends a read request to the first register through the lock interface to obtain the first serial number of the first register; the lock interface sends a read request to the second register to obtain the second serial number of the second register, judges the first serial number and the second serial number, and completes the locking, including: Sending a read request to the first register through the lock interface; The first register receives the read request, obtains the value of the first counter, and increments the value of the first counter by one; The first register uses the obtained value of the first counter as the first serial number and returns the first serial number to the lock interface; The lock interface sends a read request to the second register to obtain the second serial number of the second register; Compare the first serial number with the second serial number. If the first serial number is the same as the second serial number, the locking is completed; if the first serial number is different from the second serial number, wait and repeatedly read the second serial number until the obtained second serial number is equal to the first serial number, and the locking is completed.

10. The control method of the hardware-implemented mutex device according to claim 8, wherein When releasing the lock, the release locking interface obtains the first serial number from the locking interface, increments the obtained first serial number by one, and sends a write request to the second register; The second register receives the write request and performs a write operation to complete the lock release, including: The release locking interface obtains the first serial number, increments the obtained first serial number by one, and sends a write request to the second register; After receiving the write request, the second register determines whether the written value is equal to the current value of the second register plus one. If not, discard the current write request and keep the current value of the second register unchanged; if the written value is equal to the current value of the second register plus one, perform a write operation to update the value of the second register; After the second register completes the write operation, the release locking interface returns the status code of successfully releasing the lock to implement the lock release.

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