Providing bandwidth extension for memory subsystems including sequencer separate from controller

Abstract

The disclosure relates to providing bandwidth extension for a memory subsystem including a sequencer separate from a controller. A processing device may determine configuration parameters to be used for an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component associated with the controller. Data may be received from a host system. The processing device may generate a codeword of the data by using the ECC operation based on the configuration parameter. The codeword may be sent to a sequencer external to the controller.

Description

[0001] Relevant information on divisional applications

[0002] This application is a divisional application of a patent application for invention, with the application date of September 6, 2019, application number 201980065824.8, and invention title "Providing Bandwidth Expansion for a Memory Subsystem with a Sequencer Separated from a Controller". Technical Field

[0003] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to a controller that does not have a sequencer for providing bandwidth expansion for a memory subsystem. Background Art

[0004] A memory subsystem may be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). A memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). A memory subsystem may include one or more memory components that store data. A memory component may be, for example, a non-volatile memory component and a volatile memory component. Generally, a host system may utilize a memory subsystem to store data at and retrieve data from the memory components. Summary of the Invention

[0005] In one aspect, the present disclosure provides a method, which includes: determining configuration parameters by a processing device based on a memory type of a memory component managed by a memory system controller; receiving data from a host system; generating an instruction based on the data by performing a memory operation using the configuration parameters; identifying a sequencer among a plurality of sequencers juxtaposed within a single package external to the memory system controller, wherein each of the plurality of sequencers interfaces with a corresponding memory component; and sending the instruction to the sequencer.

[0006] In another aspect, the present disclosure provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing device, perform operations including: determining configuration parameters based on a memory type of a memory component managed by a memory system controller; receiving data from a host system; generating an instruction based on the data by performing a memory operation using the configuration parameters; identifying a sequencer among a plurality of sequencers juxtaposed within a single package external to the memory system controller, wherein each of the plurality of sequencers interfaces with a corresponding memory component; and sending the instruction to the sequencer.

[0007] On the other hand, the present disclosure provides a system that includes: a memory component that interfaces with an sequencer among a plurality of sequencers juxtaposed within a single package external to a memory system controller; a processing device operatively coupled to the memory component to perform operations including: determining configuration parameters based on a memory type of the memory component managed by the memory system controller; receiving data from a host system; generating instructions based on the data by performing a memory operation using the configuration parameters; identifying the sequencer; and sending the instructions to the sequencer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 Illustrate an example computing environment including a memory subsystem in accordance with some embodiments of the present disclosure.

[0010] Figure 2 Illustrate an example package including a plurality of sequencers operatively coupled to different memory components having different memory types in accordance with some embodiments of the present disclosure.

[0011] Figure 3 Is a flowchart of an example method for executing instructions in accordance with some embodiments of the present disclosure.

[0012] Figure 4 Is a flowchart of an example method for performing operations on a memory component in accordance with some embodiments of the present disclosure.

[0013] Figure 5 Illustrate a controller including a reduced number of pins and a reduced form factor in accordance with some embodiments of the present disclosure.

[0014] Figure 6 Is a flowchart of an example method for determining configuration parameters to be used for error correction code operations in accordance with some embodiments of the present disclosure.

[0015] Figure 7 Is a flowchart of an example method for determining configuration parameters to be used for memory management operations in accordance with some embodiments of the present disclosure.

[0016] Figure 8 Is a flowchart of an example method for determining configuration parameters to be used for memory mapping operations in accordance with some embodiments of the present disclosure.

[0017] Figure 9 Is a flowchart of an example method for determining configuration parameters for sequencer operations and for sending the configuration parameters to the sequencer in accordance with embodiments of the present disclosure.

[0018] Figure 10 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description

[0019] Aspects of the present disclosure relate to a memory subsystem that includes an on-package sequencer separate from a controller. The memory subsystem is also referred to hereinafter as a “memory device”. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to the CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), etc. In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Generally, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0020] The memory subsystem may include multiple memory components that may store data from the host system. Each memory component may include a different type of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory and flash-based memory, such as single-level cell (SLC) memory, three-level cell (TLC) memory, and quad-level cell (QLC) memory. The characteristics of different types of media may vary between one media type and another. An example of a characteristic associated with a memory component is data density. Data density corresponds to the amount of data (e.g., data bits) that can be stored per memory cell of the memory component. Using an example of flash-based memory, a quad-level cell (QLC) can store four data bits, while a single-level cell (SLC) can store one data bit. Another example of a characteristic of a memory component is access speed, which corresponds to the amount of time for the memory component to access data stored at the memory component.

[0021] The memory subsystem may also include a controller operatively coupled to the memory components. The controller may operate as a “bridge” between the host system and the memory components of the memory subsystem for data transfer and / or management. In some cases, the controller and the associated memory components may be manufactured by different vendors, and each of the controller and / or the memory components may have a corresponding package. To increase the capacity of the memory subsystem, memory components may be added to the memory subsystem. The controller must interface with multiple memory components. To interface with the memory components, in conventional systems, the controller includes a large number of pins. Including a large number of pins may increase the package size of the controller, which may in turn increase the system form factor.

[0022] In some conventional systems, the controller interfaces with the host system using serializer / deserializer (SerDes) connections (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Universal Flash Storage (UFS), etc.) to minimize the pin count. The conventional controller may include an arbiter component that interfaces with the memory components using a protocol and timing requirements specific to the memory type of the memory components (e.g., read / write latency, etc.) and directs the memory components. The controller may interface with the memory components via a parallel interface that utilizes double data rate (DDR) to obtain a specific bandwidth and capacity. Increasing the number of memory components directly interfaced with the controller may use more space and cause difficulties in routing the parallel interface. Thus, the routing path (e.g., traces) between the controller and the memory components may be long, thereby compromising signal integrity. Additionally, using a longer routing path to the memory components via the parallel interface may make the load greater, thereby consuming an undesired amount of power.

[0023] Aspects of the present disclosure address the above and other deficiencies by separating the arbiter component from the controller and including the arbiter component with one or more memory components in an individual package. The arbiter component may be fabricated in a separate die, the memory components may be fabricated in separate dies, and the separate die and the separate dies may be included in the same package. The package may refer to a housing that supports electrical contacts for connecting the package to an application board and protects against physical damage and corrosion. The application board may refer to a printed circuit board on which the controller, the package, and / or the memory components reside. Each arbiter component operates with a certain type of memory component (e.g., cross-point array, NAND flash, etc.) and may operate with multiple memory components of that type. The arbiter component may interface with the memory components via a protocol specific to the memory type. Each package may include multiple arbiter components that interface with corresponding different types of memory components. Additionally, the memory subsystem may include multiple packages each including one or more arbiter components each interfacing with one or more memory components.

[0024] The sequencer component can interface with the controller via a SerDes connection that provides higher bandwidth than a parallel interface. Additionally, the SerDes connection uses fewer pins than a parallel connection. Thus, the disclosed techniques can be used to reduce the pin count in the controller while still accommodating the same or more memory components included in a package coupled to the controller. Reducing the pin count of the controller can result in a reduced form factor of the memory subsystem that has the same capacity (e.g., the same number of memory components) as a previous conventional system with more pins.

[0025] Furthermore, signal integrity can be improved because the distance between the sequencer component and the memory components within an independent package is shorter than the distance between the sequencer component and the memory components in a conventional system where the sequencer component is within the controller. That is, the package is smaller than the application board, and thus, the traces between the sequencer component and the memory components within the package are shorter than in a conventional system where the traces run on the application board. The shorter traces can improve signal integrity, as well as reduce the load on the package and consume less power than a conventional system where the routing paths are longer.

[0026] In some embodiments, the sequencer component can attempt to maximize the interface bandwidth between the sequencer component and the memory components by enforcing the timing requirements of the memory type of the memory components. The timing requirements can relate to the latency of read / write operations performed for the memory type. The sequencer component can time the issuance of its read / write commands based on the latency of the type of memory components. Additionally, the sequencer component can reorder commands based on certain rules related to the commands and the addresses involved in the commands. That is, the sequencer component can reorder read / write requests by considering rules that ensure data coherence. For example, if there is a write request and then a read request for the same address, the rule can indicate that the read request cannot be moved before the write request because the read request would return old data. Thus, the sequencer component can reorder operations based on the bandwidth of the memory components and enforce the timing of the transmission of the operations to the memory components.

[0027] In some embodiments, a controller lacking a sequencer component can perform one or more operations related to memory management, memory mapping, and / or error correction. Data and / or the results of operations received by the controller can be stored in the storage buffer of the controller. The controller can transmit the data and / or results to the sequencer component via several output pins. Each operation can be adapted via the sequencer component for a specific type of memory component included in a package coupled to the controller.

[0028] The controller can determine one or more configuration parameters to be used for different operations, and the one or more configuration parameters can be based on the memory type of a memory component associated with the controller and coupled to an sequencer component. The memory component can determine the memory type of the memory component by receiving an indication of the memory type from a host system, accessing the memory type previously stored in the local memory of the controller, or querying the sequencer component to obtain the memory type of the memory component coupled to the sequencer component. The controller can perform operations based on configuration parameters specific to the memory type.

[0029] For example, a memory management operation can include performing wear leveling on the memory components in a package. Wear leveling can refer to making the memory components selected to perform read and / or write operations alternate to ensure that each memory component wears out evenly. Due to the different attributes of the memory type, the wear leveling scheme can be different based on the type of the memory component (e.g., cross-point array, flash, etc.). Thus, the memory component can determine a first configuration parameter for a first wear leveling scheme for a first memory component having a first memory type and a second configuration parameter for a second wear leveling scheme for a second memory component having a second memory type.

[0030] In another example, operations related to error correction can include error correction code operations that can be used to improve the reliability of data stored in a memory subsystem. Error correction code operations can refer to techniques for representing a sequence of data such that errors introduced into the data can be detected and corrected based on other remaining data. The sequence of data can be referred to as a codeword. The types of error correction codes can include block codes (e.g., Hamming code, Reed Solomon code, etc.). Generally, an encoder encodes data with additional data bits to form a codeword, and parts of the codeword can be distributed (e.g., segmented) across the memory components of the memory subsystem. When reading data, a decoder decodes the codeword by removing the additional data bits and providing the required original data.

[0031] The configuration parameters for error correction code operations can include error correction code parameters (e.g., encoding / decoding) of the memory type of the memory component. The controller can receive data from a host system and generate a codeword of the data by using error correction code operations based on the configuration parameters. Subsequently, the codeword can be sent to an sequencer component external to the controller, and the sequencer component can distribute the codeword according to the timing requirements and rules described above.

[0032] In another example, a memory mapping operation may include performing address translation. The host system may utilize an address space that is different from the actual physical address space of the memory component. Thus, the memory component may determine configuration parameters for the memory mapping operation for the memory type to be used for the memory component. The memory component may perform a logical-to-physical address mapping based on the configuration parameters for the type of memory component involved in the operation. The memory component may send the physical address in the command to the sequencer.

[0033] In another embodiment, the controller may determine configuration parameters for an operation to be performed by the sequencer component and send the configuration parameters to the sequencer component. The configuration parameters may include timing requirements for the memory type of the memory component coupled to the sequencer component. As described above, the sequencer component may time the issuance of commands to the memory component (e.g., read / write operations) based on the timing requirements for the memory type of the memory component.

[0034] Figure 1 An example computing environment 100 including a memory subsystem 110 in accordance with some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media, such as a memory component 112. The memory component 112 may be a volatile memory component, a non-volatile memory component, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem.

[0035] In some embodiments, the memory components 112 may be included in separate corresponding packages 130A through 130N. As depicted, memory components 112A(1) through 112N(1) are coupled to a first sequencer component 140A in a first package 130A, and memory components 112A(2) through 112N(2) are coupled to another sequencer component 140N in another package 130N. Each of the sequencer components 140A through 140N may be fabricated in separate silicon, and each of the memory components 112 may be fabricated in separate die. In a conventional memory subsystem, the sequencer component 140 is typically located within the memory system controller 115 (hereinafter referred to as the "controller"). The sequencer component 140 and the corresponding memory components 112 may be included in a single package and coupled via short traces 160 to improve the performance of issuing commands from the sequencer component 140 to the memory components 112. By using shorter traces between the sequencer component 140 and the memory components, the power load consumption may be reduced and the data signal integrity may be increased as compared to a conventional arrangement. Additionally, as discussed herein, moving the sequencer component 140 to a package 130 separate from the controller 115 may provide many other benefits such as reducing the form factor of the memory subsystem 110, increasing the bandwidth between the controller 115 and the memory components 112, and so on.

[0036] For example, the sequencer component 140 and the memory components 112 in the package 130 may be coupled to the controller 115 via a SerDes interface 150 as compared to a parallel interface. The SerDes interface 150 provides higher bandwidth than a parallel interface and also uses fewer outgoing pins, thereby reducing the number of pins required by the controller 115 to provide a memory subsystem 110 with the same capacity (e.g., the number of memory components 112). For example, a SerDes interface may use six pins (e.g., two for clock, two for transmit, two for receive), whereas a parallel interface may use more than twenty pins to operate. Reducing the outgoing pin count of the controller 115 may improve the form factor of the overall memory subsystem 110 by reducing the size of the controller 110. Additionally, removing the sequencer component 140 from the controller 115 may also reduce the size of the controller 115.

[0037] Sequencer components 140A to 140N can perform one or more operations and can be configured based on the type of memory component 112 to which the corresponding sequencer component is coupled. For example, sequencer component 140A can receive various data from controller 115 and schedule the time to issue read / write commands to attached memory components 112A(1) to 112A(1) based on the timing requirements of the type of attached memory components 112A(1) to 112A(1) and certain rules for ensuring data coherence, etc. In some embodiments, one sequencer component 140 is coupled to a memory component 112 having a single memory type. There can be many sequencer components 140 included in each package 130, and thus, a single package 130 can contain memory components 112 of different types coupled to different corresponding sequencer components 140 within the package 140. In additional embodiments, each package 140 can contain a memory component 112 having a single memory type, and thus, each package 130 can be dedicated to providing operational characteristics associated with the type of memory component 112 being used.

[0038] Generally, computing environment 100 can include host system 120 that uses memory subsystem 110. For example, host system 120 can write data to memory subsystem 110 and read data from memory subsystem 110. Host system 120 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such a computing device that includes memory and a processing device. Host system 120 can include or be coupled to memory subsystem 110 such that host system 120 can read data from memory subsystem 110 or write data to memory subsystem 110. Host system 120 can be coupled to memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include but are not limited to serial / serial-to-parallel conversion (SerDes) interfaces, serial advanced technology attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, universal serial bus (USB) interfaces, fiber channel, serial attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize a non-volatile memory express (NVMe) interface to access memory components 112A to 112N. The physical host interface can provide an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120.

[0039] The memory component 112 can include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include negative-and (NAND)-type flash memory. Each of the memory components 112 can include one or more arrays of memory cells, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., triple-level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include both an SLC portion and an MLC portion of memory cells. Each of the memory cells can store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, the memory component 112 can be based on any other type of memory, such as volatile memory. In some embodiments, the memory component 112 can be, but is not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, compared with many flash-based memories, cross-point non-volatile memory can perform in-place write operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. Further, the memory cells of the memory component 112 can be grouped into memory pages or data blocks, which can refer to the units of the memory component used to store data.

[0040] The controller 115 can communicate with the memory component 112 via the sequencer component 140 to perform operations such as reading data, writing data, or erasing data at the memory component 112 and other such operations. In one instance, and as further discussed below, the controller 115 can include an error component 116. Error correction codes can be used to improve the reliability of data stored in the memory subsystem 110. Error correction codes can refer to techniques for representing a sequence of data such that errors introduced into the data can be detected and corrected based on other remaining data. The sequence of data can be referred to as a codeword. Types of error correction codes can include block codes (e.g., Hamming codes, Reed Solomon codes, etc.).

[0041] Error component 116 can perform an error correction code encoding operation that encodes data with additional data bits (e.g., parity bits) received by host system 120 to form a codeword to be written to memory component 112 via sequencer component 140. Error component 116 can also perform an error correction code decoding operation that decodes the codeword by removing the additional data bits. The encoding / decoding operations can use certain configuration parameters based on the type of memory component 112 on which the data is to be stored. Controller 115 can send one or more codewords to sequencer component 140A. Sequencer component 140A can determine which portions of which codewords are stored on memory components 112A(1) to 112N(1) by considering the bandwidth and availability of memory components 112A(1) to 112N(1), the timing requirements (e.g., read / write latency) of memory components 112A(1) to 112N(1), and the rules regarding the sequencing of read / write operations. One purpose of sequencer component 116 can be to maximize the interface bandwidth between sequencer component 116 and memory components 112A(1) to 112N(1).

[0042] Controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. Controller 115 can be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. Controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of memory subsystem 110 (including handling communication between memory subsystem 110 and host system 120). In some embodiments, local memory 119 can include memory registers that store memory pointers, extracted data, etc. Local memory 119 can also include a read only memory (ROM) for storing microcode. Although Figure 1 the illustrated memory subsystem 110 has been shown to include controller 115, in another embodiment of the present disclosure, memory subsystem 110 can exclude controller 115 and instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0043] Generally, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory component 112. The controller 115 may include an error component 116 that performs error correction code operations, a memory mapping component 118 that performs address translation between logical block addresses and physical block addresses associated with the memory component 112, and a memory management component 121 that performs wear leveling operations. The processing device 117 may execute the various components 116, 118, and 121. Additionally, the various components 116, 118, and 121 may use type-specific configuration parameters for the memory component 112 included in the memory subsystem 110. The configuration parameters may be received from the host system 120 and may be pre-stored in the local memory 119 during the manufacturing process and / or may be extracted from the package 130 via the sequencer component 140 by querying what type of memory component 112 is included in the package 130. In some cases, the sequencer component 140 may provide a notification indicating the type of the memory component 112 associated therewith. Other details regarding the operations of the error component 116, the memory mapping component 118, and the memory management component 121 are described below.

[0044] The controller 115 may be responsible for other operations such as garbage collection operations, encryption operations, and / or cache operations. The controller 115 may further include a host interface circuit to communicate with the host system 120 via a physical host interface. The host interface circuit may convert commands received from the host system into command instructions to access the memory component 112 via the sequencer components 140A to 140N, and convert responses associated with the memory component 112 into information for the host system 120.

[0045] The memory subsystem 110 may further include additional circuits or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory component 112.

[0046] Figure 2Illustrate an example package 130A that includes a plurality of sequencer components 140 operatively coupled to different memory components 112 having different memory types according to some embodiments of the present disclosure. As depicted, a first sequencer component 140A(1) is coupled to a first memory component 112A(1.1) to 112N(1.2) having a first memory type (e.g., NAND flash), and a second sequencer component 140N(1) is coupled to a second memory component 112A(2.1) to 112N(2.2) having a second memory type (e.g., cross-point array). It should be understood that any number of sequencer components coupled to corresponding memory components having corresponding memory types may be included in the package 130 to meet the required performance attributes of the package 130.

[0047] Figure 3 Is a flowchart of an example method 300 for executing instructions according to some embodiments of the present disclosure. The method 300 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 300 is executed by Figure 1 the sequencer component 140A. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated process may be executed in a different order, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0048] At block 310, the processing device receives an instruction at the sequencer component 140A. The instruction may be received from the controller 115. The sequencer component 140A may be located in a package 130A that includes the sequencer component 140A coupled to one or more memory components 112A(1) to 112N(1). The sequencer component 140A may be fabricated in its own independent silicon, the memory components 112A(1) to 112N(1) may be fabricated in their own independent dies, and the independent silicon and the independent die may be included in the package 130A. The sequencer component 140A may be coupled to a controller 115 separate from the package 130A. The sequencer component 140A may be coupled to the controller 115 via a SerDes interface. The traces between the sequencer component 140A and the memory components 112A(1) to 112N(1) may be shorter than the traces between the sequencer component 140A and the controller 115.

[0049] At block 320, the processing device of sequencer component 140A performs operations on at least one of the one or more memory components 112A(1) to 112N(1) based on the instructions. The operations can include interfacing with the one or more memory components 112A(1) to 112N(1) via a type-specific protocol for the memory components 112A(1) to 112N(1), enforcing the operational timing requirements for the one or more memory components 112A(1) to 112N(1) based on the type of the memory components 112A(1) to 112N(1), and reordering the operations based on rules related to data coherence.

[0050] In some embodiments, the processing device can enforce the timing requirements for the time to issue commands based on the read / write latency of the various memory components 112A(1) to 112N(1). For example, if the latency of how long it takes for the memory components 112A(1) to 112N(1) to perform an operation is determined, then the processing device can schedule the time to issue subsequent commands to the memory components 112A(1) to 112N(1). In some cases, the latency can be determined according to configuration parameters. In another case, the processing device can dynamically determine the latency. Additionally, if the latency changes during the use of the memory component, then the processing device can consider the change when issuing other commands. The processing device can enforce the timing requirements to maximize the bandwidth between the sequencer component 140A and the memory components 112A(1) to 112N(1).

[0051] Furthermore, the processing device can reorder the operations based on rules related to the commands and addresses involved in the instructions received from the controller 115. Generally, the processing device can reorder read and write operations to maximize the bandwidth between the sequencer component 140A and the memory components 112A(1) to 112N(1). For example, if there is a read operation received for a first address, but the memory component 112A(1) containing the address is busy, then the read operation can be moved with another operation that can be executed earlier to improve performance. If the reordering satisfies the rules, then the reordering can be performed. For example, the instructions can specify a write and a read at the same address of the memory component 112A(1). In this case, the rules can specify that the operations cannot be reordered because if the read operation is reordered to be first, then the read operation will provide old data before the write operation updates the data.

[0052] In some embodiments, the second sequencer component 140N may receive a second instruction. The second sequencer component 140N may be located in another package 140N, and the second sequencer component 140N may be operatively coupled to one or more second memory components 112A(2) to 112N(2) within the second package 130N. The second sequencer component 140N may be operatively coupled to the controller 115. The memory components 112A(2) to 112N(2) in the second package 130N may include a memory type different from the memory components 112A(1) to 112N(1) in the package 130A. The second sequencer component 140N may interface with the second memory type via a protocol specific to the second memory type.

[0053] Figure 4 is a flowchart of an example method for performing operations on a memory component according to some embodiments of the present disclosure. The method 400 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 400 is executed by Figure 1 the sequencer component 140A. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated process may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0054] At block 410, the processing device of the sequencer component 140A receives an instruction from the controller 115 located external to the system that includes the sequencer component 140A. In some embodiments, the system may be the package 130A. The package 130A may include the sequencer component 140A operatively coupled to the memory component 112A(1). The sequencer component 140A may be operatively coupled to the controller 115 external to the package 130A. In some embodiments, the trace between the sequencer component 140A and the memory component 112A(1) may be shorter than the trace between the controller 115 and the sequencer component 140A. The sequencer component 140A and the controller 115 may be coupled via a SerDes interface.

[0055] At block 420, the processing device determines an operation to be performed on memory component 112A(1) based on an instruction. The instruction can be to write data to or read data from a physical address of memory component 112A(1). For example, the instruction can include a codeword, and the operation can include dividing the codeword into parts and issuing a command to store the parts on one or more data blocks of memory component 112A(1). The codeword can be encoded by controller 115 based on configuration parameters specific to the type of memory component 112A(1) included in package 130A. The processing device can determine the timing of the time to perform the operation based on the timing requirements of the memory type of memory component 112A(1).

[0056] At block 430, the processing device performs an operation on memory component 112A(1). For example, the processing device can cause memory component 112A(1) to write parts of a codeword to one or more data blocks of memory component 112A(1).

[0057] In some cases, before performing the operation, the processing device can also receive a second instruction from controller 115 external to the system. The processing device can determine a second operation to be performed on memory component 112A(1) based on the second instruction. The processing device can determine to perform the second operation before the operation based on a rule. For example, the first instruction can be associated with a read operation to an address, and the second instruction can be associated with a write operation to the address. The rule can specify to perform the write operation before the read operation so that the read operation returns current data. The processing device can then perform the second operation on memory component 112A(1) before the operation, and then perform the operation on memory component 112A(1).

[0058] Figure 5Describe a controller 115 according to some embodiments of the present disclosure that includes a reduced number of pins 500 and a reduced form factor. The controller is coupled to a package 130A via a connection 150, which may be a SerDes interface in some embodiments. As described above, the SerDes interface may use approximately six outgoing pins of the controller 115 to communicate with the sequencer component 140A. The six outgoing pins may include two pins for a clock, two pins for transmission, and two pins for reception. It should be understood that in a conventional system, a parallel interface with twenty or more pins is typically used to connect the controller 115 to the memory component 112. However, embodiments of the present disclosure may use a SerDes interface by moving the sequencer component 140A to a package 130A that has memory components 112A to 112N and indirectly connecting the controller 115 to the memory components 112A to 112N through the sequencer component 140A. Thus, the bandwidth between the controller 115 and the memory components 112A to 112N may be increased using the SerDes interface 150, the size of the controller 115 may be reduced due to the reduced number of pins 500, and the form factor of the memory subsystem 110 may be reduced, among other things.

[0059] As depicted, the controller 115 includes an error component 116, a memory mapping component 118, and a memory management component 121. The various components 115, 116, and 121 may perform various operations based on type-specific configuration parameters included in the memory components 112A to 112N contained in the package 130. Figures 6 to 8 Generally relates to a controller 115 that uses type-specific configuration parameters for the memory components 112A to 112N to perform different operations. Additionally, the controller 115 may determine the type of memory component contained in the package 130A and may provide configuration parameters related to the timing requirements of a particular memory type to the sequencer component 140A. Figure 9 Generally relates to the controller determining configuration parameters and transmitting the configuration parameters to the sequencer component 140A.

[0060] Figure 6 Is a flowchart of an example method 600 for determining configuration parameters to be used for error correction code operations according to some embodiments of the present disclosure. The method 600 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, special logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1Execute the error component 116. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be executed in a different order, and some processes can be executed in parallel. Additionally, one or more processes can be omitted in each embodiment. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0061] At block 610, the processing device determines configuration parameters to be used for error correction code (ECC) operations. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. The memory component 112A(1) can be included in the package 130A together with the sequencer component 140A. The sequencer component 140A and the memory component 112A(1) can be communicatively coupled. The controller 115 can be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface. The controller 115 can issue instructions to the sequencer component 140A, and the sequencer component 140A can determine various operations to be performed on the memory component 112A(1) associated with the controller 115.

[0062] The processing device can determine the configuration parameters in several ways. For example, at block 612, the processing device can receive from the host system 120 a first data structure (e.g., a table) containing configuration parameters for one or more types of memory components 112. In some embodiments, the processing device can be notified by the sequencer component 140A about the types of the memory components 112A to 112N included in the package 130A. In another embodiment, the sequencer component 140A can request the sequencer component 140A to provide the types of the memory components 112A to 112N included in the package 130A. The processing device can use the types of the memory components 112A to 112N to search the first data structure to determine the configuration parameters to be used for error correction code operations. Specifically, the configuration parameters can relate to the encoding / decoding scheme used, which can vary based on the type of memory component used.

[0063] Another way to determine the configuration parameters is shown at block 614, where the processing device can access in the local memory 119 a second data structure containing the configuration parameters. The second data structure can be stored in the local memory 119 after the controller 115 is manufactured and during the initial setup and data loading into the controller 115. In some embodiments, the second data structure can be stored in the local memory 119 during an update of software, firmware, or the like. Similar to the above-described content, the processing device can search the second data structure for the types of the memory components 112A to 112N used and determine the configuration parameters to be used for error correction code operations.

[0064] Another way to determine configuration parameters is shown in block 616, where the processing device may query sequencer component 140A to obtain configuration parameters. For example, sequencer component 140A may receive a request from controller 115 and determine the configuration parameters by searching the local memory of package 130A or based on the attributes of memory components 112A to 112N known to sequencer component 140A. Sequencer component 140A may provide the configuration parameters to be used for error correction code operations to controller 115.

[0065] At block 620, the processing device receives data from host system 120. The data may include data to be stored in memory subsystem 110 requested by host system 120. In one instance, the data may be user data.

[0066] At block 630, the processing device generates a codeword for the data by using ECC operations based on the configuration parameters. As described above, the configuration parameters may include ECC parameters for the memory types of memory components 112A to 112N in package 130A. The ECC parameters may specify the encoding / decoding scheme to be applied to the data during ECC operations. It should be understood that controller 115 may be associated with more than one memory component, and other memory components may have different types. Using the disclosed techniques, controller 115 may determine the configuration parameters for ECC operations to be used for each type of associated memory component and may perform ECC operations using the corresponding configuration parameters.

[0067] At block 640, the processing device sends the codeword to sequencer component 140A external to controller 115. In some cases, the codeword to be written may be stored in local memory 119 (e.g., a storage buffer), and the processing device may transmit the codeword stored at the storage buffer to sequencer component 140A via the output pins of controller 115 through a SerDes interface.

[0068] In some embodiments, controller 115 may request to read a codeword from sequencer component 140A. Sequencer component 140A may provide the codeword, and controller 115 may decode the codeword based on the determined configuration parameters. In some cases, the decoded data may be transmitted by controller 115 to host system 120.

[0069] Figure 7 is a flowchart of an example method 700 for determining configuration parameters to be used for memory management operations according to some embodiments of the present disclosure. Method 700 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 700 is performed byFigure 1 is executed by the memory management component 121. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0070] At block 710, the processing device determines configuration parameters to be used for memory management operations. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. In one example, the configuration parameters to be used for memory management operations may relate to an wear-leveling scheme for a particular type of memory component 112A(1). The memory component 112A(1) may be included in a package 130A together with an sequencer component 140A. The sequencer component 140A and the memory component 112A(1) may be communicatively coupled. The controller 115 may be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface. The controller 115 may issue instructions to the sequencer component 140A, and the sequencer component 140A may determine various operations to be performed on the memory component 112A(1) associated with the controller 115.

[0071] Similar to Figure 6 the manner in which configuration parameters to be used for ECC operations are determined, the processing device may determine the configuration parameters to be used for memory management operations in several ways. For example, at block 712, the processing device may receive from the host system 120 a first data structure (e.g., a table) containing the configuration parameters to be used for memory management operations for a particular type of memory component 112A(1). In another example, at block 714, the processing device may access in the local memory 119 a second data structure containing the configuration parameters to be used for memory management operations. In yet another example, at block 716, the processing device may query the sequencer component 140A to obtain the configuration parameters to be used for memory management operations. Additionally or alternatively, in some embodiments, the processing device may query the sequencer component 140A for the type of the memory component 112A(1) and use the received response in conjunction with any of the techniques described above.

[0072] At block 720, the processing device determines a wear leveling scheme for sequencer component 140A to apply to operations on memory component 112A(1) based on configuration parameters. Certain types (e.g., cross-point arrays, NAND flash, etc.) may have different attributes such as the rate of degradation of the physical media when performing operations. Using the configuration parameters for the type of memory component 112A(1), the processing device can determine to evenly distribute read / write operations, disproportionately distribute read operations or write operations, or some combination thereof to different data blocks of memory component 112A(1) and / or memory components 112A(1) to 112N(1) to ensure that the wear of operations is distributed into a wear leveling scheme that increases the service life of memory components 112A(1) to 112N(1).

[0073] At block 730, the processing device sends the wear leveling scheme and / or data to sequencer component 140A. The wear leveling scheme may refer to the scheduling of which memory components to use for operations, or the actual instructions to perform operations on certain memory components to implement wear leveling. In some cases, the wear leveling scheme and / or any data to be written may be stored in local memory 119 (e.g., a store buffer), and the processing device can transmit the wear leveling scheme and / or data stored at the store buffer to sequencer component 140A via the output pins of controller 115.

[0074] Sequencer component 140A can use the wear leveling scheme of when to schedule using which memory components 112A(1) to 112N(1) for certain operations and when to perform operations on memory components 112A(1) to 112N(1). Adapting the wear leveling scheme to the type of memory component 112 provides a flexible architecture where different types of memory components 112 can be used based on their required performance characteristics while still maximizing the durability of memory component 112.

[0075] Figure 8 Is a flowchart of an example method 800 for determining configuration parameters to be used for memory mapping operations according to some embodiments of the present disclosure. Method 800 can be executed by processing logic, which can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 800 is performed by Figure 1The memory mapping component 118 performs. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, all processes are not required in every embodiment. Other process flows are possible.

[0076] At block 810, the processing device determines configuration parameters to be used for a memory mapping operation. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. In one example, the configuration parameters to be used for the memory mapping operation may include a memory mapping of the physical address of the memory component 112A(1) having a particular type. The memory component 112A(1) may be included in the package 130A together with the sequencer component 140A. The sequencer component 140A and the memory component 112A(1) may be communicatively coupled. The controller 115 may be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface. The controller 115 may issue instructions to the sequencer component 140A, and the sequencer component 140A may determine various operations to be performed on the memory component 112A(1) associated with the controller 115.

[0077] Similar to the Figure 6 In a manner similar to determining the configuration parameters to be used for an ECC operation, the processing device may determine the configuration parameters to be used for the memory mapping operation in several ways. For example, at block 812, the processing device may receive a first data structure (e.g., a table) from the host system 120 that includes the configuration parameters for a particular type of memory mapping operation to be used for the memory component 112A(1). In another example, at block 814, the processing device may access a second data structure in the local memory 119 that includes the configuration parameters for the memory mapping operation. In yet another example, at block 816, the processing device may query the sequencer component 140A to obtain the configuration parameters for the memory mapping operation. Additionally or alternatively, in some embodiments, the processing device may query the sequencer component 140A for the type of the memory component 112A(1) and use the received response in conjunction with any of the techniques described above.

[0078] At block 820, the processing device uses the memory mapping to translate a logical address where read or write data is to be stored to a physical address on the memory component 112A(1). In some embodiments, the host system 120 may send data to the controller 115, and the data may include the logical address where the data is stored in the host system 120. Using the memory mapping, the processing device may translate the logical address to a physical address in the memory component 112A(1).

[0079] At block 830, the processing device sends the physical address and / or data to sequencer component 140A. In some cases, the physical address and / or data may be stored in local memory 119 (e.g., a store buffer), and the processing device may transfer the physical address and / or data stored at the store buffer to sequencer component 140A via an output pin of controller 115.

[0080] Sequencer component 140A may use the physical address to write data to memory component 112A(1). As can be appreciated, different types of memory components 112 may have different physical addresses. Thus, enabling memory mapping component 118 to translate logical addresses into any physical address specific to the target memory component 112 can provide the benefit of using different types of memory components 112 in memory subsystem 110 based on the desired performance of memory subsystem 110.

[0081] Figure 9 is a flowchart of an example method 900 for determining configuration parameters for sequencer component operation and for sending the configuration parameters to the sequencer component. Method 900 may be executed by processing logic that may comprise hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 900 is executed by Figure 1 controller 115. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated process may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0082] At block 910, the processing device determines configuration parameters for one or more operations performed by sequencer component 140A. The configuration parameters are based on the memory type of memory component 112A(1) associated with controller 115. The operations may involve imposing specific types of timing requirements on memory component 112A(1). Thus, in some embodiments, the configuration parameters may include timing parameters that vary based on the type of memory component 112A(1), different generations of memory component 112A(1), and the like. The configuration parameters may also include rules for reordering operations. Memory component 112A(1) may be included in package 130A along with sequencer component 140A. Sequencer component 140A and memory component 112A(1) may be communicatively coupled. Controller 115 may be coupled to sequencer component 140A external to controller 115 via a SerDes interface.

[0083] Similar to the reference Figure 6 Similar to the manner of determining configuration parameters to be used for ECC operations, the processing device may determine the configuration parameters to be used for operations performed by sequencer component 140A in several ways. For example, at block 912, the processing device may receive a first data structure (e.g., a table) containing the configuration parameters for the operations performed by sequencer component 140A from host system 120 based on the specific type of memory component 112A(1). In another example, at block 914, the processing device may access a second data structure in local memory 119 that contains the configuration parameters for the operations performed by sequencer component 140A. In yet another example, at block 916, the processing device may query sequencer component 140A to obtain the configuration parameters to be used for the operations. Additionally or alternatively, in some embodiments, the processing device may query sequencer component 140A for the type of memory component 112A(1) and use the received response in conjunction with any of the techniques described above.

[0084] At block 920, the processing device sends the configuration parameters and / or any data to be written to sequencer component 140A. In some cases, the configuration parameters and / or data may be stored in local memory 119 (e.g., a store buffer), and the processing device may transfer the configuration parameters and / or data stored at the store buffer to sequencer component 140A via the output pins of controller 115.

[0085] Sequencer component 140A may perform operations using configuration parameters. For example, the configuration parameters may include timing requirements for the type of memory component 112A(1), and the processing device may sequence the order of operations performed on memory component 112A(1) based on the timing requirements. Additionally, the configuration parameters may include rules for reordering the order of operations based on commands and addresses included in the instructions. As described above, sequencer component 140A may maximize the bandwidth between sequencer component 140A and memory component 112A(1) by enforcing the timing requirements and using the rules to reorder the order of operations.

[0086] Figure 10 An example machine of computer system 1000 is illustrated, within which instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 1000 may correspond to a host system (e.g., Figure 1 a host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or may be used to perform the operations of a controller (e.g., execute an operating system to perform the operations corresponding to Figure 1 error component 116, memory mapping component 118, and / or memory management component 121) or Figure 1 the operations of sequencer components 140A to 140N of

[0087] In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment as a peer machine in a peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0088] Example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030.

[0089] The processing device 1002 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1002 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. The computer system 1000 may further include a network interface device 1008 to communicate via a network 1020.

[0090] The data storage system 1018 may include a machine-readable storage medium 1024 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets 1026 or software embodying any one or more of the methods or functions described herein. The instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution by the computer system 1000, and the main memory 1004 and the processing device 1002 also constitute machine-readable storage media. The machine-readable storage medium 1024, the data storage system 1018, and / or the main memory 1004 may correspond to Figure 1 the memory subsystem 110.

[0091] In one embodiment, the instructions 1026 include those for implementing corresponding to Figure 1instructions for the functionality of the error component 116, the memory mapping component 118, the memory management component 121, and / or the sequencer components 140A to 140N. Although the machine-readable storage medium 1024 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0092] Some parts of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. In this specification, and in general, an algorithm is conceived of as a self-consistent sequence of operations that produce a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0093] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the registers and memories of the computer system and transforms the data into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0094] The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specially constructed for the required purposes or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0095] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. A variety of general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be shown in the description below. In addition, no specific programming language has been described for the present disclosure. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0096] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0097] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method, comprising: Determining configuration parameters by a processing device based on a memory type of a memory component managed by a memory system controller; Receiving data from a host system; Generating an instruction based on the data by performing a memory operation using the configuration parameters; Identifying an sequencer among a plurality of sequencers juxtaposed within a single package external to the memory system controller, wherein each of the plurality of sequencers interfaces with a corresponding memory component; And Sending the instruction to the sequencer.

2. The method according to claim 1, wherein sending the instruction to the sequencer comprises sending the instruction via a serializer / deserializer SerDes interface.

3. The method according to claim 1, wherein determining the configuration parameters further comprises: Receiving the configuration parameters from the host system; Identifying the configuration parameters in a local memory of the memory system controller; Or Querying the sequencer to obtain the memory type, wherein the configuration parameters are based on the memory type.

4. The method according to claim 1, further comprising: Determining a second configuration parameter to be used for memory management operations, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; Determining a wear leveling scheme for the sequencer to be applied to operations performed on the memory component based on the second configuration parameter; And Sending an instruction representing the wear leveling scheme to the sequencer.

5. The method according to claim 1, further comprising: Determining a second configuration parameter to be used for memory mapping operations, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; Translating a logical address associated with the data into a physical address on the memory component based on the second configuration parameter; And Sending the physical address to the sequencer.

6. The method according to claim 1, wherein sending the instruction to the sequencer comprises sending the instruction through one or more outgoing pins of the memory system controller.

7. The method according to claim 1, further comprising: Determining a second configuration parameter to be used by the sequencer to write the instruction to the memory component, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; And Sending the second configuration parameter to the sequencer for writing the instruction to the memory component.

8. The method according to claim 7, wherein the second configuration parameter includes timing requirements for the memory type of the memory component.

9. The method according to claim 1, further comprising: Determining, by the processing device, a second configuration parameter to be used for error correction code ECC operations, wherein the second configuration parameter is based on a second memory type of a second memory component associated with the memory system controller; The processing that performs the ECC operation generates a codeword using the data based on the second configuration parameter; and send the instruction to the sequencer external to the memory system controller.

10. A non - transitory computer - readable storage medium including instructions that, when executed by a processing device, perform operations including: Determine a configuration parameter based on a memory type of a memory component managed by a memory system controller; Receive data from a host system; Generate an instruction based on the data by performing a memory operation using the configuration parameter; Identify a sequencer among a plurality of sequencers juxtaposed within a single package external to the memory system controller, wherein each sequencer among the plurality of sequencers interfaces with a corresponding memory component; and Send the instruction to the sequencer.

11. The computer - readable storage medium according to claim 10, wherein, in order to send the instruction to the sequencer external to the memory system controller, the processing device further uses a serializer / deserializer (SerDes) interface to send the instruction.

12. The computer - readable storage medium according to claim 10, wherein, in order to determine the configuration parameter, the processing device further uses: Receive the configuration parameter from the host system; Access the configuration parameter in the local memory of the memory system controller; or Query the sequencer to obtain the memory type, wherein the configuration parameter is based on the memory type.

13. The computer - readable storage medium according to claim 10, wherein the processing device further uses: Determine a second configuration parameter to be used for memory management operations, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; Determine a wear - leveling scheme for the sequencer based on the second configuration parameter to be applied to operations performed on the memory component; and Send an instruction representing the wear - leveling scheme to the sequencer.

14. The computer - readable storage medium according to claim 10, wherein the processing device further uses: Determine a second configuration parameter to be used for memory mapping operations, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; Translate a logical address associated with the data into a physical address on the memory component based on the second configuration parameter; and Send the physical address to the sequencer.

15. The computer - readable storage medium according to claim 10, wherein, in order to send the instruction to the sequencer external to the memory system controller, the processing device further uses one or more outgoing pins of the memory system controller to send the instruction.

16. The computer - readable storage medium according to claim 10, wherein the processing device further uses: Determine, by the processing device, a second configuration parameter for an operation to be performed by the sequencer, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; and Send the second configuration parameter to the sequencer for use in the operation.

17. A system, comprising: A memory component interfacing with a sequencer among a plurality of sequencers juxtaposed within a single package external to a memory system controller; A processing device operatively coupled to the memory component to perform operations including: Determine a configuration parameter based on the memory type of the memory component managed by the memory system controller; Receive data from a host system; Generate an instruction based on the data by performing a memory operation using the configuration parameter; Identify the sequencer; And Send the instruction to the sequencer.

18. The system according to claim 17, wherein the processing device further performs operations including: Identify a configuration parameter for an error correction operation to be performed by the memory system controller, wherein the configuration parameter is based on the memory type of one or more memory components operatively coupled to the sequencer; and Perform the error correction operation on the data based on the configuration parameter before sending the data to the sequencer.

19. The system according to claim 17, wherein determining the configuration parameter further comprises the processing device performing operations including: Receive the configuration parameter from the host system; Identify the configuration parameter in a local memory of the memory system controller; or Query the sequencer to obtain the memory type, wherein the configuration parameter is based on the memory type.

20. The system according to claim 17, further comprising a serializer / deserializer SerDes interface coupled to the processing device, and wherein the processing device sends the data to the sequencer via the SerDes interface through the plurality of output pins.

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