Evaluation method and comprehensive design system for error correction capability of approximate arithmetic unit

Abstract

The invention relates to the technical field of approximate calculation circuit design space exploration, in particular to an evaluation method for error correction capability of an approximate arithmetic unit and a comprehensive design system, which comprehensively considers error evaluation and error correction capability values, gradually replaces the approximate arithmetic unit and selects the approximate arithmetic unit with the maximum error correction capability, thereby improving the error correction capability of the approximate arithmetic unit. The approximate arithmetic units are selected from the approximate libraries, and the approximate libraries constructed by the approximate arithmetic units enable the system to select the approximate arithmetic units according to the diversity of different calculation requirements to meet the design requirements of diversified approximate calculation circuits. On the premise that the circuit meets error constraints, the fault-tolerant capability of the circuit is effectively improved, and the optimal performance is achieved. The whole approximate calculation circuit design is applied to an approximate advanced comprehensive design system, the system with the optimal performance is obtained, and the optimal balance is obtained between precision and power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of approximate computing circuit design space exploration, and particularly to an evaluation method and an integrated design system for the error correction ability of an approximate arithmetic unit. Background Art

[0002] An approximate arithmetic unit (AAU) aims to optimize the power consumption, area, and speed of a circuit at the cost of minimal precision loss. Currently, the design methods of AAUs mainly cover logic simplification and voltage scaling. Although voltage scaling technology can reduce power consumption, it often affects the speed and stability of the circuit and has great difficulty in controlling the circuit precision. Logic simplification, on the other hand, reduces the circuit complexity and power consumption by simplifying the calculation logic (such as merging specific logic gates or reducing the number of bits). The advantage of logic simplification is that it can directly control the source and magnitude of errors, facilitating the precise adjustment of the performance and precision of the approximate computing circuit.

[0003] Therefore, most of the design research on modern AAUs focuses on logic simplification. In recent years, with the high attention of researchers in this field, a large number of open-source high-quality AAUs have emerged in technical literature. A large number of technical studies on approximate high-level synthesis (AHLS) have emerged, which use AAUs to create high-quality approximate system-level designs. To improve the quality of the approximate designs generated by AHLS, existing research mainly focuses on the search algorithms within AHLS, but ignores the fact that the effective error correction ability appears more frequently in the optimal approximate designs, and cannot determine the optimal approximate high-level synthesis system when applying the approximate design circuit to the approximate high-level synthesis (AHLS) system.

[0004] Moreover, throughout the design process of the approximate computing circuit, there is a lack of appropriate criteria for the initial design, and there are no specific steps and data to evaluate the performance of the approximate computing circuit. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide, in view of the deficiencies of the prior art, an evaluation method and an integrated design system for the error correction ability of an approximate arithmetic unit, which can effectively improve the fault tolerance of the circuit and achieve the best performance on the premise of meeting the error constraint by comprehensively considering error evaluation and error correction ability values, gradually replacing the approximate arithmetic unit, and selecting the approximate arithmetic unit with the maximum error correction ability. The designed approximate computing circuit is applied to the approximate high-level synthesis system to obtain the optimal system.

[0006] The technical problem to be solved by the present invention is realized through the following technical solutions. An evaluation method for the error correction ability of an approximate arithmetic unit specifically includes an approximate computing circuit:

[0007] Step 1: Represent the approximate computing circuit using a data flow graph (DFG). The nodes in the DFG are arranged in a topological manner, and the output of each node serves as the input of the next-level node.

[0008] Step 2: Randomly select an approximate arithmetic unit (AUU) from the approximate library of approximate high-level synthesis to replace any node in the DFG.

[0009] Step 3: Then, select several approximate arithmetic units from the approximate library of approximate high-level synthesis. Replace the next nodes along the topological tree-like path of the node selected in Step 2 with these several approximate arithmetic units respectively. Each of these several approximate arithmetic units obtains a corresponding error correction metric index at this node, and then the error correction ability value (AAU Ecc ) of each approximate arithmetic unit at this node is obtained. Select and retain the approximate arithmetic unit with the largest error correction ability value. The introduction of an approximate arithmetic unit with a larger error correction ability value results in less introduced error and more corrected error. The error correction ability value of the approximate arithmetic unit takes into account the current error characteristics when selecting the approximate arithmetic unit, and selects an approximate arithmetic unit with high adaptability according to the current error, making the use of the approximate arithmetic unit more valuable.

[0010] Step 4: Perform error evaluation on the approximate computing circuit after node replacement to obtain an error evaluation index. Compare it with a preset error constraint value to perform error constraint judgment.

[0011] If the error evaluation index is less than or equal to the error constraint value, retain the replacement of the approximate arithmetic unit at the next node of the node described in Step 3.

[0012] If the error evaluation index is greater than the error constraint value, re-perform the replacement of the approximate arithmetic unit at the node described in Step 3 until the error evaluation index obtained from the approximate computing circuit is less than or equal to the error constraint value, and then perform the replacement of the approximate arithmetic unit at the next node of the node described in Step 3.

[0013] Step 5: According to Steps 3 - 4, starting from the first selected node, along the direction from the circuit input to the output, sequentially replace the subsequent nodes with approximate arithmetic units until all nodes are replaced, and then retain the design.

[0014] By comprehensively considering error evaluation and error correction ability value, gradually replace the approximate arithmetic units and select the approximate arithmetic unit with the largest error correction ability, so that the circuit can effectively improve its fault tolerance under the premise of meeting the error constraint and achieve the best performance.

[0015] As a further solution of the present invention, the error correction metric index includes the expected improvement error (EIE), the actual improvement error (AIE), and the increased error (INE).

[0016] The expected improvement error EIE is the sum of the absolute values of the differences between all initial outputs and the exact results, expressed as:

[0017] EIE = ∑abs{E1, E2, E3... E m};

[0018] where {E1, E2, E3... E m} represents all possible initial errors in the circuit, and m represents the m-th approximate arithmetic unit;

[0019] represents the difference between the initial output and the exact result under all possible inputs, represents the initial output values under all possible inputs, represents the exact result values under all possible inputs.

[0020] The expected improvement error EIE, as a measurement tool, can clearly quantify the change in error before and after optimization in the approximate calculation process. When adjusting the approximate calculation circuit, it can quickly identify which approximate arithmetic unit is most effective in improving the error.

[0021] As a further aspect of the present invention, the formula for calculating the actual improvement error AIE is AIE = ∑{X1, X2, X3... X n}, where Xi represents the improved error at each input i, and represents the output obtained using the AAU to be evaluated. The actual improvement error is determined based on the error between the actual output and the expected output of the circuit when using the approximate arithmetic unit.

[0022] As a further aspect of the present invention, the additional error INE is used to measure the error introduced by the approximate arithmetic unit, expressed as INE = ∑{Y1, Y2, Y3... Y m}, where Yi represents the additional error at each input i, The additional error INE effectively evaluates whether the error introduced by the approximate arithmetic unit is within an acceptable range. The approximate calculation significantly improves the speed or reduces the power consumption. By understanding the degree of error, it is determined whether it is necessary to optimize the approximate calculation to keep the error within a tolerable range.

[0023] As a further aspect of the present invention, the metric AAU for evaluating the error correction ability of a single approximate arithmetic unit Ecc , is expressed as where N is the number of all possible inputs, n is the number of X i , and m is the number of Y iThe quantity. By evaluating the error characteristics under different input states, it is ensured that the approximate arithmetic unit can stably output correct results in the face of inevitable calculation errors, and accurately describe the error correction ability of the approximate arithmetic unit.

[0024] As a further aspect of the present invention, the approximate library of the approximate high-level synthesis refers to an approximate library constructed by approximate arithmetic units. When selecting an approximate arithmetic unit, one or more approximate arithmetic units are selected from the approximate library each time to replace the exact arithmetic unit at the node. The approximate library constructed by approximate arithmetic units enables the system to diversely select approximate arithmetic units according to different calculation requirements to meet the design requirements of diverse approximate calculation circuits.

[0025] As a further aspect of the present invention, an approximate high-level synthesis design system adopts an evaluation method for the error correction ability of approximate arithmetic units to obtain an optimal approximate calculation circuit. The optimal approximate calculation circuit has high calculation efficiency, low power consumption, and strong system fault tolerance. Applying the approximate calculation circuit to the approximate high-level synthesis design system obtains a system with optimal performance, achieving the best balance between accuracy and power consumption.

[0026] As a further aspect of the present invention, a computer-readable storage medium stores a computer program thereon. When the computer program is executed by a processor, it implements the steps of the evaluation method for the error correction ability of approximate arithmetic units. Combining the approximate arithmetic unit and the error correction mechanism realizes efficient and accurate design, optimizes hardware resources and power consumption, and accelerates the circuit development process. Flexibly controls the accuracy, error, and performance of the circuit to ensure efficient and fault-tolerant computing capabilities in variable application scenarios.

[0027] The beneficial effects of the present invention are as follows: An evaluation method for the error correction ability of an approximate arithmetic unit provided by the present invention, by comprehensively considering error evaluation and error correction ability values, gradually replaces the approximate arithmetic unit and selects the approximate arithmetic unit with the maximum error correction ability. The approximate arithmetic unit is selected from the approximate library. The approximate library constructed by the approximate arithmetic unit enables the system to diversely select approximate arithmetic units according to different calculation requirements to meet the design requirements of diverse approximate calculation circuits.

[0028] Enables the circuit to effectively improve the fault tolerance of the circuit under the premise of meeting the error constraints, achieving the best performance. Can apply the designed approximate calculation circuit to the approximate high-level synthesis system with the minimum accuracy to obtain an optimal system.

[0029] The error correction metric indicators include Expected Improvement Error (EIE), Actual Improvement Error (AIE), and Increase Error (INE); the Expected Improvement Error (EIE) clearly quantifies the change in error before and after optimization during the approximate calculation process. When adjusting the approximate calculation circuit, it quickly identifies which approximate arithmetic unit is most effective in improving the error. The Actual Improvement Error is determined based on the error between the actual output and the expected output of the circuit when using the approximate arithmetic unit. The Increase Error (INE) effectively evaluates whether the error introduced by the approximate arithmetic unit is within an acceptable range. The approximate calculation significantly improves speed or reduces power consumption. By understanding the degree of error, it is decided whether it is necessary to optimize the approximate calculation to keep the error within a tolerable range.

[0030] By evaluating the error characteristics under different input states, it is ensured that the approximate arithmetic unit stably outputs the correct result in the face of inevitable calculation errors, and accurately describes the error correction ability of the approximate arithmetic unit.

[0031] The entire approximate calculation circuit design is applied to the approximate high-level synthesis design system to obtain the system with the optimal performance, achieving the best balance between accuracy and power consumption. Brief Description of the Drawings

[0032] Figure 1 It is a schematic diagram for the characteristic analysis of the overall error correction ability value (Ave.AAU Ecc ) of the present invention;

[0033] Figure 2 It is a schematic diagram for comparing two search processes of the present invention;

[0034] Figure 3 It is a schematic diagram for comparing the JS search results using two metrics of the present invention. Detailed Embodiment

[0035] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] The serial numbers assigned to the components in this text itself, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. And the "connection" and "coupling" mentioned in this application, unless otherwise specified, both include direct and indirect connection (coupling). In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0037] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or simply means that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower horizontal height than the second feature.

[0038] Embodiment 1

[0039] A method for evaluating the error correction ability of an approximate arithmetic unit, specifically including an approximate calculation circuit:

[0040] Step 1: Represent the approximate calculation circuit using a data flow graph DFG. The nodes in the data flow graph DFG are arranged in a topological manner, and the output of each node is used as the input of the next-level node;

[0041] Step 2: Randomly select an approximate arithmetic unit (AUU) from the approximate library of approximate high-level synthesis to replace any node in the data flow graph DFG;

[0042] Among them, the approximate library of approximate high-level synthesis refers to an approximate library constructed by approximate arithmetic units. When selecting an approximate arithmetic unit, one or more approximate arithmetic units are selected from the approximate library each time to replace the exact arithmetic unit at the node.

[0043] Approximate High-Level Synthesis (A-HLS) is a technology that combines approximate computing techniques with high-level synthesis (HLS) methods. It designs approximate computing circuits for specific applications and automatically generates corresponding hardware implementations through high-level synthesis tools. Approximate computing can improve performance (such as accelerating computing speed, reducing power consumption, and lowering hardware complexity) by sacrificing a certain degree of precision in some application scenarios, while high-level synthesis is the process of transforming high-level algorithm descriptions into hardware circuits. The goal of approximate high-level synthesis is to automatically generate designs that can meet error constraints and achieve high approximation benefits using approximate techniques.

[0044] In approximate high-level synthesis, an approximation library refers to a library that contains various approximate arithmetic units (such as approximate adders, approximate multipliers, approximate shifters, etc.). These approximate arithmetic units reduce resource consumption or improve efficiency by implementing approximate computing methods in hardware.

[0045] An approximate arithmetic unit (AAU) is an arithmetic computing unit that improves operation speed or reduces power consumption by sacrificing a certain degree of precision. It is used in application scenarios such as image processing, audio processing, and machine learning. Without affecting the overall system performance, it reduces the consumption of computing resources and improves efficiency.

[0046] Different from traditional arithmetic units, approximate arithmetic units improve computing speed and reduce power consumption by reducing computing precision within a certain tolerance range. By simplifying or optimizing basic arithmetic operation modules such as adders, multipliers, and dividers, approximate arithmetic units can complete computing tasks faster and are suitable for application scenarios with low requirements for result precision. Due to the reduced precision, the required computing complexity is also reduced, thus significantly reducing the power consumption of the hardware, which is particularly important for battery-powered devices such as embedded systems or mobile devices. In tasks such as image denoising, compression, or filtering, a certain degree of error can usually be tolerated, so using approximate arithmetic units can accelerate the processing process. Approximate arithmetic units provide higher efficiency and lower power consumption in some specific applications by accepting a certain computing error, and it is a design choice that balances precision and performance.

[0047] Step 3: Then, select several approximate arithmetic units from the approximation library of approximate high-level synthesis, and sequentially replace the next nodes along the topological tree-like path of the selected nodes in Step 2 with the several approximate arithmetic units. The several approximate arithmetic units respectively obtain corresponding error correction metric indicators at this node, and then respectively obtain the error correction ability values of each approximate arithmetic unit at this node (AAU Ecc) Select the approximate arithmetic unit with the largest error correction ability value and retain it;

[0048] The error correction metric indicators include Expected Improvement Error (EIE), Actual Improvement Error (AIE), and Increased Error (INE);

[0049] The goal of the Expected Improvement Error EIE is to reduce the errors caused by finite precision, rounding errors, overflow, etc. by optimizing the calculation process and design scheme.

[0050] The Expected Improvement Error (EIE) is an indicator that measures the error between approximate calculation and exact calculation. It is used to evaluate how the approximate algorithm affects the accuracy of the result while maintaining low resource consumption (such as hardware complexity, power consumption, etc.).

[0051] The Expected Improvement Error EIE is the sum of the absolute values of the differences between all initial outputs and the exact results, expressed as:

[0052] EIE = ∑abs{E1, E2, E3...E m};

[0053] where {E1, E2, E3...E m} represents all possible initial errors in the circuit, and m represents the m-th approximate arithmetic unit;

[0054] represents the difference between the initial output and the exact result under all possible inputs, represents the initial output value under all possible inputs, represents the exact result value under all possible inputs.

[0055] The Actual Improvement Error (AIE) is another way to measure the error between approximate calculation and exact calculation. It is usually used to measure the error actually generated after approximate calculation. Different from the Expected Improvement Error (EIE), the Actual Improvement Error focuses more on the error performance in the real environment or actual application, rather than the theoretically expected error.

[0056] The calculation formula for the Actual Improvement Error AIE is AIE = Σ{X1, X2, X3,...X n}, where Xi represents the improved error under each input i, and represents the output obtained using the AAU to be evaluated.

[0057] The added error INE is typically used to measure the error introduced by approximate arithmetic units that perform calculations using approximate algorithms or hardware to improve the operation speed or reduce power consumption. The calculation accuracy is sacrificed in this approximate manner, and the added error becomes an important indicator for measuring the impact of this sacrifice on the final calculation result.

[0058] The added error INE is used to measure the error introduced by approximate arithmetic units, expressed as INE = Σ{Y1, Y2, Y3...Y m}, where Yi represents the added error at each input i.

[0059] The metric AAU for evaluating the error correction ability of a single approximate arithmetic unit Ecc , is expressed as where N is the number of all possible inputs, n is the number of X i 's, and m is the number of Y i 's.

[0060] Step 4: Perform error evaluation on the approximate calculation circuit after node replacement to obtain an error evaluation metric, compare it with a preset error constraint value, and perform error constraint judgment;

[0061] If the error evaluation metric is less than or equal to the error constraint value, retain the replacement of the approximate arithmetic unit of the next node of the node described in Step 3;

[0062] If the error evaluation metric is greater than the error constraint value, re-perform the replacement of the approximate arithmetic unit of the node described in Step 3 until the error evaluation metric obtained from the approximate calculation circuit is less than or equal to the error constraint value, and then perform the replacement of the approximate arithmetic unit of the next node of the node described in Step 3;

[0063] Step 5: According to Steps 3 - 4, starting from the first selected node, along the circuit input to output direction, sequentially perform the replacement of the approximate arithmetic unit of the subsequent nodes until all nodes are replaced, and then retain the design.

[0064] During the design process, if it is necessary to evaluate the performance of the entire design, calculate the average value of the error correction ability values (AAU Ecc ) of all replaced approximate arithmetic units in the entire approximate calculation circuit to obtain the overall error correction ability value (Ave.AAU Ecc ) of multiple approximate arithmetic units.

[0065] The overall approximate arithmetic unit error correction ability metric Ave.AAU Ecc metric, is expressed as:

[0066]

[0067] Among them, k is the serial number of adjacent units.

[0068] If the overall error correction ability value meets the design requirements, the current approximate calculation circuit after replacement is retained.

[0069] Comparative Example 1

[0070] The Efficient Number-Aware Pruning Framework (ENAP) refers to an automated framework that uses spatial pruning techniques to prune the design space and then uses a genetic algorithm to obtain an efficient approximate circuit.

[0071] In the Efficient Number-Aware Pruning Framework (ENAP), the genetic algorithm (GA general algorithm) is used as a search algorithm to obtain high-quality approximate designs, but the results of GA are limited by the initial design.

[0072] In the original framework, ENAP lacks a suitable criterion for creating the initial design and uses a random method to create these initial designs. In the present invention, AAU Ecc is used as an evaluation criterion to assist in the formation of the initial design.

[0073] And Ave.AAU Ecc reflects the average error correction ability of the approximate arithmetic units in the approximate design. Figure 2 Used to analyze Ave.AAU Ecc shows the exploration process of the Efficient Number-Aware Pruning Framework (ENAP) to find the optimal approximate design of 2x2 convolution under different error constraints (MED < 15 and MED < 20). Each small black dot represents an approximate design, the Y-axis represents the area saving of the approximate design, and the X-axis represents the error of the approximate design. Figure 2 All approximate designs in Ecc meet the error constraints, but the area savings of each approximate design are different. Obviously, the more the area is saved, the better the approximate design. To analyze Ave.AAU Figure 1 we list the area savings of the approximate designs within the red dashed line and the corresponding Ave.AAU Ecc in Figure 1 It can be observed from Ecc that the Ave.AAU Ecc of the approximate design increases with the increase of the area saving, which indicates that Ave.AAU EccIt means that more errors are corrected, which provides a greater opportunity for using more AAUs (Approximate Arithmetic Units) or AAUs with a larger area saving, thus achieving a greater area saving. Therefore, like AAU Ecc Ave.AAU Ecc can be used for the preliminary evaluation of approximate designs without the user having to perform physical synthesis.

[0074] Comparative Example 2

[0075] Traditionally, jump search (JS) is used to explore the design space of approximate computing circuits. An approximate arithmetic unit is randomly selected to replace the first node. The selection of the approximate arithmetic unit is determined by the figure of merit (FOM). The figure of merit (FOM) does not consider the change of error propagation and only selects the approximate arithmetic unit that can provide the largest area saving at the current moment. Therefore, it cannot guarantee to select the most suitable approximate arithmetic unit.

[0076] Modify the jump search (JS) framework and use AAU Ecc as the standard for selecting approximate arithmetic units, and select the AAU Ecc with the highest approximation for design each time.

[0077] When applying a 2×2 convolution operation, the approximate computing circuit includes 7 nodes, including 4 multiplication operations and 3 addition operations. AAU Ecc considers the current error characteristics when selecting approximate units. It selects approximate units with high adaptability according to the current error, making the use of approximate units more valuable. In contrast, FOM does not consider the current error and often leads to the same search results under different error constraints. For example, in Figure 2 , although the error constraints are different, the search results for MED = 10 and MED = 20 are the same.

[0078] Figure 3 Shows the search results using two different metrics. The Y-axis represents the area saving, and the higher the value, the better the quality of the approximate design. The X-axis represents different error constraints, and MED is used as the evaluation metric for error quality.

[0079] Figure 3 Indicates that the search results using AAU Ecc as the metric for selecting approximate units are better than FOM, especially when the error constraint increases.

[0080] The error variance of approximate units enhances the security of convolutional neural networks (CNNs); in the field of hardware security, when an intruder attempts to steal information, the error in the approximate arithmetic unit is used to mask information leakage.

[0081] Example 4

[0082] An approximate high-level synthesis design system uses the evaluation method for the error correction ability of the approximate arithmetic unit in Embodiment 1 to obtain an optimal approximate calculation circuit.

[0083] In the design process of the approximate calculation circuit of the FIR filter. It contains 24 nodes, among which there are 13 multiplication operations and 12 addition operations.

[0084] Use the quantity-aware search framework (ENAP) to generate the initial circuit design and explore two methods. The first method uses the genetic algorithm, and the second method forms the initial design randomly.

[0085] Figure 2 Shows the search process and results of the two methods when MED < 5.

[0086] The black dots in the figure represent the search process of the initial ENAP, and the red dots represent the search process of the ENAP using AAU Ecc of the ENAP. Both methods perform 10 iterations. The legend shows the highest Aue of the initial design of the two methods. AAU Ecc , which is obtained from the formula derived.

[0087] As Figure 2 shown, the search results of the ENAP using AAU Ecc are significantly better than those of the initial ENAP. In addition, the search curve of the initial ENAP does not converge to a result after ten iterations, indicating that many good results have not been found. In contrast, the ENAP using AAU Ecc converges to a result, and the result at the beginning of the convergence is much better than the result of the initial ENAP after ten iterations.

[0088] In summary, the optimal approximate calculation circuit is obtained by using the evaluation method for the error correction ability of the approximate arithmetic unit.

[0089] Embodiment 5

[0090] A computer-readable storage medium stores a computer program thereon. When the computer program is executed by a processor, it implements the steps of the evaluation method for the error correction ability of the approximate arithmetic unit.

[0091] First, for the approximate calculation circuit, use the approximate arithmetic unit with the maximum error correction ability value (such as approximate adder, approximate multiplier) to replace the corresponding nodes in the approximate calculation circuit to achieve efficient calculation, reduce the consumption of hardware resources and calculation delay, and at the same time maintain a certain calculation accuracy.

[0092] The approximate computing circuit designed by the evaluation method for error correction through an approximate arithmetic unit is realized under the control of a computer program stored in a computer-readable storage medium, which reduces the circuit complexity and power consumption while meeting the error constraint. It directly controls the source and magnitude of the error and precisely adjusts the performance and accuracy of the approximate computing circuit.

[0093] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0094] The above-described embodiments merely represent several implementation manners of the present invention, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be subject to the appended claims.

Claims

1. An evaluation method for approximating the error correction ability of an arithmetic unit, characterized in that, Specifically, it includes an approximate calculation circuit: Step 1: Represent the approximate calculation circuit using a data flow graph (DFG). The nodes in the DFG are arranged in a topological manner, and the output of each node serves as the input of the next-level node. Step 2: Randomly select an approximate arithmetic unit (AUU) from the approximate library in approximate high-level synthesis to replace any node in the DFG. Step 3: Then, select several approximate arithmetic units from the approximate library for approximate high-level synthesis, and sequentially replace the next nodes along the topological tree direction of the selected nodes in Step 2 with the several approximate arithmetic units. The several approximate arithmetic units respectively obtain corresponding error correction metric indicators at this node, and further obtain the error correction ability values (AAU Ecc ) of each approximate arithmetic unit at this node. Select the approximate arithmetic unit with the largest error correction ability value and retain it; Step 4: Evaluate the error of the approximate calculation circuit after node replacement to obtain an error evaluation index, compare it with a preset error constraint value, and perform an error constraint judgment. If the error evaluation index is less than or equal to the error constraint value, retain the replacement of the approximate arithmetic unit of the next node of the node described in Step 3. If the error evaluation index is greater than the error constraint value, re-perform the replacement of the approximate arithmetic unit of the node described in Step 3 until the error evaluation index obtained from the approximate calculation circuit is less than or equal to the error constraint value, and then perform the replacement of the approximate arithmetic unit of the next node of the node described in Step 3. Step 5: According to Steps 3-4, starting from the first selected node, along the circuit input to output direction, sequentially perform the replacement of the approximate arithmetic unit for the subsequent nodes until all nodes are replaced, and then retain the design.

2. The evaluation method for the error correction ability of an approximate arithmetic unit according to claim 1, wherein The error correction metric includes the expected improvement error (EIE), the actual improvement error (AIE), and the increased error (INE). The expected improvement error EIE is the sum of the absolute values of the differences between all initial outputs and the exact results, expressed as: EIE = ∑abs{E1, E2, E3...E m}; Among them, {E1, E2, E3... E m} represents all possible initial errors in the circuit, and m represents the m-th approximate arithmetic unit; represents the difference between the initial output and the exact result for all possible inputs, represents the initial output value for all possible inputs, represents the exact result value for all possible inputs.

3. The evaluation method for the error correction ability of an approximate arithmetic unit according to claim 2, characterized in that, The calculation formula for the actual improvement error AIE is AIE = ∑{X1, X2, X3... X n}, where Xi represents the improved error at each input i, while represents the output obtained using the AAU to be evaluated.

4. The evaluation method for the error correction ability of an approximate arithmetic unit according to claim 3, characterized in that The added error INE is used to measure the error introduced by the approximate arithmetic unit and is expressed as INE = ∑{Y1, Y2, Y3...Y m}, where Yi represents the added error at each input i, 5. The evaluation method for the error correction ability of an approximate arithmetic unit according to claim 4, wherein The metric AAU for evaluating the error correction ability of a single approximate arithmetic unit Ecc , denoted as where N is the number of all possible inputs, n is the number of X i and m is the number of Y i .

6. The evaluation method for the error correction ability of an approximate arithmetic unit according to claim 5, wherein The error correction ability index Ave.AAU of the overall approximate arithmetic unit Ecc Index, which is expressed as: where k is the serial number of the adjacent unit.

7. The evaluation method for approximating the error correction ability of an arithmetic unit according to claim 1, characterized in that The approximate library in approximate high-level synthesis refers to an approximate library constructed by approximate arithmetic units. When selecting an approximate arithmetic unit, one or more approximate arithmetic units are selected from the approximate library each time to replace the exact arithmetic unit at the node.

8. An approximate high-level synthesis design system, characterized in that, Use the evaluation method for the error correction ability of the approximate arithmetic unit according to any one of claims 1-7 to obtain the optimal approximate calculation circuit.

9. A computer-readable storage medium, characterized in that, A computer program is stored thereon, characterized in that when the computer program is executed by a processor, it implements the steps of the evaluation method for the error correction ability of the approximate arithmetic unit according to any one of claims 1-7.

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