Data access control method and device, chip, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a data access control method and device, a chip, electronic equipment and a storage medium. The method comprises the steps that a hardware control module receives a control signal and a data attribute signal transmitted by a processor module through a signal bus; under the condition that the control signal is a first signal value representing that data operation corresponding to access of the processor module to the memory module is write operation, the hardware control module determines whether the write operation is alignment access operation of a preset data unit or not according to the data attribute signal; under the condition that the write operation is not the alignment access operation of the preset data unit, the hardware control module sends an interrupt signal to the processor module; when the interrupt signal is received, the processor module stops writing the target data to the memory module. According to the scheme, the processor module is timely prevented from continuing non-aligned data access through the hardware control module, data loss or coverage of the memory module is avoided, and consistency and safety of stored data are guaranteed.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technologies, and in particular, to a data access control method, apparatus, chip, electronic device, and storage medium. Background Art

[0002] Currently, in the design of a system-on-chip, it is usually required to integrate a memory module, such as SRAM (Static Random-Access Memory), within the chip architecture, so that the processor module can efficiently access the memory module for data and perform corresponding read and write operations. Among them, the memory module can be designed to have the function of parsing the data sent by the processor module to obtain data units and performing data read and write according to the data units. The data units can be words, half-words, bytes, etc. In the actual application process, the foregoing function will increase the physical design complexity of the memory module, and thus expand the occupied area of the memory module in the chip. Specifically, there is a difference of nearly 30% in the area occupied by the memory module with or without the foregoing function in the chip. Therefore, in application scenarios with strict chip area limitations, a memory module without the foregoing function is usually selected. Correspondingly, the processor module needs to perform aligned access to the memory module according to a preset data unit.

[0003] However, in the related art, a third-party code library is introduced during the firmware development process, and the third-party code library does not necessarily follow the writing specification of the preset data unit. When the processor module in the chip attempts to write data with a non-preset data unit, it will be forcibly extended by the memory module to write data with a preset data unit, resulting in invalid or blank information in the finally written data, leading to the loss or overwriting of the original stored data in the memory module, and the consistency and security of the stored data cannot be guaranteed. Summary of the Invention

[0004] The embodiments of the present application provide a data access control method, apparatus, chip, electronic device, and storage medium, which solve the problem that the original stored data in the memory module will be lost or overwritten when the processor module writes data with a non-preset data unit in the related art, and the consistency and security of the stored data cannot be guaranteed. By adding a hardware control module in the chip, it is realized that the hardware control module can effectively identify the misaligned access behavior of the processor module, timely prevent the processor module from continuing to perform misaligned data access, avoid data loss or overwriting in the memory module, and ensure the consistency and security of the stored data.

[0005] In a first aspect, an embodiment of the present application provides a data access control method, which is applied to a chip. The chip includes a processor module, a memory module, and a hardware control module. The processor module, the memory module, and the hardware control module are respectively connected to a set signal bus. The method includes:

[0006] The hardware control module receives a control signal and a data attribute signal transmitted by the processor module through the signal bus;

[0007] When the control signal is a first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation for a preset data unit according to the data attribute signal. The data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation;

[0008] When the write operation is not an aligned access operation for a preset data unit, the hardware control module sends an interrupt signal to the processor module;

[0009] When receiving the interrupt signal, the processor module stops writing the target data to the memory module.

[0010] In a second aspect, an embodiment of the present application further provides a data access control device, including:

[0011] A hardware control module, configured to receive a control signal and a data attribute signal transmitted by a processor module through a signal bus. When the control signal is a first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, determine whether the write operation is an aligned access operation for a preset data unit according to the data attribute signal. The data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation. When the write operation is not an aligned access operation for a preset data unit, send an interrupt signal to the processor module;

[0012] A processor module, configured to stop writing the target data to the memory module when receiving the interrupt signal.

[0013] In a third aspect, an embodiment of the present application further provides a chip, which includes a processor module, a memory module, and a hardware control module. The processor module, the memory module, and the hardware control module are respectively connected to a set signal bus. The chip is used to execute the data access control method described in the embodiment of the present application.

[0014] In a fourth aspect, an embodiment of the present application further provides an electronic device, which includes the chip described in the embodiment of the present application.

[0015] In a fifth aspect, an embodiment of the present application further provides a non-volatile storage medium storing computer-executable instructions, and the computer-executable instructions are configured to execute the data access control method described in the embodiments of the present application when executed by a computer processor.

[0016] In an embodiment of the present application, a hardware control module receives a control signal and a data attribute signal transmitted by a processor module through a signal bus; when the control signal is a first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation for a preset data unit according to the data attribute signal; when the write operation is not an aligned access operation for a preset data unit, the hardware control module sends an interrupt signal to the processor module; when receiving the interrupt signal, the processor module stops writing target data to the memory module. In the above solution, a hardware control module is added to the chip, and the hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the set signal bus, which can effectively determine whether the current data operation of the processor module is a write operation and continue to process the data attribute signal. When the control signal is a first signal value indicating that the current data operation is a write operation, it can be determined whether the write operation is an aligned access operation for a preset data unit according to the data attribute signal, effectively identifying the unaligned access behavior of the processor module. Moreover, when the write operation is not an aligned access operation for a preset data unit, it is determined that the current access operation of the processor module is non-compliant, and the hardware control module sends an interrupt signal to the processor module, which can timely prevent the processor module from continuing unaligned data access, avoid data loss or overwrite in the memory module, and ensure the consistency and security of the stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of a data access control method provided by an embodiment of the present application;

[0018] Figure 2 It is a flowchart of a data access control method provided by an embodiment of the present application including a process of determining whether a write operation is an aligned access operation based on a data address signal;

[0019] Figure 3 It is a flowchart of a data access control method provided by an embodiment of the present application including a process of determining whether a write operation is an aligned access operation based on a data address signal and a data length signal;

[0020] Figure 4 It is a flowchart of another data access control method provided by an embodiment of the present application including a process of determining whether a write operation is an aligned access operation based on a data address signal and a data length signal;

[0021] Figure 5 A flowchart of a data access control method including a process of outputting an abnormal reminder message provided by an embodiment of the present application;

[0022] Figure 6 A flowchart of a data access control method including a process of changing the state of a processor module provided by an embodiment of the present application;

[0023] Figure 7 A structural block diagram of a data access control device provided by an embodiment of the present application;

[0024] Figure 8 A schematic structural diagram of a chip provided by an embodiment of the present application;

[0025] Figure 9 A schematic structural diagram of an electronic device provided by an embodiment of the present application. Specific Embodiments

[0026] The following further elaborates on the embodiments of the present application in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than limiting the embodiments of the present application. Additionally, it should be noted that for the convenience of description, only parts related to the embodiments of the present application are shown in the drawings, rather than all the structures.

[0027] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and do not limit the number of objects. For example, the first object can be one or multiple. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / ", generally represents an "or" relationship between the associated objects before and after.

[0028] The data access control method provided by the embodiments of the present application is applied to a chip. The newly added hardware control module can identify and determine whether the write operation of the processor module to the memory module is an aligned access operation. When a misaligned access operation is identified, the hardware control module triggers an interrupt of the processor module through the hardware control module, so that the processor module stops writing data, avoiding data loss or overwriting in the memory module, and ensuring the consistency and security of the stored data. The present application aims to provide a data access control method, device, chip, electronic device, and storage medium, to solve the problem in the related art that when the processor module writes data in a non-prescribed data unit, it may cause the loss or overwriting of the original stored data in the memory module, and the consistency and security of the stored data cannot be guaranteed.

[0029] Figure 1 FIG. 4 is a flowchart of a data access control method provided by an embodiment of the present application. The data access control method is applied to a chip, which includes a processor module, a memory module, and a hardware control module. The processor module, the memory module, and the hardware control module are respectively connected to the set signal bus. It should be noted that the memory module only supports access in a preset data unit. Taking the word as an example of the preset data unit, 1 word is equivalent to 4 bytes. Therefore, even if the memory module receives a single-byte or double-byte write operation from the processor module, it will be written in 4 bytes, resulting in only 1 or 2 bytes of data being valid in the written data, and the remaining byte data being blank data or random data, causing the loss or overwriting of the original stored data. In addition, the signal bus can be AHB (Advanced High-performance Bus), AXI (Advanced eXtensible Interface), etc., and can be used to transmit control signals and data attribute signals sent by the processor module to the memory module. The processor module can be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), etc. The memory module can be an SRAM (Static Random Access Memory) module, DRAM (Dynamic Random Access Memory), etc. The hardware control module can be an independent unit module with data calculation, processing, and storage capabilities, and can be applied to data access control. As Figure 1 shown, the data access control method specifically includes the following steps:

[0030] Step S101, the hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the signal bus.

[0031] Among them, the control signal can be used by the processor module to indicate to the memory module whether the currently initiated data operation is a write operation or a read operation. Specifically, the control signal can be a level signal. For example, a high-level signal indicates that the current data operation is a write operation, and a low-level signal indicates that the current data operation is a read operation. The data attribute signal can be used by the processor module to indicate the storage location, size, etc. of the target data corresponding to the currently initiated data operation. Specifically, the data attribute signal can include a data address signal, a data length signal, etc. The data address signal is used to represent the specific storage location of the target data relative to the memory module, and the data length signal is used to represent the specific data size of the target data, such as the number of bytes. Since the memory module will force the writing of data with a non-preset data unit to be extended to the writing of data with a preset data unit, therefore, by setting up a hardware control module to receive the control signal and the data attribute signal, non-aligned access operations of the processor module can be identified in advance.

[0032] Step S102: When the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation with a preset data unit according to the data attribute signal.

[0033] Among them, taking the control signal as a level signal as an example, the first signal value can be the level value "1", which is used to indicate that the data operation of the processor module accessing the memory module is a write operation. Correspondingly, the level value "0" can be the second signal value, which is used to indicate that the data operation of the processor module accessing the memory module is a read operation. The embodiments of the present application aim to prevent the processor module from writing data with a non-preset data unit. Therefore, the write operation of the processor module can be identified by first judging the specific signal value of the control signal. If the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, it can be regarded that the currently initiated data operation of the processor module is a write operation. Since the data attribute signal is used to represent the storage location and size of the target data corresponding to the write operation, and different storage locations and sizes of the target data are associated with write operations of different data units. For example, the memory module will divide the corresponding storage areas by word, half-word, and byte respectively, and the corresponding data unit can be judged through the specific storage location of the target data. Also, for example, the length size of the target data can represent the specific number of bytes, and then the corresponding data unit can be judged accordingly. In this embodiment, the memory module only supports aligned access operations with preset data units. For example, it only supports read and write operations with words as data units. Therefore, it can be judged whether the write operation is an aligned access operation with a preset data unit according to the data attribute signal, so as to identify whether there is a non-aligned access behavior of the processor module.

[0034] Step S103: When the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module.

[0035] Among them, if the write operation is not an aligned access operation of a preset data unit, it can be regarded as the processor module currently attempting to write data of a non-preset data unit, which poses a relatively large data security risk and may cause the loss or overwrite of the original stored data in the memory module. Therefore, the hardware control module can send an interrupt signal to the processor module to promptly stop the misaligned access behavior of the processor module. Optionally, the hardware control module and the processor module can be connected through a preset signal line. It can be understood that this preset signal line can be used to establish an additional information transmission channel between the processor module and the hardware control module, ensuring that the interrupt signal can be transmitted to the processor module in a timely manner without interference when the signal bus is occupied.

[0036] Step S104: When receiving the interrupt signal, the processor module stops writing the target data to the memory module.

[0037] Among them, if the interrupt signal is received, the processor module can jump to the interrupt handling function and stop writing the target data to the memory module.

[0038] As described above, the hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the signal bus; when the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal; when the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module; when the interrupt signal is received, the processor module stops writing the target data to the memory module. In the above solution, a hardware control module is added to the chip. The hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the set signal bus, can effectively determine whether the current data operation of the processor module is a write operation, and continue to process the data attribute signal. When the control signal is the first signal value indicating that the current data operation is a write operation, it can determine whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal, effectively identifying the misaligned access behavior of the processor module. Moreover, when the write operation is not an aligned access operation of a preset data unit, it is determined that the current access operation of the processor module is non-compliant. The hardware control module sends an interrupt signal to the processor module, which can promptly prevent the processor module from continuing to perform misaligned data access, avoid data loss or overwrite in the memory module, and ensure the consistency and security of the stored data.

[0039] Figure 2 The flowchart of a data access control method provided by an embodiment of the present application, which includes a process of determining whether a write operation is an aligned access operation based on a data address signal, is as follows Figure 2 shown. The data access control method specifically includes the following steps:

[0040] Step S201: The hardware control module receives a control signal and a data attribute signal transmitted by the processor module through a signal bus. Among them, the data attribute signal includes a data address signal.

[0041] Step S202: When the control signal is a first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module extracts a first data bit sequence from the data address signal based on a first preset data position, and determines that the write operation is not an aligned access operation for a preset data unit when the first numerical value corresponding to the first data bit sequence is different from the first preset numerical value.

[0042] Among them, the data address signal can be a target address used to specify the target data to be written into the memory module. The bit width of the data address signal can be 32 bits, 64 bits, etc., and can be specifically determined by the processor architecture and memory capacity of the chip in the actual application scenario. It should be noted that the data address signal is a binary data bit sequence. For the aligned access operation of a preset data unit, the address value corresponding to the data address signal needs to be an integer multiple of the number of bytes corresponding to the preset data unit. For example, if the preset data unit is a word and the corresponding number of bytes is 4, then the address value corresponding to the data address signal should be a multiple of 4. Another example is that if the preset data unit is a half-word and the corresponding number of bytes is 2, then the address value corresponding to the data address signal should be a multiple of 2. In this embodiment, a first data bit sequence is extracted from the data address signal based on a first preset data position. The first data bit sequence can be used to determine whether the address value corresponding to the data address signal is an integer multiple of the number of bytes corresponding to the preset data unit. By way of example, if the preset data unit is a word and the corresponding number of bytes is 4, correspondingly, the first preset data position can be the low two bits of the data bit sequence corresponding to the data address signal. The possible combinations of the corresponding first data bit sequence are 00, 01, 10, and 11. Only when the first data bit sequence is 00, the address value corresponding to the data address signal can be a multiple of 4. Therefore, it can be determined whether the target address corresponding to the write operation matches the preset data unit "word" by determining whether the first value corresponding to the first data bit sequence is a first preset value, that is, whether it is 0. If the first value corresponding to the first data bit sequence is different from the first preset value, the target address corresponding to the write operation does not match the preset data unit, and the write operation is not an aligned access operation for the preset data unit. If the first value corresponding to the first data bit sequence is the same as the first preset value, the target address corresponding to the write operation matches the preset data unit, and it is further necessary to combine the data length signal to determine whether the data size of the target data corresponding to the write operation matches the preset data unit.

[0043] Step S203: In the case where the write operation is not an aligned access operation for the preset data unit, the hardware control module sends an interrupt signal to the processor module.

[0044] Step S204: In the case of receiving the interrupt signal, the processor module stops writing the target data to the memory module.

[0045] As described above, by extracting the first data bit sequence from the data address signal based on the first preset data position, the reference data for determining the data unit corresponding to the current write operation can be effectively intercepted from the data address signal. When the first value corresponding to the first data bit sequence is different from the first preset value, it can be considered that the address value corresponding to the data address signal does not meet the requirements of the preset data unit, and thus it can be accurately identified that the write operation is not an aligned access operation for the preset data unit, which is beneficial to timely stopping the data writing of the processor module subsequently.

[0046] Figure 3 The flowchart of a data access control method provided by an embodiment of the present application includes a process of determining whether a write operation is an aligned access operation based on a data address signal and a data length signal. As Figure 3 shown, the data access control method specifically includes the following steps:

[0047] Step S301, the hardware control module receives a control signal and a data attribute signal transmitted by the processor module through the signal bus, where the data attribute signal includes a data address signal and a data length signal.

[0048] Step S302, when the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module extracts the first data bit sequence from the data address signal based on the first preset data position.

[0049] Step S303, when the first value corresponding to the first data bit sequence is different from the first preset value, the hardware control module determines that the write operation is not an aligned access operation for the preset data unit.

[0050] Step S304, when the first value corresponding to the first data bit sequence is the same as the first preset value, the hardware control module extracts the second data bit sequence from the data length signal based on the second preset data position, and when the second value corresponding to the second data bit sequence is different from the second preset value, determines that the write operation is not an aligned access operation for the preset data unit.

[0051] Among them, if the first value corresponding to the first data bit sequence is the same as the first preset value, the target address corresponding to the write operation matches the preset data unit, and it is necessary to further combine the data length signal to determine whether the data size of the target data corresponding to the write operation matches the preset data unit. The data length signal can be used to indicate the data size of the target data written into the memory module. The bit width of the data length signal can be 32 bits, 64 bits, etc., which can be specifically determined by the processor architecture and memory capacity of the chip in the actual application scenario. It should be noted that the data length signal is a binary-form data bit sequence. According to the second data bit sequence corresponding to the second preset data position, the byte number size of the target data written into the memory module can be determined. By way of example, the preset data unit is a word, and the corresponding number of bytes is 4. Correspondingly, the second preset data position can be the low three bits of the data bit sequence corresponding to the data length signal, and the possible combinations of its corresponding second data bit sequence are 000, 001, 010, 011, 100, etc. If the second data bit sequence is 000, its corresponding second preset value is 0, which can indicate that the data size of the transmitted target data is 1 byte. If the second data bit sequence is 001, its corresponding second preset value is 1, which can indicate that the data size of the transmitted target data is 2 bytes. If the second data bit sequence is 010, its corresponding second preset value is 2, which can indicate that the data size of the transmitted target data is 4 bytes, and so on. Therefore, it can be determined whether the data size of the target data corresponding to the write operation matches the preset data unit "word" by determining whether the second value corresponding to the second data bit sequence is the second preset value, that is, whether it is 2. If the second value corresponding to the second data bit sequence is not the same as the second preset value, the data size of the target data corresponding to the write operation does not match the preset data unit, and the write operation is not an aligned access operation for the preset data unit. If the second value corresponding to the second data bit sequence is the same as the second preset value, the data size of the target data corresponding to the write operation matches the preset data unit, and it can be determined that the write operation is not an aligned access operation for the preset data unit.

[0052] Step S305: When the write operation is not an aligned access operation for the preset data unit, the hardware control module sends an interrupt signal to the processor module.

[0053] Step S306: When receiving the interrupt signal, the processor module stops writing the target data to the memory module.

[0054] As described above, when the first value corresponding to the first data bit sequence is the same as the first preset value, it can be considered that the target address corresponding to the write operation matches the preset data unit. It is possible to further determine whether the data size matches the preset data unit based on the data length signal, and combine the judgment result that the second value corresponding to the second data bit sequence is different from the second preset value to accurately identify that the write operation is not an aligned access operation for the preset data unit, which is beneficial to timely stop the data writing of the processor module subsequently.

[0055] Figure 4 The flowchart of another data access control method provided by the embodiment of the present application, which includes a process of determining whether a write operation is an aligned access operation based on a data address signal and a data length signal, is as Figure 4 shown. The data access control method specifically includes the following steps:

[0056] Step S401: The hardware control module receives a control signal and a data attribute signal transmitted by the processor module through the signal bus, where the data attribute signal includes a data address signal and a data length signal.

[0057] Step S402: When the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module extracts a first data bit sequence from the data address signal based on a first preset data position, and extracts a second data bit sequence from the data length signal based on a second preset data position, combines the first data bit sequence and the second data bit sequence to obtain a target data bit sequence, and compares the target data bit sequence with the set reference data bit sequence. When the target data bit sequence is different from the reference data bit sequence, it is determined that the write operation is not an aligned access operation for the preset data unit.

[0058] Among them, referring to the specific description of the foregoing embodiments, both the data address signal and the data length signal are binary-form data bit sequences. A first data bit sequence is extracted from the data address signal based on a first preset data position. The first data bit sequence can be used to determine whether the address value corresponding to the data address signal is an integer multiple of the number of bytes corresponding to a preset data unit. And, a second data bit sequence is extracted from the data length signal based on a second preset data position. The second data bit sequence can be used to determine the number of bytes of the target data written to the memory module. In this embodiment, the first data bit sequence and the second data bit sequence are combined to obtain a target data bit sequence. Specifically, the first data bit sequence and the second data bit sequence can be concatenated from left to right, or the second data bit sequence and the first data bit sequence can be concatenated from left to right. This application does not make a limitation here. The target data bit sequence can be used to simultaneously determine whether both the data address signal and the data length signal match the preset data unit, so as to determine whether the write operation is an aligned access operation of the preset data unit. By way of example, the preset data unit is a word, and the corresponding number of bytes is 4. Correspondingly, the first preset data position can be the low two bits of the data bit sequence corresponding to the data address signal, and the possible combinations of the corresponding first data bit sequence are 00, 01, 10, and 11. The second preset data position can be the low three bits of the data bit sequence corresponding to the data length signal, and the possible combinations of the corresponding second data bit sequence are 000, 001, 010, 011, 100, etc. Then, by concatenating the first data bit sequence and the second data bit sequence from left to right, the possible combinations of the obtained target data bit sequence are 00000, 00001, 00010, etc. Since the first data bit sequence is 00, the address value corresponding to the data address signal can be a multiple of 4. And, since the second data bit sequence is 010, the data size of the target data corresponding to this write operation can be 4 bytes, which matches the preset data unit "word". Therefore, for an application scenario with a word as the preset data unit, referring to the data bit sequence 00010, the target data bit sequence needs to be the same as this reference data bit sequence to determine that this write operation is an aligned access operation of the preset data unit.

[0059] Step S403, in the case where the write operation is not an aligned access operation of the preset data unit, the hardware control module sends an interrupt signal to the processor module.

[0060] Step S404, in the case of receiving the interrupt signal, the processor module stops writing the target data to the memory module.

[0061] As described above, by combining the first data bit sequence and the second data bit sequence to obtain a target data bit sequence and comparing the target data bit sequence with a set reference data bit sequence, it is possible to accurately determine whether the target address and the target data size corresponding to the write operation simultaneously match a preset data unit, and further accurately determine whether the write operation is an aligned access operation of the preset data unit, which is conducive to timely stopping the data writing of the processor module subsequently.

[0062] Figure 5 The figure is a flowchart of a data access control method including a process of outputting an exception reminder message provided by an embodiment of the present application. The hardware control module includes a storage unit, as Figure 5 shown. The data access control method specifically includes the following steps:

[0063] Step S501: The hardware control module receives a control signal and a data attribute signal transmitted by the processor module through a signal bus.

[0064] Step S502: When the control signal is a first signal value indicating that the data operation corresponding to the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal, where the data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation.

[0065] Step S503: When the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module and stores the data attribute signal in the storage unit.

[0066] Among them, the storage unit may be a register, a RAM (Random Access Memory), etc., and the present application does not limit this here. The hardware control module can store the data attribute signal in the storage unit to record the relevant information of this unaligned access operation. Optionally, the data attribute signal includes a data address signal and a data length signal, and corresponding storage units can be respectively set to store different types of data attribute signals.

[0067] Step S504: When receiving the interrupt signal, the processor module stops writing the target data to the memory module, reads the data attribute signal from the storage unit, and sends an exception reminder message including the data attribute signal to the user terminal.

[0068] As described above, by reading the data attribute signal in the storage unit, the processor module can, after the data writing is stopped due to an interrupt trigger, send an exception reminder message including the data attribute signal to the user terminal, providing reference data for the relevant personnel to troubleshoot exceptions, which is conducive to restoring normal data processing.

[0069] Figure 6 The flowchart of a data access control method including the process of changing the state of the processor module provided by the embodiment of the present application is as follows Figure 6 shown, and the data access control method specifically includes the following steps:

[0070] Step S601, the hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the signal bus.

[0071] Step S602, when the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal, where the data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation.

[0072] Step S603, when the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module.

[0073] Step S604, when receiving the interrupt signal, the processor module stops writing the target data to the memory module and enters a preset infinite loop state.

[0074] As described above, after the processor module stops writing data due to an interrupt trigger, it directly enters a preset infinite loop state, ensuring that the program does not continue to execute when there is an abnormal risk of data loss or overwrite, and waiting for relevant personnel to troubleshoot and repair.

[0075] Figure 7 The structural block diagram of a data access control device provided by the embodiment of the present application, the device is configured to execute the data access control method provided by the above embodiment, and has the corresponding functional modules and beneficial effects of the execution method. As Figure 7 shown, the device specifically includes:

[0076] The hardware control module 101 is configured to receive the control signal and the data attribute signal transmitted by the processor module through the signal bus, and when the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, determine whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal, where the data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation, and when the write operation is not an aligned access operation of a preset data unit, send an interrupt signal to the processor module;

[0077] The processor module 102 is configured to stop writing the target data to the memory module when receiving the interrupt signal.

[0078] As described above, the hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the signal bus; when the control signal is the first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal; when the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module; when receiving the interrupt signal, the processor module stops writing the target data to the memory module. In the above solution, a hardware control module is added to the chip. The hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the set signal bus, can effectively determine whether the current data operation of the processor module is a write operation, and continue to process the data attribute signal. When the control signal is the first signal value indicating that the current data operation is a write operation, it can be determined whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal, effectively identifying the unaligned access behavior of the processor module. Moreover, when the write operation is not an aligned access operation of a preset data unit, it is determined that the current access operation of the processor module is non-compliant. The hardware control module sends an interrupt signal to the processor module, which can timely prevent the processor module from continuing unaligned data access, avoid data loss or overwrite in the memory module, and ensure the consistency and security of the stored data.

[0079] In a possible embodiment, the data attribute signal includes a data address signal, and the hardware control module 101 is further configured to:

[0080] Extract a first data bit sequence from the data address signal based on a first preset data position;

[0081] When the first value corresponding to the first data bit sequence is different from the first preset value, determine that the write operation is not an aligned access operation of a preset data unit.

[0082] In a possible embodiment, the data attribute signal further includes a data length signal, and the hardware control module 101 is further configured to:

[0083] When the first value corresponding to the first data bit sequence is the same as the first preset value, extract a second data bit sequence from the data length signal based on a second preset data position;

[0084] When the second value corresponding to the second data bit sequence is different from the second preset value, determine that the write operation is not an aligned access operation of a preset data unit.

[0085] In a possible embodiment, the data attribute signal includes a data address signal and a data length signal, and the hardware control module 101 is further configured to:

[0086] Extract a first data bit sequence from the data address signal based on a first preset data position, and extract a second data bit sequence from the data length signal based on a second preset data position;

[0087] Combine the first data bit sequence and the second data bit sequence to obtain a target data bit sequence;

[0088] Compare the target data bit sequence with a set reference data bit sequence. When the target data bit sequence is different from the reference data bit sequence, determine that the write operation is not an aligned access operation for a preset data unit.

[0089] In a possible embodiment, the hardware control module includes a storage unit, and the hardware control module 101 is configured to:

[0090] Store the data attribute signal in the storage unit;

[0091] Correspondingly, the processor module 102 is further configured to:

[0092] Read the data attribute signal from the storage unit and send an exception reminder message including the data attribute signal to the user terminal.

[0093] In a possible embodiment, the processor module 102 is further configured to:

[0094] Enter a preset infinite loop state.

[0095] Figure 8 This is a schematic structural diagram of a chip provided by an embodiment of the present application. As Figure 8 shown, the chip 301 includes a processor module 201, a memory module 202, and a hardware control module 203. The processor module 201, the memory module 202, and the hardware control module 203 are respectively connected to a set signal bus 204. Optionally, the hardware control module 203 is connected to the processor module 201 through a preset signal line 205, and the hardware control module 203 includes a storage unit 2031. The chip 301 is used to execute the data access control method provided in any of the foregoing embodiments.

[0096] Figure 9 This is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As Figure 9 shown, the device includes the chip 301, an input device 302, and an output device 303 provided in the foregoing embodiment; the chip 301, the input device 302, and the output device 303 in the electronic device can be connected through a bus or other means. Figure 9Take the bus connection as an example. The input device 302 can be configured to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the device. The output device 303 can include display devices such as a display screen.

[0097] The electronic device provided above can be used to execute the data access control method provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0098] The embodiment of the present application also provides a non-volatile storage medium containing computer-executable instructions. The computer-executable instructions are configured to execute a data access control method described in one of the above embodiments when executed by a computer processor. Specifically, it includes: the hardware control module receives the control signal and the data attribute signal transmitted by the processor module through the signal bus; when the control signal is the first signal value indicating that the data operation of the processor module accessing the corresponding memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal, where the data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation; when the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module; when receiving the interrupt signal, the processor module stops writing the target data to the memory module.

[0099] Storage medium - any of various types of memory devices or storage devices. The term "storage medium" is intended to include: installation media such as CD-ROMs, floppy disks, or magnetic tape devices; computer system memories or random access memories such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memories such as flash memory, magnetic media, or optical storage; registers or other similar types of memory elements, etc. The storage medium can also include other types of memories or combinations thereof. Additionally, the storage medium can be located in the first computer system in which the program is executed, or can be located in a different second computer system that is connected to the first computer system through a network (such as the Internet). The second computer system can provide program instructions to the first computer for execution. The term "storage medium" can include two or more storage media residing in different locations (such as in different computer systems connected through a network). The storage medium can store program instructions (such as specifically implemented as a computer program) executable by one or more processors.

[0100] Of course, for a storage medium containing computer-executable instructions provided in the embodiment of the present application, the computer-executable instructions are not limited to the above data access control method, and can also execute related operations in the data access control methods provided in any embodiment of the present application.

[0101] It should be noted that in the embodiments of the above data access control device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of mutual distinction and are not configured to limit the protection scope of the embodiments of the present application.

[0102] It should be noted that the numbering of each step in this solution is only used to describe the overall design framework of this solution and does not represent an inevitable sequence between steps. On the basis that the overall implementation process conforms to the overall design framework of this solution, it all belongs to the protection scope of this solution. The sequential order in the form of words during description is not an exclusive limitation on the specific implementation process of this solution. Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and a memory. The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM), and / or non-volatile memory in the form of, for example, read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0103] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, commodity or device including the element.

[0104] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments here and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A data access control method, applied to a chip, characterized in that, The chip includes a processor module, a memory module, and a hardware control module. The processor module, the memory module, and the hardware control module are respectively connected to a set signal bus. The data access control method includes: The hardware control module receives a control signal and a data attribute signal transmitted by the processor module through the signal bus; When the control signal is a first signal value indicating that the data operation of the processor module accessing the memory module is a write operation, the hardware control module determines whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal. The data attribute signal is used to represent the storage location and size of the target data corresponding to the write operation; When the write operation is not an aligned access operation of a preset data unit, the hardware control module sends an interrupt signal to the processor module; When receiving the interrupt signal, the processor module stops writing the target data to the memory module.

2. The data access control method according to claim 1, wherein The data attribute signal includes a data address signal. Determining whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal includes: Extracting a first data bit sequence from the data address signal based on a first preset data position; When the first numerical value corresponding to the first data bit sequence is different from a first preset numerical value, it is determined that the write operation is not an aligned access operation of a preset data unit.

3. The data access control method according to claim 2, wherein The data attribute signal further includes a data length signal. After extracting the first data bit sequence from the data address signal based on the first preset data position, it further includes: When the first numerical value corresponding to the first data bit sequence is the same as the first preset numerical value, extracting a second data bit sequence from the data length signal based on a second preset data position; When the second numerical value corresponding to the second data bit sequence is different from a second preset numerical value, it is determined that the write operation is not an aligned access operation of a preset data unit.

4. The data access control method according to claim 1, wherein The data attribute signal includes a data address signal and a data length signal. Determining whether the write operation is an aligned access operation of a preset data unit according to the data attribute signal includes: Extracting a first data bit sequence from the data address signal based on a first preset data position and extracting a second data bit sequence from the data length signal based on a second preset data position; Combining the first data bit sequence and the second data bit sequence to obtain a target data bit sequence; Comparing the target data bit sequence with a set reference data bit sequence. When the target data bit sequence is different from the reference data bit sequence, it is determined that the write operation is not an aligned access operation of a preset data unit.

5. The data access control method according to any one of claims 1-4, characterized in that, The hardware control module includes a storage unit. After sending the interrupt signal to the processor module, it further includes: Storing the data attribute signal in the storage unit; Correspondingly, after stopping writing the target data to the memory module, it further includes: Read the data attribute signal from the storage unit and send an exception reminder message containing the data attribute signal to the user terminal.

6. The data access control method according to claim 5, wherein After sending the exception reminder message containing the data attribute signal to the user terminal, it further includes: Enter a preset infinite loop state.

7. A data access control device, characterized in that, It includes: A hardware control module configured to receive a control signal and a data attribute signal transmitted by a processor module through a signal bus. When the control signal is a first signal value indicating that the data operation corresponding to the processor module accessing the memory module is a write operation, determine whether the write operation is an aligned access operation for a preset data unit according to the data attribute signal. The data attribute signal is used to characterize the storage location and size of the target data corresponding to the write operation. When the write operation is not an aligned access operation for the preset data unit, send an interrupt signal to the processor module; A processor module configured to stop writing the target data to the memory module when receiving the interrupt signal.

8. A chip, the chip includes a processor module, a memory module, and a hardware control module. The processor module, the memory module, and the hardware control module are respectively connected to a set signal bus. The chip is used to execute the data access control method according to any one of claims 1-4.

9. The chip according to claim 8, characterized in that, The hardware control module includes a storage unit, and the chip is further used to execute the data access control method according to any one of claims 5-6.

10. An electronic device, the electronic device includes the chip according to claim 8 or 9.

11. A non-volatile storage medium storing computer-executable instructions, the computer-executable instructions are configured to execute the data access control method according to any one of claims 1-6 when executed by a computer processor.

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