Automatic combinational logic loop simulation method and system based on 55nm process

Abstract

The invention belongs to the technical field of digital circuit simulation design, and particularly relates to a combinational logic loop automatic simulation method and system based on a 55nm process, and the method comprises the steps: firstly finding out all strong connected components in a test case through depth-first search; then finding out strong connected components which cannot generate continuous oscillation and strong connected components which can generate continuous oscillation by using a maximum flow-minimum cut theorem, and analyzing oscillation conditions; and finally, inserting a register at a node which may oscillate to destroy all strong connected components which may generate continuous oscillation, thereby automatically detecting a combinational logic ring which does not conform to expectation in the digital gate circuit, analyzing a trigger condition, providing a minimum register insertion address for disconnecting a loop, and helping a designer to discover a design problem.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuit simulation design, and particularly relates to an automatic simulation method and system for combinational logic loops based on a 55nm process. Background Art

[0002] Combinational logic loops are commonly found in basic gate circuit modules. Unintended combinational logic loops may cause multiple driving or signal oscillation, resulting in increased circuit power consumption and functional errors. Combinational logic loops are difficult to be analyzed and calculated by static timing analysis tools, which may cause the simulator to enter an infinite loop.

[0003] At the 55nm process node, the reduction of the feature size of the gate circuit leads to an increase in leakage current and an acceleration of the signal propagation speed, which makes the timing problems caused by combinational logic loops more prominent. As a special structure that starts from a certain combinational logic unit and finally forms a closed path, the positive feedback type of combinational logic loops is commonly found in circuits such as latches and SRAM memory cells, while the negative feedback type is widely used in oscillator circuit design. It should be noted that in advanced process nodes, non-functional combinational logic loops may cause the following new risks: 1. Difficulties in timing convergence: Due to the sub-microsecond characteristics of gate delay under the 55nm process, the loop may form an unpredictable cumulative propagation delay.

[0004] 2. Abnormal surge in power consumption: The reduction of the process feature size leads to an exponential increase in the dynamic power consumption during loop oscillation.

[0005] 3. Deterioration of signal integrity: The parasitic parameters of the metal interconnect layer will exacerbate the attenuation distortion of the loop signal.

[0006] There are two main technical bottlenecks in existing analysis methods: First, traditional static timing analysis tools are difficult to accurately model the non-linear transmission gate effect under the 55nm process; Second, existing loop detection algorithms do not consider the threshold voltage shift problem caused by advanced process manufacturing deviation, which may result in a misjudgment rate of up to 12.7%. Especially when dealing with complex SoCs containing multi-voltage domain designs, existing methods cannot effectively identify the potential risks of cross-voltage domain combinational logic loops. Summary of the Invention

[0007] The present invention provides an automatic simulation method and system for combinational logic loops based on a 55nm process.

[0008] The technical solution of the present invention is as follows: The present invention provides an automatic simulation method for combinational logic loops based on a 55nm process, including the following steps: S1: Obtain the gate instance data of the combinational logic circuit. Use each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph. Based on the directed graph, perform a depth-first search to identify strongly connected components; S2: Use the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes. Analyze each node in the set of nodes individually, traverse forward, represent each node as a function of the external input and the node, construct a logical formula, judge the possibility of oscillation of the node according to the logical formula, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation; S3: Insert registers at the nodes that may oscillate to break all strongly connected components.

[0009] In the above S2, using the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes is specifically as follows: Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity. After all in - points are denoted as super in - points and all out - points are denoted as super out - points, calculate the maximum flow value from the super in - points to the super out - points, which is used as the capacity of the minimum cut, that is, the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

[0010] The directed graph obtained in the above S1 is implemented through the BuildGraph() function, specifically as follows: After recording the name of each port and the gate number it belongs to, assign a unique number to each input and output port as the node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph.

[0011] In the above S1, based on the directed graph, perform a depth - first search to identify strongly connected components, specifically as follows: For unvisited nodes, call the dfs() function to obtain the DFS traversal sequence number and the backtracking value of the unvisited node; Traverse the neighbor nodes of the unvisited node. If the neighbor node is not visited, recursively process the neighbor node and use the minimum value of the backtracking value of the neighbor node and the unvisited node as the new backtracking value of the unvisited node; If the neighbor node is in the stack, use the minimum value of the DFS traversal sequence number of the neighbor node and the backtracking value of the unvisited node as the new backtracking value of the unvisited node; When backtracking to an unvisited node, if the new backtracking value of the unvisited node is equal to the DFS traversal sequence number of the unvisited node, all nodes from the node to the top of the stack form a strongly connected component.

[0012] Further, the name of each port and its corresponding gate number are recorded through the port and mpbh arrays; the connection relationship between the input port and the output port is recorded using the to array and the Edge structure.

[0013] The present invention also provides a combinational logic loop automatic simulation system based on a 55nm process, including: Strongly connected component recognition module: used to obtain the gate instance data of the combinational logic circuit, taking each input and output port as a node of the graph, constructing the edges of the graph according to the connection relationship between the input port and the output port to obtain a directed graph; based on the directed graph, performing a depth-first search to identify strongly connected components; Analysis module: using the maximum flow - minimum cut theorem, obtaining the minimum vertex cover of all strongly connected components and obtaining a set of nodes; analyzing each node in the set of nodes separately, traversing forward, representing each node as a function of external inputs and the node itself, constructing a logical formula, judging the possibility of oscillation of the node according to the logical formula, obtaining the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and taking the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation. Repair module: used to insert registers at the nodes that may oscillate to destroy all strongly connected components.

[0014] The analysis module uses the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes, specifically: Each node of the strongly connected component is split into an in-point and an out-point, the capacity between the in-point and the out-point split from the same node is set to 1, and the capacity between nodes is set to positive infinity; after all in-points are recorded as super in-points and all out-points are recorded as super out-points, calculate the maximum flow value from the super in-point to the super out-point as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

[0015] The strongly connected component recognition module performs a depth-first search, which is implemented through the dfs() function and the tarjan() function.

[0016] Beneficial effects: At the 55nm process node, the present invention first finds all strongly connected components in the test cases through depth-first search; then uses the maximum flow-minimum cut theorem to find the strongly connected components that cannot have continuous oscillations and the strongly connected components that may generate continuous oscillations, and analyzes the conditions for oscillations; finally, inserts registers at the nodes where oscillations may occur to break all the strongly connected components that may generate continuous oscillations, thereby realizing the automatic detection of unexpected combinational logic loops in digital gate circuits, analyzing the triggering conditions, providing the minimum register insertion addresses for breaking the loops, and helping designers discover design problems. Moreover, this method has a low time complexity, high detection efficiency, and high detection accuracy. Specific implementation manner

[0017] The following embodiments are intended to illustrate the present invention rather than further limit the present invention.

[0018] At the 55nm process node, the present invention provides a method for automatic simulation of combinational logic loops based on the 55nm process, including the following steps: S1: Obtain the gate instance data of the combinational logic circuit. Using each input and output port as the nodes of the graph, based on the connection relationship between the input port and the output port, construct the edges of the graph to obtain a directed graph; based on the directed graph, perform depth-first search to identify strongly connected components.

[0019] The specific operations are as follows: First, read the simulation data through the vpi interface to obtain the gate instance information of the combinational logic circuit in the.v file. During this process, since the instances are independent of each other, multi-threading can be used to process different instances. Therefore, to speed up the reading speed, parallel traversal is used to accelerate the reading task using a multi-core CPU.

[0020] After reading the gate instances, construct a directed graph. Preferably, it is implemented through the BuildGraph() function. Specifically: After recording the name and the belonging gate number of each port, assign a unique number to each input and output port as the nodes (V) of the graph. Based on the connection relationship between the input port and the output port, construct the edges (E) of the graph to obtain a directed graph.

[0021] Among them, regarding recording port information, use the port and mpbh arrays to record the name and the belonging gate number of each port. Use the to array and the Edge structure to record the connection relationship between ports.

[0022] The BuildGraph() function is as follows: void BuildGraph(){ / / build graph / / get V id / / Number the ports for convenient graph construction for(int i = 1; i <= r; i += 1) { / / Bind the gates to the output ports if(!mp[outp[i]]) mp[outp[i]] = ++tot, port[tot] = outp[i], mpbh[tot] = i; } for(int i = 1; i <= r; i += 1) { for(int j = 0; j < siz[i]; j += 1) / / At this time, the unbound ones are the input ports that are not the output ports of the gates (i.e., the input ports of the entire circuit from the outside world), so don't bind if(!mp[inp[i][j]]) mp[inp[i][j]] = ++tot, port[tot] = inp[i][j]; } / / Build E to construct the graph for(int i = 1; i <= r; i += 1) for(int j = 0; j < siz[i]; j += 1) { / / input -> output int u = mp[inp[i][j]], v = mp[outp[i]]; to[u].push_back(Edge(v, type[i])); } } Finally, based on the directed graph, perform a depth - first search to identify strongly connected components.

[0023] The depth - first search can be performed using the Tarjan algorithm. The specific operations are as follows: For an unvisited node u, call the dfs() function to obtain the DFS traversal number dfn[u] and the backtracking value low[u] of this unvisited node; Traverse the neighbor node v of the unvisited node u. If the neighbor node is unvisited, recursively process this neighbor node v, and take the minimum value of the backtracking values of this neighbor node and the unvisited node as the new backtracking value of the unvisited node, denoted as low[u] = min(low[u], low[v]); If the neighbor node is in the stack, take the minimum value of the DFS traversal number of this neighbor node and the backtracking value of the unvisited node as the new backtracking value of the unvisited node, denoted as low[u] = min(low[u], dfn[v]); When backtracking to an unvisited node u, if the new backtracking value of the unvisited node is equal to the DFS traversal number of the unvisited node, that is, low[u] == dfn[u], then all the nodes from u to the top of the stack form a strongly connected component.

[0024] In this process, two functions are used: 1. dfs(int u): The depth-first search function is used to traverse the nodes in the graph and calculate the dfn and low values of each node through the Tarjan algorithm to find strongly connected components. The code is as follows: void dfs(int u) { dfn[u] = low[u]= ++tim; / / Assign timestamp st[++top] = u; / / Push onto the stack in[u] = 1; / / Mark as in the stack for (int i = 0; i<to[u].size(); i += 1) { int v = to[u][i].v; / / Adjacent node if (!dfn[v]) { / / Unvisited dfs(v); low[u] = min(low[u], low[v]); / / Update low[u] } else if (in[v]) { / / Already in the stack low[u] = min(low[u], dfn[v]); / / Update low[u] } } if (low[u] == dfn[u]) { / / Find strongly connected component if (st[top] != u) { / / Size of strongly connected component > 1 cnt++; / / Increase the strongly connected component number while (st[top] != u) { / / Pop nodes from the stack col[st[top]] = cnt; / / Assign number scc[cnt].push_back(st[top]); / / Record the node in[st[top]] = 0; / / Mark as not in the stack top--;} col[u] = cnt; / / Assign a number scc[cnt].push_back(u); / / Record the node } top--; / / Pop u in[u] = 0; / / Mark as not in the stack } } 2. tarjan(): The main function, traverse all unvisited nodes, and call the dfs function to find all strongly connected components. The code is as follows: void tarjan() { for (int i = 1; i <= tot; i += 1) { / / Traverse all nodes if (!dfn[i]) dfs(i); / / If not visited, call dfs } } S2: Use the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get the node set; analyze each node in the node set separately, traverse forward, represent each node as a function of external inputs and the node itself, construct a logical formula, judge the possibility of oscillation of the node according to the logical formula, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation.

[0025] After obtaining the strongly connected components, to simplify the operation and shorten the running time, a node set M needs to be obtained, which requires the minimum number of nodes in the set M and at least one node in the set M for each strongly connected component. For this purpose, the present invention uses the maximum flow - minimum cut theorem to solve this problem, transforms this problem into a maximum flow problem, and obtains the minimum vertex cover by finding the minimum cut.

[0026] Preferably, using the maximum flow - minimum cut theorem, obtain the minimum vertex cover of all strongly connected components and get the node set, specifically: Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity; after all in - points are marked as super in - points and all out - points are marked as super out - points, calculate the maximum flow value from the super in - point to the super out - point as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the node set.

[0027] After obtaining the node set M, each found node is analyzed individually and traversed forward. Since the entire circuit structure is a strongly connected component, each node can ultimately be traversed and finally return to the starting node. Each node is represented as a function of external inputs and the node itself.

[0028] For example, for node A, it can be expressed as: ; Among them, , , are all functions of external inputs of the functional form.

[0029] From this, the points in set M that may oscillate can be found, that is, if there exists a set I that satisfies: F(I) = 0, K(I) = 0, and G(I) = 1; then node A may oscillate, and conversely, node A cannot oscillate. A strongly connected component containing nodes that may oscillate may oscillate, and if not, it cannot oscillate.

[0030] From the logical expressions, the oscillation conditions of all nodes that may oscillate can be directly obtained. Taking the union of the oscillation conditions of each node gives the oscillation conditions of the entire circuit.

[0031] S3: Insert registers (such as SR type) at all nodes that may oscillate, thereby destroying all strongly connected components that may oscillate, and the purpose of destroying all strongly connected components with the fewest inserted registers can be achieved. After inserting the registers, under any external input conditions, the entire logic loop will not oscillate.

[0032] For ease of understanding, a gate example is given to specifically illustrate this analysis method. The gate example information is as follows: Module name is combLogic 0: not1 I001_001 w_000_001 w_000_002 1: and2 I001_002 w_000_002 w_003_001 w_000_003 2: and2 I001_003 w_000_004 w_003_002 w_000_005 3: and2 I001_004 w_001_006 w_000_005 w_003_003 4: and2 I001_005 w_001_007 w_003_004 w_000_003 5: and2 I001_006 w_001_008 w_000_001 w_000_004 6: nand2 I001_007 w_000_005 w_001_009 w_001_010 7: and2 I001_008 w_002_012 w_001_006 w_001_007 8: nand2 I001_009 w_000_003 w_002_013 w_002_014 9: nand2 I001_010 w_001_009 w_003_005 w_001_008 10: and2 I002_012 w_001_010 w_002_012 w_003_006 11: and2 I002_013 w_002_013 w_003_007 w_002_012 12: not1 I002_014 w_002_014 w_002_015 13: and2 I002_015 w_002_015 w_001_008 w_003_008 First, find all strongly connected components, and the results are as follows: w_000_001,w_001_008,w_001_009,w_000_005,w_001_006,w_002_012,w_002_013,w_000_003,w_000_002; w_000_001,w_001_008,w_002_015,w_002_014,w_000_003,w_000_002; w_000_003,w_001_007,w_002_012,w_001_010,w_000_005,w_000_004,w_001_008,w_002_015,w_002_014; w_000_003,w_001_007,w_002_012,w_002_013; w_000_004,w_001_008,w_001_009,w_000_005; w_000_005,w_001_006,w_002_012,w_001_010; Then, find the node set M that exists in all combinational logic loops and has the smallest number (minimum cut problem). The results are as follows: w_000_003, w_000_005; Analyze each of the found nodes (w_000_003, w_000_005) separately, and represent each node (w_000_003, w_000_005) as a function of external inputs and this node. The results are as follows: ; The oscillation condition can be directly obtained from the logical formula. For the convenience of expression, use Oscflag as the signal. When Oscflag = 1, the loop oscillates. In the above example, Oscflag is expressed as follows: ; Finally, insert registers at w_000_003 and w_000_005, that is, insert the fewest registers to break all strongly connected components.

[0033] The present invention first finds all strongly connected components in the test case through depth - first search; then uses the maximum - flow minimum - cut theorem to find the strongly connected components that cannot have continuous oscillation and the strongly connected components that may have continuous oscillation, and analyzes the oscillation conditions; finally, inserts registers at the nodes that may oscillate to break all strongly connected components that may have continuous oscillation, so as to automatically detect the unexpected combinational logic loops in digital gate circuits, analyze the trigger conditions, provide the addresses of the fewest register insertions to break the loops, and help designers discover design problems. And this method has a low time complexity, high detection efficiency, and high detection accuracy.

[0034] The present invention also provides a combinational logic loop automatic simulation system based on a 55nm process, including: Strongly - connected component identification module: used to obtain the gate instance data of the combinational logic circuit, take each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input port and the output port to obtain a directed graph; based on the directed graph, perform depth - first search to identify strongly - connected components; Analysis module: use the maximum - flow minimum - cut theorem to obtain the minimum vertex cover of all strongly - connected components, and obtain a node set; analyze each node in the node set separately, traverse forward, represent each node as a function of external inputs and this node, construct a logical formula, and judge the possibility of oscillation of this node according to the logical formula to obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation; Repair module: used to insert registers at the nodes that may oscillate to break all strongly - connected components.

[0035] Furthermore, the analysis module uses the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get a node set, specifically as follows: Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity; after all in - points are denoted as super in - points and all out - points are denoted as super out - points, calculate the maximum flow value from the super in - point to the super out - point, which is used as the capacity of the minimum cut, that is, the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the node set.

[0036] In addition, the strongly connected component identification module performs a depth - first search, which is implemented by the dfs() function and the tarjan() function.

Claims

1. An automatic simulation method for combinational logic loops based on 55nm process, characterized in that, Including the following steps: S1: Obtain the gate instance data of the combinational logic circuit. Use each input and output port as a node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph. Based on the directed graph, perform a depth-first search to identify strongly connected components; S2: Use the maximum flow-minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes. Analyze each node in the set of nodes separately, traverse forward, represent each node as a function of external inputs and the node, construct a logical formula, judge the possibility of oscillation of the node according to the logical formula, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, and take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation; S3: Insert registers at the nodes that may oscillate to break all strongly connected components.

2. The automatic simulation method for a combinational logic loop based on a 55nm process according to claim 1, characterized in that In the above S2, using the maximum flow-minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and obtain a set of nodes is specifically as follows: Split each node of the strongly connected component into an in-node and an out-node, set the capacity between the in-node and the out-node split from the same node to 1, and set the capacity between nodes to positive infinity. After recording all in-nodes as super in-nodes and all out-nodes as super out-nodes, calculate the maximum flow value from the super in-nodes to the super out-nodes as the capacity of the minimum cut, which is the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the set of nodes.

3. The automatic simulation method for combinational logic loops based on 55nm process according to claim 1, wherein The directed graph obtained in the above S1 is implemented through the BuildGraph() function, specifically as follows: After recording the name of each port and the gate number it belongs to, assign a unique number to each input and output port as the node of the graph, and construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph.

4. The automatic simulation method for combinational logic loops based on 55nm process according to claim 1, characterized in that, In the above S1, based on the directed graph, perform a depth-first search to identify strongly connected components, specifically as follows: For unvisited nodes, call the dfs() function to obtain the DFS traversal sequence number and backtracking value of the unvisited node; Traverse the neighbor nodes of the unvisited node. If the neighbor node is not visited, recursively process the neighbor node, and take the minimum value of the backtracking value of the neighbor node and the unvisited node as the new backtracking value of the unvisited node; If the neighbor node is in the stack, take the minimum value of the DFS traversal sequence number of the neighbor node and the backtracking value of the unvisited node as the new backtracking value of the unvisited node; When backtracking to an unvisited node, if the new backtracking value of the unvisited node is equal to the DFS traversal sequence number of the unvisited node, all nodes from the node to the top of the stack form a strongly connected component.

5. The automatic simulation method for combinational logic loops based on 55nm process according to claim 3, characterized in that, The recording of the name of each port and the gate number it belongs to is implemented through the port and mpbh arrays; the connection relationship between the input ports and the output ports is recorded using the to array and the Edge structure.

6. A combinational logic loop automatic simulation system based on 55nm process, characterized in that, Including: Strongly connected component identification module: used to obtain the gate instance data of the combinational logic circuit, use each input and output port as a node of the graph, construct the edges of the graph according to the connection relationship between the input ports and the output ports to obtain a directed graph, and perform a depth-first search based on the directed graph to identify strongly connected components; Analysis module: Using the maximum flow - minimum cut theorem, obtain the minimum vertex cover of all strongly connected components and get the node set; Analyze each node in the node set individually, traverse forward, represent each node as a function of external inputs and the node itself, construct a logical formula, and based on the logical formula, judge the possibility of oscillation of the node, obtain the nodes that may oscillate and the oscillation conditions of the nodes that may oscillate, take the union of the oscillation conditions of all nodes that may oscillate to obtain the external input conditions for oscillation. Repair module: Used to insert registers at the nodes that may oscillate to destroy all strongly connected components.

7. The automatic simulation system for combinational logic loops based on the 55nm process according to claim 6, characterized in that, The analysis module uses the maximum flow - minimum cut theorem to obtain the minimum vertex cover of all strongly connected components and get the node set, specifically: Split each node of the strongly connected component into an in - point and an out - point, set the capacity between the in - point and the out - point split from the same node to 1, and set the capacity between nodes to positive infinity; After marking all in - points as super in - points and all out - points as super out - points, calculate the maximum flow value from the super in - point to the super out - point, which is used as the capacity of the minimum cut, that is, the minimum vertex cover, and the corresponding nodes of the minimum vertex cover are used as the node set.

8. The automatic simulation system for combinational logic loops based on 55nm process according to claim 6, characterized in that, The strongly connected component identification module performs a depth - first search, which is implemented by the dfs() function and the tarjan() function.