Chip Interposer Routing Method and Device Based on Integer Linear Programming

Abstract

The embodiments of the present disclosure disclose a chip interposer wiring method and device based on integer linear programming. A specific implementation of the method includes: determining the current chip bump real coordinate set based on the current chip physical information, wherein the current chip physical information includes: the current chip center coordinate information, the current rotation angle information and the current rotation center coordinate information; determining the target bump for each key bump in the key bump set based on the current chip bump real coordinate set to generate a target bump and obtain a target bump set; generating a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target bump based on the target bump set; generating a fan-out edge allocation bump set based on the candidate edge set and the fan-out edge set; and performing inter-chip wiring path allocation on the fan-out edge wiring to generate an inter-chip fan-out edge wiring allocation path. This implementation reduces the time required to complete the interposer wiring, and improves the wiring quality of multi-chip interconnection.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of computer technology, and more particularly to a chip interposer wiring method and apparatus based on integer linear programming. Background Art

[0002] Chip interposer routing based on integer linear programming is a technique that automatically finds the optimal inter-chip pin routing based on the interconnection relationship between the pins, within given process constraints. Currently, a common approach is to abstract the routing plane within the silicon interposer as a grid-based rectangular plane. Based on this, a maze routing algorithm is used to generate a series of potential routing paths. Subsequently, linear programming methods and continuous iterative optimization are used to ultimately determine the routing solution that uses the fewest layers.

[0003] The maze routing algorithm has a large search space for interposer routing, resulting in a long time required. The proposed existing routing framework is limited to a single horizontal track allocation, resulting in low routing quality for multi-chip interconnects.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0005] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] Some embodiments of the present disclosure propose a chip interposer wiring method and apparatus based on integer linear programming to solve the technical problems mentioned in the above background technology section.

[0007] In a first aspect, some embodiments of the present disclosure provide a chip interposer wiring method based on integer linear programming, the method comprising: determining a real coordinate set of a current chip bump according to current chip physical information, wherein the current chip physical information comprises: current chip center coordinate information, current rotation angle information and current rotation center coordinate information; traversing a plurality of external chip physical information to generate a traversed external chip physical information set; determining a key bump set between the current chip physical information and the traversed external chip physical information set, wherein the key bump set is a set of bumps that are mutually related to each chip bump in the traversed external chip physical information set. a set of key convex points connected; according to the real coordinate set of the convex points of the current chip, a target convex point is determined for each key convex point in the key convex point set to generate a target convex point and obtain a target convex point set; according to the target convex point set, a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target convex point are generated; according to the candidate edge set and the fan-out edge set, a fan-out edge allocation convex point set is generated; according to the size information of the current chip physical information and the fan-out edge allocation convex point set, a fan-out edge wiring is determined, wherein the fan-out edge wiring is the wiring from the convex point to the fan-out edge; and inter-chip wiring paths are allocated for the fan-out edge wiring to generate inter-chip fan-out edge wiring allocation paths.

[0008] In a second aspect, some embodiments of the present disclosure provide a chip interposer wiring device based on integer linear programming, the device comprising: a first determination unit, configured to determine the real coordinate set of the current chip bumps according to the current chip physical information, wherein the above-mentioned current chip physical information comprises: current chip center coordinate information, current rotation angle information and current rotation center coordinate information; a traversal unit, configured to traverse a plurality of external chip physical information to generate a traversed external chip physical information set; a second determination unit, configured to determine the key bump set of the above-mentioned current chip physical information and the above-mentioned traversed external chip physical information set, wherein the above-mentioned key bump set is the key bump set in the traversed external chip physical information set that is interconnected with each chip bump in the current chip physical information; a third determination unit, configured to determine the key bump set of the above-mentioned current chip physical information and the above-mentioned traversed external chip physical information set; The determining unit is configured to determine the target bulge for each key bulge in the key bulge set according to the real coordinate set of the current chip bulge, so as to generate the target bulge and obtain the target bulge set; the first generating unit is configured to generate the fan-out edge set corresponding to the current chip physical information and the candidate edge set of the target bulge according to the target bulge set; the second generating unit is configured to generate the fan-out edge allocation bulge set according to the candidate edge set and the fan-out edge set; the fourth determining unit is configured to determine the fan-out edge wiring according to the size information of the current chip physical information and the fan-out edge allocation bulge set, wherein the fan-out edge wiring is the wiring from the bulge to the fan-out edge; the allocating unit is configured to perform inter-chip wiring path allocation on the fan-out edge wiring to generate an inter-chip fan-out edge wiring allocation path.

[0009] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0010] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation of the first aspect is implemented.

[0011] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the chip interposer wiring method based on integer linear programming of some embodiments of the present disclosure, the time required to complete the interposer wiring is reduced, and the wiring quality of multi-chip interconnection is improved. Specifically, the reason for the low wiring quality of multi-chip interconnection is that the maze wiring algorithm has a large search space for interposer wiring, resulting in a long time required, and the proposed existing wiring framework is limited to a single horizontal track allocation, resulting in low wiring quality of multi-chip interconnection. Based on this, the chip interposer wiring method based on integer linear programming of some embodiments of the present disclosure involves 2.5D interposer wiring, which can automatically find a better wiring scheme for inter-chip pins under given process constraints based on the interconnection relationship between the pins of the chips. The interposer wiring is usually made by installing multiple chips side by side on a silicon interposer. A silicon interposer is introduced as an interface between the chip and the package, which is used to connect the bumps on multiple chips to achieve signal transmission and power distribution. By dividing 2.5D interposer routing into three phases: fan-out edge allocation for intra-chip bump signals, routing from intra-chip bumps to fan-out edges, and assigning fan-out edge routing patterns between chips, the team achieved a high-quality routing solution by completing large-scale multi-chip interconnects on the interposer in a shorter timeframe. This reduced interposer routing time and improved the routing quality of multi-chip interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0013] Figure 1 is a flow chart of some embodiments of a chip interposer routing method based on integer linear programming according to the present disclosure;

[0014] Figure 2 is a schematic structural diagram of some embodiments of a chip interposer wiring device based on integer linear programming according to the present disclosure;

[0015] Figure 3 is a schematic structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure;

[0016] Figure 4 is a target bump position of some embodiments of the chip interposer routing apparatus based on integer linear programming according to the present disclosure;

[0017] Figure 5 is a fan-out edge allocation result diagram of some embodiments of the chip interposer routing device based on integer linear programming according to the present disclosure;

[0018] Figure 6 is a track distribution diagram of some embodiments of the chip interposer routing device based on integer linear programming according to the present disclosure;

[0019] Figure 7 is a routing diagram from a bump to a fan-out area according to some embodiments of the chip interposer routing apparatus based on integer linear programming of the present disclosure;

[0020] Figure 8 1 is a wiring diagram of inter-chip fan-out edges according to some embodiments of the chip interposer wiring apparatus based on integer linear programming of the present disclosure. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0022] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0023] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0024] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0025] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0026] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0027] Figure 1 This is a process 100 of some embodiments of a chip interposer routing method based on integer linear programming according to some embodiments of the present disclosure. The chip interposer routing method based on integer linear programming includes the following steps:

[0028] Step 101: Determine the real coordinate set of the bumps of the current chip based on the physical information of the current chip.

[0029] In some embodiments, the execution body of the chip interposer wiring method based on integer linear programming (eg Figure 1 The computing device shown in FIG. 1 can determine the real coordinate set of the current chip bumps based on the current chip physical information, wherein the current chip physical information includes: the current chip center coordinate information, the current rotation angle information, and the current rotation center coordinate information.

[0030] Here, the current chip center coordinate information may refer to the current chip center coordinate information. For example, the current chip center coordinate information may refer to The above current rotation angle information may refer to the rotation angle information of the current chip. For example, the above current rotation angle information may refer to The above-mentioned current rotation center coordinate information may refer to the rotation center coordinate information of the current chip. For example, the above-mentioned current rotation center coordinate information may refer to The above subscript Indicates the center of the chip. Indicates the rotation center. The above current chip physical information contains multiple chip bumps.

[0031] As an example, the execution subject can be

[0032] According to the current chip physical information, determine the current chip bump real coordinate set. Indicates the x-axis coordinate of the current chip center coordinate information. Indicates the y-axis coordinate of the current chip center coordinate information. Indicates the x-axis coordinate of the actual coordinate of the current chip bump. The y-axis coordinate of the actual coordinate of the current chip bump. Indicates the real coordinates. The above mentioned real coordinates of the current chip bump change with the current rotation angle information. .

[0033] Step 102: traverse multiple external chip physical information to generate a traversed external chip physical information set.

[0034] In some embodiments, the execution entity may traverse multiple external chip physical information to generate a traversed external chip physical information set.

[0035] Here, the plurality of external chip physical information may refer to a plurality of external chip physical information at different locations from the current chip physical information. The external chip physical information in the plurality of external chip physical information may include: external chip center coordinate information, external rotation angle information, and external rotation center coordinate information.

[0036] As an example, the execution subject may traverse each external chip physical information in the plurality of external chip physical information to generate traversed external chip physical information and obtain a traversed external chip physical information set.

[0037] Step 103 : determining a key salient point set between the current chip physical information and the traversed external chip physical information set.

[0038] In some embodiments, the above-mentioned execution entity can determine the key bump set of the above-mentioned current chip physical information and the above-mentioned traversed external chip physical information set, wherein the above-mentioned key bump set is the key bump set in the traversed external chip physical information set that is interconnected with each chip bump in the current chip physical information.

[0039] Here, the key convex point set may refer to a set of convex points where the current chip physical information needs to establish a connection with the traversed external chip physical information set.

[0040] Step 104 , determining a target convex point for each key convex point in the key convex point set according to the current chip convex point real coordinate set, to generate a target convex point and obtain a target convex point set.

[0041] In some embodiments, the execution subject may determine a target convex point for each key convex point in the key convex point set according to the current chip convex point real coordinate set to generate a target convex point and obtain a target convex point set.

[0042] Here, the target bump refers to a bump on the chip corresponding to the traversed external chip physical information of the traversed external chip physical information set that has an interconnected relationship with the current bump corresponding to the current chip bump real coordinate set.

[0043] As an example, the execution entity may traverse each key salient point in the key salient point set to generate traversed key salient points, thereby obtaining a traversed key salient point set. Then, for each traversed key salient point in the traversed key salient point set, a target salient point is determined based on interconnection information to generate a target salient point, thereby obtaining a target salient point set. The interconnection information may refer to connection information between the key salient point and the target salient point.

[0044] Step 105 : Generate a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target bumps according to the target bump set.

[0045] In some embodiments, the execution entity may generate a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target bumps according to the target bump set.

[0046] Here, the fan-out edges in the above-mentioned fan-out edge set may refer to the four sides of the chip (for example, the top, bottom, left, and right sides), and the above-mentioned fan-out edge set is a set of edges used to lead out signals. The above-mentioned sides are pre-defined and used to lead out the bump signals inside the chip to the chip boundary. The candidate edges in the above-mentioned candidate edge set refer to the set of possible fan-out edges selected by a key bump when the relative position of the chip where the target bump is located is not in the four positive directions (for example, the top, bottom, left, and right sides). Figure 4 As shown. For relative positions Directly assigned fan-out edges (e.g., top, bottom, left, right), for relative positions at , then generate the corresponding candidate edges (for example, diagonal corners).

[0047] Optionally, the execution entity may generate a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target bumps according to the target bump set through the following steps:

[0048] The first step is to determine the relative position of the chip corresponding to each target bump in the target bump set and the physical information of the current chip to generate a relative position and obtain a relative position set.

[0049] In the second step, in response to determining that there is a relative position in the relative position set that meets a preset first direction condition, a fan-out edge set corresponding to the current chip physical information is allocated.

[0050] Here, the above-mentioned preset first direction condition may refer to directly above, directly below, directly to the left or directly to the right.

[0051] In the third step, in response to determining that there is a relative position in the relative position set that meets the preset second direction condition, a candidate edge set of the target bump corresponding to the current chip physical information is generated.

[0052] The above-mentioned preset second direction condition may refer to a diagonal direction.

[0053] Step 106: Generate a fan-out edge allocation salient point set based on the candidate edge set and the fan-out edge set.

[0054] In some embodiments, the execution entity may generate a fan-out edge allocation salient point set based on the candidate edge set and the fan-out edge set.

[0055] Optionally, the execution entity may generate a fan-out edge allocation salient point set according to the candidate edge set and the fan-out edge set through the following steps:

[0056] In the first step, based on the candidate edge set, a linear programming variable and a corresponding salient point constraint are created for each key salient point in the key salient point set, resulting in a linear programming variable set and a corresponding salient point constraint set. The linear programming variables in the linear programming variable set represent the assignment of each salient point to a corresponding edge, and the salient point constraint in the corresponding salient point constraint set represents the assignment of a candidate edge in the candidate edge set.

[0057] Here, the chip set corresponding to the above key bump set can refer to . The above It can represent the chip. The subscript n represents the serial number. The above key convex point set is ,in and Do not belong to the same chip. The relative position direction variables are Among them, the fan-out edge set of the chip is The candidate edge set of the convex point is , , , . Bump The variables assigned to the edges are . The above For the edge. is the horizontal coordinate of the key salient point. is the vertical coordinate of the key salient point. It is a binary variable, and the value 1 indicates a convex point Assign to edge , a value of 0 means no allocation. The relative position is Select a candidate edge from the convex point The relative position is located at The edge corresponding to the direction of the convex point selection The subscript k represents the number of the fan-out edge. The subscript m represents the number of the candidate edge.

[0058] In the second step, based on the linear programming variable set, the corresponding salient point constraint set and the fan-out edge set, the fan-out edge allocation salient point of each key salient point in the key salient point set is determined to generate the fan-out edge allocation salient point and obtain the fan-out edge allocation salient point set.

[0059] As an example, the execution subject may determine the fan-out edge allocation convex point of each key convex point in the key convex point set according to the linear programming variable set, the corresponding convex point constraint set and the fan-out edge set through an objective function to generate a fan-out edge allocation convex point and obtain a fan-out edge allocation convex point set. The objective function may refer to in, . The above Indicates the fan-out edge allocation convex point. The fan-out edge allocation result is as follows Figure 5 shown.

[0060] Step 107 : determining the fan-out edge routing according to the size information of the current chip physical information and the fan-out edge allocation bump set.

[0061] In some embodiments, the execution entity may determine the fan-out edge routing based on the size information of the current chip physical information and the fan-out edge allocation bump set, wherein the fan-out edge routing is routing from the bump to the fan-out edge.

[0062] Here, the size information of the current chip physical information may refer to the width, height, line width and line spacing of the current chip physical information.

[0063] As an example, after determining the fan-out edge of the bump, the above-mentioned execution entity can construct the vertical and horizontal wiring track system of each layer based on the line width and line spacing of each layer. For each bump led out from the fan-out edge of the chip, the track resources are optimized based on the linear programming method. If the layer is insufficient, the linear programming allocation solution is performed on the remaining bumps in other layers.

[0064] Optionally, the execution subject may determine the fan-out edge routing according to the size information of the current chip physical information and the fan-out edge allocation bump set through the following steps:

[0065] In the first step, according to the size information of the current chip physical information, the horizontal track positions and vertical track positions of different wiring layers are determined to obtain a horizontal track position set and a vertical track position set.

[0066] Here, the horizontal track position set is . represents the y coordinate of the horizontal track. The vertical track position set is, . Indicates the x-coordinate of the vertical track. The subscript h indicates horizontal. The subscript v indicates vertical.

[0067] In the second step, routing tracks are constructed for the horizontal track position set and the vertical track position set to generate interposer routing tracks.

[0068] Here, the interposer routing tracks are as follows Figure 6 shown.

[0069] In the third step, for each current track in the interposer routing track, the following processing steps are performed:

[0070] The first sub-step is to determine the fan-out edge salient point set according to the above current track.

[0071] Here, the above fan-out edge convex point set is The range of subscript n is 1, 3, 5, 7.

[0072] Optionally, the execution entity may determine the fan-out edge salient point set according to the current track through the following steps:

[0073] Sub-step one: in response to determining that the current track is a horizontal track, constraining and adding horizontal salient points in the fan-out edge allocation salient point set to obtain a post-addition horizontal salient point set.

[0074] Here, the above constraint can mean that each salient point is assigned to at most one track, i.e. , and the convex points on the same fan-out edge cannot be assigned to the same track, that is, .

[0075] Sub-step two: in response to determining that the added horizontal salient points in the added horizontal salient point set are located in the same current track, constraining the coordinates of the added horizontal salient points in the added horizontal salient point set to obtain a constrained horizontal salient point set.

[0076] As an example, the above execution subject is for the horizontal fan-out edge and The convex points in the above-mentioned added horizontal convex point set are located in the same current track, then The x value of the convex point coordinate is greater than The x value of the convex point in . ,in The x value of the coordinate is less than The x-value of the coordinate.

[0077] Sub-step three: in response to determining that the current track is a vertical track, constraining and adding vertical salient points in the fan-out edge allocation salient point set to obtain a vertical salient point set after adding.

[0078] Sub-step four: in response to determining that the added vertical salient points in the added vertical salient point set are located in the same current track, constraining the coordinates of the added vertical salient points in the added vertical salient point set to obtain a constrained vertical salient point set.

[0079] As an example, the above execution subject is for vertical fan-out edge and The convex points in the above-mentioned added vertical convex point set are located in the same current track, then The x value of the convex point coordinate is greater than The x value of the convex point in . ,in, The y value of the coordinate is less than The y value of the coordinate.

[0080] In sub-step five, the above-mentioned horizontal convex point set after addition, the horizontal convex point set after constraint, the vertical convex point set after addition, and the vertical convex point set after constraint are determined as the fan-out edge convex point set.

[0081] In the second sub-step, an optimization target is created for the wiring layer where the current track is located, so as to allocate the oblique edge bumps in the fan-out edge allocation bump set to obtain an allocated bump set.

[0082] Here, the above optimization goal can refer to .

[0083] In the third sub-step, the fan-out edge convex point set and the allocated convex point set are determined as the allocated convex point set.

[0084] In a fourth sub-step, in response to determining that the number of the allocated salient point sets is less than the number of salient points in the current track, continuing to perform the above processing steps.

[0085] In the fourth step, a path is generated according to the wiring pattern, and each assigned convex point set is connected by fan-out points to obtain fan-out edge wiring.

[0086] Here, the routing from the bump to the fan-out area is as follows Figure 7 shown.

[0087] Step 108 : performing inter-chip routing path allocation on the fan-out edge routing to generate inter-chip fan-out edge routing allocation paths.

[0088] In some embodiments, the execution entity may allocate inter-chip wiring paths for the fan-out edge wiring to generate inter-chip fan-out edge wiring allocation paths.

[0089] As an example, the execution entity may first generate paths for each fan-out point pair between chips according to a wiring pattern, where the wiring pattern is defined as a straight diagonal line connecting two fan-out points, and then complete wiring according to these paths according to physical constraints.

[0090] Optionally, the execution entity may allocate inter-chip wiring paths for the fan-out edge wiring through the following steps to generate inter-chip fan-out edge wiring allocation paths:

[0091] In the first step, the path intersection relationship of the fan-out edge routing is determined to obtain a fan-out edge routing path intersection relationship set.

[0092] Here, the fan-out edge routing path intersection relationship set .in, Represents two fan-out points of interconnection. Among them, the path is assigned to the variable It is a binary variable, and the value is 1. The wiring mode is assigned, and a value of 0 means no assignment.

[0093] In the second step, in response to determining that the fan-out edge routing path intersection relationship in the fan-out edge routing path intersection relationship set represents a path intersection relationship, constraint addition is performed on the fan-out edge routing representing the path intersection relationship to generate a post-addition fan-out edge routing path.

[0094] Here, the above constraint addition can refer to different fan-out points The wiring mode of the intersection, if there is a cross, the two fan-out points of the intersection are Only one can be assigned. .

[0095] In the third step, in response to determining that the fan-out edge routing path intersection relationship in the fan-out edge routing path intersection relationship set represents a path non-intersection relationship, the fan-out edge routing representing the path non-intersection relationship is determined as a fan-out edge routing path.

[0096] As an example, the above execution subject creates a linear programming optimization objective for the current layer, maximizing the sum of variables to maximize the number of track allocations in the current layer. The linear programming optimization objective of the current layer is .

[0097] In the fourth step, the additional rear fan-out edge routing path and the additional rear fan-out edge routing path are determined as inter-chip fan-out edge routing allocation paths.

[0098] The fan-out edge routing distribution path between chips is as follows Figure 8 shown.

[0099] Further references Figure 2 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a chip interposer wiring device based on integer linear programming. These device embodiments are similar to Figure 2 Corresponding to the method embodiments shown, the chip interposer wiring device based on integer linear programming can be specifically applied to various electronic devices.

[0100] like Figure 2As shown, some embodiments of the chip interposer wiring device 200 based on integer linear programming include: a first determining unit 201, a traversing unit 202, a second determining unit 203, a third determining unit 204, a first generating unit 205, a second generating unit 206, a fourth determining unit 207 and an allocating unit 208. The first determining unit 201 is configured to determine the real coordinate set of the current chip bumps according to the current chip physical information, wherein the current chip physical information includes: the current chip center coordinate information, the current rotation angle information and the current rotation center coordinate information; the traversing unit 202 is configured to traverse a plurality of external chip physical information to generate a traversed external chip physical information set; the second determining unit 203 is configured to determine the key bump set of the current chip physical information and the traversed external chip physical information set, wherein the key bump set is the key bump set in the traversed external chip physical information set that is interconnected with each chip bump in the current chip physical information; the third determining unit 204 is configured to determine the real bump set of the current chip bumps according to the real bump set of the current chip Coordinate set, target convex point determination is performed on each key convex point in the above key convex point set to generate a target convex point and obtain a target convex point set; a first generating unit 205 is configured to generate a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target convex point according to the above target convex point set; a second generating unit 206 is configured to generate a fan-out edge allocation convex point set according to the above candidate edge set and the above fan-out edge set; a fourth determining unit 207 is configured to determine the fan-out edge wiring according to the size information of the above current chip physical information and the above fan-out edge allocation convex point set, wherein the above fan-out edge wiring is the wiring from the convex point to the fan-out edge; an allocating unit 208 is configured to perform inter-chip wiring path allocation on the above fan-out edge wiring to generate an inter-chip fan-out edge wiring allocation path.

[0101] It can be understood that the various units recorded in the chip interposer wiring device 200 based on integer linear programming are similar to those in the reference Figure 1 Therefore, the operations, features and beneficial effects described above for the method are also applicable to the chip interposer wiring device 200 based on integer linear programming and the units included therein, and will not be described in detail here.

[0102] Reference below Figure 3 , which shows a structural schematic diagram of an electronic device (eg, a computing device) suitable for implementing some embodiments of the present disclosure. Figure 3 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 3As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, can enable the processor to execute any of the above-mentioned chip interposer wiring methods based on integer linear programming. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, can enable the processor to execute any of the above-mentioned chip interposer wiring methods based on integer linear programming. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0103] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0104] In one embodiment, the processor is used to run a computer program stored in a memory to implement the following steps: determining the real coordinate set of the current chip bumps based on the current chip physical information, wherein the current chip physical information includes: current chip center coordinate information, current rotation angle information and current rotation center coordinate information; traversing multiple external chip physical information to generate a traversed external chip physical information set; determining a key bump set between the current chip physical information and the traversed external chip physical information set, wherein the key bump set is the bumps in the traversed external chip physical information set that are interconnected with each other in the current chip physical information. a set of key convex points connected to the chip; according to the real coordinate set of the convex points of the current chip, a target convex point is determined for each key convex point in the key convex point set to generate a target convex point and obtain a target convex point set; according to the target convex point set, a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target convex point are generated; according to the candidate edge set and the fan-out edge set, a fan-out edge allocation convex point set is generated; according to the size information of the current chip physical information and the fan-out edge allocation convex point set, a fan-out edge wiring is determined, wherein the fan-out edge wiring is the wiring from the convex point to the fan-out edge; and inter-chip wiring paths are allocated for the fan-out edge wiring to generate inter-chip fan-out edge wiring allocation paths.

[0105] An embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the various embodiments of the chip interposer wiring method based on integer linear programming described above in the present disclosure.

[0106] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.

[0107] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0108] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A chip interposer wiring method based on integer linear programming, characterized in that: include: Determine the real coordinate set of the current chip bumps according to the current chip physical information, wherein the current chip physical information includes: current chip center coordinate information, current rotation angle information and current rotation center coordinate information; Traversing multiple external chip physical information to generate a traversed external chip physical information set; Determine a key bump set between the current chip physical information and the traversed external chip physical information set, wherein the key bump set is a key bump set in the traversed external chip physical information set that is interconnected with each chip bump in the current chip physical information; According to the current chip convex point real coordinate set, determining a target convex point for each key convex point in the key convex point set to generate a target convex point and obtain a target convex point set; Generate a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target salient points according to the target salient point set; Generate a fan-out edge allocation salient point set according to the candidate edge set and the fan-out edge set; Determine fan-out edge routing according to the size information of the current chip physical information and the fan-out edge allocation bump set, wherein the fan-out edge routing is routing from the bump to the fan-out edge; Inter-chip wiring paths are allocated for the fan-out edge wiring to generate inter-chip fan-out edge wiring allocation paths.

2. The method according to claim 1, characterized in that Generating a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target salient points according to the target salient point set includes: Determine the relative position of the chip corresponding to each target bump in the target bump set and the physical information of the current chip to generate a relative position and obtain a relative position set; In response to determining that a relative position in the relative position set satisfies a preset first direction condition, allocating a fan-out edge set corresponding to the current chip physical information; In response to determining that there is a relative position in the relative position set that satisfies a preset second direction condition, a candidate edge set of the target bump corresponding to the current chip physical information is generated.

3. The method according to claim 1, characterized in that Generating a fan-out edge allocation salient point set according to the candidate edge set and the fan-out edge set includes: According to the candidate edge set, a linear programming variable and a corresponding salient point constraint are created for each key salient point in the key salient point set to obtain a linear programming variable set and a corresponding salient point constraint set, wherein the linear programming variable in the linear programming variable set represents the assignment of each salient point to the corresponding edge, and the salient point constraint in the corresponding salient point constraint set represents the assignment of a candidate edge in the candidate edge set; According to the linear programming variable set, the corresponding salient point constraint set and the fan-out edge set, a fan-out edge allocation salient point is determined for each key salient point in the key salient point set to generate a fan-out edge allocation salient point and obtain a fan-out edge allocation salient point set.

4. The method according to claim 1, wherein The performing inter-chip routing path allocation on the fan-out edge routing to generate an inter-chip fan-out edge routing allocation path includes: Determining a path intersection relationship of the fan-out edge routing to obtain a fan-out edge routing path intersection relationship set; In response to determining that the fan-out edge routing path intersection relationship in the fan-out edge routing path intersection relationship set represents a path intersection relationship, constraint addition is performed on the fan-out edge routing representing the path intersection relationship to generate a post-addition fan-out edge routing path; In response to determining that the fan-out edge routing path intersection relationship in the fan-out edge routing path intersection relationship set represents a path non-intersection relationship, determining the fan-out edge routing representing the path non-intersection relationship as a fan-out edge routing path; The additional rear fan-out edge routing path and the additional rear fan-out edge routing path are determined as inter-chip fan-out edge routing allocation paths.

5. The method according to claim 1, wherein The determining of the fan-out edge routing according to the size information of the current chip physical information and the fan-out edge allocation bump set includes: Determining horizontal track positions and vertical track positions of different wiring layers according to the size information of the current chip physical information, and obtaining a horizontal track position set and a vertical track position set; Performing routing track construction on the horizontal track position set and the vertical track position set to generate interposer routing tracks; For each current track in the interposer routing track, the following processing steps are performed: Determine a fan-out edge salient point set according to the current track; Creating an optimization target for the wiring layer where the current track is located, so as to allocate the oblique edge bumps in the fan-out edge allocation bump set to obtain an allocated bump set; Determine the fan-out edge convex point set and the allocated convex point set as allocated convex point sets; In response to determining that the number of the allocated salient point sets is less than the number of salient points in the current track, continuing to perform the processing steps; Generate a path according to the wiring pattern, connect the obtained assigned convex point sets to fan-out points, and obtain fan-out edge wiring.

6. The method according to claim 5, characterized in that Determining a fan-out edge salient point set according to the current track includes: In response to determining that the current track is a horizontal track, constraining and adding horizontal salient points in the fan-out edge allocation salient point set to obtain an added horizontal salient point set; In response to determining that the added horizontal salient points in the added horizontal salient point set are located in the same current track, constraining the coordinates of the added horizontal salient points in the added horizontal salient point set to obtain a constrained horizontal salient point set; In response to determining that the current track is a vertical track, constraining and adding vertical salient points in the fan-out edge allocation salient point set to obtain an added vertical salient point set; In response to determining that the added vertical convex points in the added vertical convex point set are located in the same current track, constraining the coordinates of the added vertical convex points in the added vertical convex point set to obtain a constrained vertical convex point set; The added horizontal convex point set, the constrained horizontal convex point set, the added vertical convex point set and the constrained vertical convex point set are determined as fan-out edge convex point sets.

7. A chip interposer wiring device based on integer linear programming, characterized in that: include: The first determining unit is configured to determine a real coordinate set of bumps of the current chip according to the current chip physical information, wherein the current chip physical information includes: current chip center coordinate information, current rotation angle information and current rotation center coordinate information; a traversal unit configured to traverse a plurality of external chip physical information to generate a traversed external chip physical information set; A second determining unit is configured to determine a key bump set between the current chip physical information and the traversed external chip physical information set, wherein the key bump set is a key bump set in the traversed external chip physical information set that is interconnected with each chip bump in the current chip physical information; A third determining unit is configured to perform target convex point determination on each key convex point in the key convex point set according to the current chip convex point real coordinate set to generate a target convex point and obtain a target convex point set; A first generating unit is configured to generate a fan-out edge set corresponding to the current chip physical information and a candidate edge set of the target bump according to the target bump set; A second generating unit is configured to generate a fan-out edge allocation salient point set according to the candidate edge set and the fan-out edge set; a fourth determining unit configured to determine a fan-out edge routing according to size information of the current chip physical information and the fan-out edge allocation bump set, wherein the fan-out edge routing is routing from a bump to a fan-out edge; The allocating unit is configured to allocate inter-chip wiring paths for the fan-out edge wiring to generate inter-chip fan-out edge wiring allocation paths.

8. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 6.

9. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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