Complete K-SAT solver based on incremental update technology

Abstract

The invention provides a completeness K-SAT solver based on an incremental updating technology, and the solver comprises an incremental updater, and the incremental updater comprises an assignment mask unit which is used for adjusting the current assignment of a target character based on the current working mode of the assignment mask unit, and obtaining the adjusted assignment information; the register file is used for storing historical assignment information of characters contained in each clause in the Boolean formula; one end of the updating logic unit is connected with the assignment mask unit, the other end of the updating logic unit is connected with the register file, and the updating logic unit is used for determining character assignment information based on the historical assignment information and the adjusted assignment information; and the assignment mask unit is also used for outputting the character assignment information, so that the solver carries out complete K-SAT solving based on the character assignment information. According to the method, efficient storage and management of historical assignment information are realized on the hardware level, and hardware resource consumption and solution delay caused by frequent storage and backtracking in completeness analysis are effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of SAT problem solving, and particularly to a complete K-SAT solver based on incremental update technology. Background Art

[0002] The Boolean satisfiability problem (K-SAT, K≥3) is one of the most representative NP (Non-deterministic Polynomially) complete problems in computer science. Its core task is to determine whether there exists a truth assignment of a set of Boolean variables such that all clauses represented in conjunctive normal form (CNF) are satisfied.

[0003] However, most of the existing K-SAT solvers are incomplete solvers at present, which can only handle the satisfiable (SAT) cases and cannot verify the unsatisfiable (UNSAT) cases. This limitation significantly reduces the applicability of the solver in practical applications, especially in complex scenarios where it is necessary to verify whether F(x) has a solution.

[0004] Moreover, when implementing the hardware acceleration design for complete analysis, the storage of historical assignment information requires a large amount of storage resources, and frequent access and update operations will significantly increase the energy consumption of the hardware. Therefore, how to optimize the storage structure while supporting complete analysis and reduce the hardware overhead and energy consumption is an urgent problem to be solved in the hardware design of complete solvers. Summary of the Invention

[0005] The present invention provides a complete K-SAT solver based on incremental update technology, which is used to optimize the storage structure while supporting complete analysis and reduce the hardware overhead and energy consumption.

[0006] The present invention provides a complete K-SAT solver based on incremental update technology. The complete K-SAT solver includes an incremental updater, and the incremental updater includes: An assignment mask unit, which is used to adjust the current assignment of the target literal based on the current working mode of the assignment mask unit to obtain the adjusted assignment information; A register file, which is used to store the historical assignment information of the literals included in each clause in the Boolean formula; An update logic unit, one end of which is connected to the assignment mask unit and the other end of which is connected to the register file, and is used to determine the literal assignment information based on the historical assignment information and the adjusted assignment information; The assignment mask unit is further configured to output the literal assignment information, so that the complete K-SAT solver performs complete K-SAT solving based on the literal assignment information.

[0007] According to a complete K-SAT solver based on incremental update technology provided by the present invention, the assignment mask unit is specifically configured to: When the current working mode of the assignment mask unit is the conflict mode, obtain the backtracking depth information represented by binary coding; Based on the backtracking depth information, select the corresponding literal position, and determine the literal at the literal position as the target literal; Set all the corresponding literals of the variable corresponding to the target literal to 1.

[0008] According to a complete K-SAT solver based on incremental update technology provided by the present invention, the assignment mask unit is specifically configured to: When the current working mode of the assignment mask unit is not the conflict mode, obtain the output result of the clause and literal status lookup table; the output result is the sum of the unassigned literals included in each clause in the Boolean formula; Based on the current working mode of the assignment mask unit, determine the target literal to be adjusted, and adjust the current assignment of the target literal.

[0009] According to a complete K-SAT solver based on incremental update technology provided by the present invention, the assignment mask unit is specifically configured to: If the current working mode of the assignment mask unit is the propagation mode, determine the literal corresponding to the output result of the clause and literal status lookup table as the target literal; Perform a flip operation on the current assignment of the target literal.

[0010] According to a complete K-SAT solver based on incremental update technology provided by the present invention, the assignment mask unit is specifically configured to: If the current working mode of the assignment mask unit is the heuristic assignment mode, select an unpropagated literal as the target literal; Perform a flip operation on the current assignment of the target literal.

[0011] According to a complete K-SAT solver based on incremental update technology provided by the present invention, the complete K-SAT solver further includes a clause analyzer connected to the assignment mask unit, and the clause analyzer is used to: Continuously detect the overall clause status; When the overall clause status is detected as a conflict clause, send a first control word to the assignment mask unit to control the assignment mask unit to enter the conflict mode; When the overall clause status is detected as a unit clause, send a second control word to the assignment mask unit to control the assignment mask unit to enter the propagation mode; When the overall clause status is detected as a heuristic clause, send a third control word to the assignment mask unit to control the assignment mask unit to enter the heuristic assignment mode.

[0012] According to a complete K-SAT solver based on the incremental update technology provided by the present invention, the complete K-SAT solver further includes a backtracking controller connected to the incremental updater; When the address pointer of the register file receives the backtracking instruction of the backtracking controller, it returns the corresponding historical node, and reads out the historical assignment information of the backtracking literal corresponding to the historical node for logical refutation.

[0013] According to a complete K-SAT solver based on the incremental update technology provided by the present invention, the backtracking controller is specifically used for: In the historical assignment information stored in the register file, retrieve the target unpropagated literal that is the latest and has not been used for backtracking retrieval; Analyze the target unpropagated literal and calculate the backtracking depth information; Send the backtracking depth information to the assignment mask unit.

[0014] According to a complete K-SAT solver based on the incremental update technology provided by the present invention, If the backtracking depth information is within the range allowed by the preset maximum backtracking depth, select the historical assignment information of the target literal corresponding to the backtracking depth information from the register file, and perform reverse assignment on the target literal; If the backtracking depth information exceeds the range allowed by the preset maximum backtracking depth, abandon the backtracking path corresponding to the backtracking depth information, clear the corresponding historical assignment information, and re-solve based on the remaining unpropagated literals.

[0015] According to a complete K-SAT solver based on the incremental update technology provided by the present invention, the register file is at least two, and is used for hierarchically storing the historical assignment information of the literals included in each clause in the Boolean formula.

[0016] The completeness K-SAT solver based on the incremental update technology provided by the present invention realizes the efficient storage and management of historical assignment information generated during the K-SAT solving process at the hardware level by incrementally updating hardware components such as the register file, assignment mask unit, and update logic unit in the circuit. It can not only meet the requirements of completeness analysis but also quickly perform partial adjustments to the current assignment without recalculating the entire assignment space, thus effectively solving the performance bottleneck caused by historical assignment storage and frequent backtracking in completeness analysis, significantly reducing the storage overhead and energy consumption, and providing an efficient and flexible solution for the hardware acceleration of the completeness analysis of the K-SAT problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic diagram of an example of the K-SAT problem in the prior art.

[0019] Figure 2 It is one of the circuit structure diagrams of the incremental updater provided by the embodiment of the present invention.

[0020] Figure 3 It is another circuit structure diagram of the incremental updater provided by the embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of the processing method of the assignment data by the assignment mask unit in different working modes provided by the embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of the overall architecture of the incremental update provided by the embodiment of the present invention.

[0023] Figure 6 It is a schematic diagram of the flow of the backtracking logic provided by the embodiment of the present invention.

[0024] Figure 7 It is a schematic diagram of the test results of the solving speed of the incremental update architecture provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To make the objectives, technical solutions and advantages of the present invention more apparent, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] In the description of the embodiments of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0027] In the description of the embodiments of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0028] In the embodiments of the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0029] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0030] The input of the K-SAT problem is a Boolean formula F(x). The Boolean formula can be composed of several clauses C, and each clause is a disjunctive expression containing at most K Boolean variables. If a variable assignment can be found such that all clauses in F(x) are true, then F(x) is said to be satisfiable (SAT); if there is no such variable assignment, then F(x) is said to be unsatisfiable (UNSAT).

[0031] Figure 1 It is a schematic diagram of an example of the K-SAT problem in the prior art. Referring to Figure 1 , in Example 1, when x0 is 0 and x1 is 1, the two clauses in the Boolean formula are simultaneously satisfied, so this Boolean formula is satisfiable; on the contrary, in Example 2, no matter what values x0 and x1 take, the two clauses in the Boolean formula cannot be simultaneously satisfied, so this Boolean formula is unsatisfiable.

[0032] As the scale of variables and clauses increases, the solving complexity of the K-SAT problem grows exponentially, posing extremely high challenges to solving algorithms and hardware designs. Due to its theoretical importance and wide practical applications, the K-SAT problem is widely used in multiple fields. For example, in Electronic Design Automation (EDA), the K-SAT problem is used for circuit equivalence verification and test pattern generation; in formal verification, K-SAT solving is an important tool for verifying the logical consistency of a system; in fault diagnosis, the K-SAT solver is used to quickly locate the root cause of system errors. Currently, the mainstream K-SAT solving methods can be divided into two categories: completeness analysis and incompleteness analysis. From the perspective of assignment storage and management, the similarities and differences between completeness analysis and incompleteness analysis are as follows: (1) The incomplete solver does not need to store historical assignments The incomplete solver updates variable assignments through heuristic methods, focusing only on the current derivation path, and does not need to store historical assignment information, thus avoiding the extra overhead caused by frequent storage and management of historical assignments. This feature gives the incomplete solver a clear advantage in energy consumption and hardware resource usage, but it cannot meet the needs of completeness analysis (it cannot prove whether a problem has a solution).

[0033] (2) Completeness analysis requires storing historical assignments and frequent backtracking Completeness solvers need to systematically verify SAT and UNSAT situations and must rely on historical assignment information for deduction and backtracking. When a deduction path conflicts or a clause is not satisfied, the solver needs to backtrack to the previous historical assignment state to retry other paths. However, this frequent backtracking operation places extremely high demands on hardware storage and management, especially in the case of large-scale variables and clauses. The frequency and complexity of backtracking will increase dramatically, making it difficult for traditional hardware design to efficiently support it.

[0034] At present, all application-specific integrated circuit (ASIC) solutions for K-SAT problems are non-complete solvers, which focus on quickly deducing whether the current assignment satisfies the Boolean formula without storing and managing historical assignment information. Since it does not need to backtrack historical assignments, the storage and computational complexity is greatly reduced. However, this design concept limits its application capabilities in scenarios where SAT and UNSAT situations need to be verified at the same time. Completeness analysis solvers are different. They need to frequently store and backtrack historical assignment information to support systematic derivation and verification, so they face higher storage and management requirements in hardware design.

[0035] In view of the above problems, the present invention can provide an efficient history assignment storage and management architecture for completeness analysis, so that the solver can frequently backtrack and re-explore the assignment space, and provide necessary support for verifying UNSAT; while realizing completeness analysis, through methods such as hierarchical storage and incremental update, it can reduce the cache cost and energy consumption overhead introduced by saving historical assignments as much as possible, thereby providing an efficient and flexible solution for hardware acceleration of K-SAT problem completeness analysis, and filling the gap in the storage structure of completeness solution hardware acceleration, providing strong support for complete K-SAT solution in complex applications in the fields of formal verification, EDA and fault diagnosis.

[0036] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of an incremental updater provided by an embodiment of the present invention. Figure 2, an embodiment of the present invention provides a complete K-SAT solver based on incremental update technology. The complete K-SAT solver includes an incremental updater, and the incremental updater 200 includes: An assignment mask unit 210, configured to adjust the current assignment of the target literal based on the current working mode of the assignment mask unit to obtain adjusted assignment information; A register file 220, configured to store historical assignment information of the literals included in each clause in the Boolean formula; An update logic unit 230, connected to the assignment mask unit at one end and to the register file at the other end, configured to determine final literal assignment information based on the historical assignment information and the adjusted assignment information; The assignment mask unit 210 is further configured to output the literal assignment information, so that the complete K-SAT solver performs complete K-SAT solving based on the literal assignment information.

[0037] In the embodiment of the present invention, by designing an incremental updater and using the incremental updater to store and backtrack the historical assignment information (i.e., historical assignment status) of literals, different decision paths can be effectively managed during the solving process.

[0038] Among them, the assignment information of a literal may include two cases: the literal has been assigned and the literal has not been assigned.

[0039] In the embodiment of the present invention, the incremental updater may include a register file for storing the historical assignment information of literals, an update logic unit for performing assignment data processing, and an assignment mask (AM) unit for selecting and processing assignment data, so as to dynamically record assignment modifications and derivation results, and only store necessary change information, avoiding the high cost of storing redundant information in the traditional method. This incremental assignment update mechanism can effectively reduce the management complexity and storage requirements of historical assignments.

[0040] During the specific solving process, when the clause analyzer detects that the overall clause state is a specific type of clause state (i.e., the clause state is a unit clause, a conflict clause, or a heuristic clause), the incremental updater can quickly perform partial adjustment on the current assignment based on the matching result given by the clause-literal status lookup table (i.e., the output result of the clause-literal status lookup table), so as to perform incremental update on the current assignment of the literal without recalculating the assignment space. During this process, the incremental update circuit can incorporate the newly obtained unpropagated literals into the current assignment set with extremely low storage overhead and operation delay, creating conditions for subsequent solving steps.

[0041] Among them, the matching result given by the clause and literal status lookup table can be the sum of the unassigned literals included in each clause in the Boolean formula.

[0042] In an embodiment of the present invention, the working modes of the assignment mask unit may include a conflict mode, a propagation mode, and a heuristic assignment mode. The mechanisms for the assignment mask unit to select and process the assignment data in different working modes are different.

[0043] Figure 3 It is the second schematic diagram of the circuit structure of the incremental updater provided by the embodiment of the present invention. Refer to Figure 3 , in some embodiments, the update logic unit can obtain the historical literal assignment information stored in the register file through the data output port (Data Output, DOUT) of the register file, and obtain the assignment information obtained after the assignment mask unit adjusts the literal assignment through the incremental assignment path (△A), so as to perform an XOR operation based on the historical assignment information and the adjusted assignment information to achieve logical mixing and generate new literal assignment information, realizing the fusion of potential assignment information and current assignment information.

[0044] At the same time, the update logic unit can also input the literal assignment information obtained after processing the assignment data into the register file for storage through the data input port (Data Input, DIN) of the register file.

[0045] The complete K-SAT solver based on the incremental update technology designed in the embodiment of the present invention realizes the efficient storage and management of the historical assignment information generated in the K-SAT solving process at the hardware level by incrementally updating hardware components such as the register file, the assignment mask unit, and the update logic unit in the incremental update circuit. It can not only meet the requirements of completeness analysis, but also quickly perform partial adjustment on the current assignment without recomputing the entire assignment space. Thus, it effectively solves the performance bottleneck caused by the storage of historical assignments and frequent backtracking in completeness analysis, significantly reducing the storage overhead and energy consumption, and providing an efficient and flexible solution for the hardware acceleration of the completeness analysis of the K-SAT problem.

[0046] In an optional embodiment, the assignment mask unit is specifically configured to: when the current working mode of the assignment mask unit is the conflict mode, obtain the backtracking depth information represented by binary coding; select the corresponding literal position based on the backtracking depth information, and determine the literal at the literal position as the target literal; set all the corresponding literals of the variable corresponding to the target literal to 1.

[0047] The conflict mode may refer to a mode in which a conflict occurs in the K-SAT solving process and it is necessary to roll back to a certain historical decision point (which can also be called the backtracking mode). The literal position may refer to the one-hot vector positions corresponding to the two literals of a variable. For example, in the case of assigning a value to variable x, the one-hot vector positions corresponding to the positive literal and the negative literal of the variable can both be set to 1.

[0048] A variable can have two expression forms: a positive literal and a negative literal. The positive literal can represent the Boolean variable itself, and the negative literal can represent the negation of the Boolean variable. In the embodiment of the present invention, when the current working mode of the assignment mask unit is the conflict mode, the assignment mask unit can receive the backtracking depth information represented by binary coding sent by the backtracking controller, and based on the backtracking depth information, select the corresponding literal position in the assignment mask, determine the literal at that literal position as the target literal, and set all the corresponding literals of the variable corresponding to the target literal to 1, so as to import the adjusted literal into the incremental assignment path to correct the previous assignment decision.

[0049] In the embodiment of the present invention, the operation of reverse assignment of literals can be performed by updating the XOR operation in the logic unit.

[0050] Figure 4 It is a schematic diagram of the processing method of assignment data by the assignment mask unit provided in the embodiment of the present invention. Refer to Figure 4 (c). As an example, in the conflict mode, the assignment mask unit can select the corresponding third literal position and fourth literal position in the backtracking value based on the backtracking depth information, and assign the backtracked "1" to the complementary literal and send it into the incremental assignment path.

[0051] In an optional embodiment, the assignment mask unit is specifically configured to: when the current working mode of the assignment mask unit is not the conflict mode, obtain the output result of the clause and literal status lookup table; the output result is the sum of the unassigned literals included in each clause in the Boolean formula; based on the current working mode of the assignment mask unit, determine the target literal to be adjusted, and adjust the current assignment of the target literal.

[0052] Figure 5 It is a schematic diagram of the overall architecture of incremental update provided in the embodiment of the present invention. Refer to Figure 5 , The clause and literal status lookup table can provide fast status queries for the literals included in each clause, and support assignment selection and decision-making. When the current working mode of the assignment mask unit is not the conflict mode, it means that backtracking is not required at this time, and the assignment mask unit can obtain the output result (i.e., the matching result) of the clause and literal status lookup table for the selection and processing of assignment data.

[0053] Among them, the output of the clause and literal status lookup table can be the sum of the unassigned literals included in each clause in the Boolean formula.

[0054] After obtaining the output result of the clause and literal status lookup table, the assignment mask unit can select the target literal to be adjusted based on the current working mode of the assignment mask unit, so as to adjust the current assignment of the target literal and import the adjusted assignment information into the incremental assignment path.

[0055] In an optional embodiment, the assignment mask unit is specifically configured to: if the current working mode of the assignment mask unit is the propagation mode, determine the literal corresponding to the output result of the clause and literal status lookup table as the target literal; perform a flipping operation on the current assignment of the target literal.

[0056] In the embodiment of the present invention, when the assignment mask unit is in the propagation mode, the assignment mask unit can perform a flipping operation on the output result of the clause and literal status lookup table and directly send the flipped literal into the incremental assignment path (ΔA) to quickly integrate the new assignment information obtained from the propagation stage into the current decision state.

[0057] Continue to refer to Figure 4 (b), as an example, in the propagation mode, the assignment mask unit can flip the output result "1010...0" to "0101...1" and send the flipped assignment information "0101...1" into the incremental assignment path.

[0058] In an optional embodiment, the assignment mask unit is specifically configured to: if the current working mode of the assignment mask unit is the heuristic assignment mode, select an unpropagated literal as the target literal; perform a flipping operation on the current assignment of the target literal.

[0059] In the embodiment of the present invention, when the assignment mask unit is in the heuristic assignment mode, the assignment mask unit can read the corresponding output result from the clause and literal status lookup table, select a suitable unpropagated literal, flip the logical value (0 or 1) of the unpropagated literal, and import the flipped assignment information into the incremental assignment path (ΔA).

[0060] Continue to refer to Figure 4 (a), as an example, in the heuristic assignment mode, the assignment mask unit can flip the logical value "0" of an unpropagated literal and send the flipped information into the incremental assignment path.

[0061] In the embodiment of the present invention, by designing a flexible switching mechanism of the assignment mask unit to adopt different selection and processing methods for assignment data in different working modes, it is beneficial to realize the incremental update of the current assignment.

[0062] In an alternative embodiment, the completeness K-SAT solver further includes a clause analyzer connected to the assignment mask unit, and the clause analyzer is configured to: continuously detect the overall clause state; when detecting that the overall clause state is a conflict clause, send a first control word to the assignment mask unit to control the assignment mask unit to enter the conflict mode; when detecting that the overall clause state is a unit clause, send a second control word to the assignment mask unit to control the assignment mask unit to enter the propagation mode; when detecting that the overall clause state is a heuristic clause, send a third control word to the assignment mask unit to control the assignment mask unit to enter the heuristic assignment mode.

[0063] Continue to refer to Figure 5 , in the embodiment of the present invention, the clause analyzer can continuously detect the overall clause state, and sequentially identify conflict clauses, unit clauses, heuristic assignment clauses, and other possible assignment types, so as to ensure the order and efficiency of the solving process.

[0064] In some embodiments, the clause analyzer can determine the overall clause state by detecting the clause state of each clause in the Boolean formula.

[0065] If the clause analyzer detects that at least one clause is a conflict clause, it can determine that the overall clause state is a conflict clause, and send a first control word to the assignment mask unit, so as to control the assignment mask unit to enter the conflict mode (i.e., the backtracking mode) and execute the assignment data processing method corresponding to the conflict mode.

[0066] If the clause analyzer detects that none of the clauses is a conflict clause, it can continue to detect whether there is a propagation clause. If it detects that at least one clause is a propagation clause, it can determine that the overall clause state is a propagation clause, and send a second control word to the assignment mask unit, so as to control the assignment mask unit to enter the propagation mode and execute the assignment data processing method corresponding to the propagation mode.

[0067] If the clause analyzer detects that none of the clauses is a conflict clause and a propagation clause, it can determine that the overall clause state is a heuristic clause, and send a third control word to the assignment mask unit, so as to control the assignment mask unit to enter the heuristic assignment mode and execute the assignment data processing method corresponding to the heuristic assignment mode.

[0068] In an alternative embodiment, the completeness K-SAT solver further includes a backtracking controller connected to the incremental updater; when the address pointer of the register file receives a backtracking instruction from the backtracking controller, it returns to the corresponding historical node and reads out the historical assignment information of the backtracking literal corresponding to the historical node for logical refutation.

[0069] Continue to refer to Figure 5 , in the embodiment of the present invention, the backtracking controller can calculate an appropriate backtracking depth when a conflict occurs during the solving process, thereby helping the solver to reselect the decision path.

[0070] In the embodiment of the present invention, when a variable conflict or a clause conflict is detected, the register address pointer in the incremental updater can quickly return to the corresponding historical node under the guidance of the backtracking controller, read out the historical assignment information of the backtracking literal corresponding to the historical node for logical refutation, so as to obtain a new assignment vector.

[0071] In an alternative embodiment, the backtracking controller is specifically configured to: retrieve, from the historical assignment information stored in the register file, a target unpropagated literal that is the latest and has not been used for backtracking retrieval; analyze the target unpropagated literal and calculate backtracking depth information; and send the backtracking depth information to the assignment mask unit.

[0072] Figure 6 is a schematic flowchart of the backtracking logic provided by the embodiment of the present invention. Refer to Figure 6 , in the embodiment of the present invention, the backtracking logic may include a depth calculation logic and an incremental update logic. The backtracking controller can retrieve the historical assignment records stored in the register file through a depth-calculating loop, so as to find the latest unpropagated literal that has not been used for backtracking retrieval, and then calculate the backtracking depth information through the search and analysis of these unpropagated literals, and send the backtracking depth information to the assignment mask unit in the incremental updater.

[0073] The assignment mask unit can receive the backtracking depth information calculated by the backtracking controller, so that the incremental updater can determine the depth of backtracking. The depth of backtracking determines which historical decision point the solver needs to retreat to, in order to attempt to replace the assignment of a specific variable or explore a new decision path.

[0074] In an alternative embodiment, if the backtracking depth information is within the allowable range of the preset maximum backtracking depth, the historical assignment information of the target literal corresponding to the backtracking depth information is selected from the register file, and the target literal is reversely assigned; if the backtracking depth information exceeds the allowable range of the preset maximum backtracking depth, the backtracking path corresponding to the backtracking depth information is abandoned, the corresponding historical assignment information is cleared, and the solution is restarted based on the remaining unpropagated literals.

[0075] Continue to refer to Figure 6 , in the embodiment of the present invention, if the calculated backtracking depth is within the allowable range of the preset maximum backtracking depth, the update logic unit can retrieve the historical assignment status corresponding to the depth from the register file, and replace the conflicting literals that have been searched with their negations. In this way, the solver can finely adjust the previous decisions at a lower storage and time cost, thereby avoiding repeating the solution from scratch. During this process, the solver can effectively skip the decision paths that have been proven unable to bring new solutions, accelerating the overall convergence speed.

[0076] If the calculated backtracking depth exceeds the allowable range of the preset maximum backtracking depth, the incremental updater can abandon the backtracking path at this depth, clear the corresponding historical assignment record, and restart the solution process based on the remaining unpropagated literals.

[0077] Specifically, when the assignment mask unit is in the heuristic assignment mode, it can first retrieve the unassigned literals, and then the latest assignment vector can be obtained by mixing and matching the results (i.e., ML) through the assignment mask unit (i.e., AM) (i.e., ΔA = AM(ML) and AGN = AGN ^ ΔA); the latest assignment vector can be stored in the register file, and the register pointer address (i.e., ADDR) and the literal assignment can be updated (i.e., Bank[ADDR] = AGN, List.add(ΔA) and ADDR += 1, DL += 1), and then the next iteration can be performed.

[0078] When the assignment mask unit is in the propagation mode, it can first retrieve the unassigned literals, and then determine whether there is a variable conflict (i.e., Any Var. Conflict?). If there is no variable conflict, the latest assignment vector can be obtained by mixing and matching the results through the assignment mask unit, and then the next iteration can be performed; if there is a variable conflict, backtracking is required.

[0079] When the assignment mask unit is in conflict mode, the initial backtracking depth can be determined (i.e., the loop of i += 1, DL -= 1, and List[DL] Searched?), and it is judged whether there are unpropagated literals that have not been used for backtracking retrieval (i.e., DL > 0?). If there are no unpropagated literals that have not been used for backtracking retrieval, it indicates an unsatisfiable (UNSAT) situation. If there are unpropagated literals that have not been used for backtracking retrieval, it is judged whether they have been used for backtracking retrieval starting from the latest unpropagated literal until the latest unpropagated literal that has not been used for backtracking retrieval is found (i.e., set List[DL] to Searched).

[0080] Then it can be judged whether the backtracking depth exceeds the preset maximum backtracking depth allowable range (i > max depth?). If the backtracking depth exceeds the preset maximum backtracking depth allowable range, the corresponding historical assignment record is cleared (i.e., cache is cleared), the solution process is restarted based on the remaining unpropagated literals, and the next iteration is performed. If the backtracking depth does not exceed the preset maximum backtracking depth allowable range, the register address pointer is determined based on the backtracking depth (ADDR -= i), so as to retrieve the historical assignment status corresponding to the depth from the register file (i.e., Bank[ADDR]). Finally, the assignment mask unit can set the two literals at the literal positions corresponding to the backtracking depth to 1, and import the adjusted literal assignment into the incremental update unit, so as to mix the adjusted literal assignment with the historical assignment corresponding to the depth, and then perform the next iteration.

[0081] The embodiment of the present invention realizes the co - design of software and hardware for backtracking scheduling, can quickly locate relevant historical assignments and restore the state when a conflict occurs, and at the same time optimizes the backtracking path to avoid repeated calculations and unnecessary backtracking operations.

[0082] The embodiment of the present invention provides a backtracking algorithm adapted to the incremental update circuit for the common conflict and rollback requirements in the hardware solution of the K - SAT problem. Thus, by using the incremental update circuit and the matching backtracking algorithm, higher energy efficiency and speed can be achieved, and the completeness analysis of the K - SAT problem can be efficiently supported.

[0083] In an alternative embodiment, there are at least two register files, which are used for hierarchically storing the historical assignment information of the literals included in each clause of the Boolean formula.

[0084] Continue to refer to Figure 3 , in some specific implementations, the register file can be composed of Bank0, Bank1,..., Bank7, so as to realize the hierarchical storage of the historical assignment information of the literals included in each clause of the Boolean formula.

[0085] In the embodiments of the present invention, hierarchical storage is achieved through a register file, which can efficiently store and manage the historical information of variable assignments, and supports fast access and dynamic update. The hierarchical assignment storage structure of this register file can significantly reduce the occupancy of storage resources while ensuring the efficient execution of frequent backtracking operations.

[0086] Through the above mechanism, the incremental updater of the present invention can work in coordination with the assignment storage and backtracking structure. It can not only efficiently complete the incremental update of assignments, quickly record and retrieve historical states in the solution of complex K-SAT problems, but also timely adjust the solution direction when facing conflicts through a flexible backtracking strategy. The design of the present invention effectively reduces the hardware resource consumption and solution delay caused by frequent storage and backtracking, provides a solid hardware foundation for achieving completeness analysis, and accelerates the practical application of the hardware acceleration of complete K-SAT analysis.

[0087] Figure 7 It is a schematic diagram of the solution speed test results of the incremental update architecture provided by the embodiments of the present invention. Refer to Figure 7 , the incremental updater and its supporting incremental update architecture provided by the embodiments of the present invention have been taped out and verified through actual measurement under the TSMC 28nm process. According to the experimental results, for the K-SAT problems in the open-source test sets uf50-218 and uuf50-218, the average solution times of the hardware solution architecture proposed by the present invention are 17.1 microseconds and 42.1 microseconds respectively. Compared with the complete software SAT solver based on the DPLL (Davis-Putnam-Logemann-Loveland) algorithm running on an AMD Ryzen 5 4500U CPU, the present invention has a speedup of about 952 times in terms of solution speed and reduces the energy consumption by about 3.4×10 5 times, fully demonstrating the outstanding advantages of the present invention in terms of high performance and low energy consumption.

[0088] Existing ASIC hardware designs for K-SAT problems are all incomplete solvers. These incomplete solutions mainly rely on heuristic methods to quickly find satisfiable solutions (SAT) in terms of design concepts, and do not require the storage and backtracking management of historical assignment information. Therefore, they completely avoid the huge cache overhead required for storing historical decisions and intermediate states in implementation. However, this advantage of not requiring a large-scale cache is also its limitation: (1) Unable to verify the UNSAT situation: Incomplete solvers do not have the ability to verify the unsatisfiability of Boolean formulas. They can only give satisfiable solutions and cannot prove their unsolvability. This limitation makes them less applicable in scenarios that require verifying both SAT and UNSAT, such as formal verification and complex EDA tasks.

[0089] (2)Management of lack of historical assignment information: The lack of storage and backtracking mechanisms for historical assignments enables the incomplete solver to only perform derivations linearly and locally. Once a conflict occurs or it gets stuck in a local optimal solution, it is difficult to backtrack in a timely manner and explore other solution spaces.

[0090] To address the above drawbacks, the present invention designs a hardware solving structure for the K-SAT problem that supports completeness analysis. By introducing an efficient storage and backtracking mechanism for historical assignment information, it solves the fundamental problem that traditional incomplete solutions cannot perform UNSAT verification.

[0091] The present invention is the first technical solution that starts from the perspective of cache storage and supports complete solving with hardware acceleration. Since previous incomplete solvers do not require storage-related structures in their designs, there is no technical reference in ASIC implementation that can be directly compared with the present invention. At the algorithm level, there are obvious differences between the traditional completeness analysis algorithm DPLL and the specific implementation mechanism and technical route of the present invention. Compared with the DPLL algorithm, the present invention has the following advantages: (1)Different from the global search and backtracking of the DPLL algorithm at the software level, the backtracking algorithm of the present invention realizes localized and hierarchical management in hardware.

[0092] (2)The deep calculation loop is used to quickly locate the latest unpropagated literal that has not been backtracked in the hardware register file and determine the required backtracking depth. This operation does not require frequent retrieval of huge data structures in software like DPLL. The direct access and comparison of the hardware circuit can significantly reduce latency and energy consumption.

[0093] (3)During the backtracking execution stage, the backtracking algorithm of the present invention can directly retrieve the previous assignment state from the register file according to the deep calculation result and achieve ordered backtracking by negating the relevant literals. If the backtracking depth exceeds the preset upper limit, the circuit structure of the present invention can quickly clear the corresponding historical records and switch to the branch of the remaining unpropagated literals to continue the solution. This process no longer depends on software calls and stack operations like DPLL, but utilizes the hardware to quickly access, reset, and update the assignment information, greatly improving the solution efficiency.

[0094] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence, or the parts that contribute to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A complete K-SAT solver based on incremental update technology, characterized in that, The complete K-SAT solver includes an incremental updater, and the incremental updater includes: An assignment mask unit, configured to adjust the current assignment of a target literal based on the current working mode of the assignment mask unit to obtain adjusted assignment information; A register file, configured to store the historical assignment information of the literals included in each clause in the Boolean formula; An update logic unit, connected to the assignment mask unit at one end and to the register file at the other end, configured to determine literal assignment information based on the historical assignment information and the adjusted assignment information; The assignment mask unit is further configured to output the literal assignment information, so that the complete K-SAT solver performs complete K-SAT solving based on the literal assignment information.

2. The completeness K-SAT solver according to claim 1, characterized in that, Specifically, the assignment mask unit is configured to: In the case where the current working mode of the assignment mask unit is the conflict mode, obtain the backtracking depth information represented by binary encoding; Select a corresponding literal position based on the backtracking depth information, and determine the literal at the literal position as the target literal; Set all the corresponding literals of the variable corresponding to the target literal to 1.

3. The completeness K-SAT solver according to claim 1, characterized in that, Specifically, the assignment mask unit is configured to: In the case where the current working mode of the assignment mask unit is not the conflict mode, obtain the output result of the clause and literal status lookup table; the output result is the sum of the unassigned literals included in each clause in the Boolean formula; Based on the current working mode of the assignment mask unit, determine the target literal to be adjusted, and adjust the current assignment of the target literal.

4. The completeness K-SAT solver according to claim 3, wherein Specifically, the assignment mask unit is configured to: If the current working mode of the assignment mask unit is the propagation mode, determine the literal corresponding to the output result of the clause and literal status lookup table as the target literal; Perform a flip operation on the current assignment of the target literal.

5. The completeness K-SAT solver according to claim 2, characterized in that, Specifically, the assignment mask unit is configured to: If the current working mode of the assignment mask unit is the heuristic assignment mode, select an unpropagated literal as the target literal; Perform a flip operation on the current assignment of the target literal.

6. The completeness K-SAT solver according to claim 1, characterized in that, The complete K-SAT solver further includes a clause analyzer connected to the assignment mask unit, and the clause analyzer is configured to: Continuously detect the overall clause status; When detecting that the overall clause status is a conflict clause, send a first control word to the assignment mask unit to control the assignment mask unit to enter the conflict mode; When detecting that the overall clause status is a unit clause, send a second control word to the assignment mask unit to control the assignment mask unit to enter the propagation mode; When detecting that the overall clause status is a heuristic clause, send a third control word to the assignment mask unit to control the assignment mask unit to enter the heuristic assignment mode.

7. The completeness K-SAT solver according to claim 2, wherein The complete K-SAT solver further includes a backtracking controller connected to the incremental updater; When receiving a backtracking instruction from the backtracking controller, the address pointer of the register file returns to the corresponding historical node and reads out the historical assignment information of the backtracking literal corresponding to the historical node for logical refutation.

8. The completeness K-SAT solver according to claim 7, characterized in that Specifically, the backtracking controller is configured to: Retrieve the target unpropagated literal that is the latest and has not been utilized for backtracking retrieval from the historical assignment information stored in the register file; Analyze the target unpropagated literal and calculate the backtracking depth information; Send the backtracking depth information to the assignment mask unit.

9. The complete K-SAT solver according to claim 7, characterized in that If the backtracking depth information is within the allowable range of the preset maximum backtracking depth, select the historical assignment information of the target literal corresponding to the backtracking depth information from the register file, and perform reverse assignment on the target literal; If the backtracking depth information exceeds the allowable range of the preset maximum backtracking depth, abandon the backtracking path corresponding to the backtracking depth information, clear the corresponding historical assignment information, and re-solve based on the remaining unpropagated literals.

10. The completeness K-SAT solver according to claim 1, characterized in that, There are at least two register files, which are used for hierarchical storage of the historical assignment information of the literals included in each clause in the Boolean formula.

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