A dynamic quantum feedback system based on branch prediction

Abstract

The present invention discloses a dynamic quantum feedback system based on branch prediction. The system obtains the states at k moments by comparing IQ coordinate values ​​at k moments with the distances at which the states are 0 or 1. The intermediate-moment statistical probabilities that the states at k moments are all selected states are obtained by comparing the states at k moments with a state table. The overall delay time of the above-mentioned distance calculation and state table matching is short, thereby improving efficiency. The present invention utilizes a method of combining the predicted intermediate-moment statistical probabilities with historical statistical probabilities to achieve more accurate predictions for various situations.

Description

Technical Field

[0001] The present invention belongs to the technical field of quantum computing, and in particular relates to a dynamic quantum feedback system based on branch prediction. Background Art

[0002] Quantum feedback is essential for many quantum algorithms, such as fast reset, quantum state teleportation, and quantum error correction. These algorithms leverage feedback to dynamically modify operations within a quantum program based on intermediate measurement results, thereby increasing the program's flexibility. In quantum error correction, feedback is particularly crucial, with readout and bit repair typically accounting for over 70% of the time. Because current noisy quantum hardware relies on error correction to suppress errors, feedback will be a frequent feature of future quantum applications.

[0003] However, similar to conditional judgments in classical CPUs, quantum feedback introduces extremely high computational overhead in quantum programs. Furthermore, due to the uncertainty of gate operations after feedback, computations are blocked during the feedback phase, further increasing latency. Specifically, the feedback process first involves a readout on the quantum processor, followed by classical processing on the FPGA board to determine the subsequent quantum operation. In Google's quantum error correction experiments, readout and reset require classical processing times of 500ns and 160ns, respectively. The overall latency is 26.4 times that of a single gate operation. During this long feedback time, the qubit is exposed to various error sources, resulting in a high error rate. Feedback errors include both readout errors and feedback gate errors. Results from a single-bit active reset experiment on the IBM Brisbane platform showed an error rate of 2.07%. This error rate is far above the quantum error correction threshold and imposes significant error correction overhead.

[0004] Current feedback optimization methods mainly focus on accelerating feedback computation on FPGA. To reduce feedback delay, the literature Yves Salathé, Philipp Kurpiers, Thomas Karg, Christian Lang, Christian Kraglund Andersen, Abdulkadir Akin, Sebastian Krinner, Christopher Eichler, and Andreas Wallraff. 2018. Low-latency digital signal processing for feedback and feedforward in quantum computing and communication. Physical Review Applied 9, 3(2018), 034011. discloses accelerating state classification through parallel computing and pipeline processing; the literature Gang Huang, Yilun Xu, Neelay Fruitwala, Abhi D Rajagopala, Kasra Nowrouzi, Ravi K Naik, David Santiago, and Irfan Siddiqi. 2023. QubiC 2.0: A Flexible Advanced Full Stack Quantum Bit Control System. In 2023 IEEE International Conference on Quantum Computing and Engineering (QCE), Vol. 2. IEEE, 248–249. A waveform table is implemented to accelerate waveform preparation, and fine-grained DAC optimization is used to minimize feedback delay; the literature Cheng Guo, Jin Lin, Lian-Chen Han, Na Li, Li-Hua Sun, Fu-Tian Liang, Dong-Dong Li, Yu-Huai Li, Ming Gong, Yu Xu, Sheng-Kai Liao, and Cheng-ZhiPeng.2022. Low-latency readout electronics for dynamic superconductingquantum computing. AIP Advances 12, 4 (2022).) discloses the use of parallel computing in demodulating and reading IQ waveforms.However, these approaches usually only bring modest latency improvements, which are still insufficient to overcome the performance bottleneck caused by the latency wall. Summary of the Invention

[0005] The present invention provides a dynamic quantum feedback system based on branch prediction, which overcomes the performance bottleneck caused by the delay wall, introduces branch prediction more efficiently, and solves the quantum feedback problem.

[0006] A specific embodiment of the present invention provides a dynamic quantum feedback system based on branch prediction, including an FPGA, wherein the FPGA includes:

[0007] The ADC and DAC modules are used to receive the waveform data of the current shot and process the waveform data of the branch circuit information corresponding to the prediction result to obtain a simulation waveform so as to pre-execute the branch circuit;

[0008] Feedback controller, which is connected to the ADC and DAC modules via SerDes, and includes state classification, dynamic timing controller, and waveform preparation:

[0009] The state classification is used to process waveform data to obtain states at k moments, compare the states at k moments with the state table to obtain the intermediate moment statistical probability that the states at k moments are all selected states, obtain the historical statistical probability of the selected state based on the state distribution of historical shots, and combine the historical statistical probability with the intermediate moment statistical probability to obtain the predicted statistical probability that the state is the selected state;

[0010] The waveform is prepared to use the selected state as the prediction result when the received prediction statistical probability is greater than the set threshold, send a feedback signal to the dynamic timing controller, and after receiving the feedback signal through the dynamic timing controller, send the waveform data of the branch circuit information corresponding to the prediction result to the ADC and DAC modules.

[0011] Preferably, the state classification includes a stream adapter, a parameter register, a demodulator, a demodulation result queue, a history branch register, a state table and a Bayesian prediction model;

[0012] The stream adapter is used to collect and process the waveform data in the time window to obtain the real part and the imaginary part of the waveform data, and send the real part and the imaginary part of the waveform data to the demodulator;

[0013] The parameter register is used to send the quantum bit physical parameters to the solver;

[0014] The demodulator is used to demodulate the real and imaginary parts of the waveform data and the quantum bit physical parameters together to obtain the IQ coordinate value of the waveform at each moment in the time window;

[0015] The demodulation result queue is used to compare the IQ coordinate values ​​at different times with the distance of the state 0 or 1 to obtain the state at different times, and send the state at different times to the historical branch register;

[0016] The historical branch register is used to receive the state of the historical moment and the current time window, thereby obtaining the state of the latest k moments, and sending the state of the latest k moments to the state;

[0017] The state table is used to obtain the intermediate moment statistical probability that the states at k moments are all the selected states based on the states at the latest k moments received through the correspondence between the states at k moments and the statistical probabilities at the intermediate moments;

[0018] The Bayesian prediction model is used to combine the historical statistical probability of the state being the selected state in the historical period with the intermediate moment statistical probability to obtain the predicted statistical probability of the state being the selected state.

[0019] Preferably, when the waveform preparation is used and the received predicted statistical probability is less than a set threshold, the waveform preparation module does not generate a feedback signal, waits for receiving the predicted statistical probability at the next moment, and performs the threshold judgment again.

[0020] Preferably, the waveform preparation includes a branch decision maker, an operation table, a waveform library, a waveform sequence, a decoder and a feedback signal interconnection;

[0021] The branch decision maker compares the predicted statistical probability with a set threshold value. When the received predicted statistical probability is greater than the set threshold value, a feedback signal is sent to the dynamic timing controller, and the feedback signal is received through the feedback signal interconnection. The prediction result is then sent to the operation table to search for the address of the pre-executed branch circuit corresponding to the selected state. Based on the searched address, the corresponding waveform is obtained through the waveform library. The corresponding waveform is decoded by the decoder to obtain waveform data carrying the pre-executed branch circuit information. The waveform data carrying the pre-executed branch circuit information is transmitted to the ADC and DAC modules through the JESD interface.

[0022] Preferably, it also includes a data bus and a backplane. If it is necessary to trigger another FPGA to execute the corresponding branch circuit, the dynamic moment controller sends feedback information to the branch decision maker of another FPGA through the data bus and the backplane, and the corresponding branch circuit is pre-executed through the other FPGA branch decision maker.

[0023] Preferably, the waveform library includes a waveform generation unit and a cache storage unit, and the cache storage unit includes a pre-execution cache, a reusable cache and a recovery cache;

[0024] The waveform generating unit is used to retrieve a corresponding waveform from a pre-execution cache and a reusable cache based on the received search address, and send the retrieved waveform to the decoder;

[0025] The reusable cache and recovery cache are also used to trigger the waveform library to call the recovery cache or reusable cache waveform for branch recovery through the branch decision maker when the prediction result is inconsistent with the read result after the read process is completed.

[0026] Preferably, the decoder is used to decode the corresponding waveform through a run-length decoder, and then reconstruct the decoding result through Huffman decoding to obtain waveform data carrying pre-execution branch circuit information.

[0027] Preferably, the ADC and DAC module includes an ADC submodule and a DAC submodule;

[0028] The ADC submodule includes an ADC core and a digital downsampler, which sequentially captures the waveform data of the current shot through the ADC core and the digital downsampler to obtain a low-frequency waveform;

[0029] The DAC submodule includes an interpolation module and a DAC core, and the waveform data outputted carrying the pre-executed branch circuit information is sequentially interpolated by the module and the DAC core to obtain a simulation waveform.

[0030] Preferably, a clock management module is further included, and the clock management module is used to generate a reference clock, and synchronize the clocks of the ADC submodule and the DAC submodule through the generated reference clock.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention obtains the states at k moments by comparing the IQ coordinate values ​​at k moments with the distances when the states are 0 or 1, obtains the intermediate moment statistical probability that the states at k moments are all selected states by comparing the states at k moments with the state table, obtains the predicted statistical probability based on the intermediate moment statistical probability and the historical statistical probability, and takes the selected state as the prediction result if the predicted statistical probability is greater than the set threshold. Based on the prediction result, the corresponding branch circuit can be executed in advance to shorten the delay time. At the same time, the overall delay time of the above-mentioned distance calculation and state table matching is short, thereby improving efficiency. The present invention utilizes the combination of the predicted intermediate moment statistical probability and the historical statistical probability to achieve more accurate predictions for a variety of situations. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a diagram of the quantum feedback structure on a typical quantum device;

[0034] Figure 2is a typical quantum feedback delay decomposition diagram, where Figure 2 (a) is the relationship between lifetime and readout delay. Figure 2 (b) is a histogram of the minimum delay time for ADC processing, state classification, waveform preparation, and DAC processing;

[0035] Figure 3 The dynamic quantum feedback flow chart based on branch prediction and the gate pre-execution scenario diagram provided by the specific embodiment of the present invention, wherein: Figure 3 (a) is a dynamic quantum feedback flow chart based on branch prediction. Figure 3 (b) is a typical gate pre-execution diagram;

[0036] Figure 4 This is a typical branch prediction method flow chart;

[0037] Figure 5 is the quantum bit state classification diagram and reading trajectory diagram, where Figure 5 (a) is the circuit and state classification diagram for superconducting quantum bit reading. Figure 5 (b) is the reading trajectory diagram on the IQ plane;

[0038] Figure 6 A flowchart of the quantum branch prediction process provided by a specific embodiment of the present invention;

[0039] Figure 7 A block diagram of a dynamic quantum feedback system based on branch prediction provided by a specific embodiment of the present invention, wherein: Figure 7 (a) is the structure diagram of the feedback controller. Figure 7 (b) is the waveform generation and receiving module structure diagram. Figure 7 (c) is the structural diagram of the feedback controller processing unit;

[0040] Figure 8 A branch recovery flow chart provided for a specific embodiment of the present invention;

[0041] Figure 9 Flowchart of dynamic timing and static timing provided by specific embodiments of the present invention, Figure 9 (a) is a comparison diagram of static and dynamic timing control. Figure 9 (b) in the figure is the timing diagram of the feedback trigger;

[0042] Figure 10 This is a flowchart of waveform decoding provided by a specific embodiment of the present invention. DETAILED DESCRIPTION

[0043] In the face of the quantum feedback delay bottleneck, a key technology is to introduce branch prediction (BP), an important mechanism in the CPU, to optimize quantum feedback. A typical branch prediction mechanism predicts the most likely branch and executes the instructions under the branch in advance. When the prediction is successful, branch prediction can significantly reduce the overhead caused by pipeline stalls. However, if the prediction fails, the CPU requires additional instructions to restore the computing state. The effectiveness of the prediction mainly depends on the accuracy of the prediction. However, traditional branch prediction methods cannot be directly applied to quantum workloads, mainly for the following two reasons. First, quantum bits can be in a superposition state, making the readout results more random, while traditional branch prediction is designed for deterministic results. For example, when measuring a state with a 50% probability of being in a state, and When using quantum bits in a state, deterministic predictions are of no benefit. Secondly, quantum readout is a long, continuous process that provides intermediate information for prediction, while traditional readout is discrete and cannot utilize this information. Therefore, a prediction design for quantum feedback is urgently needed, and therefore a new quantum prediction method is urgently needed.

[0044] Quantum feedback is divided into two stages. First, the qubit is read out. Second, the readout information is sent to a classical feedback controller, which classifies the qubit state and determines the branch of the quantum program (0 or 1) based on the qubit state. The physical implementation used in this paper is based on superconducting quantum hardware. Figure 1 This figure illustrates the quantum feedback architecture of a typical quantum device. This architecture includes an ADC module, which captures waveforms from qubits as readout information. This information is processed by an FPGA, which includes two key units: a state classification unit that decodes the waveforms and classifies the qubit states; and a waveform preparation unit that reads waveform data for the selected branch from memory. These waveforms are synchronized by a timing controller, then buffered and transmitted to the quantum processor via a DAC.

[0045] Figure 2 The paper demonstrates the decomposition of delays in the feedback process, revealing a 660 nanosecond delay bottleneck based on current quantum hardware. Specifically for quantum processors, reducing readout latency requires increasing the coupling strength between the readout resonator and the qubit, but this also reduces the qubit lifetime (T1). Figure 2 (a) shows the relationship between lifetime and readout delay in different quantum processor designs. For example, Walter et al. achieved the minimum readout delay of 88 nanoseconds, but their quantum bit lifetime was also the shortest, at only 7.6 microseconds. In order to ensure effective lifetime, Google limited the minimum readout delay to 500 nanoseconds. On the other hand, Figure 2As shown in (b) of Figure 1, the current feedback controller includes ADC processing, state classification, waveform preparation, and DAC processing, with minimum latencies of 44 nanoseconds, 24 nanoseconds, 36 nanoseconds, and 56 nanoseconds, respectively. Overall, this creates a 660 nanosecond latency bottleneck (500 nanoseconds readout + 160 nanoseconds feedback hardware), which cannot be further reduced through hardware-level optimization. Furthermore, under the current serial feedback mechanism, it can be observed that the latest feedback controller is already close to the minimum latency, indicating that there is very limited room for optimization.

[0046] The specific embodiment of the present invention accelerates the feedback process by introducing a new branch prediction algorithm and pre-executing quantum gates. Figure 3 (a) in the figure shows the workflow of this embodiment. For a given quantum circuit, the available feedback position is first identified as the measurement sample, that is, the current shot, so that the instruction can be pre-executed, and then the program execution is started. During the feedback readout process, the probability of each branch is iteratively analyzed based on the historical branches of previous shots. When the probability of a branch exceeds the threshold θ, the quantum gate operation in the branch is pre-executed. When the readout is completed, it is determined whether the prediction is correct. If the prediction is wrong, a recovery operation needs to be performed. Specifically, since the quantum circuit is reversible, this article will apply a reverse quantum gate to offset the pre-executed gate operation, and then execute the correct branch.

[0047] The specific embodiment of the present invention accelerates the feedback process by introducing a new branch prediction algorithm and pre-executing quantum gates. Figure 3 The workflow shown in (a) in the figure is that for a given quantum circuit, the available feedback locations are first identified to allow pre-execution of instructions, and then program execution begins. During the feedback readout process, the probability of each branch is iteratively analyzed based on the historical branches of previous shots. When the probability of a branch exceeds a threshold, the quantum gate operation in that branch is pre-executed. When the readout is completed, it is determined whether the prediction is correct. If the prediction is wrong, a recovery operation needs to be performed. Specifically, since quantum circuits are reversible, this article will apply a reverse quantum gate to offset the pre-executed gate operation, and then execute the correct branch. According to the principles of quantum mechanics, all quantum gates can theoretically be pre-executed.

[0048] According to the principles of quantum mechanics, all quantum gates can be pre-executed in theory. Figure 3 The following typical gate pre-execution scenarios are summarized in (b):

[0049] Case 1: There are no other gate operations or readout operations before the X gate on q2, so the X gate can be pre-executed. This situation is common in feedback-based quantum error correction (the construction of logical T gates) and also often appears in quantum state transfer tasks, such as the construction of long-range entanglement gates.

[0050] Case 2: The feedback gate operation involves a two-bit gate operation that relies on the readout bit q1. Since the readout operation occupies q1, it cannot be pre-executed directly on q1. However, an auxiliary bit q′1 can be used. After the readout, q1 collapses to a classical state, which can be pre-prepared on q'1. The gate operation originally applied to q1 can then be applied to q'1 instead. On the other hand, q1 can be recycled after the readout is complete, minimizing the waste of qubit resources.

[0051] Case 3: For feedback operations that must be applied to a readout bit (such as a bit reset), the feedback gate must wait until the readout process is complete before applying the feedback gate. Unlike traditional methods, we can use predictive techniques to apply the feedback gate immediately after the readout is complete, eliminating over 100 nanoseconds of hardware processing delay.

[0052] Gate pre-execution essentially adjusts the timing of operations within the quantum circuit's directed acyclic graph (DAG). The four scenarios described above essentially constitute a DAG constraint analysis for quantum feedback pre-execution. For example, in scenario 1, the feedback operation on Q2 is independent and unconstrained, and the error state recovery process during dynamic circuit execution is also assumed to be unconstrained, so it can be executed in advance. Scenarios 2 and 3, on the other hand, are subject to the same constraint: operations cannot be performed on busy qubits, so gate pre-execution must be performed on auxiliary bits to convert them to a valid state. Scenarios 1 through 3 cover nearly all practical situations of quantum feedback, enabling branch prediction-based approaches to accelerate most feedback applications.

[0053] like Figure 4 As shown in Figure 1, a classic branch prediction method uses historical branches to predict possible branches in the current state and stores them in a state table consisting of <state, branch> pairs. The branch of each state in the state table is the branch that appears most frequently in that state and is dynamically updated during CPU execution. This feature is based on the temporal locality of the CPU and the current state is composed of the most recent k feedback branches. The prediction is done by table matching to find the most likely direction. For example Figure 4 In the example, when the two most recent branch directions are "1,1", the state is "11". For the state table containing <11,1>, the prediction result is branch 1, and branch 1 is pre-executed.

[0054] However, the branches in quantum feedback show higher randomness due to the existence of quantum superposition. In addition, the branch prediction in the classical CPU assumes that there is a temporal correlation between branches, so the branches of different programs can be used to predict the current branch; but the branches between different quantum programs are independent of each other. This embodiment uses a combination model to perform branch prediction. Specifically, a quantum program is usually executed multiple times (called shots). In addition, each reading has only two possible results, two possible states: 0 or 1. In one embodiment, this embodiment only needs to predict the reading result, that is, the probability P of the state being 1. predict_1 , because P predict_0 =1-P predict_1 This example uses two key features to model the probability of each shot:

[0055] 1. The historical branch distribution of the current feedback, including the read result, that is, the statistical probability P of the state being 1 history_1 ;

[0056] 2. The result of reading at an intermediate moment in the reading process of the current shot, that is, the probability of the state being 1 (i.e., P read_1 ).

[0057] Since reading in a quantum system is a continuous process, this embodiment can calculate the probability P at a certain intermediate moment in the process. read_1 .like Figure 5 As shown in (a) in Figure 1, in superconducting quantum hardware, reading is achieved through a read resonator coupled to the quantum bit. The state of each quantum bit is measured by sending a read waveform to the read resonator and identifying the frequency shift of the waveform (called dispersion shift). A portion of the read waveform can distinguish the frequency shift by its I and Q values, and longer waveforms provide higher accuracy. At time t i , the controller is read to capture a waveform, whose complex amplitude is pulse=[a1,a2,···,a L ], where L is the specified window length. The I and Q values ​​are calculated according to the demodulation formula as follows: , , where a i .real and a i .imag is the i-th amplitude a i The real and imaginary parts of , L is the number of amplitudes. Figure 5 As shown in (a), the I and Q values ​​of different states (i.e. 0 or 1) are expressed in V I and V Q The horizontal and vertical axes are located in different clusters on the IQ plane, which is used to classify the reading results. For example, Figure 5(b) in FIG shows the I and Q value trajectories from time t1 to t6.

[0058] Since the I and Q values ​​at different time points form a trajectory, prediction is done by comparing this trajectory with a pre-generated table. Specifically, at time t i , this embodiment decodes the captured read waveform to obtain the IQ value. Then, by calculating the distance between the IQ value and the center of 0 or 1 and comparing it, this embodiment can identify the most likely state at that moment. However, there is noise in the reading process, which will cause data jitter at each time point. This embodiment records the most likely state of the last k time points as a trajectory and compares it with <state,P read_1 >Compare the trajectories in the table, which records the P under different trajectories read_1 , where k is a user-defined parameter determined by the granularity of the prediction. In addition, <state,P read_1 The table comes from the first 100 shots. These shots do not enable feedback prediction, but are used to calculate the probability of reading 1 in each state. The probabilities in the state table remain unchanged during the execution of the feedback program.

[0059] This embodiment combines the historical probability and the probability based on the intermediate read waveform through the Bayesian model to predict the overall prediction probability: , when it is greater than the threshold, the pre-execution of branch 1 is started, and the subsequent prediction of the feedback in the current shot is terminated. For example, Figure 6 As shown, the historical probability P of branch 1 history_1 is 0.7. The prediction process will iteratively analyze the read waveform and record the possible readout result trajectory. The current state is the state of the last three moments, namely the state at t1, t2 and t3, which is 111. <states,P read1 > table, the probability of reading the result as 1 in the current shot is P read_1 =0.95. Combined with P history1 and P read1 , the final predicted probability of using branch 1 is: Obviously, in P read_1In the prediction, the complexity of distance calculation and table matching is O(1) (i.e., 3 clock cycles), and the clock cycles required for Bayesian calculation do not exceed 5. Therefore, the overall delay is only 32ns. In terms of accuracy, the prediction utilizes both historical results and the current readout state. Therefore, for feedback scenarios where the quantum bit states are uniformly distributed (50% are 0, 50% are 1), since the probability is uniform, the historical distribution is probabilistically attributed to 0.5, and the current readout probability can better reflect the final readout result of the shot, and a probabilistic prediction can be made based on the current readout state. On the contrary, in the case of a high readout error rate, a more accurate prediction can be achieved through historical results. At the implementation level, the historical result distribution is updated immediately after each prediction, so no delay is introduced. Therefore, the framework provided by the present embodiment has high time efficiency and accurate prediction.

[0060] In a specific embodiment, an example of updating the historical result distribution immediately after each prediction is as follows: the value of the historical statistical probability is updated before each shot. For example, before the 10th shot, the 0 / 1 ratio of the first 9 is 8:1, then the historical statistical probability is 1 / 9=0.111. The final reading result of the 10th shot is 1. Before the 11th shot, the historical statistical probability is updated. The 0 / 1 ratio of the first 10 is 8:2, and the historical statistical probability this time is 2 / 10=0.2.

[0061] Based on the above concept, the present invention provides a dynamic quantum feedback system based on branch prediction (ARTERY), such as Figure 7 As shown in (a), this embodiment provides an FPGA, a data bus, and a backplane. The FPGA includes ADC and DAC modules, a feedback controller, and a clock management module.

[0062] The clock management module provided in this embodiment generates a reference clock for the ARTERY system and provides a synchronous clock for the ADC and DAC modules.

[0063] The ADC and DAC modules responsible for waveform reception and transmission provided in this embodiment are integrated into an add-on card. These chips are connected to the feedback controller via SerDes (SERializer / DESerializer) to achieve high-speed waveform data transmission.

[0064] The FPGA provided in this embodiment is connected to the backplane via a data bus to achieve reception and transmission of feedback signals with other FPGAs.

[0065] like Figure 7As shown in (b) of the figure, the input waveform provided by this embodiment is captured by the ADC core and digital downsampler to obtain a low-frequency waveform. The ADC core is used to convert analog signals into digital signals. Furthermore, the output waveform undergoes data interpolation processing before being passed through the DAC core to generate an analog waveform. The DAC core is used to convert digital signals into analog signals. The digital downsampler and interpolation modules consume considerable time and account for the majority of the latency in the ADC and DAC processing.

[0066] like Figure 7 As shown in (c), the feedback controller provided by this embodiment includes state classification, dynamic timing controller and waveform preparation.

[0067] The state classification module provided in this embodiment includes a buffer, a stream adapter, a parameter register, a demodulator, a demodulation result queue, a history branch register, a state table, a read prediction register and a Bayesian prediction model.

[0068] In this embodiment, the readout waveform input through the JESD interface is first received and buffered, and then adjusted by the stream adapter. Two stream adapters process the input stream, one generates the real part of the waveform, and the other processes the imaginary part. The stream adapter collects the waveform data within the window length (t1, t2) and sends it to the demodulator. The waveform is then demodulated together with the pre-stored quantum bit physical parameters. The demodulation result is pushed into a deep , in the demodulation result queue, where pulse length is the time required to fully read the waveform, window length is the window length, and the IQ coordinate value of the waveform at each moment in the time window is provided. The state at different moments is obtained by comparing the IQ coordinate value at different moments with the distance of state 0 or 1, and the state at different moments is sent to the history branch register. The history branch register with width k records the preliminary classification result of the quantum state at time t2, that is, the state. Whenever the value in the history branch register is updated, the intermediate moment statistical probability P read It can be obtained through the state table, which is implemented using on-chip storage units and occupies a maximum memory size of 2k-3(k+16) bytes.

[0069] The Bayesian prediction model provided in this embodiment consists of a multiplier and a FIFO for synchronizing timing, which is used to store readout predictions and output P after k cycles. predict. The intermediate moment statistical probability is sent to the FIFO by reading the prediction register, and the intermediate moment statistical probability whose state is 1 is directly sent to the Bayesian prediction period through the FIFO. The historical statistical probability whose state is 1 is directly sent to the Bayesian prediction period, and the product of the sum is sent to the Bayesian predictor at the same time. The predicted statistical probability, that is, the prediction result, is obtained through the Bayesian predictor. The predicted statistical probability and the prediction result are sent to the branch prediction period for comparison to determine whether they exceed the preset threshold.

[0070] The waveform preparation provided in this embodiment includes a branch decision maker, an operation table, a waveform library, a waveform sequence, a decoder, and a feedback signal interconnection. The branch decision maker compares the predicted statistical probability with a set threshold. When the received predicted statistical probability is greater than the set threshold, the branch decision maker sends a feedback signal to the dynamic timing controller and receives the feedback signal through the feedback signal interconnection. The prediction result is then sent to the operation table to search for the address of the pre-executed branch circuit corresponding to the selected state. Based on the searched address, the corresponding waveform is obtained through the waveform library. The corresponding waveform is decoded by the decoder to obtain waveform data carrying the pre-executed branch circuit information. The waveform data carrying the pre-executed branch circuit information is transmitted to the ADC and DAC modules through the JESD interface.

[0071] In a specific embodiment, if it is necessary to trigger another FPGA to execute a corresponding branch circuit, the dynamic moment controller sends feedback information to the branch decision maker of another FPGA through the data bus and the backplane, and the corresponding branch circuit is pre-executed by the branch decision maker of the other FPGA.

[0072] In a specific embodiment, the waveform library includes a waveform generation unit and a cache storage unit, and the cache storage unit includes a pre-execution cache, a reusable cache, and a recovery cache;

[0073] The waveform generating unit is used to retrieve a corresponding waveform from a pre-execution cache and a reusable cache based on the received search address, and send the retrieved waveform to the decoder;

[0074] The reusable cache and recovery cache are also used when the prediction result is inconsistent with the reading result after the reading process corresponding to the pre-execution circuit is completed. It can be understood that the above-mentioned reading result is the IQ value and state, and the waveform library is triggered by the branch decision maker to call the recovery cache or the reusable cache waveform for branch recovery.

[0075] Specifically, branch recovery: when the feedback reading is completed, the final reading result is compared with the intermediate reading result. If the prediction is wrong, branch recovery is enabled. Figure 8This paper demonstrates a hardware implementation of waveform preparation with recovery functionality. The waveform generation unit locates a specific waveform based on a memory address and adds it to a waveform queue. The waveform is also cached for subsequent use. In one embodiment, for the Rx(θ) gate in the branch subcircuit, the corresponding recovery subcircuit uses Rx(-θ). The waveforms for these two operations can reuse Gaussian envelopes stored in onboard high-speed memory (DDR), reducing storage space. For two-qubit gates like the CZ gate or specialized single-qubit gates like the X gate, the waveforms do not change significantly between the branch subcircuit and the recovery subcircuit, allowing direct reuse. Based on this reusability and the temporal dependencies between executions, three waveform caches are designed for temporary storage before gate execution. The pre-execution cache stores waveforms that are not reusable in the branch subcircuit, such as gate operations; the reusable cache stores gate operations shared between the branch and recovery subcircuits; and the recovery cache stores waveforms unique to the recovery subcircuit. Because the time difference between executions (typically over 30ns) is greater than the waveform envelope-based parallel generation time (7 cycles, 28ns), waveforms in the pre-execution and restore buffers can be generated in an overlapping manner. Furthermore, the pre-execution and restore buffers can share the same memory space, reducing storage overhead.

[0076] Feedback signals between FPGAs are transmitted via a predictor-feedback signal interconnect module-backplane path. This process also includes trigger signals from a dynamic timing controller to ensure synchronization of communication between FPGAs. This design implements a scalable branch prediction method.

[0077] When the waveform preparation is used when the received predicted statistical probability is less than the set threshold, the waveform preparation module does not generate a feedback signal, waits for receiving the predicted statistical probability at the next moment, and performs the threshold judgment again.

[0078] This embodiment provides a Bayesian analysis based on branch prediction, where the timing of branch direction prediction is inherently uncertain. To support the dynamic execution of branch circuits, traditional static timing schemes need to be updated to conditional execution with dynamic timing. Designing an on-chip dynamic timing control scheme is necessary to modify the timing based on the predicted quantum state, allowing low-latency execution, avoiding alignment errors, and minimizing the idle time of the entire quantum system by adjusting the execution window.

[0079] like Figure 9As shown in (a) of Figure 1, executing quantum instructions typically requires shifting the execution of branch circuit instructions from being constrained by a fixed schedule to one controlled by feedback signals. For example, under static timing, the RX(π / 2) waveform executes at a fixed time, such as t = 200dt. In contrast, under dynamic timing, instructions are executed conditionally: upon receiving a feedback signal, the controller immediately issues the RX waveform for execution.

[0080] Figure 9 (b) shows the working strategy of the dynamic moment controller for the feedback signal provided by this embodiment. m When , the Bayesian predictor generates a probability prediction P predict , which is lower than the threshold. Therefore, the dynamic timing controller does not send a feedback signal and the branch circuit remains inactive. After the time window length L, at time t m+1 When a trigger is triggered, the Bayesian predictor updates its prediction. If the predicted value exceeds the threshold, the condition for executing the branch circuit is met. Therefore, the dynamic timing controller issues a feedback signal. If the feedback process is executed on the same FPGA, the branch decision maker immediately initiates execution of the branch circuit upon receiving the feedback signal. In the case of cross-FPGA feedback, the feedback signal is transmitted via the backplane to the branch decision maker on a different FPGA. Upon receiving the remote trigger, the other FPGA begins pre-execution of the branch circuit.

[0081] Within an FPGA, signal transmission between DACs and ADCs is significantly faster than between-FPGA transmissions via SerDes (e.g., 4ns vs. 48ns). However, due to bandwidth limitations of the Advanced eXtensible Interface (AXI), the number of DACs and ADCs that can be connected to a single FPGA is limited. Quantum waveforms typically contain a large number of "0" signals for idle operation, making them susceptible to compression. To address this issue, this embodiment employs an adaptive sampling rate approach to optimize on-chip bandwidth utilization. By dynamically adjusting the sampling rate based on the compressed waveform, this design reduces the data transmission burden, thereby maximizing the integration density of DACs on each FPGA.

[0082] When deploying the control waveform of the branch circuit, this embodiment generates high sampling rate analog-to-digital conversion data through waveform encoding. Before transmitting the data to the DAC module, a decoding unit is designed to process the encoded waveform from the waveform library. Figure 10As shown, the DAC has a 16-bit resolution and a sampling rate of 2 GSPS (200 million samples per second). For a basic gate set consisting of RX, RY, RZ, and CZ, the waveform data required for circuit execution includes a 30 ns XY waveform, a 60 ns CZ waveform, and a 2 μs readout waveform. After encoding, these waveforms are stored in an offline waveform library. When the branch decider receives feedback, it retrieves the required pre-encoded waveform from the waveform library. The waveform stream is then transmitted over the AXI bus and sent to the decoder for processing. The decoder uses a combination of run-length decoding and Huffman decoding. The waveform is first decoded using the run-length decoder, and then the original waveform is reconstructed using a Huffman table. Once decoded, the waveform is converted back to its original form and adjusted to the required DAC sampling rate. Finally, the decoded waveform is sent to the DAC module for further processing and conversion to analog signals, thereby ensuring higher DAC integration density per FPGA while maintaining the same transmission bandwidth.

Claims

1. A dynamic quantum feedback system based on branch prediction, characterized in that: comprising an FPGA, the FPGA comprising: The ADC and DAC modules are used to receive the waveform data of the current shot and process the waveform data of the branch circuit information corresponding to the prediction result to obtain a simulation waveform so as to pre-execute the branch circuit; Feedback controller, which is connected to the ADC and DAC modules via SerDes, and includes state classification, dynamic timing controller, and waveform preparation: The state classification is used to process waveform data to obtain states at k moments, compare the states at k moments with the state table to obtain the intermediate moment statistical probability that the states at k moments are all selected states, obtain the historical statistical probability of the selected state based on the state distribution of historical shots, and combine the historical statistical probability with the intermediate moment statistical probability to obtain the predicted statistical probability that the state is the selected state; The waveform is prepared to use the selected state as the prediction result when the received prediction statistical probability is greater than the set threshold, send a feedback signal to the dynamic timing controller, and after receiving the feedback signal through the dynamic timing controller, send the waveform data of the branch circuit information corresponding to the prediction result to the ADC and DAC modules.

2. The dynamic quantum feedback system based on branch prediction according to claim 1, characterized in that The state classification includes a stream adapter, a parameter register, a demodulator, a demodulation result queue, a history branch register, a state table and a Bayesian prediction model; The stream adapter is used to collect and process the waveform data in the time window to obtain the real part and the imaginary part of the waveform data, and send the real part and the imaginary part of the waveform data to the demodulator; The parameter register is used to send the quantum bit physical parameters to the solver; The demodulator is used to demodulate the real and imaginary parts of the waveform data and the quantum bit physical parameters together to obtain the IQ coordinate value of the waveform at each moment in the time window; The demodulation result queue is used to compare the IQ coordinate values ​​at different times with the distance of the state 0 or 1 to obtain the state at different times, and send the state at different times to the historical branch register; The historical branch register is used to receive the status of the historical moment and the current time window, thereby obtaining the status of the latest k moments, and sending the status of the latest k moments to the state table; The state table is used to obtain the intermediate moment statistical probability that the states at k moments are all the selected states based on the states at the latest k moments received through the correspondence between the states at k moments and the statistical probabilities at the intermediate moments; The Bayesian prediction model is used to combine the historical statistical probability of the state being the selected state in the historical period with the intermediate moment statistical probability to obtain the predicted statistical probability of the state being the selected state.

3. The dynamic quantum feedback system based on branch prediction according to claim 1, characterized in that When the waveform preparation module is used for receiving a predicted statistical probability that is less than a set threshold, the waveform preparation module does not generate a feedback signal, waits for receiving the predicted statistical probability at the next moment, and performs a threshold judgment again.

4. The dynamic quantum feedback system based on branch prediction according to claim 1, characterized in that The waveform preparation includes a branch decision maker, an operation table, a waveform library, a waveform sequence, a decoder and a feedback signal interconnection; The branch decision maker is used to compare the predicted statistical probability with a set threshold value. When the received predicted statistical probability is greater than the set threshold value, a feedback signal is sent to the dynamic timing controller, and the feedback signal is received through the feedback signal interconnection. The prediction result is then sent to the operation table to find the address of the pre-executed branch circuit corresponding to the selected state. Based on the found address, the corresponding waveform is obtained through the waveform library. The corresponding waveform is decoded by the decoder to obtain waveform data carrying the pre-executed branch circuit information. The waveform data carrying the pre-executed branch circuit information is transmitted to the ADC and DAC modules through the JESD interface.

5. The dynamic quantum feedback system based on branch prediction according to claim 4, characterized in that: It also includes a data bus and a backplane. If another FPGA needs to be triggered to execute the corresponding branch circuit, the dynamic timing controller sends feedback information to the branch decision maker of another FPGA through the data bus and the backplane, and the corresponding branch circuit is pre-executed through the other FPGA branch decision maker.

6. The dynamic quantum feedback system based on branch prediction according to claim 4, characterized in that The waveform library includes a waveform generation unit and a cache storage unit, and the cache storage unit includes a pre-execution cache, a reusable cache and a recovery cache; The waveform generating unit is used to retrieve a corresponding waveform from a pre-execution cache and a reusable cache based on the received search address, and send the retrieved waveform to the decoder; The reusable cache and recovery cache are also used to trigger the waveform library to call the recovery cache or reusable cache waveform for branch recovery through the branch decision maker when the prediction result is inconsistent with the read result after the read process is completed.

7. The dynamic quantum feedback system based on branch prediction according to claim 4, characterized in that: The decoder is used to decode the corresponding waveform through a run-length decoder, and then reconstruct the decoding result through Huffman decoding to obtain waveform data carrying pre-execution branch circuit information.

8. The dynamic quantum feedback system based on branch prediction according to claim 1, characterized in that: The ADC and DAC module includes an ADC submodule and a DAC submodule; The ADC submodule includes an ADC core and a digital downsampler, which sequentially captures the waveform data of the current shot through the ADC core and the digital downsampler to obtain a low-frequency waveform; The DAC submodule includes an interpolation module and a DAC core, and the waveform data outputted carrying the pre-executed branch circuit information is sequentially interpolated by the module and the DAC core to obtain a simulation waveform.

9. The dynamic quantum feedback system based on branch prediction according to claim 8, characterized in that It also includes a clock management module, which is used to generate a reference clock, and synchronize the clocks of the ADC submodule and the DAC submodule through the generated reference clock.

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