PCB (Printed Circuit Board) welding spot defect detection method, equipment and medium thereof

Abstract

The invention relates to the technical field of PCB detection, in particular to a PCB welding spot defect detection method and device and a medium thereof. The method comprises the following steps: acquiring a PCB welding spot image, preprocessing the PCB welding spot image to obtain a data set, and dividing the data set into a training set, a test set and a verification set; a YOLOv8n detection model is constructed, the YOLOv8n detection model is improved, and the improvement comprises the following steps that a backbone network part of the YOLOv8n detection model is replaced with a Faster Net network module with the number of layers reduced; a Head module of the YOLOv8n detection model is replaced by an LD-Head module; inputting the training set and the verification set into the improved YOLOv8n detection model for training to obtain a trained YOLOv8n detection model; the test set is tested through the trained YOLOv8n detection model, a test result is obtained, and PCB welding spot defect detection is completed, the detection precision of the PCB welding spot defects is improved, the network model is lightened, and deployment is convenient.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB detection, and particularly to a method, device and medium for detecting PCB solder joint defects. Background Art

[0002] A PCB (Printed Circuit Board) printed circuit board is a carrier and connection bridge for electronic components in modern electronic products. With the continuous progress of modern technology and the continuous expansion of application fields, the quality and performance of PCBs should be continuously improved to meet the requirements of new devices for high performance, long service life and low cost. In some specific places, some through-hole components in the PCB manufacturing process need to be manually welded, resulting in defects such as tip pulling, less solder, more solder, bridging, missed soldering, and too much rosin at the solder joints of some through-hole components on some PCBs. These welding defects will directly affect the quality of electronic products, reduce the service life of PCBs, and even affect the performance of PCBs. Therefore, research on defect detection of PCB solder joints is required.

[0003] Initially, manual observation was the main method for detecting the quality of solder joints, but this method was inefficient and prone to human errors. Compared with the manual observation method, defect detection based on machine vision can objectively and accurately evaluate the quality. Traditional machine vision detection methods rely on the fact that defects are easy to identify themselves, such as texture information, color features, target background, foreground threshold differences and other features. These methods require manually designing feature detection models for specific detection targets, and the robustness of the models is poor. In recent years, deep learning algorithms have been widely used in fields such as object detection, object recognition, and semantic segmentation of images. Many scholars have applied deep learning to the field of PCB defect detection. Deep learning algorithms are divided into two-stage detection and single-stage detection based on different requirements. The Faster Region Convolutional Neural Network algorithm (Faster-RCNN) is a typical representative of two-stage detection algorithms. The typical representatives of single-stage detection algorithms are the SSD and YOLO series algorithms. Although the current networks can be used in the defect detection of solar panels, their accuracy still has a large room for improvement, and the detection models are restricted by hardware resources and are not easy to deploy. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, the present invention provides a method for detecting PCB solder joint defects, which improves the detection accuracy of PCB solder joint defects and lightweightens the network model for easy deployment.

[0006] According to the method for detecting PCB solder joint defects of the embodiments of the present invention, the method includes the following steps:

[0007] S1. Obtain the PCB solder joint image, preprocess the PCB solder joint image to obtain a data set, and divide the data set into a training set, a test set, and a validation set;

[0008] S2. Construct a YOLOv8n detection model and improve the YOLOv8n detection model. The improvement includes the following steps:

[0009] Replace the backbone network part of the YOLOv8n detection model with a FasterNet network module with reduced layers;

[0010] Replace the Head module of the YOLOv8n detection model with an LD-Head module;

[0011] S3. Input the training set and the validation set into the improved YOLOv8n detection model for training to obtain the trained YOLOv8n detection model;

[0012] S4. Use the trained YOLOv8n detection model to test the test set to obtain test results, and complete the detection of PCB solder joint defects.

[0013] The beneficial effects of the present invention are as follows.

[0014] 1. The PCB solder joint defect detection method of the present invention makes the PCB solder joint defect data required for the experiment better meet the experimental environment by constructing a data set, which is beneficial to the improvement of detection accuracy and makes up for the problem of less research on PCB solder joint defect detection currently.

[0015] 2. The PCB solder joint defect detection method of the present invention replaces the backbone network part of the YOLOv8n detection model with a FasterNet network module with reduced layers, which is beneficial to extracting rich solder joint defect feature information while reducing the complexity of the model and improving the generalization ability of the model. Compared with the original YOLOv8n model, Recall and mAP of the improved backbone network part are increased by 3.1% and 0.1% respectively, and the computational complexity of the model is decreased by 10%;

[0016] 3. The PCB solder joint defect detection method of the present invention replaces the Head module of the YOLOv8n detection model with an LD-Head module, introduces the concept of a shared convolutional layer, reduces the computational amount of model convolutional operations, ensures the lightweight of the model, and facilitates model deployment. Compared with the original YOLOv8n model, Recall and mAP are increased by 2.9% and 1.2% respectively, and the model computational complexity is reduced by 19.8%.

[0017] According to an embodiment of the present invention, in the step S1, the preprocessing sequentially includes steps of cropping, rotating, image enhancement, and defect annotation.

[0018] According to an embodiment of the present invention, in step S2, the backbone network includes: an embedding module, at least one FasterNet Block structure module, a merging module, and an SPPF module.

[0019] According to an embodiment of the present invention, the LD-Head module includes three 1*1 Conv units, two 3*3 Conv units, and at least three Conv_CLs units;

[0020] A Scale unit is further provided at the output end of each of the Conv_CLs units.

[0021] According to an embodiment of the present invention, the number of the FasterNet Block structure modules is two, and each FasterNet Block structure is composed of a 3*3 PConv unit, two 1*1 Conv units, a BN unit, and a ReLU unit

[0022] According to an embodiment of the present invention, an LSKA attention mechanism is added to the SPPF module to be fused into an SPPF-LSKA module. The LSKA attention mechanism first decomposes a large-kernel depth convolution into two smaller-kernel depth convolutions, and then decomposes a large-kernel dilated depth convolution into two smaller-kernel dilated depth convolutions;

[0023] Among them, the output formula of the LSKA attention mechanism is:

[0024]

[0025] A C =W 1×1 *Z C (5)

[0026]

[0027] Among them, * and represent convolution and Hadamard product respectively, F is the mapping of the input feature, C is the number of input channels, H and W are the height and width of the feature map respectively, k represents the receptive field of the kernel W, d represents the dilation rate, Z C is the output obtained by convolving the input feature map with the kernel W of size k×k, A C is the attention map, which is obtained by convolving the kernel W of size 1×1 with Z C , is the final output of the LSKA attention mechanism, which is obtained by the Hadamard product of the attention map A C and the input feature map F C .

[0028] After adding the LSKA attention mechanism to the SPPF module of the present invention, the focus of the detection model on key feature information and the multi-scale feature extraction ability are enhanced. Compared with the original YOLOv8n model, the Precision, Recall, and mAP are increased by 4.3%, 3.9%, and 3.8% respectively.

[0029] According to an embodiment of the present invention, an MHSA multi-head self-attention module is added after the SPPF-LSKA module, which enhances the model's ability to extract small target features. Compared with the original YOLOv8n model, the Recall and mAP are increased by 6.3% and 3.7% respectively.

[0030] According to an embodiment of the present invention, the construction of the MHSA multi-head self-attention module includes: performing H groups of scaled dot-product self-attention operations on the input sequence in parallel to obtain multiple groups of outputs, and the calculation formula is:

[0031] MultiHead(Q,K,V)=Concat(H1,…,H h )W O (8)

[0032] H i =Attention(QW i Q ,KW i K ,VW i V ) (9)

[0033] where H i represents the calculation result of the i-th self-attention operation, W i Q , W i K , W i V respectively represent the trainable parameter matrices of the i-th head, h represents the number of groups of self-attention operations, W O represents the projection matrix of the output, Q is the query matrix, K is the key matrix, and V is the value matrix.

[0034] A computer device according to an embodiment of the present invention includes:

[0035] A processor;

[0036] A memory for storing executable instructions;

[0037] wherein, the processor is used to read the executable instructions from the memory and execute the executable instructions to implement the PCB solder joint defect detection method as described above.

[0038] A computer-readable storage medium according to an embodiment of the present invention, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the PCB solder joint defect detection method as described above.

[0039] Other features and advantages of the present invention will be described in the following specification, and in part will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification, claims, and drawings.

[0040] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, details are described as follows. Description of the Drawings

[0041] The present invention will be further described below in conjunction with the drawings and embodiments.

[0042] Figure 1 It is a schematic flowchart of the method according to Embodiment 1 of the present invention.

[0043] Figure 2 It is an image for making a PCB solder joint defect data set according to Embodiment 1 of the present invention.

[0044] Figure 3 It is a schematic diagram of the overall structure of the improved YOLOv8n detection model according to Embodiment 1 of the present invention.

[0045] Figure 4 It is a schematic diagram of the improved backbone network structure according to Embodiment 1 of the present invention.

[0046] Figure 5 It is a schematic diagram of the LD-head module structure according to Embodiment 1 of the present invention.

[0047] Figure 6 It is a schematic diagram of the SPPF-LSKA module structure according to Embodiment 1 of the present invention.

[0048] Figure 7 It is a framework diagram of the LSKA attention mechanism according to Embodiment 1 of the present invention.

[0049] Figure 8 It is a framework diagram of the multi-head self-attention mechanism according to Embodiment 1 of the present invention.

[0050] Figure 9 It is a schematic diagram of the computer device structure according to Embodiment 2 of the present invention.

[0051] In the figure, 10 is a computer device; 1002 is a processor; 1004 is a memory; 1006 is a transmission device. Detailed Embodiments

[0052] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention.

[0053] Embodiment 1

[0054] The embodiment of the present application provides a method for detecting PCB solder joint defects, as Figure 1 shown, the method includes the following steps:

[0055] S1, Obtain the PCB solder joint image, preprocess the PCB solder joint image to obtain a data set, and divide the data set into a training set, a test set, and a validation set; the preprocessing sequentially includes steps of cropping, rotating, image enhancement, and defect annotation.

[0056] For example, use a camera to take pictures of the produced PCB board to obtain the PCB solder joint image, randomly crop the PCB solder joint image, horizontally or vertically rotate the cropped pictures to enrich the pictures in the data set; use Gaussian noise and strong light interference to blur the image to enhance the image, see Figure 2 shown, use the LabelImg tool to annotate the enhanced image data, and annotate the defects in the image. After the annotation is completed, divide it into a training set, a test set, and a validation set according to the ratio of 8:1:1.

[0057] In this embodiment, 2000 PCB solder joint images are obtained, and the number increases to 10000 after preprocessing, that is, after the data set is divided, there are 8000 in the training set, 1000 in the test set, and 1000 in the validation set.

[0058] S2, Build a YOLOv8n detection model, and improve the YOLOv8n detection model. The improvement includes the following steps:

[0059] Replace the backbone network part of the YOLOv8n detection model with a FasterNet network module with reduced layers, ensuring that the YOLOv8n detection model can extract rich solder joint feature information while reducing the complexity of the model and improving the generalization ability of the model.

[0060] Replace the Head module of the YOLOv8n detection model with an LD-Head module to reduce the complexity of the YOLOv8n detection model of the detection head, so as to reduce the computational amount and the number of parameters of the detection head and ensure the lightweight of the model.

[0061] S3, Input the training set and the validation set into the improved YOLOv8n detection model for training to obtain a trained YOLOv8n detection model.

[0062] S4. Use the trained YOLOv8n detection model to test the test set, obtain the test results, and complete the detection of PCB solder joint defects.

[0063] The YOLOv8n detection model includes a backbone network (Backbone module), a Neck module, and a Head module. The backbone network is used to extract multi-scale features, the Neck module is used to fuse the multi-scale features extracted by the backbone network, and the Head module is used to perform regression prediction on the multi-scale features fused by the Neck module. Improve the YOLOv8n detection model. The improved YOLOv8n detection model is as Figure 3 shown. The improved backbone network includes: an Embedding module, at least one FasterNet Block structure module, a Merging module, and an SPPF (Fast Spatial Pyramid Pooling layer) module. FasterNet Block structure module. Specifically, the number of FasterNet Block structure modules is two, which can further reduce the computational complexity of the model while ensuring the network detection accuracy.

[0064] As Figure 4 shown, each FasterNet Block structure consists of a 3*3 PConv unit, two 1*1 Conv units, a BN unit, and a ReLU unit. Among them, the most important part is the partial convolution PConv unit (PartialConvolution). The PConv unit only uses Conv (Convolution) to extract features for some input channels, and uses the first or last continuous channel as the representative of the entire feature map for calculation, avoiding the increase in FLOPs caused by frequent memory access. The FLOPs of the PConv unit are expressed as:

[0065]

[0066] where h is the height of the output feature map, w is the width of the output feature map, k is the size of the convolution kernel, and c p is the number of output channels to which the convolution kernel belongs. When c p is only one-fourth of the regular c, the FLOPs of PConv are only one-sixteenth of the regular Conv, and the memory access amount Q of PConv is:

[0067]

[0068] At this time, the memory access amount Q of PConv is only one-fourth of the regular Conv. PConv only uses c p channels for spatial feature extraction, keeps the remaining channels unchanged, and does not delete (c - cp ) channels.

[0069] Compared with the main part of the FasterNet benchmark model, the improved YOLOv8n detection model reduces two layers of FasterNet Block structure modules and two layers of merging modules, reducing the size of the original model to half of the original model to reduce the computational complexity and memory call of the model. Therefore, the introduction of the FasterNet network module is conducive to extracting rich solder joint defect feature information while reducing the complexity of the model and improving the generalization ability of the model, thereby facilitating the deployment of the model on resource-constrained devices.

[0070] like Figure 5 As shown, the LD-Head module includes three 1*1 Conv units, two 3*3 Conv units and at least three Conv_CLs units; a Scale unit is also provided at the output end of each Conv_CLs unit. Specifically, after the LD-Head module receives the features of three different scales output by the neck, the features of three different scales are respectively input into the corresponding 1*1 Conv units to adjust the number of channels, unify the number of input channels, and then aggregate all feature layers into the 3*3 Conv unit. After two 3*3 Conv units, the target category features and spatial feature branches are extracted. In addition, in order to adapt to the different target scales of different detection heads, a Scale unit is provided at the output end of each Conv_CLs unit to perform feature scaling and enhance the detection capability of multi-scale features.

[0071] It should be noted that the two 3*3 Conv units are shared convolutional layers, which can reduce the model complexity of the detection head, thereby reducing the amount of calculation and parameters of the detection head, and do not reduce the detection accuracy of the model. The application of shared convolutional layers can avoid the problem of frequent calls to convolutional layers causing a sudden increase in the amount of calculation, and overall reduce the complexity of the model, improve the running speed of the model, make the model lightweight, facilitate the wide application of the model, and further improve the classification and positioning capabilities of the detection head. The application of the LD-Head module can not only reduce the amount of calculation of the model and improve the network running speed, but also improve the detection accuracy of the model and strengthen the multi-scale feature detection capabilities of PCB solder joints.

[0072] like Figure 6As shown in the figure, the LSKA attention mechanism is added to the SPPF module and integrated into the SPPF-LSKA module, which can improve the model's focus on key feature information and multi-scale feature extraction ability. After the LSKA attention mechanism is added to the connection layer (Concat), compared with introducing the LSKA attention mechanism after the third pooling layer in the past, the improvement of the model detection accuracy is higher. The LSKA attention mechanism first decomposes a large-kernel depth convolution into two smaller-kernel depth convolutions, and then decomposes a large-kernel dilated depth convolution into two smaller-kernel dilated depth convolutions. The way of large-kernel decomposition can alleviate the problem of quadratic growth of computational cost and strengthen the model's multi-scale feature extraction ability.

[0073] Furthermore, as Figure 7 shown in the figure, first, two one-dimensional small-kernel depth convolutions (DW-Conv) can extract multi-scale information features from horizontal and vertical angles respectively to generate a preliminary attention map to ensure that the model focuses more on the important parts of the image. Then, after obtaining the preliminary attention map, two one-dimensional small-kernel dilated depth convolutions (DW-D-Conv) further extract features using different dilation rates. Finally, the features obtained are fused through a convolutional layer (Conv) to generate the final attention map. Finally, an element-wise multiplication operation is performed between the attention map and the original input feature map, and the original feature map is weighted according to the attention map to highlight important features and suppress unimportant features, so as to enhance the network's ability to capture important features. The output formula of the LSKA attention mechanism is:

[0074]

[0075]

[0076] Among them, * and represent convolution and Hadamard product respectively, F is the mapping of the input feature, C is the number of input channels, H and W are the height and width of the feature map respectively, k represents the receptive field of the kernel W, d represents the dilation rate, Z C is the output obtained by convolving the input feature map with the kernel W of size k×k, A C is the attention map, which is obtained by convolving the kernel W of size 1×1 with Z C , is the final output of the LSKA attention mechanism, which is obtained by the Hadamard product of the attention map A C and the input feature map F C .

[0077] It should be noted that the LSKA attention mechanism can achieve performance comparable to that of the standard LKA attention mechanism, while the computational complexity and memory usage are much smaller than those required by the standard LKA module. Moreover, as the kernel size in the LSKA module increases, the attention mechanism tends to focus on the shape of the object rather than the texture.

[0078] In the embodiment, a MHSA multi-head self-attention module is added after the SPPF-LSKA module to enhance the model's ability to extract small target features.

[0079] Specifically, Figure 8 As shown in the figure, first, the input data sequence is encoded into an input matrix, and then linearly transformed with three trainable parameter matrices to obtain three projection matrices (Q, K, V), where Q is the query matrix, K is the key matrix, and V is the value matrix. The scaling dot product attention process is: the query matrix Q and the key matrix K are first dot-producted to obtain a similarity matrix, and then selective scaling is performed to divide each element in the matrix by the dimension size of the K matrix. And extract the area of ​​interest to reduce interference factors, then use the softmax function to perform normalization to get the weight matrix, and finally dot product the weight matrix with the V matrix to get the weighted sum. The calculation formula is as follows:

[0080]

[0081] The essence of the MHSA multi-head self-attention module is to perform H groups of scaled dot product self-attention operations on the original input sequence in parallel, and then obtain multiple groups of outputs, thereby obtaining richer feature information and improving the model's ability to pay attention to different features. The parallel operation of multiple groups of self-attention mechanisms also speeds up the training process and improves the generalization performance of the model. Its principle is derived from the self-attention mechanism, and the formula is as follows:

[0082] The construction of the MHSA multi-head self-attention module includes: performing H groups of scaled dot product self-attention operations in parallel on the input sequence to obtain multiple groups of outputs, thereby obtaining richer feature information and improving the model's ability to pay attention to different features. In addition, parallel operations also speed up the training process and improve the generalization performance of the model.

[0083] The calculation formula is as follows:

[0084] MultiHead(Q,K,V)=Concat(H1,…,H h )W O (8)

[0085] H i =Attention(QW i Q ,KW i K ,VWi V ) (9)

[0086] Among them, H i represents the calculation result of the i-th self-attention operation, and W i Q , and W i K , and W i V respectively represent the trainable parameter matrices of the i-th head, h represents the number of groups of multiple self-attention operations, and W O represents the output projection matrix.

[0087] To further verify the advantages of the MHSA attention mechanism compared with other attention mechanisms, comparative experiments with different attentions were conducted, including the channel attention mechanism SE (Squeeze-and-Excitation), the parameter-free attention mechanism SimAM, the channel and spatial combined attention mechanism BAM (Bottleneck Attention Module), the cross-channel attention mechanism ShuffleAttention, and the convolution and attention fusion module CAFM (Convolution and Attention Fusion Module). The experiments were all carried out on the backbone of the YOLOv8n model, and the experimental results are shown in Table 1.

[0088] Table 1 Experimental comparison of different attention mechanisms

[0089]

[0090] As can be seen from Table 1, the MHSA attention mechanism proposed in this embodiment is higher than other mainstream attention mechanisms in terms of the detection accuracy mAP@0.5. Compared with the recently open-sourced convolution and attention fusion module CAFM, the MHSA attention mechanism is 2.8% higher than the CAFM module in terms of detection accuracy, and the detection speed is better than the CAFM module. Adding the channel attention module SE, the mAP@0.5 of the model can be improved by 1.3%. When adding the BAM module that combines channel attention and spatial attention, the accuracy of the network decreases by 0.9% compared with the YOLOv8 network that only adds channel attention. Adding the cross-channel attention module ShuffleAttention, the mAP@0.5 of the model is improved by 1.2%. It can be seen that the addition of channel attention improves the accuracy of the network, but the addition of global multi-head attention can greatly improve the detection accuracy of this experiment, and the FPS value decreases very little, ensuring the feasibility of real-time detection.

[0091] To verify the impact of each improvement strategy on the model detection performance, ablation experiments were conducted based on the PCB solder joint defect detection dataset. The experimental data is shown in Table 2, and a trained PCB solder joint defect detection model was obtained.

[0092] The experimental results are shown in Table 2. It can be seen that compared with the baseline module, the improved module provided in this implementation has a better effect on improving the detection accuracy of PCB solder joint defects.

[0093] Table 2 Ablation Experiment Results

[0094]

[0095] A performance comparison experiment was conducted between the improved YOLOv8n model and the current mainstream detection models; in order to evaluate the superior performance of the network model, the improved algorithm was compared with the current mainstream object detection models. The experimental models include 7 object detection models such as the YOLO series of YOLO5 - YOLOv9 and the two - stage anchor - box model Faster R - CNN.

[0096] As can be seen from Table 3 in the final result, the improved algorithm has the highest accuracy, recall rate, and mAP@0.5 compared with the other seven object detection models. The accuracy of the two - stage object detection algorithm Faster R - CNN is much lower than that of the improved algorithm, and the detection accuracy mAP@0.5 is 6.5% lower than that of the improved algorithm, and the computational complexity is huge, with an FPS of only 13.0, far from meeting the requirements of real - time detection. Compared with other YOLO series algorithms, namely YOLOv5, YOLOv7, YOLOv8, and YOLOv9, the average detection accuracy of the improved algorithm is increased by 6.5%, 3.5%, 7.8%, and 5.7% respectively, and the computational complexity of the improved network model is relatively small, with an FPS that can reach 94.9, meeting the requirements of real - time detection. In summary, the improved algorithm can greatly improve the detection accuracy of the model and reduce the computational complexity of the model while slightly reducing the FPS value, and is convenient to be deployed on resource - constrained devices.

[0097] Table 3 Comparative Experiments of Each Detection Model

[0098]

[0099] In summary, the PCB solder joint defect detection method of the present invention has the following advantages:

[0100] 1. By constructing a dataset, the PCB solder joint defect data required for the experiment can better meet the experimental environment, which is conducive to improving the detection accuracy and makes up for the problem of less research on PCB solder joint defect detection currently.

[0101] 2. By replacing the backbone network part of the YOLOv8n detection model with the FasterNet network module with reduced layers, it is beneficial to extract rich solder joint defect feature information. At the same time, the complexity of the model is reduced, and the generalization ability of the model is improved. Compared with the original YOLOv8n model, the Recall and mAP of the improved backbone network part are increased by 3.1% and 0.1% respectively, and the computational complexity of the model is decreased by 10%.

[0102] 3. By replacing the Head module of the YOLOv8n detection model with the LD-Head module, the concept of a shared convolutional layer is introduced, reducing the computational amount of the model's convolutional operations and ensuring the lightweight of the model. Compared with the original YOLOv8n model, the Recall and mAP are increased by 2.9% and 1.2% respectively, and the computational complexity of the model is reduced by 19.8%.

[0103] 4. By adding the LSKA attention mechanism to the SPPF module, the focus of the detection model on key feature information and the multi-scale feature extraction ability can be enhanced. Compared with the original YOLOv8n model, the Precision, Recall, and mAP are increased by 4.3%, 3.9%, and 3.8% respectively.

[0104] 5. By adding the MHSA multi-head self-attention module, the ability of the model to extract small target features is enhanced. Compared with the original YOLOv8n model, the Recall and mAP are increased by 6.3% and 3.7% respectively.

[0105] Example 2

[0106] The embodiment of the present application provides a computer device, which includes a processor and a memory. At least one instruction or at least one program segment is stored in the memory, and the at least one instruction or the at least one program segment is loaded and executed by the processor to implement a PCB solder joint defect detection method as provided in the above method embodiment.

[0107] Figure 9 The hardware structure diagram of a device for implementing a PCB solder joint defect detection method provided by the embodiment of the present application is shown. The device can participate in forming or include the device or system provided by the embodiment of the present application. As Figure 9As shown, the computer device 10 may include one or more processors 1002 (the processors may include, but are not limited to, processing devices such as microprocessor MCUs or programmable logic devices FPGAs), a memory 1004 for storing data, and a transmission device 1006 for communication functions. In addition, it may further include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply, and / or a camera. Those of ordinary skill in the art can understand that Figure 9 the structure shown is only schematic and does not limit the structure of the above electronic device. For example, the computer device 10 may further include more or fewer components than Figure 9 shown therein, or have a different configuration from Figure 9 that shown.

[0108] It should be noted that the above one or more processors and / or other data processing circuits can generally be referred to as "data processing circuits" herein. The data processing circuit can be embodied in whole or in part as software, hardware, firmware, or any combination thereof. In addition, the data processing circuit can be a single independent processing module, or be incorporated in whole or in part into any one of the other elements in the computer device 10 (or mobile device). As involved in the embodiments of the present application, the data processing circuit is a kind of processor control (such as the selection of a variable resistor terminal path connected to an interface).

[0109] The memory 1004 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to a PCB solder joint defect detection method in the embodiments of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 1004, that is, implements the above-mentioned method. The memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, the memory 1004 may further include a memory remotely set relative to the processor, and these remote memories can be connected to the computer device 10 through a network. Examples of the above network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0110] The transmission device 1006 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by a communication provider of the computer device 10. In one example, the transmission device 1006 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 1006 can be a Radio Frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0111] The display can be, for example, a touch screen type Liquid Crystal Display (LCD), which enables a user to interact with the user interface of the computer device 10 (or mobile device).

[0112] Embodiment 3

[0113] The embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium can be disposed in a server to store at least one instruction or at least one segment of a program related to a PCB solder joint defect detection method in the method embodiment. The at least one instruction or the at least one segment of the program is loaded and executed by the processor to implement the PCB solder joint defect detection method provided in the above method embodiment.

[0114] Optionally, in this embodiment, the above storage medium can be located in at least one of multiple network servers in a computer network. Optionally, in this embodiment, the above storage medium can include, but is not limited to: various media that can store program codes such as a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk, or an optical disc.

[0115] Embodiment 4

[0116] The embodiment of the present invention further provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes a PCB solder joint defect detection method provided in the above various optional implementation manners.

[0117] It should be noted that the above order of the embodiments of the present application is only for description and does not represent the superiority or inferiority of the embodiments. And the above specific embodiments of the present application have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0118] Each embodiment in the present application is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, equipment, and storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments.

[0119] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware or can be completed by instructing the relevant hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk, an optical disc, etc.

[0120] Taking the above ideal embodiments of the present invention as an inspiration, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A method for detecting PCB solder joint defects, characterized in that, The method includes the following steps: S1. Obtain a PCB solder joint image, preprocess the PCB solder joint image to obtain a data set, and divide the data set into a training set, a test set, and a validation set; S2. Construct a YOLOv8n detection model and improve the YOLOv8n detection model. The improvement includes the following steps: Replace the backbone network part of the YOLOv8n detection model with a FasterNet network module with reduced layers; Replace the Head module of the YOLOv8n detection model with an LD-Head module; S3. Input the training set and the validation set into the improved YOLOv8n detection model for training to obtain the trained YOLOv8n detection model; S4. Use the trained YOLOv8n detection model to test the test set to obtain a test result, and complete the detection of PCB solder joint defects.

2. The PCB solder joint defect detection method according to claim 1, wherein, In step S1, the preprocessing sequentially includes steps of cropping, rotating, image enhancement, and defect annotation.

3. The PCB solder joint defect detection method according to claim 1, wherein In step S2, the backbone network includes: an embedding module, at least one FasterNet Block structural module, a merging module, and an SPPF module.

4. The PCB solder joint defect detection method according to claim 1, wherein The LD-Head module includes three 1*1 Conv units, two 3*3 Conv units, and at least three Conv_CLs units; A Scale unit is further provided at the output end of each Conv_CLs unit.

5. The PCB solder joint defect detection method according to claim 3, characterized in that, The number of the FasterNet Block structural modules is two, and each FasterNet Block structure is composed of a 3*3 PConv unit, two 1*1 Conv units, a BN unit, and a ReLU unit.

6. The PCB solder joint defect detection method according to claim 3, wherein, Add an LSKA attention mechanism to the SPPF module and fuse it into an SPPF-LSKA module. The LSKA attention mechanism first decomposes a large-kernel depth convolution into two smaller-kernel depth convolutions, and then decomposes a large-kernel dilated depth convolution into two smaller-kernel dilated depth convolutions; Among them, the output formula of the LSKA attention mechanism is: A C = W 1×1 * Z C (5) where * and represent convolution and Hadamard product respectively, F is the mapping of the input feature, C is the number of input channels, H and W are the height and width of the feature map respectively, k represents the receptive field of the kernel W, d represents the dilation rate, Z C is the output obtained by convolving the input feature map with the kernel W of size k×k, A C is the attention map, which is obtained by convolving the kernel W of size 1×1 with Z C ; is the final output of the LSKA attention mechanism, which is obtained by the Hadamard product of the attention map A C and the input feature map F C .

7. The PCB solder joint defect detection method according to claim 6, wherein Add an MHSA multi-head self-attention module after the SPPF-LSKA module.

8. The PCB solder joint defect detection method according to claim 7, wherein The construction of the MHSA multi-head self-attention module includes: Performing parallel H-group scaled dot-product self-attention operations on the input sequence to obtain multiple groups of outputs, and the calculation formula is: MultiHead(Q,K,V)=Concat(H1,…,H h )W O (8) H i = Attention(QW i Q ,KW i K ,VW i V )(9) Among them, H i represents the calculation result of the i-th self-attention operation, W i Q , W i K , W i V respectively represent the trainable parameter matrices of the i-th head, h represents the number of groups of multiple self-attention operations, W O represents the output projection matrix, Q is the query matrix, K is the key matrix, and V is the value matrix.

9. A computer device, characterized in that, Including: A processor; A memory for storing executable instructions; Among them, the processor is used to read the executable instructions from the memory and execute the executable instructions to implement the PCB solder joint defect detection method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is enabled to implement the PCB solder joint defect detection method according to any one of claims 1 to 8.

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