Chip on film and display device including same

Abstract

The invention relates to a chip on film and a display device including the same. The chip on film includes: a driver integrated circuit; an input pad portion including a first input pad connected to the driver integrated circuit and a second input pad separated from the driver integrated circuit; and an output pad portion including a first output pad connected to the driver integrated circuit, a second output pad directly connected to the second input pad, and a floating third output pad, the output pad portion being cut along the film cut line.

Description

Technical Field

[0001] The present disclosure relates to a chip on film and a display device including the same. Background Art

[0002] A display device includes a display panel in which a plurality of pixels are disposed and a driver integrated circuit (IC) that supplies driving signals to the pixels.

[0003] The driver IC may be mounted on a conductive film and then may be bonded to the display panel through a film on glass (FOG) bonding process. The conductive film on which the driver IC is mounted may be referred to as a chip on film (COF). The FOG bonding process is a process of applying heat and pressure to the chip on film COF using conductive balls for a certain period of time to bond the chip on film COF to the display panel. The conductive balls are compressed between the chip on film COF and the substrate by heat and pressure, and thus, the output pads of the chip on film COF are electrically connected to the signal pads of the display panel.

[0004] As the resolution of the display panel increases, the number of output pads of the chip on film COF increases. When a plurality of output pads are within a predetermined area, the alignment operation of the bonding process is difficult. Misalignment may cause bonding defects. Summary of the Invention

[0005] To overcome the above limitations of the related art, the present disclosure may provide a chip on film and a display device including the same that can reduce or prevent the occurrence of bonding defects even when it is difficult to perform an accurate alignment operation.

[0006] In addition, the present disclosure may provide a chip on film and a display device including the same in which the number of output pads exposed through the cross-sectional surface of the output pad portion can be reduced, thereby reducing or minimizing defects caused by metal migration.

[0007] In addition, the present disclosure may provide a chip on film and a display device including the same in which the uniformity of the bonding adhesive force corresponding to the output pad portion can be increased.

[0008] To achieve these advantages and other advantages and in accordance with the purpose of the present disclosure, as implemented and broadly described herein, a chip on film includes: a driver integrated circuit; an input pad portion including a first input pad connected to the driver integrated circuit and a second input pad separated from the driver integrated circuit; and an output pad portion including a first output pad connected to the driver integrated circuit, a second output pad directly connected to the second input pad, and a floating third output pad, the output pad portion being cut along a film cutting line.

[0009] In another aspect of the present disclosure, a display device includes: a display panel including a display area provided with pixels and a border area outside the display area; and a chip on film bonded to the border area, wherein the chip on film includes: a driver integrated circuit; an input pad portion including a first input pad connected to the driver integrated circuit and a second input pad separated from the driver integrated circuit; and an output pad portion including a first output pad connected to the driver integrated circuit, a second output pad directly connected to the second input pad, and a floating third output pad, and the output pad portion is cut along a film cutting line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0011] Figure 1 is a block diagram illustrating a display device according to the present embodiment;

[0012] Figure 2 is a diagram illustrating an example of electrically connecting a printed circuit board to a display panel through a chip on film according to the present embodiment;

[0013] Figure 3 is a diagram illustrating an example in which the output pad portion of the chip on film is connected to a test pad portion;

[0014] Figure 4 is a diagram illustrating the output pad portion of the chip on film cut along the film cutting line;

[0015] Figure 5 is a diagram illustrating a part of a cross-sectional surface of the output pad portion corresponding to the film cutting line; and

[0016] Figure 6 is a diagram illustrating an element for increasing the uniformity of the bonding adhesion corresponding to the output pad portion. DETAILED DESCRIPTION

[0017] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0018] The advantages, features, and methods for realizing the present disclosure will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is only defined by the scope of the claims.

[0019] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to describe the various embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals refer to the same elements. Throughout the specification, the same elements are denoted by the same reference numerals. When used herein, unless the term "only" is used, the terms "comprising," "having," "including," etc. imply that other parts may be added. When used herein, unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0020] Elements in the various embodiments of the present disclosure will be construed to include a range of errors even if not explicitly stated.

[0021] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "under," and "next to," one or more other parts may be provided between the two parts unless "exactly" or "directly" is used.

[0022] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0023] In the following description, when it is determined that a detailed description of a related known function or configuration will unnecessarily obscure the focus of the present disclosure, such detailed description will be omitted or may be provided briefly. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram illustrating a display device according to the present embodiment. Figure 2 is a diagram illustrating an example of electrically connecting a printed circuit board (PCB) to a display panel through a chip on film (COF) according to the present embodiment.

[0025] Refer to Figure 1 and Figure 2, the display device according to the present embodiment can be implemented as a flat panel display device such as a liquid crystal display (LCD) device, an electroluminescent display device, an electrophoretic display device, an electro-wetting display device, an organic light-emitting display device, or a quantum dot display device. In addition, the display device according to the present embodiment is not limited to a flat panel display device and can be implemented as various types such as a curved display device, a foldable display device, a rollable display device, and a transparent display device.

[0026] In the following embodiments, the display device may be described as a flat panel LCD device, but the inventive concept is not limited thereto.

[0027] The display panel 100 can be implemented with a glass substrate or a plastic substrate. A plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixel electrodes can be formed in the substrate of the display panel 100.

[0028] Based on the cross structure between the data lines DL and the gate lines GL, the pixels 101 can be arranged in a matrix type in the display panel 100. Each of the pixels 101 can include a thin film transistor (TFT), a pixel electrode connected to the TFT, and a storage capacitor.

[0029] In the display panel 100, the pixels 101 can configure a screen AA for displaying an input image. The screen AA can include a pixel array for displaying pixel data (hereinafter referred to as image data) DATA of the input image. The pixel array can include a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and a plurality of pixels. The pixels can be arranged in various types such as a matrix type, a stripe type, or a diamond type on the screen AA. Each pixel can include a red (R) pixel 101, a green (G) pixel 101, and a blue (B) pixel 101 to achieve colors, and may also include a white (W) pixel.

[0030] The pixel array can include a plurality of pixel columns and a plurality of pixel rows L1 to Ln intersecting the pixel columns. One pixel column can include pixels 101 arranged in the Y-axis direction. One pixel row can include pixels 101 arranged in the X-axis direction. One vertical period can be a frame period required to write the image data DATA of one frame to all the pixels 101 of the screen AA. One horizontal period can be a time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period can be a time required to write the image data DATA of one pixel row sharing the gate line GL to the pixels of one pixel row. In Figure 1 , the “D1 to D3” illustrated by circles can be data lines, and the “Gn-2 to Gn” can be gate lines.

[0031] In the display panel 100, when the area where the screen AA is set is called the display area DA, the outer area of the display area DA can be called the border area BZ. The border area BZ can be an area covered by an outer housing and may not display an image.

[0032] The display panel driver can include a source driver 110 and a gate driver 120. Based on the control of the timing controller 130, the display panel driver can write image data DATA into the pixels 101 of the display panel 100.

[0033] The source driver 110 can include a digital-to-analog converter (DAC). The DAC can receive the image data DATA and the source timing control signal DDC from the timing controller 130. The DAC can convert the image data DATA into a gamma-compensated voltage based on the source timing control signal DDC to generate a data voltage, and can supply the data voltage to the data lines DL during one horizontal period. The data voltage can be supplied to the data lines DL and then can be applied to the target electrodes of the pixels 101 through the TFTs. In an LCD device, the target electrode can be a pixel electrode, and in an electroluminescent display device, the target electrode can be the gate electrode of a driving element.

[0034] The source driver 110 can be set outside the screen AA in the display panel 100 and can be set within the border area BZ where no image is displayed. The source driver 110 can include one or more driver integrated circuits SIC.

[0035] The driver integrated circuit SIC can be mounted on a conductive film and then can be bonded to the border area BZ of the display panel 100 through a film-on-glass (FOG) bonding process. The conductive film on which the driver integrated circuit SIC is mounted can be called a chip-on-film (COF). The FOG bonding process is a process of applying heat and pressure to the chip-on-film COF for a certain time using conductive balls to bond the chip-on-film COF to the display panel 100. The conductive balls are compressed between the chip-on-film COF and the substrate by heat and pressure, and thus, the output pads of the chip-on-film COF are electrically connected to the signal pads of the display panel 100.

[0036] The signal pads of the display panel 100 can include first panel pads connected to the data link lines DLL and second panel pads connected to the gate link lines GLL. The data link lines DLL and the gate link lines GLL can be set in the border area BZ. The data link lines DLL can each be connected to the data lines DL. The gate link lines GLL can be connected to the gate driver 120.

[0037] The input pads of the chip - on - film COF can be connected to the signal lines of the printed circuit board CPCB through a bonding process. The timing controller 130 and the level shifter 140 can be mounted on the printed circuit board CPCB. The timing controller 130 can be connected to the level shifter 140 through a signal line and, in addition, can be connected to the input pads of the chip - on - film COF.

[0038] Under the control of the timing controller 130, the gate driver 120 can sequentially supply gate signals synchronized with the data voltage to the gate lines GL. The gate driver 120 can output a gate signal based on the gate timing control signal GDC transmitted through the gate link line GLL. The gate signal can simultaneously activate the pixels 101 of the pixel rows charged by the data voltage during at least one horizontal period. The gate driver 120 can include one or more gate shift registers. The gate shift register can output a gate signal while shifting the gate signal in a line - by - line / non - line - by - line scheme based on the gate timing control signal GDC. The gate signal can include one or more scan signals.

[0039] The gate driver 120 can be disposed outside the screen AA in the display panel 100 and can be formed in the border area BZ where no image is displayed.

[0040] The timing controller 130 can receive video data DATA and a timing signal synchronized with the video data DATA from the host system. The timing signal can include a vertical sync signal Vsync, a horizontal sync signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical sync signal Vsync can define a vertical period. The horizontal sync signal Hsync can define a horizontal period. The data enable signal DE can define the time during which the video data DATA is transmitted in the vertical period or the horizontal period. The vertical period and the horizontal period can be detected by a method of counting the data enable signal DE, and thus, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted.

[0041] The timing controller 130 can generate a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsynd, and DE received from the host system. The source timing control signal DDC can include a source sampling clock for sampling the image data DATA and a source output enable signal for setting the output timing of the data voltage.

[0042] The host system can be one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, an in-vehicle display system, a mobile device, and a wearable device. In the mobile device and the wearable device, the source driver 110, the timing controller 130, and the level shifter 140 can be integrated into one driver integrated circuit.

[0043] The level shifter 140 can convert the logic voltage of the gate timing control signal GDC having a first amplitude input from the timing controller 130 into a gate high voltage VGH or a gate low voltage VGL having a second amplitude greater than the first amplitude, and supply it to the gate driver 120 through a chip-on-film COF and a gate link line GLL. In the level shifter 140, the low logic voltage of the gate timing control signal GDC can be converted into the gate low voltage VGL, and the high logic voltage of the gate timing control signal GDC can be converted into the gate high voltage VGH.

[0044] The timing controller 130 can transmit the image data DATA and the source timing control signal DDC to the driver integrated circuit SIC through an internal interface circuit. The internal interface circuit can be implemented as an embedded clock point-to-point interface (EPI), but is not limited thereto.

[0045] Figure 3 FIG. is an example showing where the output pad portion of the chip-on-film is connected to the test pad portion. Figure 4 FIG. is an example showing the output pad portion of the chip-on-film cut along the film cutting line. Figure 5 FIG. is an example showing a part of the cross-sectional surface of the output pad portion corresponding to the film cutting line.

[0046] Refer to Figure 3 , according to the chip-on-film COF of the present embodiment, it can include a driver integrated circuit SIC, an input pad portion IPAD bonded to a printed circuit board, and an output pad portion OPAD bonded to a display panel.

[0047] The input pad portion IPAD can include a first input pad IPAD1 connected to the driver integrated circuit SIC and a second input pad IPAD2 not connected to the driver integrated circuit SIC. The first input pad IPAD1 can receive an EPI signal from the timing controller and transmit it to the driver integrated circuit SIC. The second input pad IPAD2 can receive a gate timing control signal from the level shifter and supply it to the second output pad OPAD2.

[0048] The output pad portion OPAD may include a first output pad OPAD1 connected to the driver integrated circuit SIC through a COF connection line, a second output pad OPAD2 directly connected to the second input pad IPAD2 through a COF connection line, and a third output pad OPAD3 that is floated and not connected to the COF connection line.

[0049] The third output pad OPAD3 may be disposed between the first output pad OPAD1 and the second output pad OPAD2 or between adjacent first output pads OPAD1 and may be in a floating state, thereby increasing the bonding margin. That is, even if the precise alignment operation is not performed between the chip-on-film COF and the display panel 100, the bonding defect between the output pad portion OPAD and the display panel 100 can be effectively reduced or prevented by the third output pad OPAD3 having a floating state.

[0050] To ensure the bonding margin, one or more first output pads may be disposed between adjacent third output pads OPAD3.

[0051] Referring to Figure 3 , a test process may be performed on the chip-on-film COF according to the present embodiment before the bonding process of bonding the printed circuit board to the display panel. The test process may be a process of testing whether the driver integrated circuit SIC and the COF connection line included in the chip-on-film COF are normal.

[0052] For the test process, the test pad portion TPAD may be connected to the output pad portion OPAD of the chip-on-film COF. The test pads included in the test pad portion TPAD may be connected to the first output pad OPAD1 and the second output pad OPAD2 of the output pad portion OPAD and may not be connected to the third output pad OPAD3. This may be because the third output pad OPAD3 has a floating state and is not connected to the COF connection line, so there is no need to test whether the connection is normal.

[0053] When the test process is completed, as shown in Figure 4 , the output pad portion OPAD of the chip-on-film COF may be cut along the film cutting line (i.e., the COF cutting line). At this time, since the lower end portion of the third output pad OPAD3 is spaced apart from the film cutting line by a certain interval DIS and is disposed inward from the film, the first output pad OPAD1 and the second output pad OPAD2 may be exposed to the outside in the cross-sectional surface of the output pad portion OPAD corresponding to the film cutting line, and the third output pad OPAD3 may not be exposed to the outside.

[0054] That is, as shown in Figure 5In this case, since the third output pad OPAD3 is not exposed to the outside on the cross-sectional surface of the output pad portion OPAD corresponding to the film cutting line, the number of output pads exposed through the cross-sectional surface of the output pad portion OPAD can be reduced. As a result, short circuit defects caused by metal migration occurring on the cross-sectional surface of the output pad portion OPAD can be reduced or minimized.

[0055] Figure 6 FIG. is an example showing an element for increasing the uniformity of the bonding adhesion corresponding to the output pad portion.

[0056] Refer to Figure 6 , the output pad portion OPAD of the chip on film COF cut along the film cutting line can be bonded to the signal pad portion of the border area BZ of the display panel 100 through the FOG bonding process.

[0057] The signal pad portion may include a plurality of first panel pads PD1 bonded to a plurality of first output pads OPAD1, a second panel pad PD2 bonded to a second output pad OPAD2, and a plurality of third panel pads PD3 bonded to a plurality of third output pads OPAD3.

[0058] The plurality of first panel pads PD1 may be connected to the data link line ( Figure 2 DLL). The data voltage output from the plurality of first output pads OPAD1 may be supplied to the data link line ( Figure 2 DLL) via the plurality of first panel pads PD1.

[0059] The second panel pad PD2 may be connected to the gate link line ( Figure 2 GLL). The gate timing control signal output from the second output pad OPAD2 may be supplied to the gate link line ( Figure 2 GLL) via the second panel pad PD2.

[0060] The plurality of third panel pads PD3 may be floating dummy pads. The plurality of third panel pads PD3 may be used for bonding to the plurality of third output pads OPAD3 and may not be connected to other signal lines.

[0061] The reason for additionally bonding the third output pad OPAD3 to the third panel pad PD3 may be to increase the stability of the FOG bonding process performed simultaneously on the output pad portion OPAD and the signal pad portion. Unless the stability of the FOG bonding process is reduced, the third panel pad PD3 used only for bonding may be omitted.

[0062] For the bonding process between the output pad portion OPAD and the display panel 100, a first alignment key AKEY1 may be included in the chip on film COF, and a second alignment key AKEY2 may be included in the display panel 100. The first alignment key AKEY1 may be the same as or similar to the second alignment key AKEY2.

[0063] In the chip on film COF, the first alignment key AKEY1 may be disposed near the output pad portion OPAD in the horizontal (X-axis) direction. In the display panel 100, the second alignment key AKEY2 may be disposed near the signal pad portion in the horizontal (X-axis) direction.

[0064] In the output pad portion OPAD, a bonding area BA may be defined with respect to the first alignment key AKEY1. Similarly, in the display panel 100, a bonding area BA may be defined with respect to the second alignment key AKEY2.

[0065] The vertical (Y-axis) length VL of the bonding area BA may be the same as or similar to the vertical (Y-axis) length VL of the first alignment key AKEY1 or the second alignment key AKEY2.

[0066] According to the present embodiment, in order to increase the uniformity of the bonding adhesion corresponding to the output pad portion OPAD, the vertical (Y-axis) length VL of the third output pad OPAD3 may be the same as or similar to the vertical (Y-axis) length VL of the first alignment key AKEY1. Therefore, bonding of the same or substantially the same area corresponding to the same or substantially the same vertical (Y-axis) length VL may be performed on all the output pads OPAD1, OPAD2, and OPAD3 included in the output pad portion OPAD, thereby increasing the uniformity of the bonding adhesion corresponding to the output pad portion OPAD.

[0067] The present embodiment can achieve the following effects.

[0068] The present embodiment can reduce or prevent the occurrence of bonding defects even when it is difficult to perform an accurate alignment operation.

[0069] In addition, the present embodiment can reduce the number of output pads exposed on the cross-sectional surface of the output pad portion, thereby reducing or minimizing defects caused by metal migration.

[0070] In addition, the present embodiment can increase the uniformity of the bonding adhesion corresponding to the output pad portion.

[0071] The effects according to the present disclosure are not limited to the above examples, and various other effects may be included in the description.

[0072] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the technical idea and scope of the present disclosure as defined by the appended claims.

[0073] Cross - reference to related applications

[0074] This application claims the benefit of Korean Patent Application No. 10 - 2024 - 0002815, filed in Korea on January 8, 2024, which is hereby incorporated by reference in its entirety as if fully set forth herein.

Claims

1. A chip on film, the chip on film comprising: A driver integrated circuit; An input pad portion, the input pad portion including a first input pad connected to the driver integrated circuit and a second input pad separated from the driver integrated circuit; and An output pad portion, the output pad portion including a first output pad connected to the driver integrated circuit, a second output pad directly connected to the second input pad, and a floating third output pad, the output pad portion being cut along a film cutting line.

2. The on-membrane chip according to claim 1, wherein, The first output pad and the second output pad are exposed to the outside in a cross-sectional surface of the output pad portion corresponding to the film cutting line, and the third output pad is not exposed to the outside.

3. The on-membrane chip according to claim 1, wherein, The third output pad is disposed between the first output pad and the second output pad or between adjacent first output pads.

4. The on-membrane chip according to claim 1, wherein, An end portion of the third output pad is spaced apart from the film cutting line by a certain interval and is disposed inward from an edge of the film of the chip on film.

5. The on-chip membrane according to claim 1, wherein One or more first output pads are disposed between adjacent third output pads.

6. The chip on film according to claim 1, the chip on film further comprising an alignment key disposed in a horizontal direction near the output pad portion for a bonding process between the output pad portion and a display panel, Among them, In the output pad portion, a bonding region is defined with respect to the alignment key, and A vertical length of the bonding region is equal to a vertical length of the alignment key.

7. The on-membrane chip according to claim 6, wherein, A vertical length of the third output pad is equal to a vertical length of the alignment key.

8. A display device, the display device comprising: A display panel, the display panel including a display region provided with pixels and a border region outside the display region; And A chip on film, the chip on film being bonded to the border region, Wherein, the chip on film comprises: A driver integrated circuit; An input pad portion, the input pad portion including a first input pad connected to the driver integrated circuit and a second input pad separated from the driver integrated circuit; and An output pad portion, the output pad portion including a first output pad connected to the driver integrated circuit, a second output pad directly connected to the second input pad, and a floating third output pad, and The output pad portion is cut along a film cutting line.

9. The display device according to claim 8, wherein, The first output pad and the second output pad are exposed to the outside in a cross-sectional surface of the output pad portion corresponding to the film cutting line, and the third output pad is not exposed to the outside.

10. The display device according to claim 8, wherein, The third output pad is disposed between the first output pad and the second output pad or between adjacent first output pads.

11. The display device according to claim 8, wherein, An end portion of the third output pad is spaced apart from the film cutting line by a certain interval and is disposed inward from an edge of the film of the chip on film.

12. The display device according to claim 8, wherein, One or more first output pads are disposed between adjacent third output pads.

13. The display device according to claim 8, wherein the display device further includes an alignment key disposed near the output pad portion in a horizontal direction for a bonding process between the output pad portion and the display panel. Among them, In the output pad portion, a bonding region is defined with respect to the alignment key, and a vertical length of the bonding region is equal to a vertical length of the alignment key.

14. The display device according to claim 13, wherein, A vertical length of the third output pad is equal to the vertical length of the alignment key.

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