Display device

Abstract

A display device includes: a first display panel displaying an image in one direction in a first mode, and including first pixels; a second display panel displaying an image in a direction opposite to the one direction in a first mode, and including second pixels; and a driving circuit supplying a data voltage to a data line connected to the first pixel and the second pixel.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0002012, filed on January 5, 2024, and Korean Patent Application No. 10 - 2024 - 0072436, filed on June 3, 2024, the disclosures of which are incorporated herein by reference in their entireties. Technical field

[0003] The present disclosure relates to a display device. Background art

[0004] With the advancement of information technology, the importance of display devices that serve as an interface between users and information has become more prominent. As a result, the use of display devices such as liquid crystal display (LCD) devices, organic light - emitting display devices, and inorganic light - emitting display devices is increasing.

[0005] A display device displays an image. There is a growing trend of display devices having a larger screen while still maintaining the same or smaller size and thickness compared to previous designs. Moreover, flexible display devices such as foldable and bendable screens are being developed. These devices can be folded and unfolded to provide a larger screen only when needed. Summary of the invention

[0006] An object of the present disclosure is to provide a display device that can drive a first display panel and a second display panel using one driving circuit.

[0007] According to an embodiment of the present disclosure, a display device includes: a first display panel that displays an image in one direction in a first mode and includes first pixels; a second display panel that displays an image in a direction opposite to the one direction in the first mode and includes second pixels; and a driving circuit that supplies a data voltage to data lines connected to the first pixels and the second pixels.

[0008] In an embodiment, the first display panel includes: a main region that displays an image; and a sub - region in which the driving circuit is disposed.

[0009] In an embodiment, a first part of the main region and a second part of the main region different from the first part are configured to be folded and face each other in a second mode.

[0010] In an embodiment, the second display panel includes: a main region that displays an image; and a sub - region that connects the main region and the first display panel, and the data lines are disposed in the sub - region.

[0011] In an embodiment, the sub - region is bendable.

[0012] In an embodiment, a second display area of the second display panel where an image is displayed is smaller than a first display area of the first display panel where an image is displayed.

[0013] In an embodiment, a length of the second display area in a first direction is shorter than a length of the first display area in the first direction, and a length of the second display area in a second direction perpendicular to the first direction is approximately equal to a length of the first display area in the second direction.

[0014] In an embodiment, the driving circuit simultaneously displays an image on the first display panel and the second display panel.

[0015] In an embodiment, the driving circuit refreshes the first display panel at a first driving frequency and refreshes the second display panel at a second driving frequency.

[0016] In an embodiment, a frame in which the first display panel is refreshed is different from a frame in which the second display panel is refreshed.

[0017] In an embodiment, the driving circuit displays an image on one of the first display panel and the second display panel.

[0018] In an embodiment, the driving circuit simultaneously displays an image on the first display panel and the second display panel in a first mode, and displays an image on one of the first display panel and the second display panel in a second mode.

[0019] In an embodiment, the driving circuit supplies a data voltage for one of the first display panel and the second display panel to a data line in one frame.

[0020] In an embodiment, a resolution of the first display panel is higher than a resolution of the second display panel.

[0021] In an embodiment, the driving circuit includes a frame memory that stores input image data of one frame, and a capacity of the frame memory has a value corresponding to a resolution of the first display panel.

[0022] According to an embodiment of the present disclosure, a display device includes: a first display panel including first pixels; a second display panel including second pixels; a first gate driver that supplies a gate signal to a first gate line connected to the first pixels; a second gate driver that supplies a gate signal to a second gate line connected to the second pixels; and a driving circuit that supplies a data voltage to a data line connected to the first pixels and the second pixels and controls the first gate driver and the second gate driver.

[0023] In an embodiment, the first display panel includes: a main area that displays an image; and a sub area where the driving circuit is disposed.

[0024] In an embodiment, the second display panel includes: a main region that displays an image; and a sub-region that connects the main region to the first display panel, and data lines are disposed in the sub-region.

[0025] In an embodiment, the driving circuit displays an image on the first display panel and the second display panel simultaneously.

[0026] In an embodiment, the driving circuit displays an image on one of the first display panel and the second display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0028] Figure 1 The figure illustrates a normal mode of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 The figure illustrates Figure 1 the inner folding mode of the display device.

[0030] Figure 3 The figure illustrates Figure 1 a perspective view of a display panel of the display device.

[0031] Figure 4 The figure illustrates Figure 1 a cross-sectional view of a display panel of the display device.

[0032] Figure 5 The figure illustrates Figure 3 a schematic plan view of a connection relationship between components of a display panel and a driving chip.

[0033] Figure 6 The figure illustrates Figure 5 a block diagram of an example of a driving chip.

[0034] Figure 7 The figure illustrates a table related to an example of driving a display panel by a display device in which Figure 1 ...

[0035] Figure 8 The figure illustrates a timing diagram related to an example of driving a display device in a first mode in which Figure 1 ...

[0036] Figure 9 The figure illustrates a timing diagram related to an example of driving a display device in a second mode in which Figure 1 ...

[0037] Figure 10The figure shows a schematic plan view of the connection relationship between components of a display panel and a driving chip according to an embodiment of the present disclosure. Detailed implementation

[0038] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0039] It will be understood that when an element is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element, it can be directly on, connected to, coupled to, or adjacent to the other element, or intervening elements may be present. It will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. It will also be understood that when an element is referred to as "covering" another element, it can be the only element covering the other element, or one or more intervening elements may also cover the other element. Other terms used to describe the relationship between elements should be interpreted in a similar manner.

[0040] For the purposes of the present disclosure, "at least one of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as by way of example XYZ, XY, YZ, and XZ). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Although terms such as "first" and "second" may be used herein to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are only used to distinguish one constituent element from another. Thus, the first constituent element discussed below may be referred to as the second constituent element without departing from the teachings of the present disclosure.

[0042] For descriptive purposes, spatial relative terms such as "below", "beneath", "under", "above", and "over" may be used herein and are used to describe the relationship of one element or feature to another (some) element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an above and a below orientation. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0043] Here, when two or more elements or values are described as being substantially the same or approximately equal to each other, it is understood that these elements or values are the same as each other, these elements or values are equal to each other within the measurement error, or if measurably unequal, then these elements or values are close enough in value to be functionally equal to each other, as would be understood by a person of ordinary skill in the art. For example, considering the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, the term "about" includes the recited value and means within an acceptable deviation for that particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations as understood by a person of ordinary skill in the art. Further, it is understood that although a parameter may be described herein as having "about" a certain value, according to an embodiment, the parameter can be exactly that certain value or approximately that certain value within the measurement error, as would be understood by a person of ordinary skill in the art. These terms and other uses of similar terms used to describe relationships between components should be interpreted in a similar manner.

[0044] Here, when two or more processes or events are described as being executed simultaneously, it is understood that these processes or events can be executed at exactly the same time or approximately the same time, or can occur at exactly the same time or approximately the same time, as would be understood by a person of ordinary skill in the art. For example, these processes or events can be executed at approximately the same time within the measurement error or can occur at approximately the same time, as would be understood by a person of ordinary skill in the art.

[0045] Embodiments of the present disclosure provide a display device as follows, which combines a first display panel and a second display panel capable of displaying images in opposite directions, all of these display panels being driven by a single driving chip. This configuration reduces the number of driving chips required, which can result in lower production costs, a smaller device size, and reduced power consumption. The flexible folding and bending functions of the device enable different usage modes in which the display can be folded and unfolded. The single driving chip can effectively operate the two display panels simultaneously or separately depending on the mode, supply data voltages and control signals, refresh them at different frequencies, and support various configurations. Therefore, embodiments of the present disclosure provide a more compact, more versatile, and more cost-effective display device.

[0046] Figure 1 FIG. shows the normal mode of the display device according to an embodiment of the present disclosure, and Figure 2 FIG. shows Figure 1 the inner folding mode of the display device.

[0047] Reference Figure 1 and Figure 2 , the display device 1000 may be a foldable display device. In this specification, "foldable" refers to any flexible state, including, for example, bendable, rollable, or similar states. Further, "foldable" encompasses various forms, such as partially or fully foldable and foldable inward or outward.

[0048] The display device 1000 may include an in-foldable display device and / or an out-foldable display device. That is, the display device 1000 may be a display device that can be used in an in-foldable mode and / or an out-foldable mode. Here, the in-foldable mode refers to a mode in which the front surface FFA of the display device 1000 is folded to face each other (see Figure 2 ). In addition, the out-foldable mode refers to a mode in which the back surface BA of the display device 1000 is folded to face each other.

[0049] Hereinafter, for convenience of description, it is assumed that the display device 1000 has a normal mode in which it is not folded (see Figure 1 ) and an in-foldable mode (see Figure 2 ).

[0050] The display device 1000 includes a first cover window WIN1 and a second cover window WIN2 and a housing HM, and a display panel 100 (see Figure 3 ) may be disposed inside the first cover window WIN1, the second cover window WIN2, and the housing HM. Accordingly, the first cover window WIN1, the second cover window WIN2, and the housing HM may be combined to form the appearance of the display device 1000.

[0051] The first cover window WIN1 and the second cover window WIN2 may include insulating panels. For example, the first cover window WIN1 and the second cover window WIN2 may be made of glass, plastic, or a combination thereof. In an embodiment, the first cover window WIN1 and the second cover window WIN2 may include a touch sensing portion capable of sensing touch.

[0052] The first cover window WIN1 may be disposed in a first display area DA1 where an image is displayed and a first non-display area NDA1 where no image is displayed. The second cover window WIN2 may be disposed in a second display area DA2 where an image is displayed and a second non-display area NDA2 where no image is displayed.

[0053] The front surface of the first cover window WIN1 may define the front surface FFA of the display device 1000. A part of the housing HM and the front surface of the second cover window WIN2 may define the back surface BA of the display device 1000.

[0054] The housing HM can be coupled to the first cover window WIN1 and the second cover window WIN2. The housing HM can be coupled to the first cover window WIN1 and the second cover window WIN2 to provide a predetermined accommodation space. The components of the display device 1000 can be accommodated in the predetermined accommodation space provided between the housing HM, the first cover window WIN1, and the second cover window WIN2.

[0055] The housing HM can include a material with relatively high rigidity. For example, the housing HM can include a plurality of frames and / or plates made of glass, plastic, metal, or a combination thereof. The housing HM can stably protect the components of the display device 1000 accommodated in the internal space formed by the housing HM, the first cover window WIN1, and the second cover window WIN2 from the impact of external shocks.

[0056] The display device 1000 can display images through the display areas DA1 and DA2. Various display devices such as an inorganic light-emitting display device, an organic light-emitting display device, and a quantum dot light-emitting display device can be used as the display device 1000.

[0057] Various modifications can be made to the shape of the display device 1000. For example, the display device 1000 can have shapes such as a rectangular shape with a long horizontal length, a rectangular shape with a long vertical length, a square, a quadrilateral shape with rounded corners (edges), other polygonal shapes, and a circular shape. The shapes of the display areas DA1 and DA2 of the display device 1000 can be similar to the overall shape of the display device 1000.

[0058] The display device 1000 can include the display areas DA1 and DA2 and the non-display areas NDA1 and NDA2. The display areas DA1 and DA2 are the areas for displaying images, and the non-display areas NDA1 and NDA2 are the areas for not displaying images. The first display area DA1 occupies most of the front surface FFA of the display device 1000, and the first non-display area NDA1 can have a structure surrounding the periphery of the first display area DA1. The second display area DA2 occupies a partial area of the back surface BA of the display device 1000, and the second non-display area NDA2 can have a structure surrounding the periphery of the second display area DA2.

[0059] In an embodiment, components such as sensors or cameras, which add various functions to the display device 1000, can be provided in a partial area of the first display area DA1 or a partial area of the second display area DA2. In an embodiment, components can be provided on the housing HM of the back surface BA of the display device 1000.

[0060] The display device 1000 may include a first non-foldable area NFA1, a second non-foldable area NFA2, and a foldable area FA disposed between the first non-foldable area NFA1 and the second non-foldable area NFA2.

[0061] The first display area DA1 is not folded in the normal mode of the display device 1000. For example, in the normal mode, the first display area DA1 may display an image in the third direction DR3, and the second display area DA2 may display an image in a direction opposite to the third direction DR3.

[0062] A first portion of the first display area DA1 (e.g., an area within the first non-foldable area NFA1) and a second portion of the first display area DA1 (e.g., an area within the second non-foldable area NFA2) may be folded to face each other directly in the inward folding mode. For example, the first portion and the second portion of the first display area DA1 may be folded based on the folding axis FX in the inward folding mode. For example, in the inward folding mode of the display device 1000, the first display area DA1 does not display an image, and the second display area DA2 may display an image in the third direction DR3. Here, a first portion and a second portion different from the first portion of the first non-display area NDA1 may also be folded to face each other in the inward folding mode.

[0063] In an embodiment, the second display area DA2 may be smaller than the first display area DA1. For example, the resolution of the first display area DA1 may be higher than the resolution of the second display area DA2. For example, the length of the second display area DA2 in the first direction DR1 may be shorter than the length of the first display area DA1 in the first direction DR1, and the length of the second display area DA2 in the second direction DR2 intersecting (e.g., perpendicular to) the first direction DR1 may be the same as the length of the first display area DA1 in the second direction DR2. However, the present disclosure is not limited to the shapes of the first display area DA1 and the second display area DA2 described above.

[0064] Figure 3 The figure shows Figure 1 a perspective view of the display panel of the display device, and Figure 4 the figure shows Figure 1 a cross-sectional view of the display panel of the display device.

[0065] Figure 3 The figure shows the display panel 100 before the first sub-area SBA1 and the second sub-area SBA2 are bent, and Figure 4 the figure shows the display panel 100 after the first sub-area SBA1 and the second sub-area SBA2 are bent.

[0066] The display panel 100 may be disposed in the form of Figure 4 inside the first cover window WIN1, the second cover window WIN2, and the housing HM (see Figure 1 ).

[0067] For ease of description, in Figure 4 , components other than the display panel 100, the driving chip 200, the circuit board 300, the first cover window WIN1, the second cover window WIN2, the protective film PFM, and the bending protective layer BPL are omitted.

[0068] Referring to Figures 1 to 3 , the display device 1000 may include a display panel 100, a driving chip 200, and a circuit board 300.

[0069] The display panel 100 may include a first display panel DP1 and a second display panel DP2. The first display panel DP1 may include a first main area MA1 and a first sub-area SBA1. The second display panel DP2 may include a second main area MA2 and a second sub-area SBA2. A first part of the first main area MA1 and a second part of the first main area MA1 different from the first part may be configured to be folded and face each other in the inner folding mode.

[0070] The first main area MA1 may include a first display area DA1 including pixels for displaying an image and a first non-display area NDA1 disposed around the first display area DA1 and not including pixels.

[0071] The first display area DA1 may emit light in a third direction DR3 (see Figure 1 ) in a normal mode (see Figure 1 ). For example, the first display area DA1 may include a pixel circuit part including transistors, a light-emitting element, and a pixel defining film having an opening defining a light-emitting area of the light-emitting element. Here, the light-emitting element may include, for example, at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0072] The first non-display area NDA1 is an area located outside the first display area DA1 and surrounding the first display area DA1. The first non-display area NDA1 may be defined as an edge area of the first display area DA1. The first non-display area NDA1 may include a first gate driver 410 (see Figure 5 ) that supplies a gate signal to the first gate line GL1 (refer to Figure 5 ).

[0073] The first sub-region SBA1 may be a region extending from one side of the first main region MA1. The first sub-region SBA1 may include a flexible material capable of being bent, folded, curled, etc. For example, when the first sub-region SBA1 is bent, the first sub-region SBA1 may overlap with the first main region MA1 in the thickness direction (e.g., the third direction DR3) (see Figure 4 ). The first sub-region SBA1 may include a pad portion connected to the driving chip 200 and the circuit board 300.

[0074] The second main region MA2 may include a second display region DA2 including pixels for displaying an image and a second non-display region NDA2 disposed around the second display region DA2 and not including pixels.

[0075] The second display region DA2 may emit light in a direction opposite to the third direction DR3 (see Figure 1 ) in a normal mode (see Figure 1 ). The configuration of the second display region DA2 is substantially the same as that of the first display region DA1, and thus, for the sake of simplicity of description, redundant descriptions will be omitted.

[0076] The second non-display region NDA2 is a region located outside the second display region DA2 and surrounding the second display region DA2. The second non-display region NDA2 may be defined as an edge region of the second display region DA2. The second non-display region NDA2 may include a second gate driver 420 (see Figure 5 ) that supplies a gate signal to the second gate line GL2 (see Figure 5 ).

[0077] The second sub-region SBA2 may be a region extending from one side of the second main region MA2. The second sub-region SBA2 may include a flexible material capable of being bent, folded, curled, etc. For example, when the second sub-region SBA2 is bent, the second sub-region SBA2 may overlap with the first main region MA1 in the thickness direction (e.g., the third direction DR3) (see Figure 4 ). A data line DL (see Figure 5 ) included in a plurality of data lines and gate control lines GCL1 and GCL2 (see Figure 5 ) included in a plurality of gate control lines may be disposed in the second sub-region SBA2. The data line DL (see Figure 5 ) and the gate control lines GCL1 and GCL2 (see Figure 5 ) are disposed in the second sub-region SBA2 such that the driving chip 200 can display an image on the second display panel DP2.

[0078] The driving chip 200 can output signals and voltages for driving the display panel 100. The driving chip 200 can supply data voltages to the data lines DL (see Figure 5 ). The driving chip 200 can supply power voltages to the power lines and can supply gate control signals to the gate drivers 410 and 420 (see Figure 5 ) and the gate control lines GCL1 and GCL2 (see Figure 5 ). The driving chip 200 can be formed as an integrated circuit (IC) and can be mounted on the display panel 100 by, for example, a chip - on - glass (COG) method, a chip - on - plastic (COP) method, or an ultrasonic bonding method. In an embodiment, the driving chip 200 can be disposed in the first sub - region SBA1. In an embodiment, the driving chip 200 can be mounted on the circuit board 300.

[0079] The circuit board 300 can be attached to the pad portion of the display panel 100 using, for example, an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be, for example, a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip - on - film.

[0080] Reference Figure 4 , the display device 1000 can include a display panel 100, a driving chip 200, a circuit board 300, a first cover window WIN1 and a second cover window WIN2, a protective film PFM, and a bending protection layer BPL.

[0081] The first sub - region SBA1 and the second sub - region SBA2 can be bent. For example, as Figure 4 shown, the first sub - region SBA1 can be bent to face the first main region MA1, and the second sub - region SBA2 can be bent such that the second main region MA2 faces the first main region MA1.

[0082] The bending protection layer BPL can be disposed on the first sub - region SBA1 and the second sub - region SBA2. The bending protection layer BPL can cover a part of the first sub - region SBA1 and can cover the second sub - region SBA2. The bending protection layer BPL can protect the first sub - region SBA1 and the second sub - region SBA2. For example, the bending protection layer BPL can protect the conductive layers in the first sub - region SBA1 and the second sub - region SBA2. The gate control lines GCL1 and GCL2 (see Figure 5 ) and the data lines DL can be disposed in the conductive layer. The bending protection layer BPL can reduce the tensile stress applied to the conductive layer. In addition, the bending protection layer BPL can protect the first sub - region SBA1 and the second sub - region SBA2 from the influence of static electricity introduced from the outside of the display device 1000.

[0083] In an embodiment, the polarization layer may be disposed between the cover windows WIN1 and WIN2 and the main regions MA1 and MA2. The polarization layer may reduce external light reflection of the display device 1000.

[0084] In an embodiment, in the display device 1000, an adhesive layer may be disposed between the protective film PFM and the main regions MA1 and MA2.

[0085] In an embodiment, the display device 1000 may include a buffer layer adjacent to a part of the protective film PFM. For example, the display device 1000 may include a buffer layer adjacent to the protective film PFM adjacent to the second main region MA2 in the third direction DR3. For example, the display device 1000 may include a buffer layer adjacent to the protective film PFM adjacent to the first main region MA1 in a direction opposite to the third direction DR3.

[0086] Figure 5 The figure shows Figure 3 a schematic plan view of the connection relationship between the components of the display panel and the driving chip.

[0087] Reference Figure 5 , in the display areas DA1 and DA2, the pixels PX1 and PX2 included in the plurality of pixels, the gate lines GL1 and GL2 included in the plurality of gate lines, and the data lines DL included in the plurality of data lines may be provided. Each of the pixels PX1 and PX2 is the smallest unit that emits light, and includes a pixel circuit portion including a transistor and a capacitor, and a light-emitting element that receives current from the pixel circuit portion.

[0088] The first display area DA1 may include the first pixel PX1. The first pixel PX1 may be connected to the first gate line GL1 and the data line DL. The second display area DA2 may include the second pixel PX2. The second pixel PX2 may be connected to the second gate line GL2 and the data line DL.

[0089] The display panel 100 may include gate drivers 410 and 420. The gate drivers 410 and 420 may generate gate signals based on gate control signals, and supply the gate signals to the gate lines GL1 and GL2.

[0090] In an embodiment, the first non-display area NDA1 may include the first gate driver 410. The first gate driver 410 may supply a gate signal to the first gate line GL1 connected to the first pixel PX1. In an embodiment, the second non-display area NDA2 may include the second gate driver 420. The second gate driver 420 may supply a gate signal to the second gate line GL2 connected to the second pixel PX2.

[0091] In the embodiments described herein, it is illustrated that the gate drivers 410 and 420 are disposed in the non-display areas NDA1 and NDA2. However, the present disclosure is not limited thereto. For example, in an embodiment, the gate drivers 410 and 420 may be disposed in the first sub-area SBA1 or the circuit board 300.

[0092] The driving chip 200 may supply data voltages to the data lines DL. The driving chip 200 may receive input image data IMG (see Figure 6 )(e.g., a graphics processing unit (GPU), etc.) from the processor 2000 (see Figure 6 ) and input control signals CONT (see Figure 6 ). For example, the input image data IMG (see Figure 6 ) may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG (see Figure 6 ) may further include white image data. In an embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data.

[0093] The driving chip 200 may generate gate control signals and data voltages based on the input image data IMG (see Figure 6 ) and the input control signals CONT (see Figure 6 ).

[0094] The gate drivers 410 and 420 may generate gate signals in response to the gate control signals. In addition, the gate drivers 410 and 420 may output the gate signals to the gate lines GL1 and GL2.

[0095] In an embodiment, the driving chip 200 may supply the gate control signal for controlling the first gate driver 410 to the first gate control line GCL1 connected to the first gate driver 410, and supply the gate control signal for controlling the second gate driver 420 to the second gate control line GCL2 connected to the second gate driver 420.

[0096] In the embodiments described herein, it is illustrated that the driving chip 200 supplies the gate control signal to each of the first gate driver 410 and the second gate driver 420. However, the present disclosure is not limited thereto. For example, in an embodiment, the driving chip 200 may supply the gate control signal to the first gate driver 410, and the first gate driver 410 may supply the signal for controlling the second gate driver 420 to the second gate driver 420. In this case, the second gate control line GCL2 may be connected between the first gate driver 410 and the second gate driver 420.

[0097] The driving chip 200 can be disposed in the first sub-region SBA1. In addition, wirings connected to the driving chip 200 (e.g., data lines DL and gate control lines GCL1 and GCL2, etc.) can be disposed in the first sub-region SBA1. The data line DL and the second gate control line GCL2 can be disposed in the second sub-region SBA2.

[0098] In this manner, since the first pixel PX1 and the second pixel PX2 are connected to the same data line DL, the first display panel DP1 and the second display panel DP2 can be driven by one driving chip 200. Accordingly, the number of required driving chips 200 can be reduced, and the production cost, size, and power consumption of the display device 1000 (see Figure 1 ) can be reduced.

[0099] Figure 6 The figure shows Figure 5 a block diagram of an example of the driving chip 200.

[0100] Referring to Figure 6 , the driving chip 200 can include an interface portion 210, a frame memory 220, a logic circuit 230, a digital-to-analog (DAC) converter 240, and an amplification portion 250. The components included in the driving chip 200 can form a driving circuit. Accordingly, the driving chip 200 can also be referred to as a driving circuit or a driving circuit chip.

[0101] The interface portion 210 can perform a function of communicating with the processor 2000 through a predetermined interface, and can receive various signals from the processor 2000. For example, the interface can include at least one of a Mobile Industry Processor Interface (MIPI) and a Serial Peripheral Interface (SPI) bus.

[0102] The frame memory 220 can store input image data IMG for one frame. For example, the frame memory 220 can act as a frame buffer.

[0103] The capacity of the frame memory 220 can have a value corresponding to one of the resolutions of the first display panel DP1 and the second display panel DP2. The driving chip 200 can output a data voltage VDATA for the first display panel DP1 or a data voltage VDATA for the second display panel DP2 in one frame. Accordingly, the capacity of the frame memory 220 can have a value corresponding to the higher resolution among the resolutions of the first display panel DP1 and the second display panel DP2.

[0104] For example, as Figure 5As shown, when the resolution of the first display panel DP1 is higher than that of the second display panel DP2, the capacity of the frame memory 220 can have a value corresponding to the resolution of the first display panel DP1. Here, the value corresponding to the resolution refers to the value of the input image data IMG for one frame of the image displayed at that resolution.

[0105] The logic circuit 230 can perform various operations executed by the driving chip 200. For example, the logic circuit 230 can load the input image data IMG from the frame memory 220 and generate a data signal DATA based on the input image data IMG and the input control signal CONT.

[0106] The logic circuit 230 can generate a timing control signal TE. The timing control signal TE can be provided to the processor 2000 through the interface portion 210. The processor 2000 can control the transfer timing of the input image data IMG based on the input timing control signal TE. The timing control signal TE is a control signal that can prevent the tearing phenomenon.

[0107] The logic circuit 230 can generate a vertical synchronization signal VSYNC for defining a frame (see Figure 8 ), which will be further described below.

[0108] In an embodiment, the logic circuit 230 can include an oscillator. The logic circuit 230 can drive the display panel 100 at a specific driving frequency through a frequency source generated by the oscillator (see Figure 5 ).

[0109] The digital-to-analog converter 240 can convert the data signal DATA as a digital signal into a data voltage VDATA as an analog signal. The amplifying portion 250 can amplify the data voltage VDATA and provide the amplified data voltage VDATA to the data line DL. For example, the amplifying portion 250 can include an amplifier.

[0110] Figure 7 The figure shows a table related to an example of a display device driving a display panel in which Figure 1 . Figure 8 The figure shows a timing diagram related to an example of the display device being driven in a first mode in which Figure 1 , and Figure 9 the figure shows a timing diagram related to an example of the display device being driven in a second mode in which Figure 1 .

[0111] Refer to Figures 5 to 7, the driving chip 200 can display (i.e., drive simultaneously) images on the first display panel DP1 and the second display panel DP2 in the first mode M1, and display (i.e., drive separately) images on one of the first display panel DP1 and the second display panel DP2 (e.g., only on one of the first display panel DP1 and the second display panel DP2) in the second mode M2.

[0112] The driving mode of the driving chip 200 can be determined by the processor 2000. In an embodiment, the driving chip 200 can generate a mode signal MS with a value of 0 or 1 based on the input control signal CONT. When the mode signal MS has a value of 0, the driving chip 200 can operate in the first mode M1. When the mode signal MS has a value of 1, the driving chip 200 can operate in the second mode M2.

[0113] In an embodiment, the driving chip 200 can receive the mode signal MS from the processor 2000 and can be driven in the first mode M1 or the second mode M2 according to the mode signal MS.

[0114] The vertical synchronization signal VSYNC can define a frame. For example, the vertical synchronization signal VSYNC can indicate the start of a frame. A mode signal MS with a value of 0 or 1 is generated before the start of each frame, and the driving chip 200 can determine the driving mode of each frame based on the generated mode signal MS.

[0115] The driving chip 200 can selectively refresh one of the first display panel DP1 and the second display panel DP2. For example, the driving chip 200 can supply the data voltage VDATA for one of the first display panel DP1 and the second display panel DP2 to the data line DL in a frame. That is, the frame in which the first display panel DP1 is refreshed and the frame in which the second display panel DP2 is refreshed can be different from each other.

[0116] Reference Figures 5 to 8 , in the first mode M1, the driving chip 200 can refresh the first display panel DP1 at a first driving frequency DF1 and refresh the second display panel DP2 at a second driving frequency DF2 that can be different from the first driving frequency DF1.

[0117] In the first mode M1, the driving chip 200 can generate a first mode option signal M1_OPT. When the first mode option signal M1_OPT has a value of 0, the driving chip 200 can refresh the first display panel DP1 by applying the data voltage VDATA for the first display panel DP1 to the data line DL. When the first mode option signal M1_OPT has a value of 1, the driving chip 200 can refresh the second display panel DP2 by applying the data voltage VDATA for the second display panel DP2 to the data line DL. The value of the first mode option signal M1_OPT can be determined by the processor 2000. For example, the driving chip 200 can generate the first mode option signal M1_OPT with a value of 0 or 1 based on the input control signal CONT.

[0118] For example, when the first mode option signal M1_OPT has a value of 0, the driving chip 200 can receive the input image data IMG for the first display panel DP1 from the processor 2000, and store the input image data IMG for the first display panel DP1 in the frame memory 220 (i.e., perform a write operation WRITE). In addition, the logic circuit 230 can load the input image data IMG for the first display panel DP1 (i.e., perform a read operation READ), and generate a data signal DATA for the first display panel DP1 based on the input image data IMG for the first display panel DP1. The digital-to-analog converter 240 can convert the data signal DATA into the data voltage VDATA. Accordingly, the driving chip 200 can refresh the first display panel DP1.

[0119] For example, when the first mode option signal M1_OPT has a value of 1, the driving chip 200 can receive the input image data IMG for the second display panel DP2 from the processor 2000, and store the input image data IMG for the second display panel DP2 in the frame memory 220 (i.e., perform a write operation WRITE). In addition, the logic circuit 230 can load the input image data IMG for the second display panel DP2 (i.e., perform a read operation READ), and generate a data signal DATA for the second display panel DP2 based on the input image data IMG for the second display panel DP2. The digital-to-analog converter 240 can convert the data signal DATA into the data voltage VDATA. Accordingly, the driving chip 200 can refresh the second display panel DP2.

[0120] The first display panel DP1 and the second display panel DP2 can display the image of the previous frame in the frame that is not refreshed. For example, in the frame in which the first display panel DP1 is refreshed, the second display panel DP2 can display the image of the previous frame. For example, in the frame in which the second display panel DP2 is refreshed, the first display panel DP1 can display the image of the previous frame.

[0121] For example, when the driving frequencies DF1 and DF2 are about 120 Hz, it is assumed that the display panels DP1 and DP2 are refreshed in each reference frame RF. When the first driving frequency DF1 is about 60 Hz and the second driving frequency DF2 is about 60 Hz, the first display panel DP1 and the second display panel DP2 can be refreshed alternately. When the first driving frequency DF1 is about 120 Hz and the second driving frequency DF2 is about 30 Hz, after the second display panel DP2 is refreshed, the first display panel DP1 can be refreshed during three frames.

[0122] The timing control signal TE can be transmitted to the processor 2000 for each reference frame RF. When the resolution of the second display panel DP2 is lower than that of the first display panel DP1, the time taken to refresh the second display panel DP2 can be shorter than the time taken to refresh the first display panel DP1. Accordingly, the timing control signal TE can rise relatively faster in the frame in which the second display panel DP2 is refreshed than in the frame in which the first display panel DP1 is refreshed.

[0123] Reference Figures 5 to 7 and Figure 9 , in the second mode M2, the driving chip 200 can display an image on the first display panel DP1 or the second display panel DP2. Different from the first mode M1, in the second mode M2, only the first display panel DP1 can display an image, or only the second display panel DP2 can display an image.

[0124] In the second mode M2, the driving chip 200 can generate a second mode option signal M2_OPT. When the second mode option signal M2_OPT has a value of 0, the driving chip 200 can display an image only on the first display panel DP1, and apply a data voltage VDATA for the first display panel DP1 to the data line DL to refresh the first display panel DP1. When the second mode option signal M2_OPT has a value of 1, the driving chip 200 can display an image only on the second display panel DP2, and apply a data voltage VDATA for the second display panel DP2 to the data line DL to refresh the second display panel DP2. The value of the second mode option signal M2_OPT can be determined by the processor 2000. For example, the driving chip 200 can generate the second mode option signal M2_OPT with a value of 0 or 1 based on the input control signal CONT.

[0125] For example, when the second mode option signal M2_OPT has a value of 0, the driving chip 200 can receive input image data IMG for the first display panel DP1 from the processor 2000, and store the input image data IMG for the first display panel DP1 in the frame memory 220 (i.e., perform a write operation WRITE). In addition, the logic circuit 230 can load the input image data IMG for the first display panel DP1 (i.e., perform a read operation READ), and generate a data signal DATA for the first display panel DP1 based on the input image data IMG for the first display panel DP1. The digital-to-analog converter 240 can convert the data signal DATA into a data voltage VDATA. Accordingly, the driving chip 200 can refresh the first display panel DP1.

[0126] For example, when the second mode option signal M2_OPT has a value of 1, the driving chip 200 can receive input image data IMG for the second display panel DP2 from the processor 2000, and store the input image data IMG for the second display panel DP2 in the frame memory 220 (i.e., perform a write operation WRITE). In addition, the logic circuit 230 can load the input image data IMG for the second display panel DP2 (i.e., perform a read operation READ), and generate a data signal DATA for the second display panel DP2 based on the input image data IMG for the second display panel DP2. The digital-to-analog converter 240 can convert the data signal DATA into a data voltage VDATA. Accordingly, the driving chip 200 can refresh the second display panel DP2.

[0127] In the second mode M2, the length of a frame can be determined by the driving frequencies DF1 and DF2. For example, when the second mode option signal M2_OPT is 0, the length of a frame can be determined by the first driving frequency DF1. For example, when the second mode option signal M2_OPT is 1, the length of a frame can be determined by the second driving frequency DF2. For example, the length of a frame when the driving frequencies DF1 and DF2 are approximately 120 Hz can be shorter than the length of a frame when the driving frequencies DF1 and DF2 are approximately 30 Hz.

[0128] The timing control signal TE can be transmitted to the processor 2000 for each reference frame RF. When the resolution of the second display panel DP2 is lower than the resolution of the first display panel DP1, the time taken to refresh the second display panel DP2 can be shorter than the time taken to refresh the first display panel DP1. Accordingly, the timing control signal TE can rise relatively faster in the frame in which the second display panel DP2 is refreshed than in the frame in which the first display panel DP1 is refreshed.

[0129] Figure 10 The figure shows a schematic plan view of the connection relationship between the components of the display panel and the driving chip of a display device according to an embodiment of the present disclosure.

[0130] Since the display device according to the embodiments described herein is substantially the same in configuration as the display device 1000 Figure 1 except for the number of display panels DP1, DP2, and DP3, the same reference numerals and reference symbols are used for the same or similar components, and redundant descriptions thereof are omitted.

[0131] Reference Figure 10 , pixels PX1, PX2, and PX3 included among the plurality of pixels, gate lines GL1, GL2, and GL3 included among the plurality of gate lines, and data lines DL included among the plurality of data lines can be set in the display areas DA1, DA2, and DA3. Each of the pixels PX1, PX2, and PX3 is the smallest unit that emits light and includes a pixel circuit portion including a transistor and a capacitor and a light-emitting element that receives current from the pixel circuit portion.

[0132] The first display area DA1 can include the first pixel PX1. The first pixel PX1 can be connected to the first gate line GL1 and the data line DL. The second display area DA2 can include the second pixel PX2. The second pixel PX2 can be connected to the second gate line GL2 and the data line DL. The third display area DA3 can include the third pixel PX3. The third pixel PX3 can be connected to the third gate line GL3 and the data line DL.

[0133] The display panel 100 may include gate drivers 410, 420, and 430. The gate drivers 410, 420, and 430 may generate gate signals based on gate control signals and supply the gate signals to gate lines GL1, GL2, and GL3.

[0134] In an embodiment, the first non-display area NDA1 may include the first gate driver 410. The first gate driver 410 may provide a gate signal to the first gate line GL1 connected to the first pixel PX1. In an embodiment, the second non-display area NDA2 may include the second gate driver 420. The second gate driver 420 may provide a gate signal to the second gate line GL2 connected to the second pixel PX2. In an embodiment, the third non-display area NDA3 may include the third gate driver 430. The third gate driver 430 may provide a gate signal to the third gate line GL3 connected to the third pixel PX3.

[0135] In the embodiments described herein, it is illustrated that the gate drivers 410, 420, and 430 are disposed in the non-display areas NDA1, NDA2, and NDA3. However, the present disclosure is not limited thereto. For example, in an embodiment, the gate drivers 410, 420, and 430 may be disposed in the first sub-area SBA1 or the circuit board 300.

[0136] The gate drivers 410, 420, and 430 may generate gate signals in response to gate control signals. In addition, the gate drivers 410, 420, and 430 may output the gate signals to the gate lines GL1, GL2, and GL3.

[0137] In an embodiment, the driving chip 200 may provide the gate control signal for controlling the first gate driver 410 to the first gate control line GCL1 connected to the first gate driver 410, provide the gate control signal for controlling the second gate driver 420 to the second gate control line GCL2 connected to the second gate driver 420, and provide the gate control signal for controlling the third gate driver 430 to the third gate control line GCL3 connected to the third gate driver 430.

[0138] In the embodiments described herein, it is illustrated that the driving chip 200 provides a gate control signal to each of the first gate driver 410, the second gate driver 420, and the third gate driver 430. However, the present disclosure is not limited thereto. For example, in an embodiment, the driving chip 200 may provide a gate control signal to the first gate driver 410, the first gate driver 410 may provide a signal for controlling the second gate driver 420 to the second gate driver 420, and the second gate driver 420 may provide a signal for controlling the third gate driver 430 to the third gate driver 430. In this case, the second gate control line GCL2 may be connected between the first gate driver 410 and the second gate driver 420, and the third gate control line GCL3 may be connected between the second gate driver 420 and the third gate driver 430.

[0139] The driving chip 200 may be disposed in the first sub-region SBA1. In addition, wirings connected to the driving chip 200 (for example, data lines DL and gate control lines GCL1, GCL2, and GCL3, etc.) may be disposed in the first sub-region SBA1. The data line DL, the second gate control line GCL2, and the third gate control line GCL3 may be disposed in the second sub-region SBA2. The data line DL and the third gate control line GCL3 may be disposed in the third sub-region SBA3.

[0140] Accordingly, the first pixel PX1, the second pixel PX2, and the third pixel PX3 are connected to the same data line DL, such that the first display panel DP1, the second display panel DP2, and the third display panel DP3 can be driven by one driving chip 200. Consequently, the number of required driving chips 200 can be reduced, and the production cost, size, and power consumption of the display device can be decreased.

[0141] The second display area DA2 can be folded like Figure 1 the first display area DA1 (see Figure 2 ). The third display panel DP3 can be bent in substantially the same manner as Figure 4 the second display panel DP2, and the first display panel DP1 can be bent in substantially the same manner as the third display panel DP3.

[0142] As is conventional in the art of the present disclosure, the embodiments are described in terms of functional blocks, units, and / or modules and illustrated in the drawings. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In cases where these blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed with software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware for performing certain functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions.

[0143] According to an embodiment of the present disclosure, in a display device, by driving a first display panel and a second display panel with one driving chip, the number of required driving chips can be reduced and the production cost of the display device can be lowered. In addition, the display device according to an embodiment of the present disclosure may have a reduced size and lower power consumption.

[0144] However, the effects of the present disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of the present disclosure.

[0145] Embodiments of the present disclosure can be applied to display devices and electronic devices including display devices. For example, embodiments of the present disclosure can be applied to digital televisions, 3D televisions, mobile phones, smart phones, VR devices, PCs (e.g., tablet computers or laptop computers), home electronic devices, PDAs, PMPs, digital cameras, music players, portable game consoles, and navigation devices, etc.

[0146] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: A first display panel that displays an image in one direction in a first mode and includes first pixels; A second display panel that displays the image in a direction opposite to the one direction in the first mode and includes second pixels; And A driving circuit that supplies a data voltage to data lines connected to the first pixels and the second pixels.

2. The display device according to claim 1, wherein, The first display panel includes: A main area that displays the image; and A sub-area in which the driving circuit is disposed.

3. The display device according to claim 2, wherein, A first part of the main area and a second part of the main area different from the first part are configured to be folded and face each other in a second mode.

4. The display device according to claim 1, wherein, The second display panel includes: A main area that displays the image; and A sub-area that connects the main area and the first display panel, and Wherein, the data lines are disposed in the sub-area.

5. The display device according to claim 4, wherein, The sub-area is bendable.

6. The display device according to claim 1, wherein, A second display area of the second display panel that displays the image is smaller than a first display area of the first display panel that displays the image.

7. The display device according to claim 6, wherein, A length of the second display area in a first direction is shorter than a length of the first display area in the first direction, and A length of the second display area in a second direction perpendicular to the first direction is equal to a length of the first display area in the second direction.

8. The display device according to claim 1, wherein The driving circuit simultaneously displays the image on the first display panel and the second display panel.

9. The display device according to claim 8, wherein, The driving circuit refreshes the first display panel at a first driving frequency and refreshes the second display panel at a second driving frequency.

10. The display device according to claim 8, wherein, Wherein a frame in which the first display panel is refreshed and a frame in which the second display panel is refreshed are different.

11. The display device according to claim 1, wherein, The driving circuit displays the image on one of the first display panel and the second display panel.

12. The display device according to claim 1, wherein, The driving circuit simultaneously displays the image on the first display panel and the second display panel in the first mode, and displays the image on one of the first display panel and the second display panel in a second mode.

13. The display device according to claim 1, wherein, The driving circuit supplies the data voltage for one of the first display panel and the second display panel to the data lines in one frame.

14. The display device according to claim 1, wherein, The resolution of the first display panel is higher than the resolution of the second display panel.

15. The display device according to claim 14, wherein, The driving circuit includes a frame memory that stores input image data of one frame, and A capacity of the frame memory has a value corresponding to the resolution of the first display panel.

16. A display device, comprising: A first display panel including first pixels; A second display panel including second pixels; A first gate driver that supplies a gate signal to a first gate line connected to the first pixels; A second gate driver that supplies the gate signal to a second gate line connected to the second pixels; And A driving circuit supplies data voltages to data lines connected to the first pixel and the second pixel, and controls the first gate driver and the second gate driver.

17. The display device according to claim 16, wherein, The first display panel includes: a main area for displaying an image; and a sub area in which the driving circuit is disposed.

18. The display device according to claim 16, wherein, The second display panel includes: a main area for displaying an image; and a sub area for connecting the main area and the first display panel, and wherein the data lines are disposed in the sub area.

19. The display device according to claim 16, wherein, The driving circuit simultaneously displays images on the first display panel and the second display panel.

20. The display device according to claim 16, wherein, The driving circuit displays an image on one of the first display panel and the second display panel.

Images