Drive module and display device

Abstract

The present application belongs to the field of display, and specifically relates to a driving module and a display device, wherein the driving module includes a power module, a power management chip, a level converter and a delay module, wherein the power management chip is connected to the power module, the level converter is connected to the power management chip, the power module outputs a power supply voltage to the power management chip, the power management chip converts the power supply voltage into an operating voltage required by the level converter, and the delay module is arranged between the power module and the level converter. When the display device is turned off, when the power supply voltage reversely jumps during the decline process, the delay module can prevent the power management chip from generating an operating voltage, or the delay module can prevent the generated operating voltage from being output to the level converter, thereby avoiding the interruption of the shutdown discharge operation, thereby avoiding the polarization of the liquid crystal caused by the residual charge in the surface, and improving or eliminating the display abnormality.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a driving module and a display device. Background Art

[0002] The pixel drive circuit of a liquid crystal display (LCD) consists of liquid crystal capacitors and storage capacitors. These capacitors provide the electric field that drives the deflection of liquid crystal molecules to display the image. When the LCD is turned off, if the charge stored in these capacitors is not effectively released, the liquid crystal molecules can become polarized, resulting in display anomalies.

[0003] Existing LCDs have a shutdown discharge function, which rapidly discharges the various signals in the pixel driver circuit to ground at a constant voltage. This discharge prevents residual charge in the display from causing liquid crystal polarization, thereby eliminating display anomalies caused by residual charge.

[0004] However, the shutdown discharge function is activated by a level shifter (LS) that recognizes a drop in the power supply voltage during shutdown. If the power supply voltage rebounds during shutdown, the shutdown discharge operation will be interrupted. Due to the protection mechanism of the level shifter, the shutdown discharge operation cannot be triggered again for a short period of time after being interrupted. This can cause residual charge in the surface, causing liquid crystal polarization and display abnormalities. Summary of the Invention

[0005] The purpose of this application is to provide a driving module and a display device to prevent liquid crystal polarization caused by residual in-plane charge, thereby improving or eliminating display abnormalities.

[0006] To achieve the above objectives, the present application provides a driving module, including a power module and a power management chip, wherein the power management chip is connected to the power module, and the driving module further includes:

[0007] a level converter, connected to the power management chip;

[0008] A delay module is arranged between the power module and the level converter. The power management chip is used to convert the power voltage provided by the power module into the operating voltage of the level converter. When the power voltage reverses during the decline process, the delay module can prevent the power management chip from generating the operating voltage, or the delay module can prevent the generated operating voltage from being output to the level converter.

[0009] Optionally, the delay module is arranged between the power management chip and the level converter. When the power supply voltage reverses during a decrease process, the delay module can prevent the generated operating voltage from being output to the level converter.

[0010] Optionally, the delay module includes a first transistor, a second transistor, a capacitor, a first resistor and a second resistor, the first end of the first transistor is connected to the power management chip through a first node, the second end of the first transistor is connected to the level converter, the first node, the first resistor, the second node, the capacitor and the ground end are connected in sequence, the control end of the second transistor is connected to the second node, the first end of the second transistor is connected to the control end of the first transistor, the second end of the second transistor is connected to the ground end, the second resistor is connected to the first node and the control end of the first transistor, the first transistor is a P-type field effect transistor, and the second transistor is a PNP-type transistor.

[0011] Optionally, the delay module also includes a first voltage regulator diode and a third resistor, the cathode of the first voltage regulator diode is connected to the second node, the anode of the first voltage regulator diode is connected to the control end of the second transistor, and the third resistor is connected to the control end of the second transistor and the ground end.

[0012] Optionally, the delay module includes a first transistor, a comparator, a capacitor, a first resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, the first end of the first transistor is connected to the power management chip through a first node, the second end of the first transistor is connected to the level converter, the first node, the first resistor, the second node, the capacitor and the ground end are connected in sequence, the first node, the fourth resistor, the third node, the fifth resistor and the ground end are connected in sequence, the non-inverting input end of the comparator is connected to the third node, the inverting input end of the comparator is connected to the second node through the seventh resistor, the positive power supply end of the comparator is connected to the first node, and the positive power supply end of the comparator is connected to the third node through the sixth resistor, and the negative power supply end of the comparator is connected to the ground end.

[0013] Optionally, the delay module further includes a second voltage regulator diode, wherein a cathode of the second voltage regulator diode is connected to the first node, and an anode of the second voltage regulator diode is connected to the second node.

[0014] Optionally, the driving module further includes a pull-down discharge module, which is arranged between the power supply module and the power management chip to prevent the power supply voltage from jumping in the reverse direction during the decline process, or the pull-down discharge module is arranged between the power management chip and the level converter to prevent the operating voltage from jumping in the reverse direction during the decline process; and / or

[0015] The driving module also includes an identification and blocking module, and the level converter includes a below-voltage locking unit. The identification and blocking module is connected to the power supply module, the power management chip and the below-voltage locking unit, and is used to disconnect the electrical connection between the power management chip and the below-voltage locking unit when the power supply voltage is lower than a preset value.

[0016] Optionally, the driving module includes a pull-down discharge module, which includes a third transistor, a fourth transistor, an eighth resistor and a ninth resistor. The first end of the third transistor is connected to the power module through the eighth resistor and the fourth node, the power management chip is connected to the fourth node, the second end of the third transistor is connected to the ground end, the control end of the third transistor is connected to the fourth node, the control end of the fourth transistor is connected between the eighth resistor and the third transistor, the first end of the fourth transistor is connected to the fourth node, the second end of the fourth transistor is connected to the ground end through the ninth resistor, the third transistor is a P-type field effect transistor, and the fourth transistor is an NPN-type transistor.

[0017] Optionally, the driving module includes an identification and blocking module, which includes a fifth transistor, a sixth transistor, a twelfth resistor and a thirteenth resistor. The first end of the fifth transistor is connected to the power management chip, the second end of the fifth transistor is connected to the below-voltage locking unit, the first end of the sixth transistor is connected to the control end of the fifth transistor, the second end of the sixth transistor is connected to the ground end, the control end of the sixth transistor is connected to the power module through the twelfth resistor, the thirteenth resistor is connected to the power module and the first end of the sixth transistor, the fifth transistor is an N-type field effect transistor, and the sixth transistor is an NPN-type transistor.

[0018] The present application also provides a display device, comprising:

[0019] The driving module;

[0020] The display panel is connected to the driving module.

[0021] The driving module and display device disclosed in this application have the following beneficial effects:

[0022] In the present application, the driving module includes a power module, a power management chip, a level converter and a delay module. The power management chip is connected to the power module, the level converter is connected to the power management chip, the power module outputs the power supply voltage to the power management chip, the power management chip converts the power supply voltage into the working voltage required by the level converter, and the delay module is arranged between the power module and the level converter. When the display device is turned off, when the power supply voltage reverses during the decline process, the delay module can prevent the power management chip from generating the working voltage, or the delay module can prevent the generated working voltage from being output to the level converter, thereby avoiding the interruption of the shutdown discharge operation, thereby avoiding the polarization of the liquid crystal caused by the residual charge in the surface, and improving or eliminating the display abnormality.

[0023] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0026] Figure 1 It is a structural diagram of the delay module in Example 1 of the present application.

[0027] Figure 2 It is a structural diagram of the driving module in Example 1 of the present application.

[0028] Figure 3 This is a schematic diagram of the reverse jump of the power supply voltage and the operating voltage during the decline process when the power is turned off.

[0029] Figure 4 This is a schematic diagram of the delay module shielding the working voltage during shutdown.

[0030] Figure 5 This is a schematic diagram of a delay module including a voltage regulator diode in an embodiment of the present application.

[0031] Figure 6 Schematic diagram of a delay module including a comparator in an embodiment of the present application.

[0032] Figure 7 It is a structural diagram of the pull-down discharge module in the second embodiment of the present application.

[0033] Figure 8 This is a structural diagram of the identification and blocking module in Example 3 of the present application.

[0034] Figure 9 It is a structural diagram of the identification and blocking module in Example 4 of the present application.

[0035] Description of reference numerals:

[0036] 100, drive module; 110, power module; 120, power management chip;

[0037] 130. Level converter; 131. Below voltage lock unit;

[0038] 140, delay module; 141, first transistor; 142, second transistor; 143, capacitor; 144, first resistor; 145, second resistor; 146, first Zener diode; 147, third resistor; 148, second Zener diode; 149, fourth resistor; 150, fifth resistor; 151, sixth resistor; 152, seventh resistor; 153, comparator;

[0039] 160. Timing controller; 170. Source driver module;

[0040] 180, pull-down discharge module; 181, third transistor; 182, fourth transistor; 183, eighth resistor; 184, ninth resistor; 185, tenth resistor; 186, eleventh resistor;

[0041] 190, identification and blocking module; 191, fifth transistor; 192, sixth transistor; 193, twelfth resistor; 194, thirteenth resistor;

[0042] 200. Display panel. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0044] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0045] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0046] Example 1

[0047] See also Figure 1 and Figure 2 As shown, in this embodiment, the driver module 100 includes a power module 110, a power management integrated circuit (PMIC) 120, and a level shifter 130. The power management chip 120 is connected to the power module 110, and the level shifter 130 is connected to the power management chip 120. The power module 110 outputs a power supply voltage Vcc to the power management chip 120, which converts the power supply voltage Vcc into the operating voltage Vdd required by the level shifter 130.

[0048] Level converter 130 performs high-to-low level conversion, for example, converting the scanning signal output by the gate driver circuit to drive the pixel driver circuit. Level converter 130 can detect a drop in the power supply voltage Vcc during shutdown and activate a shutdown discharge function, which rapidly discharges the various signals of the pixel driver circuit to ground along a voltage path. This shutdown discharge prevents residual in-plane charge from causing liquid crystal polarization, thereby eliminating display anomalies caused by residual charge.

[0049] The level converter 130 includes an Under Voltage Lockout (UVLO) unit 131. When the Under Voltage Lockout (UVLO) unit 131 is in operation, the shutdown discharge operation will be interrupted. When the display device is shut down, when the power supply voltage Vcc reversely jumps during the falling process, such as Figure 3 As shown, the reverse jump of the power supply voltage Vcc will cause the power management chip 120 to work, and the working voltage Vdd will be generated instantly, which is lower than the voltage locking unit 131 to work, and the shutdown discharge operation will be interrupted, resulting in residual in-plane charge causing liquid crystal polarization, which in turn causes display abnormality.

[0050] In this embodiment, the driver module 100 includes a delay module 140. Adding the delay module 140 can prevent a reverse jump in the power supply voltage Vcc during its decrease, thereby interrupting the shutdown discharge operation. The delay module 140 is disposed between the power module 110 and the level shifter 130. For example, the delay module 140 can be disposed between the power module 110 and the power management chip 120, or between the power management chip 120 and the level shifter 130, or the delay module 140 can be integrated into the power management chip 120.

[0051] When the display device is turned off, when the power supply voltage Vcc reversely jumps during the falling process, the delay module 140 can prevent the power management chip 120 from generating the working voltage Vdd, or the delay module 140 can prevent the generated working voltage Vdd from being output to the level converter 130. Figure 4 As shown, the shutdown discharge operation will not be interrupted.

[0052] In this embodiment, the driving module 100 includes a power module 110, a power management chip 120, a level shifter 130, and a delay module 140. The power management chip 120 is connected to the power module 110, and the level shifter 130 is connected to the power management chip 120. The power module 110 outputs a power supply voltage Vcc to the power management chip 120, which converts the power supply voltage Vcc into an operating voltage Vdd required by the level shifter 130. The delay module 140 is disposed between the power module 110 and the level shifter 130. When the display device is shut down, if the power supply voltage Vcc reverses during its decreasing process, the delay module 140 can prevent the power management chip 120 from generating the operating voltage Vdd, or the delay module 140 can prevent the generated operating voltage Vdd from being output to the level shifter 130. This prevents interruption of the shutdown discharge operation, thereby preventing liquid crystal polarization caused by residual in-plane charge, and improving or eliminating display abnormalities.

[0053] In some embodiments, the delay module 140 is disposed between the power management chip 120 and the level converter 130 . When the power voltage Vcc reverses during a decrease, the delay module 140 can prevent the generated operating voltage Vdd from being output to the level converter 130 .

[0054] The delay module 140 is disposed between the power management chip 120 and the level converter 130 . The delay module 140 is powered by the power management chip 120 . The circuit structure of the delay module 140 is simpler.

[0055] In some embodiments, the driver module 100 further includes a timing controller 160 (TCON) and a source driver module 170 (SD). Both the timing controller 160 and the source driver module 170 are directly connected to the power management chip 120. That is, the operating voltage Vdd output by the power management chip 120 to the level shifter 130 is delayed by the delay module 140, while the operating voltage Vdd output by the power management chip 120 to the timing controller 160 and the source driver module 170 is not delayed by the delay module 140.

[0056] It should be noted that the timing controller 160 and the source driver module 170 can be directly connected to the power management chip 120, but are not limited to this. The timing controller 160 and the source driver module 170 can also be connected to the power management chip 120 through the delay module 140, depending on the specific situation.

[0057] In some embodiments, the delay module 140 includes a first transistor 141, a second transistor 142, a capacitor 143, a first resistor 144, and a second resistor 145. The first end of the first transistor 141 is connected to the power management chip 120 via the first node A, and the second end of the first transistor 141 is connected to the level converter 130. The first node A, the first resistor 144, the second node B, the capacitor 143, and the ground terminal are connected in sequence. The control terminal of the second transistor 142 is connected to the second node B, the first end of the second transistor 142 is connected to the control terminal of the first transistor 141, and the second end of the second transistor 142 is connected to the ground terminal. The second resistor 145 is connected to the first node A and the control terminal of the first transistor 141. The first transistor 141 is a P-type field effect transistor, and the second transistor 142 is a PNP-type triode.

[0058] When the display device is turned off, the power supply voltage Vcc drops, the operating voltage Vdd generated by the power management chip 120 drops, the second transistor 142 is turned off, the control terminal of the first transistor 141 is disconnected from the ground terminal, and the first transistor 141 is turned off;

[0059] When the display device is turned on, the power supply voltage Vcc decreases, the power management chip 120 generates the operating voltage Vdd, the control terminal of the first transistor 141 receives a high-level signal and is turned off, the second transistor 142 is turned off, and the operating voltage Vdd continues to charge the capacitor 143. The voltage of the second node B increases, that is, the voltage of the control terminal of the second transistor 142 increases. When the voltage of the second node B increases to the point where the second transistor 142 turns on, the control terminal of the first transistor 141 is connected to the ground terminal, and the first transistor 141 turns on.

[0060] The delay in turning on the first transistor 141 is determined by the capacitance of the capacitor 143. The larger the capacitance of the capacitor 143, the longer the charging time, and the longer the delay in turning on the first transistor 141. Because charging of the capacitor 143 takes time, when the power supply voltage Vcc reverses during its decreasing process, the operating voltage Vdd generated by the reverse transition disappears before the first transistor 141 turns on and is not output to the level shifter 130, thereby preventing interruption of the shutdown discharge operation.

[0061] It should be noted that the second transistor 142 is a PNP transistor, but is not limited thereto. The second transistor 142 may also be an N-type field effect transistor, depending on the specific situation.

[0062] In some embodiments, the delay module 140 further includes a first voltage stabilizing diode 146 and a third resistor 147, wherein the cathode of the first voltage stabilizing diode 146 is connected to the second node B, and the anode of the first voltage stabilizing diode 146 is connected to the control terminal of the second transistor 142. Figure 5 The third resistor 147 is connected to the control terminal of the second transistor 142 and the ground terminal.

[0063] Disposing a first zener diode 146 between the second node B and the control terminal of the second transistor 142 can increase the turn-on voltage of the second transistor 142, thereby increasing the delay time of the delay module 140. Disposing a third resistor 147 between the control terminal of the second transistor 142 and the ground terminal can direct the reverse leakage current of the first zener diode 146 to the ground terminal, thereby reducing or eliminating leakage of the second transistor 142 during the charging process of the capacitor 143.

[0064] In some embodiments, the delay module 140 further includes a second Zener diode 148 , wherein a cathode of the second Zener diode 148 is connected to the first node A, and an anode of the second Zener diode 148 is connected to the second node B.

[0065] The second voltage stabilizing diode 148 can be used to stabilize the voltage to prevent the voltage at the first node A from being too high and causing damage to the transistor.

[0066] In some embodiments, the delay module 140 includes a first transistor 141, a capacitor 143, a first resistor 144, a fourth resistor 149, a fifth resistor 150, a sixth resistor 151, a seventh resistor 152 and a comparator 153. Figure 6As shown. The first end of the first transistor 141 is connected to the power management chip 120 via the first node A, and the second end of the first transistor 141 is connected to the level converter 130. The first node A, the first resistor 144, the second node B, the capacitor 143, and the ground are connected in sequence, and the first node A, the fourth resistor 149, the third node C, the fifth resistor 150, and the ground are connected in sequence. The non-inverting input of the comparator 153 is connected to the third node C, the inverting input of the comparator 153 is connected to the second node B via the seventh resistor 152, the positive power supply terminal of the comparator 153 is connected to the first node A, and the positive power supply terminal of the comparator 153 is connected to the third node C via the sixth resistor 151. The negative power supply terminal of the comparator 153 is connected to the ground.

[0067] When the display device is turned off, the power supply voltage Vcc decreases, the voltage V+ at the non-inverting input of the comparator 153 becomes greater than the voltage V- at the inverting input of the comparator 153, the comparator 153 outputs a high-level signal, and the first transistor 141 turns off. When the power supply voltage Vcc reverses during the decreasing process, the first transistor 141 remains off because it takes time for the capacitor 143 to charge. This is until the voltage V+ at the non-inverting input of the comparator 153 becomes less than the voltage V- at the inverting input of the comparator 153, the comparator 153 outputs a low-level signal, and the first transistor 141 turns on.

[0068] In the embodiment where the delay module 140 uses the comparator 153, the sixth resistor 151 is a positive feedback resistor, which can effectively eliminate output jitter. When the resistance values of the first transistor 141, the fourth resistor 149 and the sixth resistor 151 are equal, the delay time t of the delay module 140 is:

[0069] ;

[0070] Wherein, R5 is the resistance value of the fifth resistor 150, C is the capacitance value of the capacitor 143, According to the above formula, the delay time t of the delay module 140 is determined by the resistance value of the fifth resistor 150 and the capacitance value of the capacitor 143 .

[0071] It should be noted that, in the embodiment where the delay module 140 adopts the comparator 153, a second zener diode 148 may also be provided. The cathode of the second zener diode 148 is connected to the first node A, and the anode of the second zener diode 148 is connected to the second node B.

[0072] Example 2

[0073] See also Figure 7As shown, the driver module 100 further includes a pull-down discharge module 180, which is disposed between the power module 110 and the power management chip 120 and is configured to prevent the power supply voltage Vcc from jumping in the reverse direction during the falling process. In other embodiments, the pull-down discharge module 180 may also be disposed between the power management chip 120 and the level shifter 130 to prevent the operating voltage Vdd from jumping in the reverse direction during the falling process.

[0074] By forcibly pulling down the power supply voltage Vcc or the operating voltage Vdd through the pull-down discharge module 180 , it is possible to prevent the power supply voltage Vcc or the operating voltage Vdd from reversely jumping and causing the shutdown discharge operation to be interrupted.

[0075] For example, the pull-down discharge module 180 is provided between the power module 110 and the power management chip 120. The pull-down discharge module 180 includes a third transistor 181, a fourth transistor 182, an eighth resistor 183, and a ninth resistor 184. A first terminal of the third transistor 181 is connected to the power module 110 via the eighth resistor 183 and a fourth node D, and the power management chip 120 is connected to the fourth node D. A second terminal of the third transistor 181 is connected to ground, and a control terminal of the third transistor 181 is connected to the fourth node D. A control terminal of the fourth transistor 182 is connected between the eighth resistor 183 and the third transistor 181. A first terminal of the fourth transistor 182 is connected to the fourth node D, and a second terminal of the fourth transistor 182 is connected to ground via the ninth resistor 184. The third transistor 181 is a P-type field-effect transistor, and the fourth transistor 182 is an NPN-type transistor.

[0076] It should be noted that the fourth transistor 182 may be an NPN transistor, but is not limited thereto. The fourth transistor 182 may also be a P-type field effect transistor, depending on the specific situation.

[0077] When the display device is displaying an image, the third transistor 181 is turned off and the fourth transistor 182 is turned off, and they are not turned on to pull down. When the display device is turned off, the power supply voltage Vcc drops, the third transistor 181 is turned off and the fourth transistor 182 is also turned on, thereby turning on and pulling down the power supply voltage Vcc.

[0078] In some embodiments, the pull-down discharge module 180 may further include a tenth resistor 185 and an eleventh resistor 186. The tenth resistor 185 is connected to the fourth node D and the control terminal of the third transistor 181, and the eleventh resistor 186 is connected to the second terminal of the third transistor 181 and the ground terminal.

[0079] The tenth resistor 185 and the eleventh resistor 186 can play the role of voltage stabilization and current limiting.

[0080] Example 3

[0081] See also Figure 8 As shown, the driving module 100 further includes an identification and blocking module 190. The level converter 130 includes a below-voltage locking unit 131. The identification and blocking module 190 is connected to the power module 110, the power management chip 120, and the below-voltage locking unit 131, and is configured to disconnect the electrical connection between the power management chip 120 and the below-voltage locking unit 131 when the power supply voltage Vcc is below a preset value.

[0082] When the display device is turned off, the power supply voltage Vcc drops. When the power supply voltage Vcc is lower than a preset value, the power supply of the below-voltage lockout unit 131 is cut off, that is, the function of the below-voltage lockout unit 131 is blocked. Even if the power supply voltage Vcc and the operating voltage Vdd jump in the opposite direction, the shutdown discharge operation will not be interrupted.

[0083] In some embodiments, the identification and blocking module 190 includes a fifth transistor 191, a sixth transistor 192, a twelfth resistor 193, and a thirteenth resistor 194. A first terminal of the fifth transistor 191 is connected to the power management chip 120, and a second terminal of the fifth transistor 191 is connected to the below-voltage lockout unit 131. A first terminal of the sixth transistor 192 is connected to the control terminal of the fifth transistor 191, a second terminal of the sixth transistor 192 is connected to the ground terminal, and a control terminal of the sixth transistor 192 is connected to the power module 110 via the twelfth resistor 193. The thirteenth resistor 194 connects the power module 110 and the first terminal of the sixth transistor 192. The fifth transistor 191 is an N-type field-effect transistor, and the sixth transistor 192 is an NPN-type transistor.

[0084] It should be noted that the sixth transistor 192 may be an NPN transistor, but is not limited thereto. The fourth transistor 182 may also be a P-type field effect transistor, depending on the specific situation.

[0085] When the display device is turned off, the power supply voltage Vcc drops, and the sixth transistor 192 is turned on, thereby pulling down the voltage at the control terminal of the fifth transistor 191 . The fifth transistor 191 is turned off, and the power supply of the locking unit 131 is cut off.

[0086] Example 4

[0087] See also Figure 9 As shown, the display device in this embodiment includes the driving module 100 and the display panel 200 disclosed in the first to third embodiments, and the display panel 200 is connected to the driving module 100. It should be noted that the driving module 100 may include one, a combination of any two, or all three of the delay module 140, the pull-down discharge module 180, and the identification and blocking module 190.

[0088] In this embodiment, a display device includes a driving module 100, which includes a power module 110, a power management chip 120, a level shifter 130, and a delay module 140. The power management chip 120 is connected to the power module 110, and the level shifter 130 is connected to the power management chip 120. The power module 110 outputs a power supply voltage Vcc to the power management chip 120, which converts the power supply voltage Vcc into an operating voltage Vdd required by the level shifter 130. The delay module 140 is disposed between the power module 110 and the level shifter 130. When the display device is shut down, if the power supply voltage Vcc reverses during a decreasing process, the delay module 140 can prevent the power management chip 120 from generating the operating voltage Vdd, or the delay module 140 can prevent the generated operating voltage Vdd from being output to the level shifter 130. This prevents interruption of the shutdown discharge operation, thereby preventing liquid crystal polarization caused by residual in-plane charge, and improving or eliminating display abnormalities.

[0089] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0090] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0091] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A driving module, comprising a power module and a power management chip, wherein the power management chip is connected to the power module, characterized in that: The driving module further includes: a level converter, connected to the power management chip, and configured to convert the power voltage provided by the power module into an operating voltage of the level converter; a delay module, disposed between the power management chip and the level converter, and capable of preventing the generated operating voltage from being output to the level converter when the power supply voltage reverses during a decreasing process; In which, the delay module includes a first transistor, a comparator, a capacitor, a first resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, the first end of the first transistor is connected to the power management chip through a first node, the second end of the first transistor is connected to the level converter, the first node, the first resistor, the second node, the capacitor and the ground end are connected in sequence, the first node, the fourth resistor, the third node, the fifth resistor and the ground end are connected in sequence, the non-inverting input end of the comparator is connected to the third node, the inverting input end of the comparator is connected to the second node through the seventh resistor, the positive power supply end of the comparator is connected to the first node, and the positive power supply end of the comparator is connected to the third node through the sixth resistor, and the negative power supply end of the comparator is connected to the ground end.

2. The driving module according to claim 1, characterized in that: The delay module further includes a second Zener diode, wherein a cathode of the second Zener diode is connected to the first node, and an anode of the second Zener diode is connected to the second node.

3. The driving module according to claim 1, wherein: The driving module further includes a pull-down discharge module, which is arranged between the power supply module and the power management chip, and is used to prevent the power supply voltage from jumping in the reverse direction during the decline process, or the pull-down discharge module is arranged between the power management chip and the level converter, and is used to prevent the operating voltage from jumping in the reverse direction during the decline process; and / or The driving module also includes an identification and blocking module, and the level converter includes a below-voltage locking unit. The identification and blocking module is connected to the power supply module, the power management chip and the below-voltage locking unit, and is used to disconnect the electrical connection between the power management chip and the below-voltage locking unit when the power supply voltage is lower than a preset value.

4. The driving module according to claim 3, characterized in that: The driving module includes a pull-down discharge module, which includes a third transistor, a fourth transistor, an eighth resistor and a ninth resistor. The first end of the third transistor is connected to the power module through the eighth resistor and the fourth node, the power management chip is connected to the fourth node, the second end of the third transistor is connected to the ground end, the control end of the third transistor is connected to the fourth node, the control end of the fourth transistor is connected between the eighth resistor and the third transistor, the first end of the fourth transistor is connected to the fourth node, the second end of the fourth transistor is connected to the ground end through the ninth resistor, the third transistor is a P-type field effect transistor, and the fourth transistor is an NPN-type transistor.

5. The driving module according to claim 4, characterized in that: The driving module includes an identification and blocking module, which includes a fifth transistor, a sixth transistor, a twelfth resistor and a thirteenth resistor. The first end of the fifth transistor is connected to the power management chip, the second end of the fifth transistor is connected to the below-voltage locking unit, the first end of the sixth transistor is connected to the control end of the fifth transistor, the second end of the sixth transistor is connected to the ground end, the control end of the sixth transistor is connected to the power module through the twelfth resistor, the thirteenth resistor is connected to the power module and the first end of the sixth transistor, the fifth transistor is an N-type field-effect transistor, and the sixth transistor is an NPN-type transistor.

6. A display device, characterized in that: include: The drive module according to any one of claims 1 to 5; The display panel is connected to the driving module.

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