Self-refreshing page buffer, electronic equipment and full-page programming method

Abstract

The invention provides a self-refreshing page buffer, electronic equipment and a full-page programming method, and the self-refreshing page buffer comprises a self-refreshing signal generation module which generates and latches a valid self-refreshing trigger signal based on an external trigger signal, and invalidates the self-refreshing trigger signal after a last-stage delay control signal output by a delay module is valid; the delay module is used for delaying the self-refreshing trigger signal to obtain N delay control signals which are lagged in sequence; the grouped driving module is used for generating corresponding driving signals based on the delay control signals, and the driving signals are lagged in sequence; and the data caching module is used for respectively driving the corresponding M rows of storage units to write data on the basis of the driving signals. According to the invention, the data sending time is saved, so that the test cost is saved, and the product competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memories, and particularly to a self-refresh page buffer, an electronic device, and a full-page programming method. Background Art

[0002] A page buffer circuit is a circuit for storing and managing data, usually applied to a storage device, which serves as a transfer station during the process of data reading and writing, can improve the efficiency of data transmission; can also improve the threshold voltage distribution of storage cells, thereby improving the reading reliability of the storage device; in addition, the page buffer can also optimize the performance of the storage device, reduce the reading time, improve the integration degree of the storage device, and flexibly respond to different operation requirements.

[0003] Such as Figure 1 There is a page buffer 1, which includes a static random access memory circuit 12 (SRAM) and logic circuits 11, 13. Among them, the static random access memory circuit 12 is the circuit for storing data in the page buffer 1, including a memory array composed of a plurality of memory cells; the logic circuit 11 includes a NAND gate 111 and an inverter 112, and the corresponding word line WL of the static random access memory circuit 12 is selected by the simultaneous action of the address signal ADDR_H and the trigger signal TRI_SNG. The logic circuit 13 includes two inverters 131, 132 and MOS transistors M1, M2, M3, M4. The write data WR_DATA is loaded onto the bit lines BL, BLN of the static random access memory circuit 12 through the address signal ADDR_L. Through the opening and closing of the word line and the bit line, the data is written and latched into the static random access memory circuit 12. Each operation selects 1 word line WL and 8 bit lines BL.

[0004] The main parameter related to the page buffer circuit is the overall time required for caching a page (page), especially when the capacity of the page is large and the whole chip is programmed, this time is very large, and this time is related to the external clock frequency f (f = 1 / T, T is the external clock period). Such as Figure 2As shown, the memory chip is only allowed to be operated when the chip select signal CS is pulled low; subsequently, the chip receives the write command CMD and the write address ADDR; then it receives the write data WR_DATA. The write data WR_DATA is an 8-bit wide data bus. One clock samples 1 bit of the write data (usually at the rising edge of the clock signal CLK). Therefore, it takes 8 clocks to receive 1 byte (8 bits) of write data. When the trigger signal TRI_SNG is pulled low, the write data WR_DATA is stored in the static random access memory circuit 12. The page buffer pulls low the trigger signal TRI_SNG every time it stores 1 byte of the write data WR_DATA. So, it takes 8 clocks to store 1 byte of write data.

[0005] In certain specific test processes (including but not limited to checkerboard, reverse checkerboard), the entire chip needs to be programmed (writing the same data to each storage unit), and the external master sends data to the FLASH chip. The time proportion of this link is very large. Taking a 64M capacity as an example, for programming the entire chip, in the normal test method: the maximum capacity of the page where the page buffer stores data is 2048 bits, and it can store 256 bytes of data to be written. There are 32768 pages in the entire chip. Assuming the external clock frequency is 20M, the time required for the page buffer to store the write data when programming the entire chip satisfies the following relationship:

[0006] T page = 256·8·T = 256·8·1 / f = 256·8·50ns = 102.4us,

[0007] T all = 32768·T page = 32768·102.4us ≈ 3.355s,

[0008] Among them, T page is the time required to fill the entire page buffer, and T all is the overall time required to store the data of the entire chip. It can be seen that the time required for the programming test is very long.

[0009] Therefore, how to shorten the programming test time and reduce the production cost has become one of the problems that need to be solved urgently by those skilled in the art.

[0010] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0011] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a self-refresh page buffer, an electronic device, and a full-page programming method, which are used to solve the problems of long programming test time and high production cost in the prior art.

[0012] To achieve the above object and other related objects, the present invention provides a self-refresh page buffer, and the self-refresh page buffer at least includes:

[0013] A self-refresh signal generation module, a delay module, a grouping driving module, and a data cache module;

[0014] The self-refresh signal generation module receives an external trigger signal and is connected to the output end of the delay module, generates and latches a valid self-refresh trigger signal based on the external trigger signal, and invalidates the self-refresh trigger signal after the last-stage delay control signal output by the delay module becomes valid.

[0015] The delay module is connected to the output end of the self-refresh signal generation module, and delays the self-refresh trigger signal to obtain N sequentially lagged delay control signals;

[0016] The grouping driving module is connected to the output end of the delay module, generates corresponding driving signals based on each delay control signal, and each driving signal lags sequentially;

[0017] The data cache module receives each driving signal and drives the corresponding M rows of storage units to write data respectively based on each driving signal;

[0018] Wherein, N and M are natural numbers greater than or equal to 2 respectively.

[0019] Optionally, the self-refresh signal generation module includes a delay unit, a first logic unit, a second logic unit, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a latching unit;

[0020] The delay unit receives the external trigger signal and outputs a delayed signal of the external trigger signal;

[0021] The first logic unit is connected to the output end of the delay unit and receives the external trigger signal, and outputs a valid first control signal when both the external trigger signal and the output signal of the delay unit are valid;

[0022] The second logic unit receives an enable signal and the last-stage delay control signal, and outputs a valid second control signal when the enable signal is invalid or the last-stage delay control signal is valid;

[0023] The first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series between the power supply and the ground in sequence; the gates of the first PMOS transistor and the first NMOS transistor are connected to the output terminal of the first logic unit, and the gate of the second NMOS transistor is connected to the output terminal of the second logic unit;

[0024] The input terminal of the latch unit is connected to the drains of the first PMOS transistor and the first NMOS transistor, and the output terminal outputs the self-refresh trigger signal.

[0025] Optionally, the delay module includes N delay units, and the delay units are connected in series in sequence.

[0026] More optionally, the delay module further includes a delay inversion unit, and the delay inversion unit is connected to the input terminal of the first-stage delay unit, and delays the self-refresh trigger signal by a preset duration and inverts it, and then provides it to each delay unit.

[0027] Optionally, the grouped driving module includes N driving units, and each driving unit receives a delay control signal respectively and generates a corresponding driving signal.

[0028] Optionally, the data cache module includes a storage array and a bit line control circuit;

[0029] The storage units in the same row in the storage array are connected to the same word line, and the storage units in the same column are connected to the same bit line;

[0030] The bit line control circuit is connected to the bit lines of each storage unit and is used to control the opening and closing of the corresponding bit lines.

[0031] More optionally, the bit line control circuit includes I groups of control units, and each group of control units is respectively connected to the corresponding J groups of bit lines, where I and J are natural numbers greater than or equal to 1, and I * J is equal to the number of columns of the storage array;

[0032] Each group of control units includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; among them, the source of the third NMOS transistor is grounded, the gate is connected to the write data, and the drain is connected to the source of the fourth NMOS transistor; the gate of the fourth NMOS transistor is controlled by the enable signal, and the drain is connected to the first bit line of the corresponding storage unit; the source of the fifth NMOS transistor is grounded, the gate is connected to the inverse signal of the write data, and the drain is connected to the source of the sixth NMOS transistor; the gate of the sixth NMOS transistor is controlled by the enable signal, and the drain is connected to the second bit line of the corresponding storage unit.

[0033] More optionally, M is set to 2 - 32.

[0034] To achieve the above and other related objectives, the present invention further provides an electronic device, which at least includes: a processor, a main memory, and the above-mentioned self-refresh page buffer;

[0035] The self-refresh page buffer is arranged between the processor and the main memory, and is used for temporarily storing the data read from the main memory or caching the data to be written into the main memory.

[0036] To achieve the above and other related objectives, the present invention further provides a full-page programming method, which at least includes:

[0037] After the page buffer is enabled and receives the programming test data, the external trigger signal becomes valid and triggers the generation of a valid self-refresh trigger signal, and the self-refresh trigger signal undergoes multiple levels of delay to obtain N sequentially lagged delay control signals; wherein, each bit of data in the programming test data is the same;

[0038] Based on each delay control signal, corresponding drive signals are respectively generated, and the drive signals act with sequential delay, and each drive signal drives the corresponding M rows of memory cells to write data simultaneously;

[0039] When the last-level delay control signal becomes valid, the self-refresh trigger signal jumps to an invalid state, and all the memory cells in the current page buffer complete data writing and latching;

[0040] Wherein, N and M are natural numbers greater than or equal to 2 respectively.

[0041] Optionally, the programming test data is 1-byte data, and one drive signal based on 1-byte data refreshes 8 bytes, 16 bytes, 32 bytes, or 64 bytes of the storage capacity in the page buffer each time, and fills the entire storage capacity of the page buffer through N refreshes.

[0042] As described above, the self-refresh page buffer, electronic device, and full-page programming method of the present invention have the following beneficial effects:

[0043] The self-refresh page buffer, electronic device, and full-page programming method of the present invention can open the word lines of all static random access memory circuits in sequence and store the write data into the entire page capacity only by receiving external write data once and a valid trigger signal once; greatly shortening the time for the page buffer to store write data in the programming operation, improving efficiency and saving test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It shows a schematic structural diagram of a page buffer.

[0045] Figure 2Shown as Figure 1 Schematic diagram of the working principle of the page buffer.

[0046] Figure 3 Shown as the block diagram of the self-refresh page buffer of the present invention.

[0047] Figure 4 Shown as the structural schematic diagram of the self-refresh signal generation module of the present invention.

[0048] Figure 5 Shown as the structural schematic diagram of the delay module of the present invention.

[0049] Figure 6 Shown as the structural schematic diagram of the group driving module of the present invention.

[0050] Figure 7 Shown as the structural schematic diagram of the data cache module of the present invention.

[0051] Figure 8 Shown as the structural schematic diagram of the storage unit of the present invention.

[0052] Figure 9 Shown as the schematic diagram of the working principle of the self-refresh page buffer of the present invention.

[0053] Figure 10 Shown as the block diagram of the electronic device of the present invention.

[0054] Description of component labels

[0055] 1 Page buffer

[0056] 11, 13 Logic circuit

[0057] 111 NAND gate

[0058] 112 Inverter

[0059] 12 Static random access memory circuit

[0060] 131, 132 Inverter

[0061] 2 Self-refresh page buffer

[0062] 21 Self-refresh signal generation module

[0063] 211 Delay unit

[0064] 212 First logic unit

[0065] 213 Second logic unit

[0066] 214 Latch unit

[0067] 21a, 21b, 21c Inverter

[0068] 21d, 21e First, second OR gates

[0069] 21f, 21g Inverters

[0070] 22 Delay module

[0071] 221 Delay unit

[0072] 222 Delay inversion unit

[0073] 22a, 22b Delay circuits

[0074] 22c Inverter

[0075] 23 Group drive module

[0076] 231 Drive unit

[0077] 23a, 23b Buffers

[0078] 24 Data cache module

[0079] 241 Storage array

[0080] 242 Bit line control circuit

[0081] 24a Inverter

[0082] 24b Storage cell

[0083] 3 Processor

[0084] 4 Main memory Detailed implementation manners

[0085] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0086] Please refer to Figures 3 to 10 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0087] Such as Figure 3As shown in the figure, the present invention provides a self-refresh page buffer 2, which includes a self-refresh signal generation module 21, a delay module 22, a packet driving module 23, and a data cache module 24.

[0088] As Figure 3 shown, the self-refresh signal generation module 21 receives an external trigger signal TRI_SNG and is connected to the output end of the delay module 22, generates and latches a valid self-refresh trigger signal en_tri (which remains valid throughout the process when the self-refresh page buffer 2 caches the full-page data), and invalidates the self-refresh trigger signal en_tri after the last-stage delay control signal output by the delay module 22 becomes valid.

[0089] Specifically, as Figure 4As shown, for example, the self-refresh signal generation module 21 includes a delay unit 211, a first logic unit 212, a second logic unit 213, a first PMOS transistor P1, a first NMOS transistor N1, a second NMOS transistor N2, and a latch unit 214. Among them, the delay unit 211 receives an external trigger signal TRI_SNG and outputs a delayed signal of the external trigger signal TRI_SNG; in this embodiment, the delay unit 211 is implemented by three (or other odd numbers) cascaded inverters 21a, 21b, and 21c, and the delay time is the gate delay of three inverters. The first logic unit 212 is connected to the output end of the delay unit 211 and receives the external trigger signal TRI_SNG, and outputs a valid first control signal when both the external trigger signal TRI_SNG and the output signal of the delay unit 211 are valid; in this embodiment, the first logic unit 212 is implemented by a first OR gate 21d. At this time, the trigger signal TRI_SNG is active low, and the first control signal is active low. The second logic unit 213 receives an enable signal EN_INI and the last-stage delay control signal (in this embodiment, the last-stage delay control signal is delay15_en), and outputs a valid second control signal when the enable signal EN_INI is invalid or the last-stage delay control signal delay15_en is valid; in this embodiment, the second logic unit 213 is implemented by a second OR gate 21e. At this time, the enable signal EN_INI is active low, the delay control signal is active high, and the second control signal is active high. The source of the first PMOS transistor P1 is connected to the power supply, the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected and receive the first control signal, and the drains of the first PMOS transistor P1 and the first NMOS transistor N1 are connected; the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2; the gate of the second NMOS transistor N2 receives the second control signal, and the source is grounded. The input end of the latch unit 214 is connected to the drains of the first PMOS transistor P1 and the first NMOS transistor N1, and the output end outputs a self-refresh trigger signal en_tri; in this embodiment, the latch unit 214 is implemented by two cross-coupled inverters 21f and 21g. In actual use, appropriate logic gate circuits and analog devices can be selected according to needs to implement the function of the self-refresh signal generation module 21 of the present invention, and it is not limited to this embodiment.

[0090] Specifically, when the enable signal EN_INI is active low, the self-refresh signal generation module 21 is in the working state; when the trigger signal TRI_SNG is active low, the delay unit 211 provides the delayed signal of the trigger signal TRI_SNG to the first logic unit 212. The first logic unit 212 outputs a low-level signal to turn on the first PMOS transistor P1 and turn off the first NMOS transistor N1. At this time, the second NMOS transistor N2 is also in the cut-off state. The latch unit 214 latches the low-level signal output from the drains of the first PMOS transistor P1 and the first NMOS transistor N1 to obtain a self-refresh trigger signal en_tri that is active low. Subsequently, the first control signal output by the first logic unit 212 jumps to a high level, turning off the first PMOS transistor P1 and turning on the first NMOS transistor N1. At this time, due to the function of the latch unit 214, the self-refresh trigger signal en_tri remains in the active low state. The self-refresh trigger signal en_tri is delayed by the subsequent delay module 22 to obtain a delay control signal. When the last-stage delay control signal delay15_en is active high, the second control signal jumps to a high level and the second NMOS transistor N2 is turned on. Then, the input signal of the latch unit 214 is pulled low, the latch state changes, and the self-refresh trigger signal en_tri jumps from the active low state to the invalid high state. The active levels of the signals can be set according to actual needs and are not limited to this embodiment.

[0091] As Figure 3 shown, the delay module 22 is connected to the output terminal of the self-refresh signal generation module 21 to delay the self-refresh trigger signal en_tri to obtain N sequentially lagging delay control signals, where N is a natural number greater than or equal to 2.

[0092] Specifically, in this embodiment, N is set to 16; in actual use, it is configured according to actual needs. As Figure 4As shown, the delay module 22 includes 16 delay units 221, and the delay units 221 are connected in series in sequence to output the first to sixteenth delay control signals delay0_en... delay15_en (in this embodiment, the high level of each delay control signal is valid); the structure of the delay unit 221 is not limited and will not be elaborated one by one here. As another example, the delay module 22 further includes a delay inversion unit 222. The delay inversion unit 222 is connected to the input end of the first-stage delay unit 221 (that is, the delay inversion unit 222 is connected in series with each delay unit 221 in sequence), delays the self-refresh trigger signal en_tri by a preset duration and inverts it, and then provides it to each delay unit 221; in this embodiment, the delay inversion unit 222 includes a delay circuit 22a, a delay circuit 22b, and an inverter 22c connected in series in sequence; the delay inversion unit 222 is used to adjust the delay time of the entire signal path and the logic level of the signal, and the corresponding circuit structure is set according to needs, not limited to this embodiment.

[0093] Specifically, the self-refresh trigger signal en_tri is delayed and its logic level is changed through the delay inversion unit 222, and then each delay control signal is sequentially and laggedly output through each delay unit 221, that is, each delay control signal is generated by delaying the previous delay control signal; as Figure 5 shown, the first delay control signal delay0_en is delayed to obtain the second delay control signal delay1_en, and so on, the fifteenth delay control signal delay14_en is delayed to obtain the sixteenth delay control signal delay15_en.

[0094] As Figure 3 shown, the grouped driving module 23 is connected to the output end of the delay module 22 and generates corresponding driving signals based on each delay control signal.

[0095] Specifically, as Figure 6 shown, in this embodiment, the grouped driving module 23 includes 16 driving units 231. The driving units 231 are independent of each other, each receives a delay control signal, and generates a corresponding driving signal. Each driving signal lags in sequence (in this example, the lag duration is determined by the delay module 22). As an example, each driving unit 231 includes two series-connected buffers 23a and 23b with an inverting function; any circuit structure that can improve the signal driving ability is applicable to the driving unit of the present invention, not limited to this embodiment. As Figure 6As shown, the first delay control signal delay0_en is buffered to obtain the first drive signal drv0_en, the second delay control signal delay1_en is buffered to obtain the second drive signal drv1_en, and so on. The fifteenth delay control signal delay14_en is buffered to obtain the fifteenth drive signal drv14_en, and the sixteenth delay control signal delay15_en is buffered to obtain the sixteenth drive signal drv15_en. Each drive unit has the same delay duration. Therefore, the delay durations and corresponding relationships of the drive signals are the same as those of the delay control signals.

[0096] As Figure 3 shown, the data buffer module 24 receives each drive signal and drives the corresponding M rows of memory cells to write data based on each drive signal, where M is a natural number greater than or equal to 2.

[0097] Specifically, as Figure 7 shown, the data buffer module 24 includes a memory array 241 and a bit line control circuit 242; the memory array 241 is composed of memory cells for storing data, including but not limited to SRAM; the bit line control circuit 242 is connected to the bit lines of each memory cell for controlling the opening and closing of the corresponding bit lines.

[0098] More specifically, in this embodiment, the memory array 241 includes 64 rows × 32 columns of memory cells. The word lines WL of the memory cells in the same row are connected together, and the column lines BL of the memory cells in the same column are connected together; as Figure 8 shown, as an example, each memory cell 24b adopts a 6T structure, including cross-coupled inverters XS1, XS2, and select transistors MS1, MS2 (either PMOS or NMOS transistors are acceptable). The select transistor MS1 is connected to the first bit line BL, the select transistor MS2 is connected to the second bit line BLN, and the gates of the select transistors MS1 and MS2 are both connected to the word line WL. In this embodiment, M is set to 4, that is, every 4 word lines WL receive the same drive signal. As Figure 7 shown, the word lines WL<3:0> receive the first drive signal drv0_en, the word lines WL<7:4> receive the second drive signal drv1_en, and so on. The word lines WL<59:56> receive the fifteenth drive signal drv14_en, and the word lines WL<63:60> receive the sixteenth drive signal drv14_en; considering the drive capability and efficiency issues, generally M is set to 2 - 32, including but not limited to 6, 8, 12, 24, which will not be elaborated here one by one. In actual use, the value of M can be set according to actual needs, as long as N*M = the total number of rows of the memory array, and this is not limited to this embodiment.

[0099] More specifically, the bit line control circuit 242 includes I groups of control units, and each group of control units is respectively connected to the corresponding J groups of bit lines. I and J are natural numbers greater than or equal to 1, and I*J is equal to the number of columns of the memory array. In this embodiment, I is set to 8 and J is set to 4, and I*J = 32, that is, 32 columns are divided into 4 groups, with 8 columns in each group (that is, the written data is 8-bit data WR_DATA<7:0>, and each bit of data in the same group corresponds to a column of memory cells). In actual use, the values of I and J can be set according to the specific array capacity, and are not limited to this embodiment. As an example, each group of control units includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. Among them, the source of the third NMOS transistor N3 is grounded, the gate is connected to the write data WR_DATA, and the drain is connected to the source of the fourth NMOS transistor N4. The drain of the fourth NMOS transistor N4 is connected to the first bit line BL of the corresponding memory cell. The source of the fifth NMOS transistor N5 is grounded, and the gate is connected to the inverted signal of the write data The drain is connected to the source of the sixth NMOS transistor N6. The drain of the sixth NMOS transistor N6 is connected to the second bit line BLN of the corresponding memory cell. The gates of the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are controlled by the enable signal EN_INI (in this example, the enable signal EN_INI is connected to the gates of the fourth NMOS transistor N4 and the sixth NMOS transistor N6 after passing through the inverter 24a).

[0100] More specifically, when the enable signal EN_INI is valid, the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are selected. After receiving the write data, each data is loaded onto the corresponding bit line. When the corresponding word line WL is selected, 4 rows of memory cells are written with data simultaneously. 16 word lines are sequentially selected, and finally 64 rows of memory cells all complete the data writing.

[0101] As Figure 9 shown, the present invention also provides a full-page programming method, which is applied to testing, wherein the data written in each memory cell of the whole chip is the same. In this embodiment, the full-page programming method is implemented based on the self-refresh page buffer 2 of the present invention. In actual use, any structure that can implement this method is applicable to the present invention. This method includes:

[0102] After the page buffer is enabled and receives the programming test data, the external trigger signal is valid and triggers the generation of a valid self-refresh trigger signal. The self-refresh trigger signal passes through multiple delays to obtain N sequentially lagging delay control signals. Among them, each bit of data in the programming test data is the same;

[0103] Based on each delay control signal, corresponding driving signals are respectively generated. Each driving signal acts with a delay in sequence, and each driving signal drives the corresponding M rows of memory cells to write data simultaneously;

[0104] After the last - stage delay control signal becomes valid, the self - refresh trigger signal jumps to the invalid state, and all storage units in the current page buffer complete data writing and latching.

[0105] Wherein, N and M are natural numbers greater than or equal to 2 respectively.

[0106] Specifically, since it takes time to receive and transmit programming test data (i.e., write data WR_DATA) one bit per clock CLK, in this embodiment, the programming test data is set to 1 - byte data to shorten the data transmission duration (data transmission can be completed in 8 clocks); of course, in actual use, the number of bits of the programming test data can be set according to actual needs, including but not limited to 2 bytes, which will not be elaborated here one by one. In this embodiment, one drive signal refreshes 16 - byte (4 rows × 32 - column storage units) of the storage capacity in the page buffer each time based on 1 - byte data, and fills the entire storage capacity of the page buffer after 16 refreshes; in actual use, the storage capacity refreshed each time can be configured as 8 bytes, 32 bytes, 64 bytes, etc., which will not be elaborated here one by one.

[0107] The specific steps of the present invention are as follows:

[0108] 1) The chip - select signal CS is pulled low, and the current page buffer is selected; through several clocks CLK, the write command CMD and the initial write address ADDR sent externally are received. At this time, the enable signal EN_INI flips from high level to low level (valid); subsequently, the write data WR_DATA required for the programming test operation is received. When 1 - byte write data is received inside the self - refresh page buffer 2, the external trigger signal TRI_SNG is pulled low, and the data storage operation of the page buffer starts.

[0109] 2) After the self - refresh signal generation module 21 receives the valid low - level external trigger signal TRI_SNG (the external trigger signal TRI_SNG is pulled high after half a clock CLK) and the enable signal EN_INI, it generates the self - refresh trigger signal en_tri of the page buffer. The self - refresh trigger signal en_tri is valid during the process of the page buffer storing full - page data and always remains low - level; and the enable signal EN_INI simultaneously turns on all bit - line switches and temporarily stores the received write data WR_DATA in each bit - line.

[0110] 3) The self - refresh trigger signal en_tri is used as the input signal of the delay module 22 to generate 16 delay signal lines in sequence. These 16 delay signal lines generate 16 drive signals through the grouped drive module 23, and each drive signal becomes valid with a delay in sequence.

[0111] 4) The driving signals generated by the grouping driving module 23 are used to drive the word lines of the storage units in the data storage module 24. Each driving signal drives 4 word lines. Since there is a time delay between every two adjacent effective driving signals, the bit lines in the storage array are grouped in sets of 4, and each set is turned on in sequence. Each effective driving signal can store 16 bytes of data into the data storage module. Until the last driving signal becomes effective, the page buffer is filled with the data of the entire page.

[0112] 5) The last delay signal becomes effective and acts on the self - refresh signal generation module 21. The self - refresh trigger signal en_tri flips from low level to high level (invalid), sequentially pulls down all the delay signal lines and driving signal lines, turns off all the word lines in the storage array, and latches the written data into the page buffer. Finally, the chip select signal CS is pulled high, and the full - chip programming is completed.

[0113] It can be seen from this that the self - refresh page buffer and the full - page programming method of the present invention only need to receive one write data WR_DATA and one effective external trigger signal TRI_SNG to perform the operation of storing and writing data for the entire page, realizing the function of refreshing the data storage of the entire page, greatly improving the efficiency of the page buffer, and shortening the test time in some test processes. Taking the example of a full - chip capacity of 64M, 32768 pages in the whole chip, and an external clock frequency equal to 20M, when performing a full - chip programming operation, the total time required for the self - refresh page buffer of the present invention to store and write data satisfies the following relationship:

[0114] T npage = 8·T = 8·1 / f = 8·50ns = 400ns,

[0115] T nall = 32768·T npage = 32768·400ns≈13.11ms

[0116] Among them, T npage is the time required to fill the entire self - refresh page buffer of the present invention, and T nall is the overall time required to store the data of the entire chip (constituted by the self - refresh page buffer of the present invention).

[0117] T nall is 256 times smaller than T all This is only the time saved by testing one chip. The larger the capacity and the more the number of storage chips, the more significant the effect of time reduction. The self - refresh page buffer of the present invention greatly improves the time for the main control to send data during the programming test, not only improving the efficiency of the overall test process, but also saving the test cost.

[0118] Such as Figure 10As shown in the figure, the present invention also provides an electronic device, including: the self-refresh page buffer 2 of the present invention, a processor 3, and a main memory 4. Among them, the self-refresh page buffer 2 is disposed between the processor 3 and the main memory 4, and is used to temporarily store the data read from the main memory 4 or cache the data to be written into the main memory 4. The electronic device includes but is not limited to SPI FLASH, which will not be elaborated here one by one.

[0119] In summary, the present invention provides a self-refresh page buffer, an electronic device, and a full-page programming method. Among them, the self-refresh page buffer includes: a self-refresh signal generation module, a delay module, a grouped driving module, and a data caching module; the self-refresh signal generation module receives an external trigger signal and is connected to the output end of the delay module, generates and latches a valid self-refresh trigger signal based on the external trigger signal, and invalidates the self-refresh trigger signal after the last-stage delay control signal output by the delay module becomes valid; the delay module is connected to the output end of the self-refresh signal generation module, delays the self-refresh trigger signal to obtain N sequentially lagging delay control signals; the grouped driving module is connected to the output end of the delay module, generates corresponding driving signals based on each delay control signal, and each driving signal lags sequentially; the data caching module receives each driving signal and drives the corresponding M rows of memory cells to write data respectively based on each driving signal; N and M are natural numbers greater than or equal to 2. The self-refresh page buffer, electronic device, and full-page programming method of the present invention can open the word lines of all static random access memory circuits in sequence and then store the write data for programming tests into the capacity of the entire page by receiving only one external write data and one valid trigger signal once; it saves the time of sending data, thereby saving the test cost and enhancing the competitiveness of the product. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0120] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A self-refreshing page cache, characterized in that, The self-refresh page buffer at least includes: a self-refresh signal generation module, a delay module, a group driving module, and a data buffer module; The self-refresh signal generation module receives an external trigger signal and is connected to the output end of the delay module, generates and latches a valid self-refresh trigger signal based on the external trigger signal, and invalidates the self-refresh trigger signal after the last-stage delay control signal output by the delay module becomes valid; The delay module is connected to the output end of the self-refresh signal generation module, and delays the self-refresh trigger signal to obtain N sequentially lagged delay control signals; The group driving module is connected to the output end of the delay module, generates corresponding driving signals based on the respective delay control signals, and the driving signals lag sequentially; The data buffer module receives the driving signals and drives the corresponding M rows of memory cells to write data respectively based on the driving signals; wherein, N and M are natural numbers greater than or equal to 2 respectively.

2. The self-refreshing page buffer according to claim 1, wherein: The self-refresh signal generation module includes a delay unit, a first logic unit, a second logic unit, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a latching unit; The delay unit receives the external trigger signal and outputs a delayed signal of the external trigger signal; The first logic unit is connected to the output end of the delay unit and receives the external trigger signal, and outputs a valid first control signal when both the external trigger signal and the output signal of the delay unit are valid; The second logic unit receives an enable signal and the last-stage delay control signal, and outputs a valid second control signal when the enable signal is invalid or the last-stage delay control signal is valid; The first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are sequentially connected in series between the power supply and the ground; the gates of the first PMOS transistor and the first NMOS transistor are connected to the output end of the first logic unit, and the gate of the second NMOS transistor is connected to the output end of the second logic unit; The input end of the latching unit is connected to the drains of the first PMOS transistor and the first NMOS transistor, and the output end outputs the self-refresh trigger signal.

3. The self-refreshing page buffer according to claim 1, wherein: The delay module includes N delay units, and the delay units are sequentially connected in series.

4. The self-refreshing page buffer according to claim 3, wherein: The delay module further includes a delay inverting unit, and the delay inverting unit is connected to the input end of the first-stage delay unit, delays the self-refresh trigger signal by a preset duration and inverts it, and then provides it to each delay unit.

5. The self-refreshing page buffer according to claim 1, wherein: The group driving module includes N driving units, and each driving unit receives a delay control signal respectively and generates a corresponding driving signal.

6. The self-refreshing page buffer according to claim 1, wherein: The data buffer module includes a memory array and a bit line control circuit; In the memory array, the memory cells in the same row are connected to the same word line, and the memory cells in the same column are connected to the same bit line; The bit line control circuit is connected to the bit lines of the memory cells, and is used to control the opening and closing of the corresponding bit lines.

7. The self-refreshing page buffer according to claim 6, wherein: The bit line control circuit includes I groups of control units, and each group of control units is respectively connected to the corresponding J groups of bit lines. I and J are natural numbers greater than or equal to 1, and I * J is equal to the number of columns of the memory array; Each control unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; wherein, the source of the third NMOS transistor is grounded, the gate is connected to the write data, and the drain is connected to the source of the fourth NMOS transistor; the gate of the fourth NMOS transistor is controlled by an enable signal, and the drain is connected to the first bit line of the corresponding memory cell; the source of the fifth NMOS transistor is grounded, the gate is connected to the inverse signal of the write data, and the drain is connected to the source of the sixth NMOS transistor; the gate of the sixth NMOS transistor is controlled by the enable signal, and the drain is connected to the second bit line of the corresponding memory cell.

8. The self-refreshing page buffer according to claim 1 or 6, characterized in that: M is set to 2 - 32.

9. An electronic device, characterized in that, The electronic device at least includes: a processor, a main memory, and the self - refreshing page buffer as described in any one of claims 1 - 8; The self - refreshing page buffer is disposed between the processor and the main memory, and is used for temporarily storing the data read from the main memory, or for temporarily storing the data to be written into the main memory.

10. A full-page programming method, characterized in that, The full - page programming method at least includes: After the page buffer is enabled and receives the programming test data, the external trigger signal becomes valid and triggers the generation of a valid self - refreshing trigger signal, and the self - refreshing trigger signal obtains N sequentially lagging delay control signals through multiple - stage delays; wherein, each bit of data in the programming test data is the same; Based on each delay control signal, corresponding driving signals are respectively generated, and each driving signal acts with a sequential delay, and each driving signal drives the corresponding M rows of memory cells to write data simultaneously; When the last - stage delay control signal becomes valid, the self - refreshing trigger signal jumps to an invalid state, and all the memory cells in the current page buffer complete data writing and are latched; Wherein, N and M are natural numbers greater than or equal to 2 respectively.

11. The full-page programming method according to claim 10, characterized in that: The programming test data is 1 - byte data, and one driving signal refreshes the storage capacity of 8 bytes, 16 bytes, 32 bytes, or 64 bytes in the page buffer each time based on 1 - byte data, and fills the entire storage capacity of the page buffer through N times of refreshing.

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