Memory device including merged sub-arrays

Abstract

A memory device includes a peripheral circuit structure and a cell array structure, where the cell array structure overlaps the peripheral circuit structure in a first direction, where the cell array structure includes a merged sub-array in which at least four sub-array regions are merged, where the merged sub-array includes a memory cell region, and where the memory cell region includes a plurality of memory cells. The memory cell region includes: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure includes a merged bank in which at least four banks are merged, and the merged bank includes: a first bit line sense amplifier (BLSA), a second BLSA, a first sub-word line driver (SWD), and a second SWD, and in which a free space is defined between the first bit line and the second bit line.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0003125, filed with the Korean Intellectual Property Office on January 8, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a memory device including a merged sub - array having a word - line and bit - line partitioning structure to reduce the chip size of the memory device. Background art

[0004] Recently, with the multi - functionalization of information and communication devices, the demand for high - capacity and high - integration memory devices has been increasing. As the size of high - integration memory cells decreases, the operation circuits and / or wiring structures for the operation of the memory device and electrical connection included in the memory device also become complex. Accordingly, the demand for a memory device having good electrical characteristics while improving the integration of the memory device has increased. To increase the storage capacity and integration of the memory device, vertical channel transistors vertically formed on a semiconductor substrate have been introduced.

[0005] A memory device (e.g., a dynamic random access memory (DRAM)) may include a plurality of memory cells, each memory cell including a vertical channel transistor and a capacitor, and may operate in a manner of writing and reading data using the charge stored in the capacitor.

[0006] A DRAM may have a cell - on - periphery (CoP) structure including a cell array structure and a peripheral circuit structure vertically overlapping each other. The cell array structure may include a memory cell array and a peripheral circuit structure. The memory cell array includes a plurality of memory cells each including a vertical channel transistor and a capacitor. The peripheral circuit structure may include an idle area and a peripheral circuit. The peripheral circuit includes a sub - word - line driver, a bit - line sense amplifier, etc. As the memory size continues to shrink, the ratio of the area occupied by the peripheral circuit region to the area occupied by the memory cell array region increases. Accordingly, the chip size of a DRAM having a CoP structure is dominated by the area of the peripheral circuit region, resulting in low utilization efficiency of the idle area.

[0007] To reduce the chip size of a DRAM, the area of the peripheral circuit region may be reduced, or the idle area may be used. Summary of the invention

[0008] Embodiments of the present disclosure provide a storage device including a merged sub-array having a word line and bit line partitioning structure to reduce the chip size of the storage device by expanding the free area of the merged bank.

[0009] According to one aspect of the present disclosure, a storage device includes: a peripheral circuit structure; and a cell array structure over the peripheral circuit structure, wherein the cell array structure overlaps the peripheral circuit structure in a first direction, wherein the cell array structure includes a merged sub-array in which at least four sub-array regions are merged, wherein the merged sub-array includes a memory cell region, the memory cell region including: a plurality of first bit lines and a plurality of second bit lines arranged in a second direction perpendicular to the first direction; and a plurality of first word lines and a plurality of second word lines arranged in a third direction perpendicular to the second direction; wherein the peripheral circuit structure includes a merged bank in which at least four banks are merged, and wherein the merged bank includes: a first bit line sense amplifier (BLSA) configured to sense a voltage difference of the plurality of first bit lines; a second BLSA configured to sense a voltage difference of the plurality of second bit lines; a first sub-word line driver (SWD) configured to drive even-numbered word lines among the plurality of first word lines and even-numbered word lines among the plurality of second word lines; and a second SWD configured to drive odd-numbered word lines among the plurality of first word lines and odd-numbered word lines among the plurality of second word lines, wherein a free space is defined between a first region corresponding to the plurality of first bit lines and a second region corresponding to the plurality of second bit lines.

[0010] According to one aspect of the present disclosure, a storage device includes: a peripheral circuit structure; and a cell array structure over the peripheral circuit structure, wherein the cell array structure overlaps the peripheral circuit structure in a first direction, wherein the cell array structure includes a merged sub-array in which at least 4n sub-array regions are merged, where n is a natural number greater than zero, wherein the merged sub-array includes: a first bit line half-group and a second bit line half-group and a first word line half-group and a second word line half-group, the first bit line half-group and the second bit line half-group being obtained by partitioning a plurality of first bit lines and a plurality of second bit lines arranged in a second direction perpendicular to the first direction, the first word line half-group and the second word line half-group being obtained by partitioning a plurality of first word lines and a plurality of second word lines arranged in a third direction perpendicular to the second direction, and wherein the peripheral circuit structure includes a merged bank in which at least 4n banks are merged.

[0011] According to one aspect of the present disclosure, a storage device includes: a peripheral circuit structure; and a cell array structure on the peripheral circuit structure, wherein the cell array structure overlaps the peripheral circuit structure in a first direction, wherein the cell array structure includes a merged sub-array in which at least 4n sub-array regions are merged, where n is a natural number greater than zero, wherein the merged sub-array includes a storage cell region, the storage cell region including (i) a plurality of first bit lines and a plurality of second bit lines arranged in a second direction perpendicular to the first direction, and (ii) a plurality of first word lines and a plurality of second word lines arranged in a third direction perpendicular to the second direction, wherein the storage cell region includes a first bit line half-group and a second bit line half-group, and a first word line half-group and a second word line half-group, the first bit line half-group and the second bit line half-group being obtained by dividing the plurality of first bit lines and the plurality of second bit lines according to a first predetermined criterion, the first word line half-group and the second word line half-group being obtained by dividing the plurality of first word lines and the plurality of second word lines according to a second predetermined criterion, wherein the peripheral circuit structure includes a merged bank in which at least 4n banks are merged, and wherein the merged bank includes: a first bit line sense amplifier (BLSA) configured to sense a voltage difference of the plurality of first bit lines, a second BLSA configured to sense a voltage difference of the plurality of second bit lines, a first sub-word line driver (SWD) configured to drive even-numbered word lines among the plurality of first word lines and even-numbered word lines among the plurality of second word lines, a second SWD configured to drive odd-numbered word lines among the plurality of first word lines and odd-numbered word lines among the plurality of second word lines, and wherein a free space is defined between a first region corresponding to the plurality of first bit lines and a second region corresponding to the plurality of second bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present disclosure will be understood more clearly from the following detailed description in conjunction with the accompanying drawings:

[0013] Figure 1 is a block diagram of a storage device according to one or more embodiments;

[0014] Figure 2 is a perspective view schematically showing the structure of a storage device according to one or more embodiments;

[0015] Figure 3 is a circuit diagram of a storage cell array according to one or more embodiments;

[0016] Figure 4 is a circuit diagram of parasitic capacitors included in a storage cell array according to one or more embodiments;

[0017] Figure 5 is a perspective view specifically showing the structure of a storage device according to one or more embodiments;

[0018] Figure 6 is a cross-sectional view of a memory device taken along line A1-A2; Figure 5 of

[0019] Figure 7A and Figure 7B is a perspective view schematically showing the structure of a memory device according to one or more embodiments;

[0020] Figure 8 is a perspective view showing a word line division structure and method according to one or more embodiments;

[0021] Figure 9 is a perspective view showing a bit line division structure and method according to one or more embodiments;

[0022] Figure 10 is a perspective view showing a word line and bit line division structure and method according to one or more embodiments; and

[0023] Figure 11 is a block diagram of an electronic device including a memory device according to one or more embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Unless otherwise indicated by reference numerals, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface", etc. are understood with reference to the accompanying drawings.

[0026] It will be understood that although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0027] It will be understood that when an element or layer is referred to as being “above,” “over,” “on,” “under,” “beneath,” “below,” “connected to,” or “coupled to” another element or layer, it can be directly above, over, on, under, beneath, below, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly above,” “over,” “on,” “under,” “beneath,” “below,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0028] Figure 1 is a block diagram of a memory device 100 according to one or more embodiments.

[0029] Reference Figure 1 , the memory device 100 may correspond to, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), or any other suitable memory structure known to those skilled in the art.

[0030] The memory device 100 may include a memory cell array 110 and a peripheral circuit 111. In one or more examples, the peripheral circuit may refer to circuits or components peripheral to the memory cell array.

[0031] In one or more examples, the memory cell array 110 may include a plurality of memory cells arranged in rows and columns.

[0032] In one or more examples, the peripheral circuit 111 may include a row decoder 120, a sub-word line driver (SWD) 121, a back-gate driver (BGD) 122, a bit-line sense amplifier (BLSA) 123, a column decoder 124, a voltage generation circuit 125, a command decoder 126, a mode register set / extended mode register set (MRS / EMRS) circuit 127, an address buffer 128, and a data input / output (I / O) circuit 129.

[0033] The row decoder 120 may decode the row address in the address signal ADD output from the address buffer 128 to specify the word line connected to the memory cell to input or output data DQ. For example, in a data write mode or a data read mode, the row decoder 120 may select a corresponding word line (e.g., referred to as the selected word line) by decoding the row address output from the address buffer 128. In one or more examples, the row decoder 120 may generate a word line drive voltage to be applied to the word line corresponding to the row address.

[0034] The SWD 121 can apply a word line drive voltage to the selected word lines based on the decoded row addresses. The SWD 121 can be connected to multiple word lines formed in each sub-array region. The SWD 121 can drive one or more of the multiple word lines by supplying the word line drive voltage to one or more word lines. In one or more examples, the SWD 121 is configured to drive a subset of the multiple word lines.

[0035] The BGD 122 can apply a back gate voltage to the back gate line. The BGD 122 can be implemented by a regulator (e.g., a low dropout (LDO) regulator).

[0036] In one or more examples, the BLSA is a circuit for amplifying and detecting small signals in a memory device. The BLSA 123 can read the data DQ of a memory cell through a bit line. The BLSA 123 can read and amplify the data DQ of the memory cell and store the data DQ in the memory cell. The BLSA 123 can be implemented by a cross-coupled amplifier connected between a bit line and a complementary bit line (e.g., a bit strip) included in the memory cell array 110.

[0037] In one or more examples, the column decoder 124 can decode the column address in the address signal ADD output from the address buffer 128 to specify the bit line connected to the memory cell to input or output data. The memory cell array 110 can output data from the memory cell specified by the row address and the column address, or write data to the memory cell.

[0038] In one or more examples, the voltage generation circuit 125 can generate various internal voltages for driving the circuits in the memory device 100. The voltage generation circuit 125 can generate a high voltage (e.g., VPP), a negative voltage (e.g., VBB), a bit line precharge voltage (e.g., VEQ), an internal power supply voltage (e.g., VINTA), or any other suitable voltage by using a power supply voltage (e.g., VDD) applied from outside the memory device 100. The high voltage (e.g., VPP) can be provided to the row decoder 120, has a voltage level higher than the power supply voltage (e.g., VDD), and is used for the word line drive circuit to turn on the N-type metal oxide semiconductor (NMOS) cell transistors connected to the word lines. The negative voltage (e.g., VBB) can have a negative (-) voltage level lower than the power supply voltage (e.g., VDD), and can be used to increase the data retention time by increasing the threshold voltage (e.g., Vth) of the NMOS transistors. The negative voltage (e.g., VBB) can be applied to the well region in which the NMOS transistors are formed, and is generally referred to as the body bias voltage or the reverse bias voltage. The bit line precharge voltage (e.g., VEQ) can be used to equalize the bit line (e.g., BL) and the bit line strip (e.g., BLB) before reading the voltage difference between the bit line (e.g., BL) and the bit line strip (e.g., BLB) in the BLSA 123. The internal power supply voltage (e.g., VINTA) can be provided to the first read drive voltage line and the second read drive voltage line (e.g., LA and LAB) of the BLSA 123. The BLSA 123 can read and amplify the voltage difference between the bit line (e.g., BL) and the bit line strip (e.g., BLB) according to the first read drive voltage line and the second read drive voltage line (e.g., LA and LAB).

[0039] In one or more examples, the command decoder 126 can receive a command signal CMD applied from outside the memory device 100, and decode the command signal CMD to internally generate a command according to the decoded command signal.

[0040] In one or more examples, the MRS / EMRS circuit 127 can configure an internal mode register in response to an MRS / EMRS command and an address signal ADD for specifying the operation mode of the memory device 100. The MRS / EMRS circuit 127 can be programmed to set the operation parameters, options, various functions, features, and modes of the memory device 100. When an MRS command is issued from a memory controller coupled to the memory device 100, the MRS / EMRS circuit 127 can store a parameter code, which includes appropriate bit values provided through the command / address (CA) bus of the memory bus.

[0041] The data DQ input through the data I / O circuit 129 can be written to the memory cell array 110 based on the address signal ADD, and the data DQ read from the memory cell array 110 based on the address signal ADD can be output to the outside through the data I / O circuit 129. In order to specify which memory cell to write data to or read data from, the address signal ADD can be input to the address buffer 128. For example, the data DQ input to the memory device 100 can be written to each sub-array, or the data DQ read from each sub-array can be output to the outside through the data I / O circuit 129.

[0042] The address buffer 128 can temporarily store the address signal ADD input from the outside. When reading the memory cell corresponding to the address signal ADD, the stored address signal ADD can be removed from the address buffer 128.

[0043] The memory device 100 may further include a clock circuit configured to generate a clock signal, a power generation circuit configured to receive a power supply voltage applied from the outside and generate or distribute an internal voltage, a voltage detection circuit configured to detect a voltage level, a test circuit capable of performing a test operation in the memory device 100, a control circuit configured to control the operation of the circuits in the peripheral circuit 111, or any other suitable circuit structure known to those skilled in the art.

[0044] Figure 2 is a perspective view schematically showing the structure of the memory device 100 according to one or more embodiments.

[0045] Reference Figure 2 , the memory device 100 may include a cell array structure CAS and a peripheral circuit structure PCS. The cell array structure CAS can be on the peripheral circuit structure PCS in the vertical direction (e.g., the Z direction, the first direction). For example, the peripheral circuit structure PCS can be below the cell array structure CAS in the vertical direction. In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS can be bonded to each other through pads in the vertical direction (e.g., the Z direction, the first direction). The bonding method can be, for example, the bonding between Cu pads and Cu pads, but is not limited thereto. In one or more examples, a first group of pads can be bonded to the CAS, and a second group of pads can be bonded to the PCS, where the pads in the first group of pads are bonded to the corresponding pads in the second group of pads. Other bonding techniques can include silicon direct bonding, anodic bonding, etc.

[0046] The cell array structure CAS may include Figure 1The memory cell array 110. According to one or more embodiments, the memory cell array 110 may include multiple word lines, multiple bit lines, and multiple back gate lines connected to multiple memory cells. For example, the bit line BL may extend in a first horizontal direction (e.g., the Y direction) and may be arranged in parallel in a second horizontal direction (e.g., the X direction). The word line WL may extend in the second direction (e.g., the X direction) and be arranged in parallel in the first direction (e.g., the Y direction), and the back gate line BGL may extend in the second direction (e.g., the X direction) and be arranged in parallel in the first direction (e.g., the Y direction). The memory cell MC may be connected to each of the bit line BL, the word line WL, and the back gate line BGL. The memory cell MC may include a cell transistor and a cell capacitor. In some embodiments, the cell transistor may include a forward gate connected to the word line WL and a back gate connected to the back gate line BGL. The memory cell MC may share a back gate with an adjacent memory cell through one back gate line BGL.

[0047] The peripheral circuit structure PCS may include Figure 1 The peripheral circuit 111. According to one or more embodiments, the peripheral circuit 111 may be configured to apply a word line drive voltage to a word line (e.g., WL) selected from among multiple word lines. The peripheral circuit 111 may be configured to apply a back gate voltage to a back gate line (e.g., BGL) that is connected to a memory cell (e.g., MC) connected to the selected word line (e.g., WL). The peripheral circuit 111 may be configured to read data through at least one bit line (e.g., BL) selected from among multiple bit lines.

[0048] Since the memory device 100 according to an embodiment of the present disclosure includes a stacked structure of a cell array structure CAS and a peripheral circuit structure PCS, word lines in the cell array structure CAS can extend without being cut off by circuit elements other than memory cells. For example, compared with a non-stacked structure in which PCS and CAS are included in the same plane, the stacked structure provides additional space for word lines.

[0049] Figure 3 is a circuit diagram of the memory cell array 110 according to one or more embodiments.

[0050] Reference Figure 2 and Figure 3 and, the memory cell array 110 may include multiple word lines (e.g., WL), multiple bit lines (e.g., BL), multiple back gate lines (e.g., BGL), and multiple memory cells (e.g., MC).

[0051] Figure 3Shows the first word line to the eighth word line WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, the first bit line to the third bit line BL1, BL2, and BL3, the first back gate line to the fourth back gate line BGL1, BGL2, BGL3, and BGL4, and 24 memory cells. However, the memory cell array 110 according to an embodiment of the present disclosure is not limited thereto. In this regard, as understood by those of ordinary skill in the art, the memory cell array may include fewer or more word lines, bit lines, back gate lines, and memory cells.

[0052] Each of the plurality of memory cells may include a cell transistor CT and a cell capacitor CC. The cell transistor CT may include a front gate connected to the word line, a back gate shared with an adjacent cell transistor CT through the back gate line, and a plurality of electrodes. The cell transistor CT may store a charge corresponding to the stored information. For example, the cell transistor CT storing a charge may correspond to binary "1", while the cell transistor CT not storing a charge may correspond to binary "0".

[0053] For example, the cell transistor CT of the first memory cell MC1 may include a front gate connected to the first word line WL1, a back gate connected to the first back gate line BGL1, a first electrode connected to the cell capacitor CC, and a second electrode connected to the first bit line BL1. For example, the cell transistor CT of the second memory cell MC2 may include a front gate connected to the second word line WL2, a back gate connected to the first back gate line BGL1, a first electrode connected to the cell capacitor CC, and a second electrode connected to the first bit line BL1. For example, the cell transistor CT of the third memory cell MC3 may include a front gate connected to the third word line WL3, a back gate connected to the second back gate line BGL2, a first electrode connected to the cell capacitor CC, and a second electrode connected to the first bit line BL1.

[0054] In one or more examples, the cell transistor CT of the first memory cell MC1 and the cell transistor CT of the second memory cell MC2 may share the back gate of the first memory cell MC1 and the second memory cell MC2 through the first back gate line BGL1. The cell transistor CT of the first memory cell MC1 and the cell transistor CT of the second memory cell MC2 may be adjacent cell transistors.

[0055] In some embodiments, the channel of the unit transistor CT may be formed in the vertical direction (e.g., the Z direction, the first direction). The unit transistor CT including the channel formed in the vertical direction (e.g., the Z direction, the first direction) may be referred to as a vertical channel transistor. In some embodiments, the unit transistor CT may be implemented by an n-type transistor, but is not limited thereto. When a back gate is included in the unit transistor CT, the floating body can be controlled, and the threshold voltage of the unit transistor CT can be easily controlled.

[0056] In one or more examples, when the unit transistor CT shares a back gate with an adjacent unit transistor, the chip size of the memory device 100 can be reduced, and the memory device 100 can be further integrated. In some embodiments, every two word lines may share a back gate. However, the embodiments of the present disclosure are not limited thereto.

[0057] The unit capacitor CC may store charges corresponding to the capacitance of data of a single bit (e.g., bit "0" or bit "1"). According to one or more embodiments, the unit capacitor CC may store charges corresponding to the capacitance of data of multiple bits (e.g., two-bit data). The unit capacitor CC may be restored to charges corresponding to the capacitance of data of a single bit or multiple bits. The unit capacitor CC may be connected between the first electrode of the unit capacitor CC and the ground. For example, the first electrode of the unit capacitor CC may be connected to the first electrode of the unit transistor CT, and the second electrode of the unit capacitor CC may be connected to the ground.

[0058] Figure 4 is a circuit diagram of parasitic capacitances included in the memory cell array 110 according to one or more embodiments. Parasitic capacitance may refer to the capacitance existing between parts of electronic components or circuits due to their proximity to each other. For example, when two conductors at different voltages are close to each other, the electric field between them causes charges to be stored on these two conductors, resulting in parasitic capacitance. For the sake of convenience of description, the following will be described with reference to the first bit line BL1, the first to third word lines WL1, WL2, WL3, the first back gate line BGL1 and the second back gate line BGL2, and the first to third memory cells MC1, MC2, MC3 Figure 4 shown first to fourth parasitic capacitances PC1, PC2, PC3, PC4.

[0059] Reference Figure 4, the first storage unit MC1 and the second storage unit MC2 can be connected to the first back gate line BGL1, and the third storage unit MC3 can be connected to the second back gate line BGL2. Because there is a first parasitic capacitance PC1 due to the coupling between the first back gate line BGL1 and the second word line WL2, the potential of the first back gate line BGL1 may change or ripple in response to the application of a word line driving voltage to the second word line WL2. If the potential of the first back gate line BGL1 ripples, due to the second parasitic capacitance PC2 and the third parasitic capacitance PC3 between the first back gate line BGL1 and the cell transistor CT of the first storage unit MC1, the potentials of the first electrode and the second electrode of the cell transistor CT of the first storage unit MC1 may also ripple, and the potential of the first word line WL1 may also ripple. As a result, since the potential of the first word line WL1 also ripples, the threshold voltage of the cell transistor CT of the first storage unit MC1 may change (e.g., decrease).

[0060] Figure 5 is a perspective view schematically showing the structure of a memory device 100A according to one or more embodiments. Figure 5 The memory device 100A can be Figure 2 a modified embodiment of the memory device 100 shown here. The reference Figure 2 description is omitted.

[0061] The cell array structure CAS can include a plurality of sub-array regions 11, 12, 21, and 22, and dummy regions.

[0062] Each of the plurality of sub-array regions 11, 12, 21, and 22 can include a plurality of word lines WL<1> to WL <n>, a plurality of bit lines BL<1>, BL<2>,..., BL <n-1>and BL <n>, and a plurality of memory cells. A plurality of bit lines BL<1>, BL<2>,..., BL included in each sub-array region <n-1>, BL <n>It may extend in a first horizontal direction (e.g., the Y direction, the second direction) and be arranged in parallel in a second horizontal direction (e.g., the X direction, the third direction). A plurality of word lines WL<1> to WL included in each sub-array region <n>It may extend in a second horizontal direction (e.g., the X direction) and be arranged parallel in a first horizontal direction (e.g., the Y direction). Each memory cell may be connected to a plurality of bit lines BL<1>, BL<2>,..., BL <n-1>and BL <n>each one of, and multiple word lines WL<1> to WL <n>Each one of them. Each memory cell may include a cell transistor and a cell capacitor. Each memory cell formed in the plurality of sub-array regions 11, 12, 21, and 22 may include a cell transistor connected to a bit line BL and a word line WL, and a cell capacitor. Each of the plurality of sub-array regions 11, 12, 21, and 22 may include a plurality of memory blocks. For example, connected to a plurality of word lines WL<1> to WL <n>The memory cells can form a memory bank. The multiple sub-array regions 11, 12, 21, and 22 can be arranged such that at least one side of each of the multiple sub-array regions 11, 12, 21, and 22 is spaced apart from another sub-array region. Each of the multiple sub-array regions 11, 12, 21, and 22 can include a plurality of pads formed such that the peripheral circuit structure PCS is connected to a plurality of bit lines BL<1>, BL<2>,..., BL <n-1>and BL <n>and multiple word lines WL<1> to WL <n>Each one of them. For example, each sub-array region may include a first pad and a second pad. The first pad may connect the BLSA of the peripheral circuit structure PCS to a plurality of bit lines BL<1>, BL<2>,..., BL <n-1>and BL <n>。The second pad can connect the SWD of the peripheral circuit structure PCS to multiple word lines WL<1> to WL <n>For example, each of regions 11, 12, 21, and 22 may be associated with corresponding first and second BLSAs, SWDs, and shared spaces in the PCS.

[0063] Dummy regions may be between multiple sub-array regions 11, 12, 21, and 22. For example, dummy region 30 may be between two different sub-array regions. Dummy region 30 may be parallel to each sub-array region in a horizontal direction. Dummy region 30 may include multiple pads connected to the peripheral circuit structure PCS. In some embodiments, dummy region 30 may not include multiple bit lines BL<1>, BL<2>,..., BL <n-1>and BL <n>, multiple word lines WL<1> to WL <n>, and a plurality of memory cells. In one or more examples, a dummy region may refer to a non-active region that does not include circuitry.

[0064] The peripheral circuit structure PCS may include a peripheral circuit region in which a peripheral circuit is formed. One or more peripheral circuits may be formed in a partial region of the peripheral circuit region. One or more other peripheral circuits may be formed in another partial region of the peripheral circuit region. The peripheral circuit may be configured to apply a word line drive voltage to word lines WL<1> to WL from a plurality of word lines <n>Selected word lines from among them. The peripheral circuit may be configured to, from among a plurality of bit lines BL<1>, BL<2>,..., BL <n-1>and BL <n>Read data from at least one bit line selected therefrom.

[0065] In one or more examples, the peripheral circuit may include a row decoder, a column decoder, or any other suitable components known to those skilled in the art. In one or more examples, the middle region (MIDDLE) or spare region (SPARE) of the peripheral circuit structure PCS may include a command decoder 126, an MRS / EMRS circuit 127, an address buffer 128, a data I / O circuit 129, a voltage generation circuit 125, a test circuit, or any other circuit structure known to those skilled in the art. Although Figure 1 regions 11, 12, 21, and 22 are shown to be of equal size, embodiments of the present disclosure are not limited to these structures. For example, at least one of regions 11, 12, 21, and 22 may have a size different from that of the other regions. Figure 5 For example, each region of the peripheral circuit structure PCS other than the middle region (MIDDLE) or the spare region may include a row decoder, a column decoder, and a bank. A bank may include one or more memory array tiles (MATs). One memory array tile may include a first BLSA, a second BLSA, and an SWD. One memory array tile may also include a conjunction.

[0066]

[0067] Since the memory device 100A according to an embodiment of the present disclosure includes a stacked structure of a cell array structure CAS and a peripheral circuit structure PCS, word lines in the cell array structure CAS can extend without being cut off by circuit elements other than memory cells. For example, since the PCS is on a different plane from the CAS, there is extra space for the word lines.

[0068] Figure 6 Figure 5 is a cross-sectional view of the memory device 100A taken along line A1 - A2 of

[0069] Figure 6 Referring to

[0070] , the memory device 100A may include a cell array structure CAS and a peripheral circuit structure PCS bonded to each other in a vertical direction (e.g., the Z direction). Since the cell array structure CAS may include a plurality of sub-array regions 11, 12, 21, and 22, and the peripheral circuit structure PCS may include a peripheral circuit, the memory device 100A may have a structure in which the sub-arrays are above the peripheral circuit (e.g., a CoP structure). As understood by those of ordinary skill in the art, the CoP structure provides a three-dimensional memory device including a plurality of memory cells repetitively stacked with respect to a surface, which advantageously results in high integration.

[0070] In one or more examples, the cell array structure CAS may include memory cells having vertical channel transistors. Bit lines BL may extend in a first horizontal direction (e.g., the Y direction), and word lines WL may extend in a second horizontal direction (e.g., the X direction). There may be multiple memory cells, bit lines BL, and word lines WL respectively.

[0071] In one or more examples, the peripheral circuit structure PCS may include a semiconductor substrate. The peripheral circuit may be formed by forming semiconductor devices (e.g., transistors) and patterns for wiring the devices on the semiconductor substrate. After forming the peripheral circuit in the peripheral circuit structure PCS, a cell array structure CAS including a plurality of sub-array regions 11, 12, 21, and 22 and a dummy region 30 may be formed, and patterns for electrically connecting the word lines WL and bit lines BL in each sub-array region to the peripheral circuit formed in the peripheral circuit structure PCS may be formed.

[0072] In one or more examples, the peripheral circuit structure PCS may include a substrate 210, a first interlayer insulating layer 215, a plurality of circuit devices (e.g., a first circuit device 211a and a second circuit device 211b) formed on the substrate 210, first metal patterns 212a and 212b respectively connected to the first circuit device 211a and the second circuit device 211b, second metal patterns 214a and 214b respectively formed on the first metal patterns 212a and 212b, a third metal pattern 216 formed on the second metal pattern 214b, a fourth metal pattern 218 formed on the third metal pattern 216, a fifth metal pattern 220 formed on the fourth metal pattern 218, and a first pad 222 formed on the fifth metal pattern 220.

[0073] Although Figure 6 only the first metal patterns 212a and the second metal patterns 214a are shown, the peripheral circuit structure PCS is not limited thereto, and at least one metal pattern may be further formed on the second metal pattern 214a. The metal pattern may also be referred to as a metal layer. In some embodiments, the metal pattern may include at least one metal line extending in one horizontal direction and arranged in parallel in another horizontal direction. Although Figure 6 Only the first metal pattern 212b, the second metal pattern 214b, the third metal pattern 216, the fourth metal pattern 218, and the fifth metal pattern 220 are shown, but the peripheral circuit structure PCS is not limited thereto, and metal patterns with less than five metal patterns can also be stacked, or at least one metal pattern can be further formed on the fifth metal pattern 220. In one or more embodiments, the first metal patterns 212a and 212b can be formed of tungsten having a relatively high resistance value, and the second metal patterns 214a and 214b can be formed of Cu having a relatively low resistance value. At least some of the one or more metal patterns formed on the second metal patterns 214a and 214b can be formed of aluminum or any other suitable material having a lower resistance value than the Cu forming the second metal patterns 214a and 214b.

[0074] The first interlayer insulating layer 215 can be on the substrate 210. The first interlayer insulating layer 215 can cover the first circuit device 211a and the second circuit device 211b, the first metal patterns 212a and 212b, the second metal patterns 214a and 214b, the third metal pattern 216, the fourth metal pattern 218, the fifth metal pattern 220, and the first pad 222. The first interlayer insulating layer 215 can include an insulating material (e.g., silicon oxide or silicon nitride).

[0075] The first circuit device 211a and the second circuit device 211b can be connected to at least one of the circuit devices constituting the peripheral circuit. For example, the first circuit device 211a can be any one of the transistors included in the SWD. The second circuit device 211b can be any one of the transistors included in the BLSA. However, the embodiments of the present disclosure are not limited thereto.

[0076] The first pad 222 can be on the top metal pattern of the peripheral circuit structure PCS and bonded to the second pad 232. The first pad 222 can be formed of Cu, but is not limited thereto.

[0077] The cell array structure CAS can include a second pad 232, a plurality of metal patterns 234, 236, 238, and 240 stacked on the second pad 232, a second interlayer insulating layer 225, a wire 230 on the second interlayer insulating layer 225, a cell structure CS on the wire 230, and a capacitor structure 290 on the cell structure CS.

[0078] The second pad 232 can be below the bottom metal pattern of the cell array structure CAS and bonded to the first pad 222. The second pad 232 can be formed of Cu, but is not limited thereto.

[0079] Although Figure 6 The cell array structure CAS is shown to include four metal patterns, but the cell array structure CAS is not limited thereto, and metal patterns with less than four metal patterns may be stacked, or at least one metal pattern may be further formed on the second pad 232 or under the wire 230. In one or more examples, more than four metal patterns may be included. In one or more embodiments, the plurality of metal patterns 234, 236, 238, and 240 may be formed of a material having a certain resistance value (e.g., Cu, tungsten, aluminum, or any other suitable material).

[0080] In one or more examples, the second interlayer insulating layer 225 may be formed to cover the side surfaces of the second pad 232, the side surfaces of the plurality of metal patterns 234, 236, 238, and 240, and the lower and side surfaces of the wire 230. The second interlayer insulating layer 225 may be formed to fill the space between the second pad 232, the plurality of metal patterns 234, 236, 238, and 240, and the wire 230.

[0081] In one or more examples, the wire 230 may extend in a first horizontal direction (e.g., the Y direction). The wires 230 may be spaced apart from each other in a second horizontal direction (e.g., the X direction) perpendicular to the first horizontal direction (e.g., the Y direction). The wire 230 may be used as a bit line BL of the memory device 100A.

[0082] In one or more examples, the isolation insulating layer 235 may be formed on the wire 230. The isolation insulating layer 235 may include channel trenches 235T and a plurality of insulating patterns spaced apart from each other by the channel trenches 235T. The channel layer 236 may be formed in the channel trenches 235T. The channel layer 236 may extend along the side and bottom surfaces of the channel trenches 235T and be electrically connected to the wire 230. The gate dielectric layer 242 may be formed on the channel layer 236 in the channel trenches 235T. The gate dielectric layer 242 may be between the channel layer 236 and the gate electrode 250. The gate electrode 250 may be formed on the gate dielectric layer 242 in the channel trenches 235T. In some embodiments, the gate electrode 250 may include a first gate electrode 250A and a second gate electrode 250B opposite to each other in one channel trench 235T. In this case, a structure of two transistors per channel layer 236 may be implemented. The first gate electrode 250A may be used as the first word line of the sub-array, and the second gate electrode 250B may be used as the second word line of the sub-array.

[0083] In some embodiments, a blocking insulating layer 262 and a gap-fill insulating layer 264 may be formed between the first gate electrode 250A and the second gate electrode 250B. The first gate electrode 250A and the second gate electrode 250B may be spaced apart from each other by the blocking insulating layer 262 and the gap-fill insulating layer 264. The gap-fill insulating layer 264 may be formed on the blocking insulating layer 262 and fill the region between the first gate electrode 250A and the second gate electrode 250B.

[0084] In one or more examples, the cell structure CS may include a structure of a vertical-channel transistor. The vertical-channel transistor may indicate a structure in which the channel length of the channel layer 236 extends in a vertical direction (e.g., the Z direction) perpendicular to the upper surface of the substrate 210. The vertical-channel transistor may include a channel layer 236, a gate electrode 250, and a gate dielectric layer 242 between the channel layer 236 and the first gate electrode 250A. The channel layer 236 of the vertical-channel transistor may include a first source / drain region and a second source / drain region disposed in the vertical direction (e.g., the Z direction). For example, the lower portion (e.g., the horizontal portion) of the channel layer 236 may be used as the first source / drain region, and the upper portion (e.g., the vertical portion having a width narrower than the horizontal portion) of the channel layer 236 may be used as the second source / drain region. The portion of the channel layer 236 between the first source / drain region and the second source / drain region may be used as the channel region.

[0085] In one or more examples, a contact layer 270 in contact with the upper surface of the channel layer 236 may be formed on the channel layer 236. The contact layer 270 may connect the channel layer 236 to the capacitor structure 290. The upper surface of the channel layer 236 adjacent to the first gate electrode 250A may be in contact with one contact layer 270, and the upper surface of the channel layer 236 adjacent to the second gate electrode 250B may be in contact with a different contact layer 270.

[0086] In one or more examples, the capacitor structure 290 may be formed on the isolation insulating layer 235 and the contact layer 270. The capacitor structure 290 may be in contact with the upper surface of the contact layer 270. The capacitor structure 290 may be controlled by the wire 230 and the gate electrode 250 to store data therein. The capacitor structure 290 may include a lower electrode 292, a capacitor dielectric layer 294, and an upper electrode 296. The capacitor structure 290 may store charges in the capacitor dielectric layer 294 by using the potential difference generated between the lower electrode 292 and the upper electrode 296.

[0087] In one or more examples, one of the plurality of vertical-channel transistor structures and one of the capacitor structures 290 may constitute a storage cell, and thus, the cell array structure CAS may include a plurality of storage cells including a plurality of cell structures CS and a plurality of capacitor structures 290.

[0088] According to the requirements for high-performance and high-integration storage devices, the integration and complexity of the peripheral circuits in the peripheral circuit structure PCS can be increased, and the complexity of the wiring for signal communication between circuits (e.g., row decoder (R / D), column decoder (C / D), etc.) can also be increased. To increase the signal rate between circuits of high-performance peripheral circuits, the wiring for signal communication can be arranged in a non-complex manner. However, due to the limitation of the physical size of the peripheral circuit structure PCS, there may be a lack of space occupied by the wiring connecting the circuits to each other in the peripheral circuit structure PCS. To address this situation, a merged sub-array in which a plurality of sub-arrays included in the cell array structure CAS are merged can be included, and the word lines and bit lines included in the merged sub-array can be divided and arranged according to a predetermined standard to increase the size of the free area in the peripheral circuit structure PCS. If the size of the free area increases, the free area can include peripheral circuits, and thus, the free area can be effectively used, and the size of the storage chip can be reduced.

[0089] Figure 7A and Figure 7B are perspective views schematically showing the structures of storage devices 100A and 100B according to one or more embodiments.

[0090] Figure 7A and Figure 7B The storage devices 100A and 100B can be storage devices in which a plurality (i.e., four) of sub-array regions 11, 12, 21, and 22 are merged. Descriptions made with reference to Figure 5 are omitted here. Figure 5

[0091] Referring to Figure 7A and Figure 7B the storage devices 100A and 100B can include a cell array structure CAS and a peripheral circuit structure PCS.

[0092] The cell array structure CAS can include a merged sub-array 200. The merged sub-array 200 can include a plurality of left word lines (e.g., first word lines) WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n>, a plurality of right word lines (e.g., second word lines) WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n>, a plurality of upper bit lines (e.g., first bit lines) BL<1>, BL<2>,..., BL<2n - 1> and BL<2n>, a plurality of lower bit lines (e.g., second bit lines) BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n>, and a plurality of storage cells. ​

[0093] The number of left word lines WL_L<1>, WL_L<2>, …, WL_L<2n-1>, WL_L<2n>, the number of right word lines WL_R<1>, WL_R<2>, …, WL_R<2n-1>, WL_R<2n>, the number of upper lines BL<1>, BL<2>, …, BL<2n-1>, BL<2n>, and the number of lower lines BL_B<1>, BL_B<2>, …, BL_B<2n-1>, BL_B<2n> can each be 2n (n is a natural number).

[0094]

[0095] The plurality of upper lines BL<1>, BL<2>, …, BL<2n-1>, BL<2n> and the plurality of lower lines BL_B<1>, BL_B<2>, …, BL_B<2n-1>, BL_B<2n> included in the merge sub-array 200 may extend in a first horizontal direction (e.g., the Y direction) and may be arranged in parallel in a second horizontal direction (e.g., the X direction). The plurality of left word lines WL_L<1>, WL_L<2>, …, WL_L<2n-1>, WL_L<2n> and the plurality of right word lines WL_R<1>, WL_R<2>, …, WL_R<2n-1>, WL_R<2n> included in the merge sub-array 200 may extend in the second horizontal direction (e.g., the X direction) and may be arranged in parallel in the first horizontal direction (e.g., the Y direction).

[0096] In some embodiments, the complementary bit lines of the plurality of upper lines BL<1>, BL<2>, …, BL<2n-1>, BL<2n> may be the plurality of lower lines of the merge sub-array adjacent to the merge sub-array 200 on one side of the first BLSA 311, and the complementary bit lines of the plurality of lower lines BL_B<1>, BL_B<2>, …, BL_B<2n-1>, BL_B<2n> may be the plurality of upper lines of the merge sub-array adjacent to the merge sub-array 200 on one side of the second BLSA 312, but some embodiments are not limited thereto.Each memory cell can be connected to one bit line and one word line among a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n>, a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n>, a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n>, and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n>. Each memory cell can include a cell transistor and a cell capacitor. Each memory cell formed in the merged sub - array 200 can include a cell capacitor and a cell transistor, and the cell transistor is connected to one bit line and one word line among a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n>, a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n>, a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n>, and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n>.

[0097] Reference Figure 7A and Figure 7B , the peripheral circuit structure PCS can include a merged bank 300. The merged bank 300 can include one memory array sheet, and the one memory array sheet can include a first BLSA 311, a second BLSA 312, a free space 350, a first SWD 321, and a second SWD 322. Accordingly, compared with Figure 5 the whole area of the PCS is dedicated to one memory array sheet instead of multiple memory array sheets.

[0098] In one or more embodiments, n right word lines among a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n> may be connected to the first SWD 321, and the other n right word lines may be connected to the second SWD 322. n left word lines among a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n> may be connected to the first SWD 321, and the other n left word lines may be connected to the second SWD 322. n upper lines among a plurality of upper lines may be connected to the first BLSA 311, and the other n upper lines among the plurality of upper lines may be connected to the second BLSA 312. n lower lines among a plurality of lower lines may be connected to the first BLSA 311, and the other n lower lines among the plurality of lower lines may be connected to the second BLSA 312. Although Figure 7A a disconnection between the bit line group and the word line group is shown, this disconnection may be for illustrative purposes only to show that a plurality of bit lines may be divided into upper lines (e.g., the first bit line) and lower lines (e.g., the second bit line), and a plurality of word lines may be divided into left word lines (e.g., the first word line) and right word lines (e.g., the second word line).

[0099] For example, when n is 4, the cell array structure CAS may include eight right word lines WL_R<1> to WL_R<8>, eight left word lines WL_L<1> to WL_L<8>, eight upper lines BL<1> to BL<8>, and eight lower lines BL_B<1> to BL_B<8>.

[0100] As Figure 7A and Figure 7B shown, the odd right word lines WL_R<1>, WL_R<3>, WL_R<5>, and WL_R<7> among the eight right word lines WL_R<1> to WL_R<8> may be connected to the first SWD 321, and the other right word lines (i.e., the even right word lines WL_R<2>, WL_R<4>, WL_R<6>, and WL_R<8>) may be connected to the second SWD 322. The eight upper lines BL<1> to BL<8> may be connected to the first BLSA 311, and the eight lower lines BL_B<1> to BL_B<8> may be connected to the second BLSA 312.

[0101] However, the embodiments are not limited thereto, and as another example, four right word lines among the eight right word lines WL_R<1> to WL_R<8> (for example, WL_R<1>, WL_R<2>, WL_R<3>, and WL_R<4>) may be connected to the first SWD 321, and the other four right word lines (for example, WL_R<5>, WL_R<6>, WL_R<7>, and WL_R<8>) may be connected to the second SWD 322.

[0102] Although Figure 7A and Figure 7B show a merged sub-array 200, the embodiments are not limited thereto. The cell array structure CAS may include a plurality of merged sub-arrays. Each merged sub-array may be arranged such that at least one side of the merged sub-array is spaced apart from another merged sub-array. For example, the plurality of merged sub-arrays may extend in a first horizontal direction (for example, the Y direction) and be arranged in parallel in a second horizontal direction (for example, the X direction). As another example, the plurality of merged sub-arrays may extend in the second horizontal direction (for example, the X direction) and be arranged in parallel in the first horizontal direction (for example, the Y direction). Refer to Figure 10 for a description of the structure in which a plurality of merged sub-arrays are arranged.

[0103] In one or more examples, although Figure 7A and Figure 7B show that the merged sub-array 200 includes four sub-arrays merged therein, the embodiments are not limited thereto. For example, the merged sub-array 200 may include eight sub-arrays merged therein. For example, the merged sub-array 200 may include 4n (n is a natural number) sub-arrays merged therein.

[0104] The merged sub-array 200 may include a plurality of pads formed such that a peripheral circuit structure PCS is connected to a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n>, a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n>, a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n>, and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n>.

[0105] For example, the merge sub-array 200 may include a first pad, a second pad, and a third pad. The first pad may connect a first BLSA 311 of the peripheral circuit structure PCS to a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1>, and BL<2n>. The second pad may connect a second BLSA 312 of the peripheral circuit structure PCS to a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1>, and BL_B<2n>. And the third pad may connect a first SWD 321 and a second SWD 322 of the peripheral circuit structure PCS to a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1>, and WL_L<2n> and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1>, and WL_R<2n>. Embodiments of the present disclosure are not limited to any particular pad arrangement. The pads may be arranged in a manner that optimizes the bonding between the CAS and the PCS.

[0106] In one or more embodiments, the merge sub-array 200 may include a first word line half-group WLHG1, a second word line half-group WLHG2, a first bit line half-group BLHG1, and a second bit line half-group BLHG2.

[0107] In one or more embodiments, the merge sub-array 200 may include a plurality of (e.g., 2n) left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1>, and WL_L<2n>, a plurality of (e.g., 2n) right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1>, and WL_R<2n>, a plurality of (i.e., 2n) upper bit lines BL<1>, BL<2>,..., BL<2n - 1>, and BL<2n>, and a plurality of (e.g., 2n) lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1>, and BL_B<2n>. And thus, the merge sub-array 200 may include a first word line half-group WLHG1 and a second word line half-group WLHG2, each including n left word lines among the plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1>, and WL_L<2n> and n right word lines among the plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1>, and WL_R<2n>, and include a first bit line half-group BLHG1 and a second bit line half-group BLHG2, each including n upper bit lines among the plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1>, and BL<2n> and n lower bit lines among the plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1>, and BL_B<2n>.

[0108] For example, the first word line half group WLHG1 may include n left word lines and n right word lines, and similarly, the second word line half group WLHG2 may also include another n left word lines and another n right word lines. The first bit line half group BLHG1 may include n upper bit lines and n lower bit lines, and similarly, the second bit line half group BLHG2 may also include another n upper bit lines and another n lower bit lines.

[0109] If n is assumed to be 2, the merged sub-array 200 may include four left word lines WL_L<1>, WL_L<2>, WL_L<3>, and WL_L<4>, four right word lines WL_R<1>, WL_R<2>, WL_R<3>, and WL_R<4>, four upper bit lines BL<1>, BL<2>, BL<3>, and BL<4>, and four lower bit lines BL_B<1>, BL_B<2>, BL_B<3>, and BL_B<4>.

[0110] For example, in the merged sub-array 200, the first word line half group WLHG1 may include four odd-numbered word lines (e.g., WL_L<1>, WL_L<3>, WL_R<1>, and WL_R<3>), the second word line half group WLHG2 may include four even-numbered word lines (e.g., WL_L<2>, WL_L<4>, WL_R<2>, and WL_R<4>), the first bit line half group BLHG1 may include four upper bit lines (e.g., BL<1>, BL<2>, BL<3>, and BL<4>), and the second bit line half group BLHG2 may include four lower bit lines (e.g., BL_B<1>, BL_B<2>, BL_B<3>, and BL_B<4>).

[0111] As described above, the first word line half group and the second word line half group may divide multiple word lines into odd-numbered word lines and even-numbered word lines. The first bit line half group and the second bit line half group may divide multiple bit lines into upper bit lines and lower bit lines. However, this embodiment is not limited thereto, and the first word line half group and the second word line half group may divide multiple word lines into left word lines and right word lines, and the first bit line half group and the second bit line half group may divide multiple bit lines into odd-numbered bit lines and even-numbered bit lines. In one or more examples, the number of bit lines in each bit line group and the number of word lines in each word line group are not equal. For example, the number of bit lines in the first group of bit lines may be M, and the number of bit lines in the second group of bit lines may be N, where M is not equal to N. In another example, the number of word lines in the first group of word lines may be M, and the number of word lines in the second group of word lines may be N, where M is not equal to N.

[0112] For example, in the merged sub-array 200, the first word line half-group WLHG1 may include four left word lines (e.g., WL_L<1>, WL_L<2>, WL_L<3>, and WL_L<4>), the second word line half-group WLHG2 may include four right word lines (e.g., WL_R<1>, WL_R<2>, WL_R<3>, and WL_R<4>), the first bit line half-group BLHG1 may include four odd bit lines (e.g., BL<1>, BL<3>, BL_B<1>, and BL_B<3>), and the second bit line half-group BLHG2 may include four even bit lines (e.g., BL<2>, BL<4>, BL_B<2>, and BL_B<4>).

[0113] In one or more examples, the peripheral circuit structure PCS may include a peripheral circuit region in which a peripheral circuit is formed. A part of the peripheral circuit may be formed in a partial region of the peripheral circuit region. Another part of the peripheral circuit may be formed in another partial region of the peripheral circuit region. The peripheral circuit may be configured to apply a word line drive voltage to a word line selected from a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1>, and WL_L<2n> and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1>, and WL_R<2n>. The peripheral circuit may be configured to read data through at least one bit line selected from a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1>, and BL<2n> and a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1>, and BL_B<2n>.

[0114] In one or more examples, the size of the free space 350 of the merged memory bank 300 may be greater than Figure 5 the size of the free space of one memory bank shown. For example, when Figure 5 the four sub-array regions 11, 12, 21, and 22 of Figure 7A and Figure 7B are merged into the Figure 5 and Figure 7A and Figure 7B merged sub-array 200, and Figure 7A and Figure 7B the four memory banks of Figure 5 are merged into the Figure 5 and Figure 7A and Figure 7B merged memory bank 300, Figure 5 the size of the free space 350 of the merged memory bank 300 shown may be four times the size of the free area SPARE of one memory bank of Figure 7A and Figure 7B When merging the memory banks 300, Figure 7A and Figure 7B the size of the free space 350 of the merged memory bank 300 shown can be Figure 5 4n times the size of the spare area SPARE of one memory bank.

[0115] The free space 350 of the peripheral circuit structure PCS may include a command decoder, MRS / EMRS circuits, an address buffer, data I / O circuits, a voltage generation circuit, a test circuit, or any other suitable circuit structure known to those skilled in the art.

[0116] The memory device 100B according to an embodiment of the present disclosure may include a merged sub-array 200 in which a plurality of sub-arrays included in the cell array structure CAS are merged, and the word lines and bit lines included in the merged sub-array 200 may be divided and arranged according to a predetermined standard to increase the size of the free space 350 of the peripheral circuit structure PCS. If the size of the free space 350 increases, the free space 350 may include peripheral circuits (e.g., a command decoder, MRS / EMRS circuits, an address buffer, data I / O circuits, a voltage generation circuit, and a test circuit), and thus, the memory chip size may be reduced.

[0117] In one or more examples, since the free space 350 may include peripheral circuits, the free area may be effectively used, and the memory integration degree may be improved.

[0118] Figure 8 is a perspective view showing a word line division structure and method of a memory device 200A according to one or more embodiments.

[0119] Referring to Figure 8 , the memory device 200A may include a cell array structure CAS and a peripheral circuit structure PCS. The cell array structure CAS may include a merged sub-array 200. The merged sub-array 200 may include multiple (i.e., 2n) left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n>, multiple (e.g., 2n) right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n>, and multiple (e.g., 2n) bit lines BL<1>, BL<2>, BL<2n - 1> and BL<2n>. The peripheral circuit structure PCS may include a first BLSA 311, a second BLSA 312, a free space 350, a first SWD 321, and a second SWD 322.

[0120] Figure 8 With Figure 7A and Figure 7B The difference is that multiple left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n> and multiple right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n> are partitioned, while multiple bit lines BL<1> to BL<2n> are not partitioned.

[0121] In one or more embodiments, the odd - numbered right word lines among multiple right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n> can be connected to the first SWD 321, and the other right word lines (e.g., even - numbered right word lines) can be connected to the second SWD 322. The odd - numbered left word lines among multiple left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n> can be connected to the first SWD 321, and the other left word lines (e.g., even - numbered left word lines) can be connected to the second SWD 322. The odd - numbered bit lines among multiple bit lines BL<1> to BL<2n> can be connected to the first BLSA 311, and the other bit lines (e.g., even - numbered bit lines) can be connected to the second BLSA 312.

[0122] In some embodiments, the complementary bit lines of the odd - numbered bit lines BL<1>, BL<3>,..., BL<2n - 3> and BL<2n - 1> can be multiple even - numbered bit lines of the merged sub - array adjacent to the merged sub - array 200 on one side of the first BLSA 311, and the complementary bit lines of the even - numbered bit lines BL_B<2>, BL_B<4>, …, BL_B<2n - 2> and BL_B<2n> can be multiple odd - numbered bit lines of the merged sub - array adjacent to the merged sub - array 200 on one side of the second BLSA 312, but some embodiments are not limited thereto.

[0123] According to the word - line partitioning structure and method, the merged sub - array 200 according to one or more embodiments can include a first word - line half - group WLHG1 and a second word - line half - group WLHG2.

[0124] For example, the merged sub-array 200 may include a first word line half-group WLHG1 and a second word line half-group WLHG2. The first word line half-group WLHG1 and the second word line half-group WLHG2 respectively include odd and even word lines divided from a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n> and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n>. The first word line half-group WLHG1 may include n odd left word lines and n odd right word lines. Similarly, the second word line half-group WLHG2 may also include another n even left word lines and another n even right word lines.

[0125] For example, if n is assumed to be 4, the merged sub-array 200 may include 8 left word lines WL_L<1> to WL_L<8>, 8 right word lines WL_R<1> to WL_R<8>, and 4 bit lines BL<1> to BL<4>.

[0126] Among the eight right word lines WL_R<1> to WL_R<8>, the odd right word lines (e.g., WL_R<1>, WL_R<3>, WL_R<5>, and WL_R<7>) may be connected to the first SWD 321, and the other right word lines (e.g., the even right word lines (e.g., WL_R<2>, WL_R<4>, WL_R<6>, and WL_R<8>)) may be connected to the second SWD 322. Among the eight left word lines WL_L<1> to WL_L<8>, the odd left word lines (e.g., WL_L<1>, WL_L<3>, WL_L<5>, and WL_L<7>) may be connected to the first SWD 321, and the other left word lines (e.g., the even left word lines (e.g., WL_L<2>, WL_L<4>, WL_L<6>, and WL_L<8>)) may be connected to the second SWD 322. Among the four bit lines BL<1> to BL<4>, the odd bit lines (e.g., BL<1> and BL<3>) may be connected to the first BLSA 311, and the other bit lines (i.e., the even bit lines (e.g., BL<2> and BL<4>)) may be connected to the second BLSA 312.

[0127] However, this embodiment is not limited thereto, and other embodiments may also be adopted.

[0128] Figure 9 is a perspective view showing a bit line division structure and method according to one or more embodiments.

[0129] Reference Figure 9 , the memory device 200B may include a cell array structure CAS and a peripheral circuit structure PCS. The cell array structure CAS may include merged sub-arrays 200. The merged sub-arrays 200 may include multiple (e.g., 2n) right word lines WL_R<1>,..., WL_R <n>, and WL_R<n+1>,..., WL_R<2n>, multiple (e.g., 2n) left word lines WL_L<1>,..., WL_L <n>, and WL_L<n+1>,..., WL_L<2n>, multiple (e.g., 2n) upper bit lines BL<1>, BL<2>,..., BL<2n-1> and BL<2n>, and multiple (e.g., 2n) lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n-1> and BL_B<2n>. The peripheral circuit structure PCS may include a first BLSA 311, a second BLSA 312, a free space 350, a first SWD 321, and a second SWD 322.

[0130] Figure 9 and Figure 7A and Figure 7B is different from that of, n word lines WL<1>, WL<2>,..., WL <n-1>and WL <n>Not divided, multiple upper wires BL<1>, BL<2>,..., BL<2n - 1> and BL<2n> and multiple lower wires BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n> are divided.

[0131] In one or more embodiments, n word lines WL<1>, WL<2>,..., WL <n-1>and WL <n>Among the odd-numbered word lines can be connected to the first SWD 321, and the other word lines (e.g., even-numbered word lines) can be connected to the second SWD 322. A plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n> can be connected to the first BLSA 311, and a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n> can be connected to the second BLSA 312.

[0132] According to the bit line partitioning structure and method, the merged sub-array 200 according to one or more embodiments may include a first bit line half-group BLHG1 and a second bit line half-group BLHG2.

[0133] For example, the first bit line half-group BLHG1 may include a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n>, and the second bit line half-group BLHG2 may include a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n>.

[0134] When n is 4, the merged sub-array 200 may include four word lines WL<1> to WL<4>, eight upper bit lines BL<1> to BL<8>, and eight lower bit lines BL_B<1> to BL_B<8>.

[0135] The first bit line half-group BLHG1 of the merged sub-array 200 may include 8 upper bit lines BL<1> to BL<8>, and the second bit line half-group BLHG2 may include 8 lower bit lines BL_B<1> to BL_B<8>. The first bit line half-group BLHG1 may be connected to the first BLSA 311, and the second bit line half-group BLHG2 may be connected to the second BLSA 312. n word lines WL<1>, WL<2>,..., WL <n-1>and WL <n>Among the odd-numbered word lines can be connected to the first SWD 321, and the other word lines (e.g., even-numbered word lines) can be connected to the second SWD 322.

[0136] Figure 10 is a perspective view showing a word line division structure, a bit line division structure, and a method according to one or more embodiments.

[0137] Reference Figure 10 , the memory device 500A can include a first merged sub-array 501, a second merged sub-array 502, and two merged banks. The cell array structure CAS can include the first merged sub-array 501 and the second merged sub-array 502. Figure 7A and Figure 7B The merged sub-array 200 shown can be applied to Figure 10 the first merged sub-array 501 and the second merged sub-array 502. The references Figure 7A and Figure 7B described are omitted here.

[0138] Each of the first merged sub-array 501 and the second merged sub-array 502 can include multiple (i.e., 2n) left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1>, and WL_L<2n>, multiple (i.e., 2n) right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1>, and WL_R<2n>, multiple upper bit lines BL<1>, BL<2>,..., BL<2n - 1>, and BL<2n>, and multiple lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1>, and BL_B<2n>.

[0139] Each of the first merged sub-array 501 and the second merged sub-array 502 can include a first word line half-group WLHG1 and a second word line half-group WLHG2 divided from multiple left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1>, and WL_L<2n> and multiple right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1>, and WL_R<2n> according to a predetermined criterion. In one or more examples, each of the first merged sub-array 501 and the second merged sub-array 502 can include a first bit line half-group BLHG1 and a second bit line half-group BLHG2 divided from multiple upper bit lines BL<1>, BL<2>,..., BL<2n - 1>, and BL<2n> and multiple lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1>, and BL_B<2n> according to a predetermined criterion.

[0140] As an example of a predetermined standard, in each of the first merging sub-array 501 and the second merging sub-array 502, a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n> can be divided into two groups of n left word lines each, a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n> can be divided into two groups of n right word lines each, a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n> can be divided into two groups of n upper bit lines each, and a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n> can be divided into two groups of n lower bit lines each.

[0141] As an example of a predetermined standard, in each of the first merging sub-array 501 and the second merging sub-array 502, a plurality of left word lines WL_L<1>, WL_L<2>,..., WL_L<2n - 1> and WL_L<2n> and a plurality of right word lines WL_R<1>, WL_R<2>,..., WL_R<2n - 1> and WL_R<2n> can be divided into odd-numbered word lines and even-numbered word lines, and a plurality of upper bit lines BL<1>, BL<2>,..., BL<2n - 1> and BL<2n> and a plurality of lower bit lines BL_B<1>, BL_B<2>,..., BL_B<2n - 1> and BL_B<2n> can be divided into odd-numbered bit lines and even-numbered bit lines.

[0142] The cell array structure CAS according to an embodiment of the present disclosure may include a first merging sub-array 501 and a second merging sub-array 502, wherein each of the first merging sub-array 501 and the second merging sub-array 502 may include word lines and bit lines that are divided and arranged according to a predetermined standard. By dividing and arranging the word lines and bit lines, the size of the free area of the peripheral circuit structure can be increased, and since the peripheral circuit may be included in the free area, the size of the memory chip can be reduced, and the memory integration degree can be improved.

[0143] Reference Figure 10 , may include a first merging sub-array 501 and a second merging sub-array 502. The first merging sub-array 501 may include multiple word lines and multiple bit lines in the cell array structure CAS, and include a first BLSA 311, a second BLSA 312, a first SWD 321, a second SWD 322, and a free space 350 in the peripheral circuit structure PCS. The second merging sub-array 502 may also include multiple word lines and multiple bit lines in the cell array structure CAS, and include a first BLSA 311, a second BLSA 312, a first SWD 321, a second SWD 322, and a free space 350 in the peripheral circuit structure PCS.

[0144] The multiple word lines and multiple bit lines included in the cell array structure CAS of each of the first merging sub-array 501 and the second merging sub-array 502 may be respectively connected to the first SWD 321 and the second SWD 322, and the first BLSA 311 and the second BLSA 312 of the peripheral circuit structure PCS, as Figure 7A and Figure 7B shown.

[0145] Figure 10 In contrast to Figure 7A and Figure 7B , the two merging sub-arrays shown in Figure 7A and Figure 7B are symmetrically formed. Figure 10 The first merging sub-array 501 and the second merging sub-array 502 shown in Figure 10 may be formed such that the free space of the first merging sub-array 501 faces the free space of the second merging sub-array 502. Therefore, Figure 7A or Figure 7B the size of the free space of the merged bank (including two merged banks) shown in

[0146] is eight times the size of the free space 350 of the merged bank 300 shown in

[0147] Figure 11 is a block diagram showing an electronic device 2000 including a storage device according to one or more embodiments.

[0148] Refer to Figure 11 , the electronic device 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. The electronic device 2000 may be implemented as a laptop computer, a mobile terminal, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. Alternatively, the electronic device 2000 may be implemented as a server or a PC.

[0149] The camera 2100 may capture a still image or a moving image according to a user's control, store the captured image / video data therein, or send the captured image / video data to the display 2200. The audio processor 2300 may process audio data included in the content in the flash memories 2600a and 2600b or from a network. The modem 2400 may modulate and send signals for wired / wireless data transmission and reception, and demodulate the signals into original signals on the receiving side. The I / O devices 2700a and 2700b may include devices configured to provide digital input and / or output functions such as a universal serial bus (USB), a storage device, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, and a touch screen.

[0150] The AP 2800 may control general operations of the electronic device 2000. The AP 2800 may include a controller 2810, an accelerator 2820, and an interface 2830. The AP 2800 may control the display 2200 to display a part of the content stored in the flash memories 2600a and 2600b on the display 2200. If a user input is received through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include the accelerator 2820 as a dedicated circuit for artificial intelligence (AI) data calculation, or the accelerator 2820 may be set separately from the AP 2800. The DRAM 2500b may be additionally installed in the accelerator 2820. An accelerator is a functional block configured to specifically execute a specific function of the AP 2800, and may include a graphics processing unit (GPU) as a functional block configured to specifically execute graphics data processing, a neural processing unit (NPU) as a block configured to specifically execute AI calculation and inference, and a data processing unit (DPU) as a block configured to specifically execute data transmission.

[0151] The electronic device 2000 may include multiple DRAMs. The AP 2800 may control the DRAMs 2500a and 2500b according to the standards of the Joint Electron Device Engineering Council (JEDEC) through commands and a mode register set (MRS), or communicate with the DRAMs 2500a and 2500b by setting a DRAM interface protocol to use company-specific functions (e.g., low voltage / high speed / reliability, etc.) and a cyclic redundancy check (CRC) / error correction code (ECC) function. For example, the AP 2800 may communicate with the DRAM 2500a through an interface compliant with JEDEC standards (e.g., low power double data rate 4 (LPDDR4) or LPDDR5), and the accelerator 2820 may communicate with the DRAM 2500b by setting a new DRAM interface protocol to control the DRAM 2500b with a higher bandwidth than the DRAM 2500a, where the DRAM 2500b is used for the accelerator.

[0152] Although Figure 11 Only the DRAMs 2500a and 2500b are shown, but this embodiment is not limited thereto, and any memory such as a phase change random access memory (PRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), or a hybrid RAM may be used as long as the bandwidth, response speed, and voltage conditions of the AP 2800 or the accelerator 2820 are satisfied. Compared with the I / O devices 2700a and 2700b or the flash memories 2600a and 2600b, the DRAMs 2500a and 2500b have relatively small latency and bandwidth. The DRAMs 2500a and 2500b may be initialized at the power-on time point of the electronic device 2000 and used as a temporary memory for the operating system and application data by loading the operating system and application data thereon, or used as an execution space for various software codes.

[0153] In DRAMs 2500a and 2500b, four basic arithmetic operations of addition / subtraction / multiplication / division, vector operations, address calculations, or fast Fourier transform (FFT) operations can be performed. In one or more examples, in DRAMs 2500a and 2500b, a function for performing inference can be executed. In this document, inference can be performed by using a deep learning algorithm of an artificial neural network. The deep learning algorithm can include a training operation for training a model with various data and an inference operation for identifying data by using the trained model. In one or more embodiments, an image captured by a user through camera 2100 can be signal-processed and stored in DRAM 2500b, and accelerator 2820 can perform AI data calculations for identifying data by using the data stored in DRAM 2500b and the function for inference.

[0154] Electronic device 2000 may include multiple storage devices or flash memories 2600a and 2600b having a capacity greater than that of DRAMs 2500a and 2500b. Accelerator 2820 can perform training operations and AI data calculations by using flash memories 2600a and 2600b. In one or more embodiments, each of flash memories 2600a and 2600b may include a storage controller 2610 and a flash memory device 2620, and the training operations and inference AI data calculations performed by AP 2800 and / or accelerator 2820 can be executed relatively efficiently by using the computing devices included in storage controller 2610. Flash memories 2600a and 2600b can store pictures taken through camera 2100 or data received through a data network. For example, augmented reality / virtual reality, high definition (HD) or ultra-high definition (UHD) content can be stored in flash memories 2600a and 2600b.

[0155] In electronic device 2000, DRAMs 2500a and 2500b may include reference Figures 1 to 10 The described memory device. The memory device may include a peripheral circuit structure formed on a semiconductor substrate and a cell array structure on the peripheral circuit structure to overlap the peripheral circuit structure in a vertical direction. The cell array structure may include a plurality of memory blocks in a memory cell region, where a plurality of vertical channel transistor structures and a plurality of capacitor structures respectively connected to the plurality of vertical channel transistor structures are formed in the memory cell region. The cell array structure may include a merged sub-array. The merged sub-array may include a first half-word line group and a second half-word line group obtained by dividing a plurality of left word lines and a plurality of right word lines according to a predetermined criterion. In one or more examples, the merged sub-array may include a first half-bit line group and a second half-bit line group obtained by dividing a plurality of upper bit lines and a plurality of lower bit lines according to a predetermined criterion. The peripheral circuit structure may include a peripheral circuit region in which a merged memory bank and peripheral circuits are formed. The merged memory bank may include a first BLSA, a second BLSA, an SWD, and free space. As the free space of the merged memory bank increases, the peripheral circuits may be included in the increased free space, and thus, the memory chip size may be reduced.

[0156] A memory device according to an embodiment of the present disclosure may include a merged sub-array in which a plurality of sub-arrays included in a cell array structure are merged, where the word lines and bit lines included in the merged sub-array may be divided and arranged according to a predetermined criterion to increase the size of the free region of the peripheral circuit structure. If the size of the free space increases, the free space may include peripheral circuits (e.g., a command decoder, an MRS / EMRS circuit, an address buffer, a data I / O circuit, a voltage generation circuit, and a test circuit), and thus, the memory chip size may be reduced. In one or more examples, since the free space may include peripheral circuits, the free space may be effectively used, and the memory integration degree may be improved.

[0157] Although embodiments thereof have been specifically shown and described with reference to embodiments of the present disclosure, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A storage device, comprising: A peripheral circuit structure; And A cell array structure, on the peripheral circuit structure, Wherein, the cell array structure overlaps with the peripheral circuit structure in a first direction, Wherein, the cell array structure includes a merged sub-array in which at least four sub-array regions are merged, Wherein, the merged sub-array includes a storage cell region, and the storage cell region includes: A plurality of first bit lines and a plurality of second bit lines, arranged in a second direction perpendicular to the first direction; and A plurality of first word lines and a plurality of second word lines, arranged in a third direction perpendicular to the second direction, Wherein, the peripheral circuit structure includes a merged bank in which at least four banks are merged, and Wherein, the merged bank includes: A first bit line sense amplifier BLSA, configured to read the voltage difference of the plurality of first bit lines, A second BLSA, configured to read the voltage difference of the plurality of second bit lines, A first sub-word line driver SWD, configured to drive the even-numbered word lines among the plurality of first word lines and the even-numbered word lines among the plurality of second word lines, and A second SWD, configured to drive the odd-numbered word lines among the plurality of first word lines and the odd-numbered word lines among the plurality of second word lines, and Wherein, free space is defined between a first region corresponding to the plurality of first bit lines and a second region corresponding to the plurality of second bit lines.

2. The storage device according to claim 1, wherein, The storage cell region further includes a plurality of storage cells, and each of the plurality of storage cells has a vertical channel transistor VCT structure.

3. The memory device according to claim 2, wherein, Each of the plurality of storage cells includes: A cell transistor, connected to a word line from the plurality of first word lines or the plurality of second word lines, a bit line from the plurality of first bit lines or the plurality of second bit lines, and a back gate line; and A cell capacitor, connected between a first electrode of the cell transistor and ground.

4. The storage device according to claim 1, wherein, The merged sub-array includes: A first word line half-group and a second word line half-group, and each of the first word line half-group and the second word line half-group includes n first word lines among the plurality of first word lines and n second word lines among the plurality of second word lines; and A first bit line half-group and a second bit line half-group, and each of the first bit line half-group and the second bit line half-group includes n first bit lines among the plurality of first bit lines and n second bit lines among the plurality of second bit lines.

5. The memory device according to claim 4, wherein, The first word line half-group includes a first word line and a second word line from the plurality of first word lines, and a first word line and a second word line from the plurality of second word lines, and Wherein, the second word line half-group includes a third word line and a fourth word line from the plurality of first word lines, and a third word line and a fourth word line from the plurality of second word lines.

6. The storage device according to claim 4, wherein, The first bit line half-group includes a first bit line and a second bit line from the plurality of first bit lines, and a first bit line and a second bit line from the plurality of second bit lines, and Among them, the second bit line half group includes the third bit line and the fourth bit line from the multiple first bit lines, and the third bit line and the fourth bit line from the multiple second bit lines.

7. The storage device according to claim 1, wherein, The merged sub-array includes: A first word line half group, including the odd-numbered word lines among the multiple first word lines and the multiple second word lines; A second word line half group, including the even-numbered word lines among the multiple first word lines and the multiple second word lines; A first bit line half group, including the odd-numbered bit lines among the multiple first bit lines and the multiple second bit lines; and A second bit line half group, including the even-numbered bit lines among the multiple first bit lines and the multiple second bit lines.

8. The memory device according to claim 7, wherein The first word line half group includes the first word line and the third word line from the multiple first word lines, and the first word line and the third word line from the multiple second word lines, and Among them, the second word line half group includes the second word line and the fourth word line from the multiple first word lines, and the second word line and the fourth word line from the multiple second word lines.

9. The memory device according to claim 7, wherein, The first bit line half group includes the first bit line and the third bit line from the multiple first bit lines, and the first bit line and the third bit line from the multiple second bit lines, and Among them, the second bit line half group includes the second bit line and the fourth bit line from the multiple first bit lines, and the second bit line and the fourth bit line from the multiple second bit lines.

10. The storage device according to claim 1, wherein, The free space of the merged memory bank is greater than the free space of a single memory bank.

11. The memory device according to claim 10, wherein, The peripheral circuit is formed in the free space of the merged memory bank.

12. A storage device, including: A peripheral circuit structure; And A cell array structure, on the peripheral circuit structure, Among them, the cell array structure overlaps with the peripheral circuit structure in a first direction, Among them, the cell array structure includes a merged sub-array in which at least 4n sub-array regions are merged, Among them, n is a natural number greater than zero, Among them, the merged sub-array includes: A first bit line half group and a second bit line half group, obtained by dividing multiple first bit lines and multiple second bit lines arranged in a second direction perpendicular to the first direction, and A first word line half group and a second word line half group, obtained by dividing multiple first word lines and multiple second word lines arranged in a third direction perpendicular to the second direction, and Among them, the peripheral circuit structure includes a merged memory bank in which at least 4n memory banks are merged.

13. The memory device according to claim 12, wherein Each of the first bit line half group and the second bit line half group is formed by n bit lines among the multiple first bit lines and n bit lines among the multiple second bit lines, and each of the first word line half group and the second word line half group is formed by n word lines among the multiple first word lines and n word lines among the multiple second word lines.

14. The storage device according to claim 13, wherein, n is 4. The first bit line half-group includes the first to the fourth bit lines from the multiple first bit lines and the first to the fourth bit lines from the multiple second bit lines. The second bit line half-group includes the fifth to the eighth bit lines from the multiple first bit lines and the fifth to the eighth bit lines from the multiple second bit lines. The first word line half-group includes the first to the fourth word lines from the multiple first word lines and the first to the fourth word lines from the multiple second word lines. And the second word line half-group includes the fifth to the eighth word lines from the multiple first word lines and the fifth to the eighth word lines from the multiple second word lines.

15. The storage device according to claim 12, wherein, The first bit line half-group and the second bit line half-group are formed by respectively dividing the multiple first bit lines and the multiple second bit lines into odd-numbered bit lines and even-numbered bit lines. And wherein, the first word line half-group and the second word line half-group are formed by respectively dividing the multiple first word lines and the multiple second word lines into odd-numbered word lines and even-numbered word lines.

16. The memory device according to claim 15, wherein, The first bit line half-group includes the odd-numbered bit lines from the multiple first bit lines and the odd-numbered bit lines from the multiple second bit lines. The second bit line half-group includes the even-numbered bit lines from the multiple first bit lines and the even-numbered bit lines from the multiple second bit lines. The first word line half-group includes the odd-numbered word lines from the multiple first word lines and the odd-numbered word lines from the multiple second word lines. And the second word line half-group includes the even-numbered word lines from the multiple first word lines and the even-numbered word lines from the multiple second word lines.

17. The storage device according to claim 12, wherein, The free space of the merged memory bank is 4n times the free space of each memory bank, where n is a natural number greater than zero.

18. A storage device, comprising: A peripheral circuit structure; And A cell array structure, on the peripheral circuit structure, wherein, the cell array structure overlaps the peripheral circuit structure in a first direction, wherein, the cell array structure includes a merged sub-array in which at least 4n sub-array regions are merged, where n is a natural number greater than zero, wherein, the merged sub-array includes a storage unit region, and the storage unit region includes: Multiple first bit lines and multiple second bit lines, arranged in a second direction perpendicular to the first direction; and Multiple first word lines and multiple second word lines, arranged in a third direction perpendicular to the second direction, wherein, the storage unit region includes a first bit line half-group, a second bit line half-group, a first word line half-group, and a second word line half-group. The first bit line half-group and the second bit line half-group are obtained by dividing the multiple first bit lines and the multiple second bit lines according to a first predetermined criterion. The first word line half-group and the second word line half-group are obtained by dividing the multiple first word lines and the multiple second word lines according to a second predetermined criterion. Among them, the peripheral circuit structure includes a merged memory bank in which at least 4n memory banks are merged, and Among them, the merged memory bank includes: A first bit line sense amplifier BLSA configured to read the voltage difference of the plurality of first bit lines, A second BLSA configured to read the voltage difference of the plurality of second bit lines, A first sub-word line driver SWD configured to drive the even-numbered word lines among the plurality of first word lines and the even-numbered word lines among the plurality of second word lines, A second SWD configured to drive the odd-numbered word lines among the plurality of first word lines and the odd-numbered word lines among the plurality of second word lines, and Among them, free space is defined between a first region corresponding to the plurality of first bit lines and a second region corresponding to the plurality of second bit lines.

19. The memory device according to claim 18, wherein, The plurality of first bit lines, the plurality of second bit lines, the plurality of first word lines, and the plurality of second word lines are each divided into units of 2n, Among them, the first half-bit line group includes 2n bit lines among the plurality of first bit lines and 2n bit lines among the plurality of second bit lines, and the second half-bit line group includes the remaining 2n bit lines among the plurality of first bit lines and the remaining 2n bit lines among the plurality of second bit lines, and Among them, the first half-word line group includes 2n word lines among the plurality of first word lines and 2n word lines among the plurality of second word lines, and the second half-word line group includes the remaining 2n word lines among the plurality of first word lines and the remaining 2n word lines among the plurality of second word lines.

20. The memory device according to claim 18, wherein The plurality of first bit lines, the plurality of second bit lines, the plurality of first word lines, and the plurality of second word lines are each divided into odd-numbered lines and even-numbered lines, Among them, the first half-bit line group includes the odd-numbered bit lines from the plurality of first bit lines and the odd-numbered bit lines from the plurality of second bit lines, Among them, the second half-bit line group includes the even-numbered bit lines from the plurality of first bit lines and the even-numbered bit lines from the plurality of second bit lines, Among them, the first half-word line group includes the odd-numbered word lines from the plurality of first word lines and the odd-numbered word lines from the plurality of second word lines, and Among them, the second half-word line group includes the even-numbered word lines from the plurality of first word lines and the even-numbered word lines from the plurality of second word lines.

Images