Correction circuit, storage device, storage system, and electronic apparatus

Abstract

The invention discloses a correction circuit, a storage device, a storage system and electronic equipment, and relates to the technical field of semiconductors. The correction circuit is used for correcting a first semiconductor device of the storage circuit, the first semiconductor device comprises a first end, a second end and a first control end, a first channel is formed between the first end and the second end, and the first control end is used for controlling the conduction capability of the first channel. The correction circuit comprises a second semiconductor device which is matched with the first semiconductor device and comprises a third end, a fourth end and a second control end, a second channel is formed between the third end and the fourth end, the second control end is used for controlling the conduction capability of the second channel, and the third end is coupled with the constant current; the feedback control branch is connected with the third end and outputs correction voltage based on the voltage of the third end, the second control end is coupled with the correction voltage, the correction voltage is used for stabilizing the channel current of the second channel, and the correction voltage is used for the first control end. The correction circuit can reduce precision reduction caused by environmental factors.

Description

Technical Field

[0001] This application relates to the field of semiconductor technologies, and more particularly, to a calibration circuit, a storage device, a memory-computation system, and an electronic device. Background Art

[0002] In traditional computing modes, such as in the von Neumann architecture, storage and computing are physically separated. When using this computing mode for data processing, data is frequently transferred between storage devices and computing devices, resulting in data transfer latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the amount of data processed has increased rapidly, and the demand for data transfer has also increased rapidly. The resulting transfer latency and energy consumption have become increasingly prominent, restricting the development of data processing capabilities and making it difficult for traditional computing modes to meet the processing capacity requirements.

[0003] The memory-computation integrated architecture can physically integrate storage and computing, either by implementing computing through storage devices or storing data in computing devices, thereby reducing the need for data transfer, lowering transfer latency and energy consumption, and greatly improving data processing efficiency. However, the memory-computation integrated architecture still faces challenges. For example, the computing accuracy of the memory-computation integrated architecture still needs to be improved. Summary of the Invention

[0004] This application provides a calibration circuit, a storage device, a memory-computation system, and an electronic device to improve the computing accuracy of the memory-computation integrated architecture.

[0005] In a first aspect, a calibration circuit is provided for calibrating a first semiconductor device of a storage circuit. The first semiconductor device includes a first terminal, a second terminal, and a first control terminal. A first channel is formed between the first terminal and the second terminal, and the first control terminal is used to control the conduction ability of the first channel. The calibration circuit includes: a second semiconductor device, which is matched with the first semiconductor device and includes a third terminal, a fourth terminal, and a second control terminal. A second channel is formed between the third terminal and the fourth terminal, and the second control terminal is used to control the conduction ability of the second channel. The third terminal is coupled to a constant current; a feedback control branch, connected to the third terminal, outputs a calibration voltage based on the voltage of the third terminal. The second control terminal is coupled to the calibration voltage. The calibration voltage is used to stabilize the channel current of the second channel and is used for the first control terminal.

[0006] The second semiconductor device is matched with the first semiconductor device. The channel currents or channel conduction abilities of the two are affected by environmental factors in the same or similar ways. The calibration voltage generated based on the second semiconductor device can be used to reduce or offset the influence of environmental factors on the channel current or channel conduction ability of the first semiconductor device, and reduce the reduction in the reading accuracy or computing accuracy of the storage device and the memory-computation system caused by changes in environmental factors.

[0007] In certain implementations of the first aspect, the feedback control branch includes: a feedback control circuit, coupled to a reference voltage and connected to the third terminal, the feedback control circuit being configured to adjust and output a correction voltage based on the voltage at the third terminal and the reference voltage.

[0008] In certain implementations of the first aspect, the feedback control circuit includes: an operational amplifier, including a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to the reference voltage, the second input terminal being connected to the third terminal, and the output terminal being configured to output the correction voltage.

[0009] In certain implementations of the first aspect, the first semiconductor device further includes a third control terminal, the third control terminal being configured to be coupled to an input signal and control the conductivity of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal, the fourth control terminal being configured to be coupled to a first voltage.

[0010] In certain implementations of the first aspect, the first voltage is input signal determined.

[0011] In certain implementations of the first aspect, the correction circuit includes a plurality of second semiconductor devices, the second control terminals of the plurality of second semiconductor devices being connected together, and the third terminals of the plurality of second semiconductor devices being connected together.

[0012] In certain implementations of the first aspect, the correction circuit further includes: a drive circuit, connected between the second control terminal of the second semiconductor device and the first control terminal of the first semiconductor device, for boosting the output power of the correction voltage output by the feedback control branch.

[0013] In certain implementations of the first aspect, the second semiconductor device includes a transistor; the second control terminal includes a substrate, and the fourth control terminal includes a gate; alternatively, the second control terminal includes a first gate, and the fourth control terminal includes a second gate.

[0014] In a second aspect, a storage device is provided, including: a storage circuit, including a first semiconductor device, the first semiconductor device including a first terminal, a second terminal, and a first control terminal, a first channel being formed between the first terminal and the second terminal, the first control terminal being configured to control the conductivity of the first channel; a correction circuit according to the first aspect or any possible implementation manner in the first aspect.

[0015] In certain implementations of the second aspect, the first semiconductor device further includes a third control terminal, the third control terminal being configured to be coupled to an input signal and control the conductivity of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal, the fourth control terminal being configured to be coupled to a first voltage.

[0016] In some implementations of the second aspect, the storage circuit includes a group of storage units, the group of storage units includes a plurality of first semiconductor devices. Among the first semiconductor devices within the group of storage units, third control terminals are respectively coupled to a plurality of input signals, and third terminals are connected to each other and connected to the same output line. The group of storage units is configured to convert the plurality of input signals into a plurality of output signals based on the weight data respectively stored in the first semiconductor devices within the group of storage units, and output an accumulated signal of the plurality of output signals on the same output line.

[0017] In a third aspect, there is provided a memory computing system, including the storage device in the second aspect or any possible implementation of the second aspect.

[0018] In a fourth aspect, there is provided an electronic device, including the memory computing system in the third aspect or any possible implementation of the third aspect. Description of the Drawings

[0019] Figure 1 A schematic diagram of a memory computing system according to an exemplary embodiment of the present application is shown.

[0020] Figure 2 A schematic diagram of another memory computing system according to an exemplary embodiment of the present application is shown.

[0021] Figure 3 A schematic diagram of a storage device according to an exemplary embodiment of the present application is shown.

[0022] Figure 4 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown.

[0023] Figure 5 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown.

[0024] Figure 6 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown.

[0025] Figure 7 A schematic diagram of a calibration circuit according to an exemplary embodiment of the present application is shown.

[0026] Figure 8 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown.

[0027] Figure 9 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown.

[0028] Figure 10 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown.

[0029] Figures 11 to 13 The figure shows a schematic diagram of various semiconductor devices according to an exemplary embodiment of the present application.

[0030] Figures 14 to 17 The figure shows a schematic diagram of various calibration circuits according to an exemplary embodiment of the present application.

[0031] Figure 18 The figure shows a schematic diagram of another memory - computing system according to an exemplary embodiment of the present application.

[0032] Figure 19 The figure shows a schematic diagram of an electronic device according to an exemplary embodiment of the present application. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings.

[0034] For the sake of simplicity of the drawings, only the parts related to the corresponding embodiments are schematically shown in the drawings of the embodiments of the present application, and they do not represent the actual structure of the product. In addition, for the sake of simplicity of the drawings and easy understanding, in some drawings, only some structures or components are schematically shown, and there may actually be more or fewer identical or similar structures or components.

[0035] The business scenarios described in the embodiments of the present application are used to exemplarily illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the evolution of technology and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0036] In the present application, unless otherwise clearly specified and limited, "connection" includes direct connection or indirect connection between objects: the connected objects can be directly connected through a medium (for example, wires, traces, etc.), or can be indirectly connected through other components, or can be internally connected. "Coupling" includes signal connection between objects, which can be directly achieved through a medium (for example, wires, traces, etc.), or can be achieved through other components for signal connection, etc. "Grounding" includes direct grounding or indirect grounding. Indirect grounding, for example, includes grounding through other components.

[0037] In this application, unless otherwise clearly stipulated and defined, ordinal numbers such as "first", "second", etc. are only used to distinguish the described objects and cannot be construed as indicating or implying the relative importance or order between the described objects. In addition, ordinal numbers do not represent the quantity of the described objects. "Plurality" includes two or more, and other quantifiers are similar. "Or", "and / or" are used to describe the relationship between objects, and they represent non-exclusive inclusion. For example, "A and / or B", "A or B" can include: "A alone", "B alone", or "A and B". Again, "A, B and / or C", "A, B or C" can include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C". Additionally, " / " in this application is used to represent the "or" relationship between the front and back objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of the above "A and / or B", "A or B". The meaning of "one or more of A, B and C" or "at least one of A, B and C" is the same as the above "A, B and / or C", "A, B or C".

[0038] In the in-memory computing technology, storage and computing (or arithmetic) are physically integrated. Such physical integration may include, for example, integrating the storage and computing parts in close proximity through processes such as packaging. Another example is integrating a processing circuit with processing capabilities in a memory to achieve the integration of in-memory processing functions. Yet another example is to implement computing through storage devices or store data in computing devices to achieve the tight integration of storage and computing. According to some embodiments, the in-memory computing system may include a storage circuit and a processing circuit (or control circuit). The storage circuit is used to store data. The processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computing, or sensing of the computing results of data. For example, the processing circuit may call the data stored in the storage circuit and perform computing based on the called data. Another example is that the processing circuit may control the computing of the storage circuit. Yet another example is that the processing circuit may be used to read or sense the computing results of the storage circuit and process the computing results. This application does not limit the type of memory, and the memory may include, for example, but not limited to: non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, for example, but not limited to: static random access memory (SRAM) or dynamic random access memory (DRAM). Non-volatile memory may include, for example, but not limited to: flash, resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or phase change memory (PCM), etc.

[0039] For ease of understanding, Figure 1 FIG. shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of the present application. This in-memory computing system is described by taking in-memory computing implemented with a memory as a carrier as an example.

[0040] As Figure 1As shown, the memory-computation system 100 may include a memory circuit (or memory-computation circuit) 110 and a control circuit 120. The memory circuit 110 may be used to store weight data (also referred to as weights); the control circuit 120 may be used to control the working state of the memory circuit 110. The working state of the memory circuit 110 includes, for example, a programming state and a computing state. In the programming state, the weight data is written into the memory circuit 110. In the computing state, the memory circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The memory circuit 110 may store multiple weight data, and the multiple weight data may be equivalent to at least one vector (or matrix). The memory circuit 110 may store the weight data in units of memory cells, and the memory cells may also be referred to as storage units or storage structures. For example, the memory circuit 110 includes a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array.

[0041] The memory cell may include a semiconductor device and utilize the conduction ability of the semiconductor device, such as conductivity or transconductance, to implement the storage of weight data. For example, the memory cell may include a resistive memory device or a transistor memory device. For example, the storage of weight data can be achieved by controlling the conductivity of the resistive memory device, or the storage of weight data can be achieved by controlling the transconductance of the transistor memory device. Alternatively, the memory cell may utilize the energy stored in the energy storage element to implement the storage of weight data, such as using the charge stored in a capacitor to implement the storage of weight data; the energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conduction ability.

[0042] The memory circuit 110 may perform calculations in groups. For example, the memory cell array includes at least one memory cell group, and the memory cell group includes a plurality of memory cells and can store multiple weight data, and the multiple weight data may be equivalent to a first data vector (or a first data matrix). In the programming state, the weight data is written into the memory cells, which is equivalent to writing the first data vector (or the first data matrix) into the memory cell group in the memory cell array. In the computing state, the memory circuit 110 receives an input signal, and the conduction ability of the memory cell can change the input signal to obtain an output signal. Cumulatively outputting the output signals in the memory cell group can achieve an equivalent multiplication operation. The memory cell array may include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc. The memory cell group includes a plurality of memory cells in the same row or the same column in the memory cell array, or a plurality of memory cells in multiple rows or multiple columns, etc., and the plurality of memory cells can output collinearly.

[0043] In some possible embodiments, the memory - computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 may convert the input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on the weight data; the output circuit 140 may convert the output signal Sout into output data D2 for output. The at least one input signal may be equivalent to a second data vector (or a second data matrix), and the output data D2 may be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0044] As an example, Figure 2 FIG. shows a schematic diagram of another memory - computing system according to an exemplary embodiment of the present application.

[0045] As Figure 2 shown, the memory - computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes a plurality of memory cells S ij , where i ∈ [1, m], j ∈ [1, n], m is the number of rows of the memory cell array, and n is the number of columns of the memory cell array. The memory cell S ij can store weight data W ij . When the memory cell array 210 is in the programming state, the conduction ability of the memory cell S ij can be controlled based on the weight data to reach the target state, so as to achieve the storage of the weight data. When the memory cell array 210 is in the computing state, an input signal, such as an input voltage V ij , can be provided to the memory cell S ij through the input terminal IN of the memory cell S i ; the memory cell S ij outputs its output signal at the output terminal OUT, such as an output current. The output terminals of multiple memory cells (such as S 1j -S mj ) can output collinearly. According to Kirchhoff's law, the output signals of multiple memory cells accumulate, and the obtained output signal I j satisfies the following formula:

[0046]

[0047] In some possible embodiments, the input data includes digital input signals, and the input signal V of the memory cell array 210 iIt may include an analog signal. The input circuit 230 may include, for example, a digital to analog converter (DAC) that converts a digital signal into an analog signal and provides it to the memory cell array 210. In some possible embodiments, the input signal of the memory cell array 210 may include a digital signal, which is represented by the waveform characteristics of the signal, such as the pulse width, amplitude, or area of the signal. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain an input signal and provide it to the memory cell array 210.

[0048] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and then outputting it to the subsequent circuit. Such conversion includes, for example, one or more of signal type conversion, signal magnitude conversion, etc., such as one or more of current-voltage conversion, analog-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For example, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 may convert the current signal into a voltage signal. Again, for example, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented by, for example, a sampling circuit. Optionally, the signal obtained by the conversion of the first conversion circuit 241 may be further provided to the second conversion circuit 242 for the second conversion. Exemplarily, the first conversion circuit 241 includes, for example, a transimpedance amplifier (TIA) to convert the current signal into a voltage signal; the second conversion circuit 242 includes, for example, an analog to digital converter (ADC) to convert the analog signal into a digital signal and provide it to the subsequent circuit. Again, for example, the output circuit may include a sense amplifier (SA), and the SA may perform sensing, amplification processing, etc. on the signal obtained from the memory cell array 210 or the first conversion circuit 241. Additionally, in Figure 2 the example, the memory computing system 200 may further include a control circuit 220, and the control circuit 220 may be used to control the operating state of the memory cells S ij in the memory cell array 210, such as the programming state and the computing state described above.

[0049] Figure 2 Only as an example, a connection method of the memory cells in a memory cell array 210 is shown. In addition to Figure 2In addition to the connection manner shown, other connection manners can also be adopted. For example, the input ends of the memory cells are connected in common by column, and the output ends of the memory cells are connected in common by row. For another example, the input end of the memory cell may include the gate of the transistor memory device, or the input end of the memory cell may include the source or drain of the transistor memory device. The embodiments of the present application do not limit this. The present application also does not limit the type of the memory cell. For example, the memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase change structures, etc. The present application also does not limit the type of the transistor. For example, it includes metal oxide semiconductor field effect transistors (MOSFETs), floating gate transistors (FGTs), ferroelectric field effect transistors (FeFETs), thin film transistors, etc. The memory cell may include multiple transistors; exemplarily, the memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") is connected to the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube"), and the charge stored at the gate of the first transistor can be used to represent the weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0050] The performance of a semiconductor device of a memory cell may change with the environment, and this change in performance may cause the output of the memory cell to vary with the environment, resulting in different read results or calculation results for the memory computing system under the same input signal and weight data, affecting the read accuracy or calculation accuracy of the memory computing system. For example, a transistor can regulate the channel current using the gate voltage or the substrate voltage. Taking the gate voltage or the substrate voltage as the input voltage of the memory cell and the channel current as the output of the memory cell, the channel current is related to the input voltage and the threshold voltage, that is, Id = f(Vg, Vth), where Id represents the channel current, Vg represents the gate voltage, Vth represents the threshold voltage, and f() represents the relationship function between the channel current and the input voltage and the threshold voltage. However, the threshold voltage Vth may change with temperature, that is, Vth = g(T), where T represents the temperature and g() represents the relationship function between the threshold voltage and the temperature; or rather, temperature affects the conduction ability of the channel of the transistor. Therefore, at different temperatures, the channel current of the semiconductor device will be different, and the memory cell or the memory cell group will generate different output currents, thereby obtaining different read or calculation results, resulting in a reduction in the read accuracy or calculation accuracy of the memory device and the memory computing system.

[0051] In view of this, embodiments of the present application propose a correction circuit, a memory device, a memory computing system, and an electronic device. By means of the feedback control branch of the correction circuit, the influence of environmental factors such as temperature on the conduction ability of the channel or the channel current of the semiconductor device is corrected, and the output of the memory cell at different temperatures is stabilized, thereby improving the read accuracy or calculation accuracy of the memory device and the memory computing system, and expanding the operating temperature range and application scenarios of the memory computing system.

[0052] Figure 3 Shows a schematic diagram of a memory device according to an exemplary embodiment of the present application. As Figure 3 shown, the memory device 300 may include a memory circuit 310 and a correction circuit 320.

[0053] The storage circuit 310 may include a semiconductor device 311. The semiconductor device 311 may be used as a storage unit or a part of a storage unit. The semiconductor device 311 may include a first terminal t1, a second terminal t2, and a first control terminal c1. A first channel is formed between the first terminal t1 and the second terminal t2. The first control terminal c1 may control the conduction ability of the first channel. The first control terminal c1 may be coupled to a calibration voltage VT, and the calibration voltage VT may be provided by a calibration circuit 320. The calibration circuit 320 adaptively obtains the calibration voltage VT by using a semiconductor device 321 that matches the semiconductor device 311, so that the calibration voltage VT can change adaptively following environmental factors (such as temperature). The influence of the calibration voltage VT on the channel current or channel conduction ability of the semiconductor device 311 may reduce or offset the influence of environmental factors on the channel current or channel conduction ability of the semiconductor device 311. In this way, the reduction in the reading accuracy or calculation accuracy of the storage device and the memory-computation system caused by changes in environmental factors can be reduced.

[0054] The calibration circuit 320 may include a semiconductor device 321 and a feedback control branch 322. The semiconductor device 321 may include a third terminal t3, a fourth terminal t4, and a second control terminal c2. A second channel is formed between the third terminal t3 and the fourth terminal t4. The second control terminal c2 may control the conduction ability of the second channel. The third terminal t3 is coupled to a constant current I0. The feedback control branch 322 may be connected to the third terminal t3 and output the calibration voltage VT based on the voltage of the third terminal t3. The second control terminal c2 is coupled to the calibration voltage VT, and the calibration voltage VT may be used to stabilize the channel current of the second channel. The semiconductor device 321 may match the semiconductor device 311, and the calibration voltage VT may be used for the first control terminal c1.

[0055] This application does not limit the flow direction of the constant current I0. For example, it may flow from the third terminal t3 to the fourth terminal t4, or from the fourth terminal t4 to the third terminal t3. Figure 3 The arrow in

[0056] According to some embodiments, the fourth terminal t4 may be coupled to conduct the voltage V2 of the channel of the semiconductor device 321. The magnitude of the voltage V2 is not limited in this application. For example, it may include a positive supply voltage (VDD) or a negative supply voltage / ground voltage (VSS). Exemplarily, the voltage V2 may include a ground voltage. The feedback control branch 322 adaptively outputs a correction voltage VT based on the voltage of the third terminal t3. By controlling the channel conduction ability of the semiconductor device 321, the channel current of the semiconductor device 321 is stabilized as a constant current I0, for example, thereby reducing or offsetting the influence of environmental factors (such as temperature) on the channel current or channel conduction ability of the semiconductor device 321. The semiconductor device 321 is matched with the semiconductor device 311, and the channel current or channel conduction ability of the two is affected by environmental factors in the same or similar way. The correction voltage VT generated based on the semiconductor device 321 can be used to reduce or offset the influence of environmental factors on the channel current or channel conduction ability of the semiconductor device 311, and reduce the reduction of the reading accuracy or calculation accuracy of the storage device and the memory computing system caused by changes in environmental factors.

[0057] According to some embodiments, the feedback control branch 322 may include a circuit from the third terminal t3 to the second control terminal c2. The constant current I0 may include a first component flowing through the semiconductor device 321 and a second component flowing through the feedback control branch 322. The first component corresponds to the channel current of the semiconductor device 321, and the second component tends to 0. The second component is less than or equal to a first current threshold. The first current threshold is an error tolerance current, and its value is not limited in the embodiments of this application. As long as the second component can be considered equal to or approximately equal to 0 within the error tolerance range. In this way, the first component or the channel current can tend to the constant current I0. The difference between the first component or the channel current and the constant current I0 is less than or equal to a second current threshold. The second current threshold is an error tolerance current, and its value is not limited in the embodiments of this application. As long as the first component or the channel current can be considered equal to or approximately equal to the constant current I0 within the error tolerance range. The second current threshold may be equal to the first current threshold. Additionally, the feedback control branch 322 may include an output terminal, and the output terminal may be connected to the second control terminal c2.

[0058] The present application does not limit the manner of providing the constant current I0. The constant current I0 can be generated by a current source or can be provided by a conversion circuit that can convert a voltage into a current. For example, the current source can generate the constant current I0 based on the voltage V1. For example, the voltage V1 can include the voltage provided by a bandgap reference circuit. Further, the current source includes a zero temperature coefficient (ZTC) current source. Further, the conversion circuit can include a current-mode DAC, etc. The constant current I0 is less affected by environmental factors. For example, the constant current I0 can be unaffected by temperature, or the influence of temperature on the constant current I0 can be negligible. The temperature coefficient of the constant current I0 can be low, for example, lower than the current temperature coefficient threshold. The influence of temperature on the constant current I0 is less than the influence of temperature on the threshold voltage of a semiconductor device. For example, the influence of temperature on the constant current I0 and the influence of temperature on the threshold voltage of a semiconductor device both affect the channel current, and the influence of temperature on the channel current through the constant current I0 is less than the influence of temperature on the channel current through the threshold voltage of a semiconductor device.

[0059] According to some embodiments, the semiconductor device 321 can be matched with the semiconductor device 311. The device parameters of the semiconductor device 321 can be matched with the device parameters of the semiconductor device 311. For example, at least one of the following parameters of the semiconductor device 321 and the semiconductor device 311 is approximately the same or identical: threshold voltage, temperature coefficient of the threshold voltage, channel conduction ability, temperature coefficient of the channel conduction ability, transconductance, size parameter, thermal parameter, or noise parameter, etc. The difference in the device parameters of the semiconductor devices 311 and 321 can include a difference within an allowable range caused by errors. The semiconductor devices 311 and 321 can be fabricated by the same or the same process. For example, the semiconductor devices 311 and 321 can be formed on the same substrate. The semiconductor devices 311 and 321 can include transistors. The semiconductor devices 311 and 321 can include the same type of transistors. For example, the semiconductor devices 311 and 321 can include n-type transistors, or the semiconductor devices 311 and 321 can include p-type transistors. Thus, the correction voltage of the semiconductor device 321 can be used as the correction voltage of the semiconductor device 311, and the control terminals c1 and c2 can be used as correction terminals.

[0060] Figure 4 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown. As Figure 4As shown, according to some embodiments, the third terminal t3 and the second control terminal c2 may be directly connected, for example, by a trace connection. The calibration voltage VT may be directly determined based on the voltage of the third terminal t3. The second control terminal c2 may include a voltage control terminal, and no current or a current less than a threshold value will flow through the second control terminal c2. The threshold value is an error tolerance current value, and the embodiments of the present application do not limit its value, as long as the current can be considered equal to or approximately equal to 0 within the error tolerance range. In this way, the feedback control branch may have a simple structure and control method, and the design, manufacture, and control of the circuit are simplified.

[0061] Figure 5 FIG. shows a schematic diagram of another storage device according to an exemplary embodiment of the present application. As Figure 5 shown, according to some embodiments, the feedback control branch 322 may include a voltage adjustment circuit 3222. The voltage adjustment circuit 3222 may be connected between a constant current and the third terminal t3. A voltage drop may be generated across the two ends of the voltage adjustment circuit 3222. In this way, the voltage of the third terminal t3 and the voltage fed back to the second control terminal c2 may be different, and the voltage of the third terminal t3 coupled to the calibration voltage of the second control terminal c2 may be controlled to be different, so that the change in the calibration voltage caused by environmental factors (such as temperature) will not act on the third terminal t3 in the same way, and the simple association between the calibration voltage and the voltage of the third terminal can be prevented from restricting the voltage value of the third terminal. In this way, it is possible to prevent the voltage of the third terminal t3 of the semiconductor device 321 from being too different from the voltage of the first terminal t1 of the semiconductor device 311 and affecting the calibration effect of the calibration voltage. According to some embodiments, the voltage adjustment circuit 3222 may include a transistor or a resistor; for example, the transistor may include a P-type transistor or an N-type transistor, and the source or drain of the transistor may be coupled to the constant current, the drain or source may be connected to the third terminal t3, and the gate may be coupled to the voltage V3 to drive the transistor to operate.

[0062] Figure 6 FIG. shows a schematic diagram of another storage device according to an exemplary embodiment of the present application. As Figure 6 shown, according to some embodiments, the feedback control branch 322 may include a feedback control circuit 3221. The feedback control circuit 3221 may be coupled to the reference voltage Vr and connected to the third terminal t3. The feedback control circuit 3221 may adjust and output the calibration voltage VT based on the voltage of the third terminal t3 and the reference voltage Vr. The introduction of the feedback control circuit 3221 and the reference voltage can prevent the simple association between the calibration voltage and the voltage of the third terminal from restricting the voltage value of the third terminal. In this way, it is possible to prevent the voltage of the third terminal t3 of the semiconductor device 321 from being too different from the voltage of the first terminal t1 of the semiconductor device 311 and affecting the calibration effect of the calibration voltage.

[0063] According to some embodiments of the present application, the feedback control circuit 3221 may include an operational amplifier. For example, Figure 7 FIG. shows a schematic diagram of a calibration circuit according to an exemplary embodiment of the present application. As Figure 7 shown, the calibration circuit 700 may include a semiconductor device 710 and a feedback control circuit 720, and the feedback control circuit 720 may include an operational amplifier 721. The operational amplifier 721 may include an input terminal in1 and in2 and an output terminal out1. The input terminal in1 may be coupled to a reference voltage Vr, the input terminal in2 may be connected to the third terminal t3 of the semiconductor device 710, and the output terminal out1 may be connected to the second control terminal c2 of the semiconductor device 710. The output terminal out1 may output a calibration voltage VT. The input terminal in1 may include an inverting input terminal, and the input terminal in2 may include a non-inverting input terminal; alternatively, the input terminal in1 may include a non-inverting input terminal, and the input terminal in2 may include an inverting input terminal.

[0064] Based on the characteristics of the operational amplifier, such as virtual short, the voltage value of the input terminal in2 may be determined based on the voltage of the input terminal in1, for example, determined based on the reference voltage Vr. The temperature coefficient of the reference voltage Vr may be relatively low, for example, lower than the voltage temperature coefficient threshold. The voltage of the input terminal in2 may be equal to or close to the voltage of the input terminal in1. The voltage difference between the input terminals in1 and in2 may be less than or equal to a first voltage threshold, and the first voltage threshold is an error tolerance voltage. The embodiments of the present application do not limit its value, as long as it can be considered that the first voltage threshold is equal to or approximately equal to 0 within the error tolerance range. Additionally, based on the characteristics of the operational amplifier, such as virtual open, a current less than the threshold or no current will flow through the input terminal in2. The channel current of the semiconductor device 321 may be equal to or close to a constant current I0. The channel current of the semiconductor device 321 may be determined based on the constant current I0. The description of the threshold is the same as the above embodiments and will not be repeated here.

[0065] Continuing to refer to Figure 3 , according to some embodiments, the semiconductor device 311 may further include a third control terminal c3. The third control terminal c3 may be used as a signal input terminal. The third control terminal c3 may be coupled to an input signal Vin and control the conduction ability of the first channel of the semiconductor device 311 based on the input signal Vin. During reading, the semiconductor device 311 may output the stored weight data in the form of a channel current under the drive of the input signal. During calculation, the semiconductor device 311 may perform calculations based on the stored weight data and the input signal received through the third control terminal c3, and the calculation result is output in the form of a channel current through the joint control of the weight data and the input signal on the channel conduction ability.

[0066] The storage circuit may include multiple semiconductor devices 311. The input signals Vin of different semiconductor devices 311 may be the same or different, which is not limited in this application and is specifically related to the input data corresponding to the service executed by the storage circuit.

[0067] According to some embodiments, the semiconductor device 321 may further include a fourth control terminal c4. The fourth control terminal c4 corresponds to the third control terminal c3. The fourth control terminal c4 may be coupled to the voltage Vinr. The voltage Vinr may be referred to as an input reference voltage, and the fourth control terminal c4 may be referred to as an input reference terminal. The voltage Vinr may be determined based on the voltage of the input signal Vin. The storage circuit includes multiple semiconductor devices 311, and some or all of the input signals Vin of the multiple semiconductor devices may be used to determine the voltage Vinr. For example, the voltage Vinr may be determined based on the maximum voltage, the minimum voltage, or the average value of the maximum voltage and the minimum voltage among the input signals Vin of the multiple semiconductor devices. As another example, the voltage Vinr may be determined based on the average value or the mode value of the input signals Vin of the multiple semiconductor devices. By way of example, the voltage Vinr may be equal to or approximately equal to the maximum voltage, the minimum voltage, or the average value of the maximum voltage and the minimum voltage among the input signals Vin of the multiple semiconductor devices, or may be equal to or approximately equal to the average value or the mode value of the input signals Vin of the multiple semiconductor devices.

[0068] According to some embodiments, the semiconductor device 311 and the semiconductor device 321 may further include more control terminals. For example, please refer to Figure 8 , which shows a schematic diagram of another storage device according to an exemplary embodiment of the present application. As Figure 8As shown, the semiconductor device 311 may include control terminals c1, c3, …, c2m-1, where m is a positive integer. The semiconductor device 321 may include control terminals c2, c4, …, c2n, where n is a positive integer. The control terminals other than the control terminals c1 to c4 may be referred to as reference control terminals. The reference control terminals c2p-1 and c2q may be coupled to the reference voltages V2p-1 and V2q respectively, where p ∈ (2, m], q ∈ (2, n]. The reference voltages V2p-1 and V2q may include fixed bias voltages. The reference control terminals of the semiconductor device 311 may control the conduction ability of the channel of the semiconductor device 311 with a stable reference voltage during calculation or reading, preventing the reference voltage of the reference control terminals from affecting the output result. The reference control terminals of the semiconductor device 321 may control the conduction ability of the channel of the semiconductor device 321 with a stable reference voltage when the correction circuit generates a correction voltage, such that the output correction voltage is not affected by the reference voltage of the reference control terminals. The reference control terminals and reference voltages of the semiconductor devices 311 and 321 may correspond to each other. For example, when p = q, the reference control terminal c2p-1 and the reference control terminal c2q may correspond, and the reference control terminal c2p-1 and the reference control terminal c2q may include the same type of ports. For example, when p = q, the reference voltage V2p-1 and the reference voltage V2q may correspond, and the difference between the reference voltage V2p-1 and the reference voltage V2q may be less than a second voltage threshold, where the second voltage threshold is an error tolerance voltage, and the embodiments of the present application do not limit its value, as long as it can be considered that the second voltage threshold is equal to or approximately equal to 0 within the error tolerance range.

[0069] According to some embodiments, n may be equal to m. Thus, the semiconductor device 311 and the semiconductor device 321 are matched and may include the same type of devices.

[0070] According to some embodiments, n may not be equal to m. Thus, the semiconductor device 311 and the semiconductor device 321 may include different numbers of reference control terminals. In the case where one of the semiconductor device 311 and the semiconductor device 321 includes one or more reference control terminals that do not correspond to the reference control terminals of the other of the semiconductor device 311 and the semiconductor device 321, by controlling the one or more reference control terminals to be coupled to their corresponding reference voltages, the one or more reference control terminals can be prevented from affecting the correction, reading, or calculation. Thus, the semiconductor device 311 and the semiconductor device 321 may be referred to as being controlled and matched. In the case of controlled matching, the correction circuit 320 may still generate a correction voltage for the semiconductor device 311. The semiconductor device 321 being matched with the semiconductor device 311 may include the semiconductor device 321 being controlled and matched with the semiconductor device 311.

[0071] According to some embodiments, the storage circuit 310 may include semiconductor devices 311 arranged in an array. The third control terminal c3 of the semiconductor device 311 may be used as a signal input terminal (e.g., Figure 2 input terminal IN), and the first terminal t1 or the second terminal t2 of the semiconductor device 311 may be used as a signal output terminal (e.g., Figure 2 output terminal OUT). The first control terminal c1 of the semiconductor device 311 may be used as a correction terminal. The horizontal direction and the vertical direction represent the directions in the drawings. The horizontal direction may include the row direction, and the vertical direction may include the column direction, or the vertical direction may include the row direction, and the horizontal direction may include the column direction. The signal input terminals of the semiconductor devices 311 arranged in the horizontal direction may be connected to the same input line, and the signal output terminals of the semiconductor devices 311 arranged in the vertical direction may be connected to the same output line, or the signal input terminals of the semiconductor devices 311 arranged in the vertical direction may be connected to the same input line, and the signal output terminals of the semiconductor devices 311 arranged in the horizontal direction may be connected to the same output line. The semiconductor devices 311 connected to the same input line may be coupled to the same input signal Vin. The semiconductor devices 311 connected to different input lines may be coupled to different input signals Vin. The different input signals Vin may include the same or different signal values, such as the same or different voltage values. The signal input terminals of the semiconductor devices 311 within the storage cell group may be respectively coupled to a plurality of input signals. During calculation, the storage cell group converts the plurality of input signals into a plurality of output signals based on the weight data stored by the semiconductor devices 311 within the storage cell group, and outputs the cumulative signal of the plurality of output signals on the same output line.

[0072] The first control terminals c1 of the semiconductor devices 311 arranged in the horizontal direction may be connected to the same trace, or the first control terminals c1 of the semiconductor devices 311 arranged in the vertical direction may be connected to the same trace, or the first control terminals c1 of the semiconductor devices 311 arranged in a two-dimensional array in the horizontal and vertical directions may be connected to the same trace. The first control terminals connected to the same trace may receive a correction voltage through the same trace, simplifying the manner of applying the correction voltage to a plurality of semiconductor devices.

[0073] According to some embodiments, in addition to being used as a correction terminal, the first control terminal c1 may also have other uses. For example, the first control terminal c1 may also be used as an erase terminal. The connection manner of the first control terminal c1 may be determined according to this other use. In this way, the connection manner of the first control terminal may enable the first control terminal to serve multiple functions.

[0074] Figure 9 A schematic diagram of another storage device according to an exemplary embodiment of the present application is shown. As Figure 9As shown, the storage device 300 may include a storage circuit 310 and a correction circuit 320. The correction circuit 320 may include a plurality of semiconductor devices 321. The plurality of semiconductor devices 321 may be connected in parallel. The second control terminals c2 of the plurality of semiconductor devices 321 may be connected together, and the third terminals t3 of the plurality of semiconductor devices 321 may be connected together. The correction circuit including a plurality of semiconductor devices can reduce the influence of the process error of the semiconductor devices and improve the driving ability of the correction voltage for the subsequent-stage circuit. In addition, the correction circuit including a plurality of semiconductor devices can improve the reliability. Even if some of the plurality of semiconductor devices cannot work properly, the remaining normally working semiconductor devices can still ensure the normal operation of the correction circuit.

[0075] According to some embodiments, the plurality of fourth terminals t4 may be connected together. The plurality of reference control terminals c2q may be connected together, where q ∈ (2, n]. Connecting the corresponding ports can help simplify the wiring and simplify the application manner of the control signal (such as the reference voltage). However, the embodiments are not limited thereto. The plurality of fourth terminals t4 may not be connected together. The plurality of reference control terminals c2q may not be connected together. Not connecting the corresponding ports can flexibly control different ports of the semiconductor devices. In addition, whether the corresponding ports are connected or not may be consistent with the connection relationship of the respective ports of the semiconductor device 311 that matches the semiconductor device 321 in the storage circuit. In this way, the same or similar wiring manner can be adopted in the storage circuit and the correction circuit, and the circuit design can be reused.

[0076] Figure 10 The figure shows a schematic diagram of another storage device according to an exemplary embodiment of the present application. As Figure 10 shown, the storage device 300 may include a storage circuit 310 and a correction circuit 320. The correction circuit 320 may further include a driving circuit 323. The driving circuit 323 may be connected between the second control terminal c2 of the semiconductor device 321 and the first control terminal c1 of the semiconductor device 311, and is configured to increase the output power of the correction voltage VT output by the feedback control branch 322. The output power of the correction voltage VT output by the feedback control branch 322 via the driving circuit 323 is higher than the output power of the correction voltage VT directly output by the feedback control branch 322. The driving circuit 323 may increase the power of the input signal and then output it without changing the voltage of the input signal, that is, without changing the correction voltage VT. The output voltage of the driving circuit 323 may be the same as the input voltage of the driving circuit 323. The output voltage being the same as the input voltage may include: the difference between the input voltage and the output voltage is less than a threshold value, and the threshold value is an error tolerance voltage value. The embodiments of the present application do not limit its value, and as long as it is within the error tolerance range, it can be considered equal to or approximately equal to 0. In this way, the correction voltage can stably correct the influence of environmental factors (such as temperature) on the storage circuit, and can correct a larger number of semiconductor devices / storage units in the storage circuit.

[0077] According to some embodiments, the calibration circuit 320 may include a plurality of semiconductor devices 321, which can improve the driving ability and driving stability of the calibration voltage for the driving circuit 323, so that the driving circuit 323 can more stably increase the driving power of the calibration voltage.

[0078] The semiconductor devices 311, 321, and 710 may include flash memory devices, ferroelectric devices, DRAM devices, transistor devices (such as thin film transistor devices), etc. Thus, the semiconductor devices 311, 321, and 710 may include gates and substrates. The gate or the substrate may control the conduction ability of the channel and may be used as the control terminal of the semiconductor devices 311, 321, and 710.

[0079] For example, Figures 11 to 13 A schematic diagram of various semiconductor devices according to an exemplary embodiment of the present application is shown.

[0080] Referring to Figure 11 , the semiconductor device 1100 may include non-control gates 1101 and 1102 and control gates 1103, 1104, and 1105. The semiconductor device 1100 may include a split-gate floating-gate transistor, such as a triple-gate floating-gate transistor. The semiconductor device 1100 may be used as a memory cell. The control gate 1103 may include a control gate (CG), the control gate 1104 may include a select gate (SG) or a word line (WL), and the control gate 1105 may include an erase gate (EG). According to some embodiments, the semiconductor device 1100 may further include a back control gate, which may include a substrate or a back gate. The non-control gates 1101 and 1102 may include a source and a drain, respectively. The non-control gate 1101 may include a source, the non-control gate 1102 may include a drain, or alternatively, the non-control gate 1102 may include a source, and the non-control gate 1101 may include a drain.

[0081] The semiconductor device 1100 can be used in semiconductor devices 311, 321, and 710. According to some example embodiments, the non-control electrode 1101 can be used as the first terminal t1 and the third terminal t3, and the non-control electrode 1102 can be used as the second terminal t2 and the fourth terminal t4. Alternatively, the non-control electrode 1101 can be used as the second terminal t2 and the fourth terminal t4, and the non-control electrode 1102 can be used as the first terminal t1 and the third terminal t3. According to some example embodiments, the control electrode 1103 can be used as the control terminals c3 and c4, and the control electrode 1104 or 1105 can be used as the control terminals c1 and c2. Thus, the control electrode 1103 (e.g., CG) of the semiconductor device 1100 serves as the signal input terminal of the semiconductor device, and the input signal can be precisely controlled. According to some example embodiments, the control electrode 1103 can be used as the control terminals c1 and c2, and the control electrode 1104 or 1105 can be used as the control terminals c3 and c4. The control electrode or the back control electrode that is not used as the control terminals c1 to c4 can be used as a reference control terminal, such as the control terminals c2p-1 and c2q, where p ∈ (2, m], q ∈ (2, n]. Thus, the control electrode 1103 (e.g., CG) of the semiconductor device 1100 serves as a correction terminal, and the influence of environmental factors (e.g., temperature) on the channel conduction ability can be precisely corrected.

[0082] Referring Figure 12 , the semiconductor device 1200 can include non-control electrodes 1201 and 1202 and control electrodes 1203 and 1204. The semiconductor device 1200 can include a split-gate floating-gate transistor, such as a double-gate floating-gate transistor. The semiconductor device 1200 can be used as a memory cell. For example, the control electrode 1203 can include a control gate (CG), and the control electrode 1204 can include a select gate (SG) or a word line (WL). According to some embodiments, the semiconductor device 1200 can further include a back control electrode, and the back control electrode can include a substrate or a back gate. The non-control electrodes 1201 and 1202 can include a source and a drain, respectively. The non-control electrode 1201 can include a source, and the non-control electrode 1202 can include a drain. Alternatively, the non-control electrode 1202 can include a source, and the non-control electrode 1201 can include a drain.

[0083] The semiconductor device 1200 can be used in semiconductor devices 311, 321, and 710. According to some example embodiments, the non-control electrode 1201 can be used as the first terminal t1 and the third terminal t3, and the non-control electrode 1202 can be used as the second terminal t2 and the fourth terminal t4. Alternatively, the non-control electrode 1201 can be used as the second terminal t2 and the fourth terminal t4, and the non-control electrode 1202 can be used as the first terminal t1 and the third terminal t3. According to some example embodiments, the control electrode 1203 can be used as the control terminals c3 and c4, and the control electrode 1204 can be used as the control terminals c1 and c2. Thus, the control electrode 1203 (e.g., CG) of the semiconductor device 1200 serves as the signal input terminal of the semiconductor device, and the input signal can be precisely controlled. According to some example embodiments, the control electrode 1203 can be used as the control terminals c1 and c2, and the control electrode 1204 can be used as the control terminals c3 and c4. The control electrode or the back control electrode that is not used as the control terminals c1 to c4 can be used as a reference control terminal, such as the control terminals c2p-1 and c2q, where p ∈ (2, m], q ∈ (2, n]. Thus, the control electrode 1203 (e.g., CG) of the semiconductor device 1200 serves as a correction terminal, and the influence of environmental factors (e.g., temperature) on the channel conductivity can be more precisely corrected.

[0084] Referring to Figure 13 , the semiconductor device 1300 can include non-control electrodes 1301 and 1302 and a control electrode 1303. Although Figure 13 it is shown that the semiconductor device 1300 includes a non-floating gate transistor, the embodiments are not limited thereto. The semiconductor device 1300 can include a floating gate transistor, a ferroelectric field effect transistor, a thin film transistor (e.g., IGZO, MoS2, etc.). The semiconductor device 1300 can be used as a memory cell or a part of a memory cell (e.g., used as a read transistor). The control electrode 1303 can include a gate. The semiconductor device 1300 can further include a back control electrode 1304, and the back control electrode 1304 can include a substrate or a back gate. The non-control electrodes 1301 and 1302 can respectively include a source and a drain. The non-control electrode 1301 can include a source, and the non-control electrode 1302 can include a drain. Alternatively, the non-control electrode 1302 can include a source, and the non-control electrode 1301 can include a drain.

[0085] The semiconductor device 1300 can be used in semiconductor devices 311, 321, and 710. According to some example embodiments, the non-control electrode 1301 can be used as the first terminal t1 and the third terminal t3, and the non-control electrode 1302 can be used as the second terminal t2 and the fourth terminal t4. Alternatively, the non-control electrode 1301 can be used as the second terminal t2 and the fourth terminal t4, and the non-control electrode 1302 can be used as the first terminal t1 and the third terminal t3. According to some example embodiments, the back control electrode 1304 can be used as the control terminals c1 and c2, and the control electrode 1303 can be used as the control terminals c2 and c4. In this way, the control electrode 1303 of the semiconductor device 1300 serves as the signal input terminal of the semiconductor device, and the input signal can be precisely controlled. According to some example embodiments, the back control electrode 1304 can be used as the control terminals c3 and c4, and the control electrode 1303 can be used as the control terminals c1 and c2. In this way, the control electrode 1303 of the semiconductor device 1300 serves as the correction terminal, and the influence of environmental factors (such as temperature) can be corrected more precisely.

[0086] Referring to Figure 3 and Figures 11 to 13 , according to some embodiments, in addition to serving as the correction terminal, the first control terminal c1 can also have other uses. For example, when the first control terminal c1 includes the control electrode 1104 or 1105, the first control terminal c1 can also be used as, for example, WL or EG. For example, when it can also be used as EG, the first control terminal c1 can be used as the correction terminal during reading or calculation and as the erasing terminal during erasing. The connection method of the first control terminal c1 can be determined according to this other use. In this way, the connection method of the first control terminal can enable the first control terminal to have multiple functions.

[0087] According to some embodiments, the second control terminal c2 can include a substrate, and the fourth control terminal c4 can include a gate, such as a control electrode. Correspondingly, the first control terminal c1 can include a substrate, and the third control terminal c3 can include a gate. In this way, using the substrate instead of the gate as the correction terminal can avoid the design limitations brought by the multiple uses of the gate, enabling a more flexible selection of the control terminal connection method.

[0088] According to some embodiments, the control terminals c2 and c4 can respectively include a first gate and a second gate, such as the control electrodes 1103 and 1104. Correspondingly, the control terminals c1 and c3 include different gates. In this way, the first control terminal c1 can have multiple functions, improving its utilization rate. At the same time, it is not necessary to divide the substrate, reducing the process complexity.

[0089] Figures 14 to 17 The schematic diagrams of various correction circuits according to the exemplary embodiments of the present application are shown.

[0090] Figure 14 The correction circuit 1400 is shown. Referring to Figure 14, the calibration circuit 1400 may include a semiconductor device 1410 and a feedback control circuit 1420. The semiconductor device 1410 may include non-control gates 1411 and 1412 and control gates 1413, 1414, and 1415. The semiconductor device 1410 may include a split-gate floating-gate transistor, such as a triple-gate floating-gate transistor. The control gate 1413 may include a control gate (CG), the control gate 1414 may include a select gate (SG) or a word line (WL), and the control gate 1415 may include an erase gate (EG). According to some embodiments, the semiconductor device 1410 may further include a back control gate. The feedback control circuit 1420 may include an operational amplifier 1421. The input terminal in2 of the operational amplifier 1421 is coupled to a reference voltage Vr, and the input terminal in1 is connected to the non-control gate 1411 of the semiconductor device 1410. The control gate 1413 of the semiconductor device 1410 may be used as an input reference terminal, the control gate 1414 may be used as a reference control terminal, the control gate 1415 may be used as a calibration terminal, and the non-control gate 1412 may be coupled to, for example, a voltage V2. The output voltage of the output terminal of the operational amplifier 1421 may be used as a calibration voltage for a semiconductor device that matches the semiconductor device 1410 in the memory circuit, such as the semiconductor device 311. The output terminal of the operational amplifier 1421 may be connected to, for example, directly connected to the calibration terminal of the semiconductor device, such as the first control terminal c1 of the semiconductor device 311.

[0091] According to some embodiments, the calibration circuit 1400 may further include a drive circuit 1430. The drive circuit 1430 may receive the output of the operational amplifier 1421. The drive circuit 1430 may boost the power of the input signal and then output it without changing the voltage of the input signal, that is, without changing the calibration voltage VT. The output voltage of the drive circuit 1430 may be the same as the input voltage of the drive circuit 1430. That the output voltage is the same as the input voltage may include: the difference between the input voltage and the output voltage is less than a threshold, and the threshold is an error tolerance voltage value. The embodiments of the present application do not limit its value, as long as it is within the error tolerance range, it can be considered equal to or approximately equal to 0. Thus, the calibration voltage can stably correct the influence of environmental factors (such as temperature) on the memory circuit, and can correct a larger number of semiconductor devices / memory cells in the memory circuit. The output terminal of the drive circuit 323 may be connected to the calibration terminal of the semiconductor device, such as the first control terminal c1 of the semiconductor device 311. The drive circuit 1430 may include an operational amplifier.

[0092] According to some embodiments, referring to Figure 14, the calibration circuit 1400 may include a plurality of semiconductor devices 1410. The plurality of semiconductor devices 1410 may be connected in parallel. The non-control electrodes 1411 of the plurality of semiconductor devices 1410 may be connected to each other and connected to the input terminal of the operational amplifier 1421. Additionally, the non-control electrodes 1411 of the plurality of semiconductor devices 1410 may be coupled to a constant current I0. The control electrodes 1415 of the plurality of semiconductor devices 1410 may be connected to each other and connected to the output terminal of the operational amplifier 1421. In this way, the calibration circuit including a plurality of semiconductor devices can reduce the influence of the process errors of the semiconductor devices and improve the driving ability of the calibration voltage for the subsequent-stage circuit. Additionally, the calibration circuit including a plurality of semiconductor devices can improve the reliability. Even if the plurality of semiconductor devices include semiconductor devices that cannot work properly, the remaining normally working semiconductor devices can still ensure the normal operation of the calibration circuit.

[0093] According to some embodiments, a plurality of non-control electrodes 1412 may be connected to each other. A plurality of control electrodes 1413 may be connected to each other. A plurality of control electrodes 1414 may be connected to each other. Connecting the corresponding control electrodes or non-control electrodes to each other can help simplify the wiring and simplify the application manner of the control signal (such as the reference voltage). However, the embodiments are not limited thereto. A plurality of non-control electrodes 1412 may not be connected to each other. A plurality of control electrodes 1413 may not be connected to each other. A plurality of control electrodes 1414 may not be connected to each other. Not connecting the corresponding control electrodes or non-control electrodes to each other can flexibly control different electrodes of the semiconductor devices. Additionally, whether the corresponding control electrodes or non-control electrodes are connected to each other may be consistent with the connection relationship of the electrodes of the semiconductor devices used as storage units that match the semiconductor devices in the storage circuit. In this way, the same or similar wiring manner can be adopted in the storage circuit and the calibration circuit to reuse the circuit design.

[0094] Additionally, the semiconductor device 1410, the feedback control circuit 1420, and the driving circuit 1430 may refer to the descriptions of the corresponding devices or circuits in other embodiments.

[0095] Figure 15The calibration circuit 1500 is shown. The calibration circuit 1500 may include a semiconductor device 1510 and a feedback control circuit 1520. The semiconductor device 1510 may include non-control gates 1511 and 1512 and control gates 1513, 1514, and 1515. The semiconductor device 1510 may include a split-gate floating-gate transistor, such as a triple-gate floating-gate transistor. The control gate 1513 may include a control gate (CG), the control gate 1514 may include a select gate (SG) or a word line (WL), and the control gate 1515 may include an erase gate (EG). The feedback control circuit 1520 may include an operational amplifier 1521. According to some embodiments, the calibration circuit 1500 may further include a drive circuit 1530. The semiconductor device 1510, the feedback control circuit 1520, and the drive circuit 1530 may be referred to the descriptions of corresponding devices or circuits in other embodiments.

[0096] The calibration circuit 1500 and Figure 14 the same or similar features of the calibration circuit 1400 of Figure 14 may be referred to its related description and will not be elaborated here. The differences between the calibration circuit 1500 and

[0097] Figure 16 The calibration circuit 1600 is shown. The calibration circuit 1600 may include a semiconductor device 1610 and a voltage adjustment circuit 1620. The semiconductor device 1610 may include non-control gates 1611 and 1612 and control gates 1613 and 1614. The semiconductor device 1610 may include a split-gate floating-gate transistor, such as a double-gate floating-gate transistor. The control gate 1613 may include a control gate (CG), and the control gate 1614 may include a select gate (SG) or a word line (WL). The voltage adjustment circuit 1620 may include a transistor or a resistor. The voltage adjustment circuit 1620 may be connected between a constant current I0 and the non-control gate 1611. The constant current I0 may also be connected to the control gate 1614. According to some embodiments, the calibration circuit 1600 may further include a drive circuit 1630. The semiconductor device 1610, the voltage adjustment circuit 1620, and the drive circuit 1630 may be referred to the descriptions of corresponding devices or circuits in other embodiments.

[0098] Figure 17The calibration circuit 1700 is shown. The calibration circuit 1700 may include a semiconductor device 1710 and a feedback control circuit 1720. The semiconductor device 1710 may include non-control electrodes 1711 and 1712, control electrodes 1713, and a back control electrode 1714. The back control electrode 1714 may include a substrate or a back gate. The feedback control circuit 1720 may include an operational amplifier 1721. According to some embodiments, the calibration circuit 1700 may further include a drive circuit 1730. The semiconductor device 1710, the feedback control circuit 1720, and the drive circuit 1730 may be referred to the descriptions of corresponding devices or circuits in other embodiments.

[0099] Figure 18 The schematic diagram of another memory-computation system according to an exemplary embodiment of the present application is shown.

[0100] The memory-computation system 1800 may include any one of the above storage devices 1810 for storing data or performing calculations on data. The memory-computation system 1800 may further include a control circuit 1820 for controlling the working state of the storage device. The working state may include, for example, a programming state, a reading state, a calculation state, an erasing state, etc. The control circuit 1820 may also be used to control the calibration circuit of the storage device 1810 to generate a calibration voltage, thereby correcting the reduction in the reading accuracy and calculation accuracy of the storage device 1810 or the memory-computation system 1800 caused by temperature changes.

[0101] Figure 19 The schematic diagram of an electronic device according to an exemplary embodiment of the present application is shown.

[0102] The electronic device 1900 may include any one of the above memory-computation systems 1910 for processing the data of the electronic device. The electronic device 1900 may further include an input / output device 1920 for receiving user input or outputting the processing result. The present application does not limit the input type and output type. For example, the input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may further include a processor 1930. The processor 1930 may process the data provided to the memory-computation system 1910, or may process the output data of the memory-computation system 1910. The output of the above input / output device 1920 may be based on the output of the processor 1930 or the output of the memory-computation system 1910.

[0103] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include a wearable device. Wearable devices include, for example, but are not limited to: head-mounted devices (such as helmets or hats, etc.), devices that can be worn on the ears (such as headphones), devices that can be worn on the wrists (such as watches), devices that can be worn on other parts (such as electronic necklaces, medical monitoring devices, or glasses, etc.). According to some embodiments, the electronic device may include a portable terminal. For example, the electronic device may include, but is not limited to, mobile phones, general computing devices (such as laptop computers or tablet computers, etc.), personal digital assistants, and so on. According to some embodiments, the electronic device may include other types of end-side devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products, etc. According to some embodiments, the electronic device may also include devices such as servers.

[0104] In the above embodiments, the descriptions of different embodiments have different focuses. For parts that are not described or recorded in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. And the above different embodiments can be freely combined as needed. And with the evolution of technology, the elements described in this application can be replaced by equivalent elements that appear after this application.

Claims

1. A calibration circuit, characterized in that, A first semiconductor device for calibrating a memory circuit, the first semiconductor device including a first terminal, a second terminal, and a first control terminal, a first channel being formed between the first terminal and the second terminal, the first control terminal being configured to control the conductivity of the first channel, the calibration circuit including: A second semiconductor device, matching the first semiconductor device, and including a third terminal, a fourth terminal, and a second control terminal, a second channel being formed between the third terminal and the fourth terminal, the second control terminal being configured to control the conductivity of the second channel, the third terminal being coupled to a constant current; A feedback control branch, connected to the third terminal, outputting a calibration voltage based on the voltage of the third terminal, the second control terminal being coupled to the calibration voltage, the calibration voltage being configured to stabilize the channel current of the second channel, the calibration voltage being for the first control terminal.

2. The calibration circuit according to claim 1, wherein The feedback control branch includes: A feedback control circuit, coupled to a reference voltage and connected to the third terminal, the feedback control circuit being configured to adjust and output the calibration voltage based on the voltage of the third terminal and the reference voltage.

3. The calibration circuit according to claim 2, the feedback control circuit including: An operational amplifier, including a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to the reference voltage, the second input terminal being connected to the third terminal, the output terminal being configured to output the calibration voltage.

4. The calibration circuit according to any one of claims 1 to 3, characterized in that, The first semiconductor device further includes a third control terminal, the third control terminal being configured to be coupled to an input signal and control the conductivity of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal, the fourth control terminal being configured to be coupled to a first voltage.

5. The calibration circuit according to claim 4, wherein The first voltage is determined based on the input signal.

6. The correction circuit according to any one of claims 1 to 5, characterized in that, Including a plurality of second semiconductor devices, the second control terminals of the plurality of second semiconductor devices being connected together, the third terminals of the plurality of second semiconductor devices being connected together.

7. The calibration circuit according to any one of claims 1 to 5, characterized in that, Further includes: A drive circuit, connected between the second control terminal of the second semiconductor device and the first control terminal of the first semiconductor device, for boosting the output power of the calibration voltage output by the feedback control branch.

8. The calibration circuit according to any one of claims 4 to 7, characterized in that, The second semiconductor device includes a transistor; The second control terminal includes a substrate, the fourth control terminal includes a gate; or, the second control terminal includes a first gate, the fourth control terminal includes a second gate.

9. A storage device, characterized in that, Includes: A memory circuit, including a first semiconductor device, the first semiconductor device including a first terminal, a second terminal, and a first control terminal, a first channel being formed between the first terminal and the second terminal, the first control terminal being configured to control the conductivity of the first channel; The calibration circuit according to any one of claims 1 to 8.

10. The memory device according to claim 9, the first semiconductor device further includes a third control terminal, the third control terminal being configured to be coupled to an input signal and control the conductivity of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal, the fourth control terminal being configured to be coupled to a first voltage.

11. The storage device according to claim 10, wherein The memory circuit includes a memory cell group, the memory cell group including a plurality of the first semiconductor devices, In a first semiconductor device within the memory cell group, a third control terminal is respectively coupled to a plurality of input signals, and third terminals are connected to each other and connected to the same output line. The memory cell group is configured to convert the plurality of input signals into a plurality of output signals based on weight data respectively stored in the first semiconductor devices within the memory cell group, and output an accumulated signal of the plurality of output signals on the same output line.

12. A memory - computing system, characterized in that, Comprising: The storage device according to any one of claims 9 to 11.

13. An electronic device, characterized in that, Comprising the memory and computing system according to claim 12.

Images