Dynamic random access memory cell structure and method for manufacturing same

Abstract

The invention provides a dynamic random access memory cell structure and a method for manufacturing the same. The dynamic random access memory cell structure includes a semiconductor substrate having a well region and an original semiconductor surface, an access transistor located in the well region and having a gate structure, a bit line electrically coupled to the access transistor, a storage capacitor electrically coupled to the access transistor, and a word line electrically coupled to the gate structure of the access transistor. An isolation structure within the well and surrounding the access transistor; and a conductive interconnect structure within the isolation structure and electrically connected to the well of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a memory cell structure and a method for manufacturing the same, and more particularly to a dynamic random access memory (DRAM) cell structure having an embedded interconnect structure with a well region for a dynamic random-access memory (DRAM) and a method for manufacturing the same. Background Art

[0002] Each DRAM cell includes an access transistor and a storage capacitor. The gate of the access transistor is electrically coupled to a word line (WL), and a sense amplifier is electrically coupled to the access transistor through a bit line (BL). The DRAM cell uses the access transistor as a switch to control the storage of charge from the bit line (BL) to the storage capacitor in the WRITE mode or to control the transfer of charge to the bit line in the READ mode. Therefore, the access transistor needs to be well controlled to provide a stable switch in the write / read mode, and also needs to have a low leakage current when the access transistor is in the off state to avoid the loss of charge in the storage capacitor. Thus, the applied voltage on the access transistor should meet the design level and is not likely to be affected by the parasitic resistance in the interconnect structure.

[0003] Examples of the voltage applied to the access transistor are listed in Table 1. As the control gate of the access transistor, the WL (word line) can be set to 2.8V to turn on the device and can be set to -0.2V to turn off the device. As the drain side of the access transistor, the BL (bit line) can be set to 1.0V to write charge into the storage capacitor to reach the "High" state, and can be set to 0V to discharge the storage capacitor for the "Low" state. When the DRAM cell is in the standby mode (not operating), the BL (bit line) is maintained in the "Equalization" state, which is between the "High" state and the "Low" state. The well region where the access transistor is located cannot be floating. The well region needs to be connected to a voltage level to ensure that the turn-on and turn-off of the device can be well controlled and the leakage current of the device can be well controlled to avoid the loss of stored charge.

[0004] [Table 1]

[0005]

[0006]

[0007] FIG. 1a shows a conventional DRAM cell structure having a metal contact component at the boundary of a memory cell array. FIG. 1b is a schematic top view showing the conventional DRAM cell structure 1. FIG. 1c is a schematic cross-sectional view of the conventional DRAM cell structure 1 taken along the section line AA' of FIG. 1b. The conventional DRAM cell structure 1 includes a substrate 2, three sets of active regions 4 in the substrate 2, two isolation structures 6 in the substrate 2, three sets of word lines 7S in the substrate 2, a plurality of bit lines 9 on the substrate 2, and a plurality of bit line contact components 8 on the substrate 2. The semiconductor substrate 2 has a well region 2W. Each set of active regions 4 includes a plurality of active regions AA arranged along a first direction D1 and separated from each other. The plurality of active regions AA are in the well region 2W of the semiconductor substrate 2. A plurality of access transistors of the DRAM cell structure 1 are formed in the plurality of active regions AA. The isolation structures 6 are located between two sets of active regions 4 and within the well region 2W. Each set of word lines 7S includes a pair of word lines 7. The plurality of word lines 7 are arranged along a second direction D2, and the second direction D2 is perpendicular to the first direction D1. The plurality of word lines 7 extend across the plurality of active regions AA. The plurality of bit lines 9 are arranged along the first direction D1. The plurality of bit lines 9 extend across the plurality of sets of active regions 4 and the plurality of sets of word lines 7S. The plurality of bit line contact components 8 are located at the intersections of the plurality of active regions AA and the plurality of bit lines 9. The plurality of isolation structures 6 and the plurality of word lines 7 may be located below the original semiconductor surface of the substrate 2 in a third direction D3, and the third direction D3 is perpendicular to the first direction D1 and the second direction D2. The plurality of isolation structures 6 and the plurality of word lines 7 may be embedded in the substrate 2. In the conventional DRAM cell structure, the well region where the access transistor is located is connected to a voltage source through a metal contact component, and the metal contact component is at the boundary of the memory cell array or at the boundary of the memory cell array block, and the voltage from the voltage source is directly distributed to each memory cell through the well region.

[0008] However, in the conventional DRAM cell structure, the resistance of such an electrical connection through the well region (made of a lower doped semiconductor) is usually high because the path of such an electrical connection is long and the doping concentration of the well region is low. Once the doping concentration of the well region, the size of the DRAM cell structure, or the DRAM cell array block changes, the performance of the access transistor may be affected. In addition, since there are many components above the well region, a large number of metal contact components for the DRAM cell array block must be provided, as shown in FIG. 2. SUMMARY OF THE INVENTION

[0009] Embodiments of the present invention provide a DRAM cell structure. The DRAM cell structure includes a semiconductor substrate having a well region and an original semiconductor surface, an access transistor located in the well region and having a gate structure, a bit line electrically coupled to the access transistor, a storage capacitor electrically coupled to the access transistor, a word line electrically coupled to the gate structure of the access transistor, an isolation structure in the well region and surrounding the access transistor, and a conductive interconnect structure located in the isolation structure and electrically connected to the well region of the semiconductor substrate.

[0010] According to one aspect of the present invention, a bottom surface of the conductive interconnect structure contacts the well region of the semiconductor substrate.

[0011] According to one aspect of the present invention, a bottom surface of the conductive interconnect structure is lower than a bottom surface of the gate structure.

[0012] According to one aspect of the present invention, an upper surface of the conductive interconnect structure is covered by the isolation structure and is lower than the original semiconductor surface of the semiconductor substrate.

[0013] According to one aspect of the present invention, an upper surface of the conductive interconnect structure is lower than a bottom surface of the gate structure.

[0014] According to one aspect of the present invention, the DRAM cell structure further includes a trench in the semiconductor substrate. The isolation structure and the conductive interconnect structure are in the trench.

[0015] According to one aspect of the present invention, the word line and the conductive interconnect structure extend along a first direction, and the bit line extends along a second direction, where the first direction is different from the second direction.

[0016] According to one aspect of the present invention, the conductive interconnect structure has a first sidewall and a second sidewall opposite to the first sidewall, and both the first sidewall and the second sidewall are covered by the isolation structure.

[0017] According to one aspect of the present invention, the conductive interconnect structure extends to a position close to the boundary of the well region.

[0018] According to one aspect of the present invention, the semiconductor substrate further includes a memory cell array block (cell array block) accommodating the access transistor, and the conductive interconnect structure extends to a position close to the boundary of the memory cell array block.

[0019] According to one aspect of the present invention, the DRAM cell structure further includes a metal contact component (metal contact) close to the boundary of the memory cell array block. The metal contact component is electrically connected to the conductive interconnect structure.

[0020] According to one aspect of the present invention, the conductive interconnect structure includes highly doped silicon, tungsten, titanium nitride, or a combination thereof.

[0021] Embodiments of the present invention provide a DRAM cell structure. The DRAM cell structure includes a semiconductor substrate having a well region and an original semiconductor surface, a first set of active regions within the well region, a second set of active regions within the well region, a first word line extending across the first set of active regions, a second word line extending across the second set of active regions, an isolation structure between the first set of active regions and the second set of active regions, and a conductive interconnect structure located within the isolation structure and electrically connected to the well region.

[0022] According to one aspect of the present invention, the first word line, the second word line, and the conductive interconnect structure extend along a first direction.

[0023] According to one aspect of the present invention, a bottom surface of the conductive interconnect structure contacts the well region of the semiconductor substrate.

[0024] According to one aspect of the present invention, the semiconductor substrate further includes a memory cell array block accommodating the first set of active regions and the second set of active regions, and the conductive interconnect structure extends to a position close to a boundary of the memory cell array block.

[0025] According to one aspect of the present invention, the DRAM cell structure further includes a metal contact component outside a boundary of the memory cell array block. The metal contact component is electrically connected to the conductive interconnect structure.

[0026] According to one aspect of the present invention, an upper surface of the conductive interconnect structure is covered by the isolation structure.

[0027] Embodiments of the present invention provide a method for manufacturing a DRAM cell structure. The method includes: providing a semiconductor substrate having an original semiconductor surface; defining active regions; forming trenches in the semiconductor substrate and near the active regions; forming an isolation structure and a conductive interconnect structure in the trenches, wherein the conductive interconnect structure is surrounded by the isolation structure; and forming a well region accommodating the active regions. A bottom surface of the conductive interconnect structure contacts the well region of the semiconductor substrate. The conductive interconnect structure extends along a first direction and is remote from the active regions.

[0028] According to one aspect of the present invention, forming the isolation structure and the conductive interconnect structure in the trenches includes: forming a first dielectric material covering sidewalls of the trenches; forming the conductive interconnect structure surrounded by the first dielectric material; and forming a second dielectric material on an upper surface of the conductive interconnect structure, wherein the first dielectric material and the second dielectric material form the isolation structure.

[0029] For a better understanding of the above and other aspects of the present invention, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0030] FIG. 1a shows a conventional DRAM cell structure having a metal contact component at a memory cell array boundary;

[0031] FIG. 1b is a schematic top view showing a conventional DRAM cell structure;

[0032] FIG. 1c is a schematic cross-sectional view of the conventional DRAM cell structure taken along the section line AA' of FIG. 1b;

[0033] FIG. 2 shows a conventional configuration of a metal contact component for a DRAM cell array block;

[0034] Figure 3 is a circuit diagram showing a DRAM cell structure according to an embodiment of the present invention;

[0035] Figure 4 is a schematic top view showing a DRAM cell structure according to an embodiment of the present invention;

[0036] Figure 5 is along Figure 4 The schematic cross-sectional view of the DRAM cell structure drawn along the section line BB';

[0037] Figure 6 is a schematic cross-sectional view showing a DRAM cell structure according to another embodiment of the present invention;

[0038] Figure 6a is a schematic cross-sectional view showing a DRAM cell structure according to still another embodiment of the present invention;

[0039] Figure 7 is a configuration of a conductive interconnect structure for a DRAM cell array block according to some embodiments of the present invention;

[0040] Figure 8 is a configuration of a conductive interconnect structure for a DRAM cell array block according to some embodiments of the present invention;

[0041] Figures 9 to 19 is a schematic cross-sectional view showing multiple stages in a method for manufacturing a DRAM cell structure according to an embodiment of the present invention; and

[0042] Figures 20 to 26 is a schematic cross-sectional view showing multiple stages in a method for manufacturing a DRAM cell structure according to another embodiment of the present invention.

[0043] Reference numerals:

[0044] 1, 10, 20, 30, 40: DRAM cell structure

[0045] 2: Substrate

[0046] 2W, 22W, 114: Well region

[0047] 4: A set of active regions

[0048] 6: Isolation structure

[0049] 7, 17, 27: Word lines

[0050] 7S: A set of word lines

[0051] 8, 28: Bit line contact components

[0052] 9, 19, 29: Bit lines

[0053] 11: Access transistor

[0054] 13: Storage capacitor

[0055] 15: Conductive interconnect structure

[0056] 22: Semiconductor substrate

[0057] 22AB: DRAM cell array block

[0058] 22U: Original semiconductor surface

[0059] 24-1: The first set of active regions

[0060] 24-2: The second set of active regions

[0061] 24-3: The third set of active regions

[0062] 25-1, 35-1: The first conductive interconnect structure

[0063] 25-2, 35-2: The second conductive interconnect structure

[0064] 26-1: The first isolation structure

[0065] 26-2: The second isolation structure

[0066] 27-1: The first set of word lines

[0067] 27-2: The second set of word lines

[0068] 27-3: The third set of word lines

[0069] 32: Dielectric part

[0070] 34: Dielectric barrier layer

[0071] 36: Storage node contact component

[0072] 38: Dielectric film

[0073] 100: Metal contact component

[0074] 111: Gate structure

[0075] 112: Source structure

[0076] 113: Drain structure

[0077] 271: Conductive part

[0078] 272: Conductive layer

[0079] 273: Gate dielectric layer

[0080] 274: Dielectric capping layer

[0081] 901: Pad oxide layer

[0082] 902: Pad nitride layer

[0083] 1003: Photoresist layer

[0084] 1004,1004A: Trench

[0085] 1205,2005,2206: Dielectric material

[0086] 1506,1506A: SOD film

[0087] 1507,2207: HDP oxide film

[0088] 1907,2607: Gate dielectric film

[0089] 2206A: First dielectric part

[0090] 2206B: Second dielectric part

[0091] 2206C: Third dielectric part

[0092] AA,AA1,AA2,AA3: Active region

[0093] AA’,BB’: Hatch line

[0094] BS1,BS2: Bottom surface

[0095] D1: First direction

[0096] D2: Second direction

[0097] D3: Third direction

[0098] S1,S2,S3,S4: Sidewall Detailed implementation mode

[0099] Various embodiments will now be described more fully with reference to the accompanying drawings, which are provided for purposes of illustration and not limitation. For clarity, components may not be drawn to scale. In addition, some components and / or component symbols may be omitted in certain drawings. It is contemplated that components and features of one embodiment may be advantageously incorporated into another embodiment without further recitation. In the following methods for manufacturing semiconductor devices, one or more additional operations may exist between the operations described, and the order of operations may be varied. Like / similar component symbols are used in the drawings to denote like / similar components.

[0100] The ordinal numbers used in the specification and claims to modify components, such as "first", "second", etc., do not imply and represent a specific position, or arrangement order, or manufacturing order in the structure. These ordinal numbers are only used to clearly distinguish multiple components with the same name. The spatially relative terms used in the specification and claims, such as "on", "above", "on the", "higher than", "top", "under", "below", "under the", "lower than", "bottom", etc., are used to describe the relative spatial or positional relationship of one component to another in the drawings, and unless otherwise specified, these spatial or positional relationships may be direct or indirect (there may or may not be other components disposed between the two components). The spatially relative terms may cover structures shown in other orientations and are not limited to the orientations shown in the drawings. The structure may be flipped or rotated at various angles, and the spatially relative descriptions used herein may be interpreted accordingly. The singular forms "a" and "the" used in the specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. The "and / or" used in the specification and claims includes any combination and all combinations of one or more of the listed items.

[0101] In addition, the terms "electrically connected" and "electrically coupled" in the specification and the claims may mean that multiple components form an ohmic contact, or may mean that current flows between multiple components, or may mean that multiple components have an operational association. The operational association may be, for example, one component driving another component, but current may not directly flow between the two components. The term "deposition" in the specification and the appended claims includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and epitaxial growth. Those of ordinary skill in the art to which the present invention pertains can select a suitable technique for forming the material according to the type of material to be formed. The terms "etching" and "etch-back" in the specification and the appended claims include, but are not limited to, dry etching and wet etching. The term "polishing process" in the specification and the appended claims includes, but is not limited to, chemical-mechanical planarization (CMP) and ion milling. The terms "etching", "etch-back", and "polishing process" in the specification and the appended claims may replace each other, and those of ordinary skill in the art to which the present invention pertains can select a suitable removal technique according to the structure and material.

[0102] Please refer to Figure 3 。 Figure 3 is a circuit diagram showing a DRAM cell structure 10 according to an embodiment of the present invention. The DRAM cell structure 10 includes an access transistor 11, a storage capacitor 13, a conductive interconnect structure 15, a word line 17, and a bit line 19. The access transistor 11 includes a gate structure 111, a source structure 112, and a drain structure 113. The access transistor 11 is located in a well region 114. The word line 17 is electrically coupled to the gate structure 111 of the access transistor 11. The bit line 19 is electrically coupled to the drain structure 113 of the access transistor 11. The conductive interconnect structure 15 is electrically coupled to the well region 114. The storage capacitor 13 is electrically coupled to the source structure 112 of the access transistor 11. The storage capacitor 13 may be located above the access transistor 11.

[0103] Please refer to Figure 4 and Figure 5 。 Figure 4 is a schematic top view showing a DRAM cell structure 20 according to an embodiment of the present invention. Figure 5 is a schematic cross-sectional view of the DRAM cell structure 20 taken along the Figure 4 section line BB'. For clarity, Figure 4 and Figure 5 the storage capacitor and the access transistor of the DRAM cell structure 20 are omitted; Figure 3The electrical connections between the multiple components of the DRAM cell structure 10 shown are also applicable to Figure 4 and Figure 5 the DRAM cell structure 20 shown. The number of components of the DRAM cell structure 20 is not limited to Figure 4 and Figure 5 the form shown. The DRAM cell structure 20 includes a semiconductor substrate 22, a first group of active regions 24-1, a second group of active regions 24-2, a third group of active regions 24-3, a first conductive interconnect structure 25-1, a second conductive interconnect structure 25-2, a first isolation structure 26-1, a second isolation structure 26-2, a first group of word lines 27-1, a second group of word lines 27-2, a third group of word lines 27-3, and a plurality of bit lines 29. The semiconductor substrate 22 has a well region 22W and an original semiconductor surface 22U.

[0104] The first group of active regions 24-1, the second group of active regions 24-2, and the third group of active regions 24-3 are within the well region 22W of the semiconductor substrate 22. The first group of active regions 24-1 includes a plurality of active regions AA1 arranged along a first direction D1 and separated from each other. The second group of active regions 24-2 includes a plurality of active regions AA2 arranged along the first direction D1 and separated from each other. The third group of active regions 24-3 includes a plurality of active regions AA3 arranged along the first direction D1 and separated from each other. The configuration of the plurality of active regions AA1 of the first group of active regions 24-1 may be symmetric to the configuration of the plurality of active regions AA2 of the second group of active regions 24-2. The configuration of the plurality of active regions AA1 of the first group of active regions 24-1 and the configuration of the plurality of active regions AA2 of the second group of active regions 24-2 may be mirror images of each other. The configuration of the plurality of active regions AA2 of the second group of active regions 24-2 may be symmetric to the configuration of the plurality of active regions AA3 of the third group of active regions 24-3. The configuration of the plurality of active regions AA2 of the second group of active regions 24-2 and the configuration of the plurality of active regions AA3 of the third group of active regions 24-3 may be mirror images of each other. In other embodiments, the configuration of the plurality of active regions AA1 of the first group of active regions 24-1, the configuration of the plurality of active regions AA2 of the second group of active regions 24-2, and the configuration of the plurality of active regions AA3 of the third group of active regions 24-3 may be the same as each other. The shapes of the plurality of active regions AA1~AA3 are not limited to Figure 4 the form shown. The first group of active regions 24-1, the second group of active regions 24-2, and the third group of active regions 24-3 are arranged along a second direction D2. The second direction D2 is different from the first direction D1. The second direction D2 may be perpendicular to the first direction D1. A plurality of access transistors of the DRAM cell structure 20 are formed in the plurality of active regions AA1~AA3. The access transistors of the DRAM cell structure 20 are located within the well region 22W.

[0105] The first conductive interconnect structure 25-1, the second conductive interconnect structure 25-2, the first isolation structure 26-1, and the second isolation structure 26-2 are located in the semiconductor substrate 22. The first conductive interconnect structure 25-1, the second conductive interconnect structure 25-2, the first isolation structure 26-1, and the second isolation structure 26-2 may extend along a first direction D1. As Figure 5 shown, the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 may be completely embedded in the semiconductor substrate 22. The first conductive interconnect structure 25-1 may be located within the first isolation structure 26-1. The second conductive interconnect structure 25-2 may be located within the second isolation structure 26-2. As Figure 5 shown, the first conductive interconnect structure 25-1 may be embedded or buried in the first isolation structure 26-1, and the second conductive interconnect structure 25-2 may be embedded or buried in the second isolation structure 26-2. The first isolation structure 26-1, the second isolation structure 26-2, the first conductive interconnect structure 25-1, and the second conductive interconnect structure 25-2 may be below the original semiconductor surface 22U of the semiconductor substrate 22 in a third direction D3. The first direction D1, the second direction D2, and the third direction D3 may be perpendicular to each other. The upper surfaces of the first isolation structure 26-1, the second isolation structure 26-2, the first conductive interconnect structure 25-1, and the second conductive interconnect structure 25-2 may be coplanar with the original semiconductor surface 22U of the semiconductor substrate 22. The first isolation structure 26-1 is located on the sidewalls S1 and S2 of the first conductive interconnect structure 25-1. The sidewall S2 of the first conductive interconnect structure 25-1 is relative to the sidewall S1 of the first conductive interconnect structure 25-1. The sidewalls S1 and S2 of the first conductive interconnect structure 25-1 may be at least partially covered or completely covered by the first isolation structure 26-1. The first isolation structure 26-1 may isolate the sidewalls S1 and S2 of the first conductive interconnect structure 25-1 from the semiconductor substrate 22. The second isolation structure 26-2 is located on the sidewalls S3 and S4 of the second conductive interconnect structure 25-2. The sidewall S4 of the second conductive interconnect structure 25-2 is relative to the sidewall S3 of the second conductive interconnect structure 25-2. The sidewalls S3 and S4 of the second conductive interconnect structure 25-2 may be at least partially covered or completely covered by the second isolation structure 26-2. The second isolation structure 26-2 may isolate the sidewalls S3 and S4 of the second conductive interconnect structure 25-2 from the semiconductor substrate 22.

[0106] The bottom surface BS1 of the first conductive interconnect structure 25-1 contacts the well region 22W of the semiconductor substrate 22. The bottom surface BS2 of the second conductive interconnect structure 25-2 contacts the well region 22W of the semiconductor substrate 22. The bottom surface BS1 of the first conductive interconnect structure 25-1 and the bottom surface BS2 of the second conductive interconnect structure 25-2 can be lower than the bottom surface of the word line 27 in the third direction D3. The bottom surface of the word line 27 in the active region can be understood as the bottom surface of the gate structure of the access transistor. The first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 are electrically connected to the well region 22W of the semiconductor substrate 22. The first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 extend to a position close to the boundary of the well region. A bias voltage can be applied to the well region 22W through the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2. The first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 will be connected out at the memory cell array boundary.

[0107] A first conductive interconnect structure 25-1 and a first isolation structure 26-1 are between a first group of active regions 24-1 and a second group of active regions 24-2. A second conductive interconnect structure 25-2 and a second isolation structure 26-2 are between the second group of active regions 24-2 and a third group of active regions 24-3. The first isolation structure 26-1 can separate the first group of active regions 24-1 and the second group of active regions 24-2 or can electrically isolate the first group of active regions 24-1 from the second group of active regions 24-2. The second isolation structure 26-2 can separate the second group of active regions 24-2 and the third group of active regions 24-3 or can electrically isolate the second group of active regions 24-2 from the third group of active regions 24-3. The semiconductor substrate 22 can comprise or be made of semiconductor material, such as silicon. The first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 can comprise conductive material, such as highly doped semiconductor material and / or metal. In one embodiment, the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 comprise highly doped silicon, tungsten (W), titanium nitride (TiN), or a combination thereof, or the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 are made of highly doped silicon, tungsten (W), titanium nitride (TiN), or a combination thereof. The well region 22W of the semiconductor substrate 22 is a doped region. The doping type of the doped region (well region 22W) of the semiconductor substrate 22, the doping type of the first conductive interconnect structure 25-1, and the doping type of the second conductive interconnect structure 25-2 can be the same as each other. For example, the doped region (well region 22W) of the semiconductor substrate 22 has P-type doping, and the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 comprise P+ polysilicon or P+ selective epitaxial growth silicon or are made of P+ polysilicon or P+ selective epitaxial growth silicon. The first isolation structure 26-1 and the second isolation structure 26-2 can comprise dielectric material, such as spin-on dielectric (SOD) material.

[0108] The first set of character lines 27-1, the second set of character lines 27-2, and the third set of character lines 27-3 are located in the semiconductor substrate 22. The first set of character lines 27-1, the second set of character lines 27-2, and the third set of character lines 27-3 may be embedded in the semiconductor substrate 22. The first set of character lines 27-1, the second set of character lines 27-2, and the third set of character lines 27-3 may be below the original semiconductor surface 22U of the semiconductor substrate 22 in the third direction D3. The first set of character lines 27-1 extends across the first set of active regions 24-1. The second set of character lines 27-2 extends across the second set of active regions 24-2. The third set of character lines 27-3 extends across the third set of active regions 24-3. The first conductive interconnect structure 25-1 and the first isolation structure 26-1 are between the first set of character lines 27-1 and the second set of character lines 27-2. The second conductive interconnect structure 25-2 and the second isolation structure 26-2 are between the second set of character lines 27-2 and the third set of character lines 27-3. The first set of character lines 27-1 includes two character lines 27 extending along the first direction D1. The second set of character lines 27-2 includes two character lines 27 extending along the first direction D1. The third set of character lines 27-3 includes two character lines 27 extending along the first direction D1. The plurality of character lines 27 may be separated from each other. The character line 27 includes a conductive portion 271, a conductive layer 272, a gate dielectric layer 273, and a dielectric capping layer 274. The conductive layer 272 may be on the sidewalls and the bottom surface of the conductive portion 271. The conductive portion 271 may be surrounded by the conductive layer 272. The conductive layer 272 may be between the conductive portion 271 and the gate dielectric layer 273. The gate dielectric layer 273 may be on the sidewalls and the bottom surface of the conductive layer 272. The conductive portion 271 and the conductive layer 272 may be surrounded by the gate dielectric layer 273. The dielectric capping layer 274 may be on the upper surface of the conductive portion 271, the upper surface of the conductive layer 272, and the upper surface of the gate dielectric layer 273. The gate dielectric layer 273 and the dielectric capping layer 274 may contact the semiconductor substrate 22. The conductive portion 271 may include a conductive material, such as tungsten (W). The conductive layer 272 may include a conductive material, such as titanium nitride (TiN). The gate dielectric layer 273 may include a dielectric material, such as an oxide. The dielectric capping layer 274 may include a dielectric material, such as a nitride. In one embodiment, the dielectric capping layer 274 includes silicon nitride.

[0109] A plurality of bit lines 29 are located on the semiconductor substrate 22. The plurality of bit lines 29 can be above the original semiconductor surface 22U of the semiconductor substrate 22 in the third direction D3. The plurality of bit lines 29 can be arranged along the first direction D1 and can be separated from each other. Each bit line 29 can extend along the second direction D2. The plurality of bit lines 29 extend across the first group of active regions 24-1, the second group of active regions 24-2, the third group of active regions 24-3, the first conductive interconnect structure 25-1, and the second conductive interconnect structure 25-2. The bit lines 29 can include a conductive material, such as a metal or a metal compound. The bit lines 29 can include a combination of a plurality of conductive materials. In one embodiment, the bit lines 29 include tungsten (W), tungsten silicide (WSi x ), titanium nitride (TiN), and titanium (Ti). The DRAM cell structure 20 further includes a plurality of bit line contact components 28 located at the intersections of the plurality of active regions AA1, AA2, and AA3 and the plurality of bit lines 29. The plurality of bit line contact components 28 can be between the plurality of bit lines 29 and the semiconductor substrate 22 and above the original semiconductor surface 22U of the semiconductor substrate 22. The bit line contact components 28 can include a conductive material, such as polysilicon. Each bit line 29 can be electrically coupled to a corresponding doped region (not shown in the figure) through the bit line contact component 28, and the doped region can be between two word lines 27 in a group of word lines (e.g., the first group of word lines 27-1 or the second group of word lines 27-2 or the third group of word lines 27-3). The shape of the bit line contact component 28 is not limited to Figure 4 the aspect shown.

[0110] The DRAM cell structure 20 may further include a dielectric portion 32, a dielectric barrier layer 34, a storage node contact component 36, and a dielectric film 38. The dielectric portion 32 may cover the bit line contact component 28 and the bit line 29. The dielectric portion 32 may be above the original semiconductor surface 22U of the semiconductor substrate 22. The dielectric portion 32 may contact the dielectric covering layer 274 of the word line 27. The dielectric portion 32 may serve as a hard mask. The dielectric portion 32 may include a dielectric material, such as nitride. In one embodiment, the dielectric portion 32 includes silicon nitride. The dielectric barrier layer 34 may be on the outer surface of the dielectric portion 32. The dielectric barrier layer 34 may be above the original semiconductor surface 22U of the semiconductor substrate 22. The dielectric barrier layer 34 may contact the dielectric covering layer 274 of the word line 27. The dielectric barrier layer 34 may include a dielectric material, such as nitride or oxynitride. In one embodiment, the dielectric barrier layer 34 includes silicon nitride or silicon oxynitride. The storage node contact component 36 may be on the outer surface of the dielectric barrier layer 34. The dielectric barrier layer 34 may be between the dielectric portion 32 and the storage node contact component 36. The storage node contact component 36 may be above the original semiconductor surface 22U of the semiconductor substrate 22. The storage capacitor of the DRAM cell structure 20 is electrically coupled to the source structure of the access transistor of the DRAM cell structure 20 through the storage node contact component 36. The storage node contact component 36 may be understood as a capacitor contact component. The storage node contact component 36 may include a conductive material, such as polysilicon. The dielectric film 38 may be above the original semiconductor surface 22U of the semiconductor substrate 22. The dielectric film 38 may be on the outer surface of the storage node contact component 36. The storage node contact component 36 may be between the dielectric barrier layer 34 and the dielectric film 38. The dielectric film 38 may be between the first group of word lines 27-1 and the second group of word lines 27-2, and may be between the second group of word lines 27-2 and the third group of word lines 27-3. The dielectric film 38 may be located on the first isolation structure 26-1 and the second isolation structure 26-2. The isolation film 38 may contact the first isolation structure 26-1 and the second isolation structure 26-2. The dielectric film 38 may contact the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2. The dielectric film 38 may include a dielectric material, such as nitride. In one embodiment, the dielectric film 38 includes silicon nitride. The material of the dielectric film 38 may be different from the materials of the first isolation structure 26-1 and the second isolation structure 26-2.

[0111] Please refer to Figure 6 。 Figure 6 is a schematic cross-sectional view showing a DRAM cell structure 30 according to another embodiment of the present invention. Figure 6 The DRAM cell structure 30 of Figure 5The DRAM cell structure 20 is different in that the conductive interconnect structure has a different size and / or configuration relative to the isolation structure. The DRAM cell structure 30 includes a first conductive interconnect structure 35-1 in a first isolation structure 26-1 and a second conductive interconnect structure 35-2 in a second isolation structure 26-2. The first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 are located in the semiconductor substrate 22 and can extend along a first direction D1. The first conductive interconnect structure 35-1 can be located within the first isolation structure 26-1. The second conductive interconnect structure 35-2 can be located within the second isolation structure 26-2. The first conductive interconnect structure 35-1 can be embedded or buried in the first isolation structure 26-1, and the second conductive interconnect structure 35-2 can be embedded or buried in the second isolation structure 26-2. The first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 can be below the original semiconductor surface 22U of the semiconductor substrate 22 in a third direction D3. The upper surface of the first conductive interconnect structure 35-1 is covered by the first isolation structure 26-1 and is lower than the original semiconductor surface 22U of the semiconductor substrate 22. The upper surface of the second conductive interconnect structure 35-2 is covered by the second isolation structure 26-2 and is lower than the original semiconductor surface 22U of the semiconductor substrate 22. The first isolation structure 26-1 can separate the first conductive interconnect structure 35-1 from the dielectric film 38. The second isolation structure 26-2 can separate the second conductive interconnect structure 35-2 from the dielectric film 38. The first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 are electrically connected to the well region 22W of the semiconductor substrate 22. The first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 extend to a position close to the boundary of the well region. The materials of the first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 can be the same as those of the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2. The size of the first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 in the third direction D3 can be smaller than the size of the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 in the third direction D3. By the size and / or configuration of the first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2, the coupling effect between the conductive interconnect structure and the word line can be reduced.

[0112] The upper surface of the conductive interconnect structure according to the present invention can be coplanar with the original semiconductor surface 22U of the semiconductor substrate 22 (as Figure 5 shown), or can be lower than the original semiconductor surface 22U of the semiconductor substrate 22 and higher than the bottom surface of the gate structure (as Figure 6 shown), or can be coplanar with the bottom surface of the gate structure, or can be lower than the bottom surface of the gate structure (as Figure 6a shown). In Figure 6aIn the DRAM cell structure 40, the upper surface of the first conductive interconnect structure 35-1 is covered by the first isolation structure 26-1 and is lower than the bottom surface of the gate structure (the bottom surface of the word line 27), and the upper surface of the second conductive interconnect structure 35-2 is covered by the second isolation structure 26-2 and is lower than the bottom surface of the gate structure (the bottom surface of the word line 27).

[0113] The present invention uses buried / embedded metal or highly doped silicon as the conductive interconnect structures (such as the first conductive interconnect structure 25-1, the second conductive interconnect structure 25-2, the first conductive interconnect structure 35-1, and the second conductive interconnect structure 35-2) for electrically connecting the well regions, so as to obtain a firm connection with each memory cell and have an effective low resistance, such that the performance of the access transistor will not be affected by the well region doping concentration, the DRAM cell structure, and the DRAM cell array size changes at all.

[0114] In one embodiment, the semiconductor substrate 22 further includes one or more DRAM cell array blocks 22AB. The DRAM cell array block 22AB houses a plurality of access transistors, and the conductive interconnect structures of the present invention can extend to a position close to the boundary of the DRAM cell array block 22AB; the DRAM cell structure may further include one or more metal contact components 100 that are electrically connected to the conductive interconnect structures, as Figure 7 shown in Figure 8 FIG. Figure 7 FIG. shows a configuration of a plurality of conductive interconnect structures for the DRAM cell array block 22AB according to some embodiments of the present invention. Figure 8 FIG. shows a configuration of a plurality of conductive interconnect structures for the DRAM cell array block 22AB according to some embodiments of the present invention. The DRAM cell array block 22AB houses a plurality of access transistors of the DRAM cell structure. Compared with the conventional configuration of the metal contact components shown in FIG. 2, the conductive interconnect structures according to the present invention (such as the first conductive interconnect structure 25-1, the second conductive interconnect structure 25-2, the first conductive interconnect structure 35-1, and the second conductive interconnect structure 35-2) can be flexibly configured on one side of the DRAM cell array block 22AB (as Figure 7 shown in Figure 8 FIG. Figure 8(as shown), the number of metal contact components 100 can be reduced while providing a low-resistance, good and stable electrical connection of the well region of the DRAM cell structure and having, to provide a stable voltage to each memory cell. Compared with the conventional configuration of the metal contact components shown in FIG. 2, in the present invention, the density of the metal contact components in the bit line sense amplifier (SA) or word line driver (WLD) region around the DRAM cell array block boundary can be reduced. In the conventional configuration of the metal contact components shown in FIG. 2, there is no specific connection to the well region in each DRAM cell, and the DRAM cell array block uses metal contact components to connect the well region to the voltage source instead of using the well region to distribute the voltage to each DRAM cell. FIGS. 2, Figure 7 and Figure 8 The DRAM cell array block shown in FIG. 4 contains a plurality of DRAM cells, such as 512×512 DRAM cells.

[0115] Some benefits of the DRAM cell structure of the present invention are described as follows:

[0116] (1) Electrical connection to each DRAM cell can be achieved to provide a stable voltage to the well region.

[0117] (2) A low-resistance electrical connection to the well region of each DRAM cell can be achieved without being affected by changes in the doping concentration of the substrate and / or changes in the cell structure.

[0118] (3) A low-resistance electrical connection to the well region of each DRAM cell can be achieved without being affected by an increase in the size of the DRAM cell array block. For example, even if the size of the DRAM cell array block increases from 512×512 to 688×1024, a low-resistance electrical connection to the well region of each DRAM cell can still be achieved.

[0119] (4) Through good, stable, and low-resistance electrical connection to the well region, the area of the well region connection (i.e., the area for configuring the conductive interconnect structure) can be reduced, and a more feasible layout of the bit line sense amplifier or word line driver region can be obtained.

[0120] (5) The DRAM chip size can be reduced by increasing the size of the DRAM cell array block (for example, the size of the DRAM cell array block can be increased from 512×512 to 688×1024). Therefore, the number of DRAM cell array blocks can be reduced, and the area of the peripheral circuit or bit line sense amplifier or word line driver can be reduced by removing the well region connection.

[0121] Figures 9 to 19 is a structural cross-sectional schematic diagram showing multiple stages in a method for manufacturing a DRAM cell structure according to an embodiment of the present invention.

[0122] Figure 9 It is a schematic cross-sectional view of a stage of a manufacturing method. A semiconductor substrate 22 is provided. Through a deposition process, a pad oxide layer 901 and a pad nitride layer 902 are sequentially formed above the semiconductor substrate 22 to define a plurality of active regions. The pad oxide layer 901 may include an oxide, such as silicon oxide. The pad nitride layer 902 may include a nitride, such as silicon nitride.

[0123] Figure 10 It is a schematic cross-sectional view of a stage of a manufacturing method. Through a deposition process, a photoresist layer 1003 is formed on the pad nitride layer 902, and the photoresist layer 1003 is patterned to define a plurality of trenches 1004 in the photoresist layer 1003. The plurality of trenches 1004 extend along a third direction D3 and expose a part of the pad nitride layer 902.

[0124] Figure 11 It is a schematic cross-sectional view of a stage of a manufacturing method. A plurality of trenches 1004A are formed in the semiconductor substrate 22. The plurality of trenches 1004A extend along the third direction D3 and expose a part of the pad oxide layer 901, a part of the pad nitride layer 902, and a part of the semiconductor substrate 22. The positions of the trenches 1004 may correspond to the positions of the trenches 1004A. An etching process may be performed through the plurality of trenches 1004 to remove a part of the pad oxide layer 901, a part of the pad nitride layer 902, and a part of the semiconductor substrate 22 to form the plurality of trenches 1004A. The length of the trenches 1004A in the third direction D3 may be greater than the length of the trenches 1004 in the third direction D3. The active regions may be defined between the plurality of trenches 1004A and in the semiconductor substrate 22. The trenches 1004A are near the active regions.

[0125] Figure 12 It is a schematic cross-sectional view of a stage of a manufacturing method. Through an etching process or a grinding process, the photoresist layer 1003 is removed. Through a deposition process, a dielectric material 1205 is formed on the sidewalls and the bottom of the plurality of trenches 1004A. The dielectric material 1205 may grow along the semiconductor substrate 22 exposed by the trenches 1004A. The upper surface of the dielectric material 1205 may be lower than the upper surface of the pad nitride layer 902 in the third direction D3. In the third direction D3, the upper surface of the dielectric material 1205 may be coplanar with the upper surface of the pad oxide layer 901, or coplanar with the upper surface of the semiconductor substrate 22, or lower than the upper surface of the pad oxide layer 901 and higher than the upper surface of the semiconductor substrate 22. The dielectric material 1205 may include a dielectric material, such as a spin-on dielectric (SOD) material.

[0126] Figure 13It is a schematic cross-sectional view of a stage of a manufacturing method. Through an etching process, a portion of the dielectric material 1205 at the bottom of the trench 1004A is removed, and a portion of the dielectric material 1205 on the sidewalls of the trench 1004A is retained. A portion of the semiconductor substrate 22 is exposed by the trench 1004A. The retained portion of the dielectric material 1205 on the sidewalls of the trench 1004A can be defined as the first isolation structure 26-1 and the second isolation structure 26-2.

[0127] Figure 14 It is a schematic cross-sectional view of a stage of a manufacturing method. Through a deposition process, a conductive material is filled in the trench 1004A and on the upper surface of the pad nitride layer 902, and through an etch-back process, a portion of the conductive material above the upper surface of the semiconductor substrate 22 is removed to form the first conductive interconnect structure 25-1 and the second conductive interconnect structure 25-2 in the trench 1004A respectively. The first isolation structure 26-1 and the first conductive interconnect structure 25-1 are in one trench 1004A among the plurality of trenches 1004A, and the second isolation structure 26-2 and the second conductive interconnect structure 25-2 are in another trench 1004A among the plurality of trenches 1004A. The upper surfaces of the first isolation structure 26-1, the upper surface of the second isolation structure 26-2, the upper surface of the first conductive interconnect structure 25-1, and the upper surface of the second conductive interconnect structure 25-2 can be coplanar, or can have the same height in the third direction D3.

[0128] Figure 15 It is a schematic cross-sectional view of a stage of a manufacturing method. Through a deposition process, an SOD film 1506 and an HDP (high density plasma) oxide film 1507 are sequentially formed on the pad nitride layer 902. A portion of the SOD film 1506 is in the trench 1004A and can contact the first isolation structure 26-1, the second isolation structure 26-2, the first conductive interconnect structure 25-1, and the second conductive interconnect structure 25-2. In one embodiment, the formation of the SOD film 1506 can include a pre-growth process of an oxide.

[0129] Figure 16 It is a schematic cross-sectional view of a stage of a manufacturing method. Through a polishing process, a portion of the SOD film 1506 above the upper surface of the pad nitride layer 902 and the HDP oxide film 1507 are removed to expose the pad nitride layer 902, and a portion of the SOD film 1506 in the trench 1004A is retained. The retained portion of the SOD film 1506 can be defined as the SOD film 1506A. The upper surface of the SOD film 1506A and the upper surface of the pad nitride layer 902 can be coplanar.

[0130] Figure 17It is a schematic cross-sectional view of a stage of a manufacturing method. The pad nitride layer 902 is removed by an etching process. The sidewalls of the SOD film 1506A and the upper surface of the pad oxide layer 901 are exposed.

[0131] Figure 18 It is a schematic cross-sectional view of a stage of a manufacturing method. An ion implantation process (indicated by arrows) is performed to define well regions and channels of a plurality of access transistors.

[0132] Figure 19 It is a schematic cross-sectional view of a stage of a manufacturing method. The pad oxide layer 901 is removed by an etching process to expose the semiconductor substrate 22, and a gate dielectric film 1907 is formed on the semiconductor substrate 22 by epitaxial growth. The gate dielectric film 1907 can contact the semiconductor substrate 22 and the SOD film 1506A. Therefore, a semiconductor structure including a plurality of conductive interconnect structures can be provided, and the conductive interconnect structures are within isolation structures. The manufacturing steps for forming transistors in the active regions can be performed Figure 19 after the stage shown.

[0133] Figures 20 to 26 It is a schematic cross-sectional view showing multiple stages in a method for manufacturing a DRAM cell structure according to another embodiment of the present invention. In one embodiment, it can be performed after the manufacturing steps Figures 9 to 12 described in conjunction with Figures 20 to 26 and after the manufacturing steps

[0134] Figure 20 It is a schematic cross-sectional view of a stage of a manufacturing method. A portion of the dielectric material 1205 at the bottom of the trench 1004A is removed by an etching process, and a portion of the dielectric material 1205 on the sidewalls of the trench 1004A is retained. A portion of the semiconductor substrate 22 is exposed by the trench 1004A. The retained portion of the dielectric material 1205 on the sidewalls of the trench 1004A can be defined as the dielectric material 2005.

[0135] Figure 21 It is a schematic cross-sectional view of a stage of a manufacturing method. A conductive material is filled into the trench 1004A and on the upper surface of the pad nitride layer 902 by a deposition process; a portion of the conductive material above the upper surface of the semiconductor substrate 22 and a portion of the conductive material in the upper part of the trench 1004A are removed by an etch-back process to form a first conductive interconnect structure 35-1 and a second conductive interconnect structure 35-2 in the trench 1004A, respectively. The upper surface of the dielectric material 2005 can be higher than the upper surfaces of the first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 in the third direction D3. The first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2 can be formed on the sidewalls of the dielectric material 2005.

[0136] Figure 22 It is a schematic cross-sectional view of a stage of a manufacturing method. Through a deposition process, a dielectric material 2206 and an HDP (high density plasma) oxide film 2207 are sequentially formed on the pad nitride layer 902. The dielectric material 2206 may include a first dielectric portion 2206A in the trench 1004A and in the semiconductor substrate 22, a second dielectric portion 2206B in the trench 1004A and above the semiconductor substrate 22, and a third dielectric portion 2206C above the pad nitride layer 902. The first dielectric portion 2206A of the dielectric material 2206 is in the upper part of the trench 1004A. The first dielectric portion 2206A of the dielectric material 2206 is on the upper surfaces of the first conductive interconnect structure 35-1 and the second conductive interconnect structure 35-2. The first dielectric portion 2206A of the dielectric material 2206 may be on the sidewalls of the dielectric material 2005 and may contact the dielectric material 2005, the first conductive interconnect structure 35-1, and the second conductive interconnect structure 35-2. The second dielectric portion 2206B of the dielectric material 2206 may be on the sidewalls of the pad oxide layer 901 and the pad nitride layer 902. The second dielectric portion 2206B of the dielectric material 2206 may contact the pad oxide layer 901, the pad nitride layer 902, the first dielectric portion 2206A, and the third dielectric portion 2206C. The third dielectric portion 2206C of the dielectric material 2206 may contact the pad nitride layer 902 and the HDP oxide film 2207 and may be between the pad nitride layer 902 and the HDP oxide film 2207. In one embodiment, the formation of the dielectric material 2206 may include a pre-growth treatment of an oxide. The dielectric material 2206 may include a dielectric material, such as a spin-on dielectric (SOD) material. The first dielectric portion 2206A in one of the plurality of trenches 1004A and the dielectric material 2005 in the same trench 1004A may form (or may be defined as) a first isolation structure 26-1, and the first dielectric portion 2206A in another one of the plurality of trenches 1004A and the dielectric material 2005 in the same trench 1004A may form (or may be defined as) a second isolation structure 26-2.

[0137] Figure 23 It is a schematic cross-sectional view of a stage of a manufacturing method. Through a grinding process, the third dielectric portion 2206C of the dielectric material 2206 and the HDP oxide film 2207 are removed to expose the pad nitride layer 902, and the first dielectric portion 2206A and the second dielectric portion 2206B are retained. The upper surface of the second dielectric portion 2206B and the upper surface of the pad nitride layer 902 may be coplanar.

[0138] Figure 24 It is a schematic cross-sectional view of a stage of a manufacturing method. Through an etching process, the pad nitride layer 902 is removed. The sidewalls of the second dielectric portion 2206B and the upper surface of the pad oxide layer 901 are exposed.

[0139] Figure 25 It is a schematic cross-sectional view of a stage of a manufacturing method. An ion implantation process (indicated by arrows) is performed to define well regions and channels of a plurality of access transistors.

[0140] Figure 26 It is a schematic cross-sectional view of a stage of a manufacturing method. The pad oxide layer 901 is removed by an etching process to expose the semiconductor substrate 22, and an epitaxial growth is performed to form a gate dielectric film 2607 on the semiconductor substrate 22. The gate dielectric film 2607 can contact the semiconductor substrate 22 and the second dielectric portion 2206B. Accordingly, a semiconductor structure including a plurality of conductive interconnect structures can be provided, and the conductive interconnect structures are within isolation structures. The manufacturing steps for forming transistors in the active regions can be performed Figure 26 after the stage shown.

[0141] It should be noted that the structures and methods described above are for illustration purposes. The present invention is not limited to the above-described configurations and steps of the invention. Other embodiments with different configurations of known components can be applied, and the structures of the examples can be adjusted and changed based on the actual requirements of practical applications. Of course, it should be noted that the configurations of the drawings are only for demonstration and not for limitation. Therefore, those of ordinary skill in the art should know that the relevant components and layers in the semiconductor structure, the shape or positional relationship of the components, and the step details can be adjusted or changed according to the actual requirements of practical applications and / or manufacturing steps.

[0142] Although the present invention has been described by way of examples and in terms of exemplary embodiments, it should be understood that the present invention is not limited thereto. On the contrary, the present invention is intended to cover various variations, as well as similar configurations and steps. Therefore, the scope of the appended claims should be given the broadest interpretation so as to cover all such variations, as well as similar configurations and steps.

Claims

1. A dynamic random access memory cell structure, comprising: A semiconductor substrate having a well region and an original semiconductor surface; An access transistor located within the well region and having a gate structure; A bit line electrically coupled to the access transistor; A storage capacitor electrically coupled to the access transistor; A word line electrically coupled to the gate structure of the access transistor; An isolation structure within the well region and surrounding the access transistor; And A conductive interconnect structure located within the isolation structure and electrically connected to the well region of the semiconductor substrate.

2. The dynamic random access memory cell structure according to claim 1, characterized in that, A bottom surface of the conductive interconnect structure contacts the well region of the semiconductor substrate.

3. The dynamic random access memory cell structure according to claim 1, wherein, A bottom surface of the conductive interconnect structure is lower than a bottom surface of the gate structure.

4. The dynamic random access memory cell structure according to claim 1, wherein, An upper surface of the conductive interconnect structure is covered by the isolation structure and lower than the original semiconductor surface of the semiconductor substrate.

5. The dynamic random access memory cell structure according to claim 4, wherein The upper surface of the conductive interconnect structure is lower than a bottom surface of the gate structure.

6. The dynamic random access memory cell structure as claimed in claim 1, wherein Further comprising a trench in the semiconductor substrate, wherein the isolation structure and the conductive interconnect structure are within the trench.

7. The dynamic random access memory cell structure according to claim 1, wherein The word line and the conductive interconnect structure extend along a first direction, the bit line extends along a second direction, and the first direction is different from the second direction.

8. The dynamic random access memory cell structure as claimed in claim 1, wherein, The conductive interconnect structure has a first sidewall and a second sidewall opposite to the first sidewall, and both the first sidewall and the second sidewall are covered by the isolation structure.

9. The dynamic random access memory cell structure as claimed in claim 1, wherein The conductive interconnect structure extends to a position close to a boundary of the well region.

10. The dynamic random access memory cell structure as described in claim 1, wherein, The semiconductor substrate further comprises a memory cell array block accommodating the access transistor, and the conductive interconnect structure extends to a position close to a boundary of the memory cell array block.

11. The dynamic random access memory cell structure as described in claim 10, characterized in that, Further comprising a metal contact component close to the boundary of the memory cell array block, and the metal contact component is electrically connected to the conductive interconnect structure.

12. The dynamic random access memory cell structure according to claim 1, wherein The conductive interconnect structure comprises highly doped silicon, tungsten, titanium nitride, or a combination thereof.

13. A dynamic random access memory cell structure, comprising: A semiconductor substrate having a well region and an original semiconductor surface; A first group of active regions within the well region; A second group of active regions within the well region; A first word line extending across the first group of active regions; A second word line extending across the second group of active regions; An isolation structure between the first group of active regions and the second group of active regions; And A conductive interconnect structure located within the isolation structure and electrically connected to the well region.

14. The dynamic random access memory cell structure according to claim 13, wherein The first word line, the second word line and the conductive interconnect structure extend along a first direction.

15. The dynamic random access memory cell structure according to claim 13, wherein A bottom surface of the conductive interconnect structure contacts the well region of the semiconductor substrate.

16. The dynamic random access memory cell structure according to claim 14, wherein The semiconductor substrate further comprises a memory cell array block accommodating the first group of active regions and the second group of active regions, and the conductive interconnect structure extends to a position close to a boundary of the memory cell array block.

17. The dynamic random access memory cell structure as described in claim 16, wherein, Further comprising a metal contact component outside the boundary of the memory cell array block, wherein the metal contact component is electrically connected to the conductive interconnect structure.

18. The dynamic random access memory cell structure as described in claim 13, wherein, An upper surface of the conductive interconnect structure is covered by the isolation structure.

19. A method for manufacturing a dynamic random access memory cell structure, comprising: Providing a semiconductor substrate having an original semiconductor surface; Define an active region; Form a trench in the semiconductor substrate and near the active region; Form an isolation structure and a conductive interconnect structure in the trench, wherein the conductive interconnect structure is surrounded by the isolation structure; And Form a well region that houses the active region, wherein a bottom surface of the conductive interconnect structure contacts the well region of the semiconductor substrate, and the conductive interconnect structure extends along a first direction and away from the active region.

20. The method according to claim 19, wherein Forming the isolation structure and the conductive interconnect structure in the trench includes: Forming a first dielectric material that covers sidewalls of the trench; Forming the conductive interconnect structure surrounded by the first dielectric material; and Forming a second dielectric material on an upper surface of the conductive interconnect structure, wherein the first dielectric material and the second dielectric material form the isolation structure.

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