Testing method and control device for three-dimensional integrated memory chip

Abstract

The present invention relates to a testing method for a three-dimensional integrated chip and a control device. In the testing method, a chip select signal is first sent to the Mth storage layer of the three-dimensional integrated memory chip to select the Mth storage layer. Read and write operations are then performed on the Mth storage layer through the IO interface of the logic circuit layer. The data transmission path between the global sense amplifier circuit that receives the written data in the Mth storage layer and the corresponding storage array is disconnected. This isolates the data written by the read and write operations within the global sense amplifier circuit before being read and returned to the logic circuit layer. A determination is then made as to whether the read data is consistent with the written data. If so, the chip interconnection path between the logic circuit layer and the Mth storage layer is fault-free. If not, a fault exists. The testing method eliminates the impact of storage array faults on test results, improves the accuracy of test results, and contributes to improved manufacturing processes. The control device can execute the above-described testing method.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a testing method for a three-dimensional integrated chip and a control device. Background Art

[0002] A three-dimensional integrated chip comprises two or more vertically interconnected chips, offering advantages such as high integration, fast response time, and low energy consumption. For example, a three-dimensional integrated memory chip comprises at least two memory die (such as DRAM die) stacked on a logic die. The logic die forms the logic circuit layer of the three-dimensional integrated memory chip, while each memory die forms a memory layer. The logic circuit layer and each memory layer are vertically interconnected via chip interconnect pathways. During operation, power signals, control signals, and data are transmitted via these chip interconnect pathways.

[0003] The failure rate of chip interconnect pathways directly impacts the yield of 3D integrated chips. Therefore, detecting and locating faults in these pathways is crucial for improving manufacturing processes. However, current data read and write tests can detect faults in either the chip interconnect pathways or the storage array within the memory layer. Furthermore, the fault location cannot be pinpointed, making it impossible to determine the presence or location of the fault in the chip interconnect pathways. Summary of the Invention

[0004] In order to detect faults in chip interconnection paths and facilitate determination of fault locations, the present invention provides a method for testing a three-dimensional integrated memory chip and a control device.

[0005] In one aspect, the present invention provides a method for testing a three-dimensional integrated memory chip, the three-dimensional integrated memory chip comprising a logic circuit layer and a first to an Nth memory layer stacked sequentially on one side of the logic circuit layer, where N is an integer greater than 1, the logic circuit layer and each memory layer being vertically interconnected via at least one chip interconnection path, each memory layer comprising a global sense amplifier circuit connected to the logic circuit layer via a corresponding chip interconnection path, and a memory array that obtains data via the global sense amplifier circuit; the testing method comprising:

[0006] Step 1: Sending a chip select signal to the Mth storage layer through the logic circuit layer to select the Mth storage layer, where M is an integer and 1≦M≦N, and the remaining storage layers are shielded by the chip select signal;

[0007] Step 2: Performing read and write operations on the Mth storage layer through the IO interface of the logic circuit layer, and disconnecting the data transmission path between the global sense amplifier circuit of the Mth storage layer that receives the written data and the corresponding storage array, so that the data written by the read and write operations is isolated in the global sense amplifier circuit, and then read out and returned to the logic circuit layer;

[0008] Step three, determine whether the read data is consistent with the written data. If they are consistent, the chip interconnection path between the logic circuit layer and the Mth storage layer is faulty. If they are inconsistent, the chip interconnection path between the logic circuit layer and the Mth storage layer is faulty.

[0009] Optionally, the N global readout amplifier circuits respectively arranged in the 1st storage layer to the Nth storage layer are connected to the logic circuit layer using a common chip interconnection path, wherein the data of the read and write test are written and read through the chip interconnection path between the Mth storage layer and the logic circuit layer.

[0010] Optionally, the testing method includes:

[0011] Set M to gradually increase from 1 or gradually decrease from N, and loop through steps 1 to 3 to determine one by one whether there is a fault in the chip interconnection path between the logic circuit layer and the Mth storage layer.

[0012] Optionally, when M is greater than 1 and the chip interconnection path between the logic circuit layer and the (M-1)th storage layer has no faults but the chip interconnection path between the logic circuit layer and the Mth storage layer has a fault, the fault is located in the chip interconnection path between the (M-1)th storage layer and the Mth storage layer.

[0013] Optionally, in the first storage layer to the Nth storage layer, a first number of the global read-out amplifier circuits respectively arranged in a first number of the storage layers share a first chip interconnection path connected to the logic circuit layer, and a second number of the global read-out amplifier circuits respectively arranged in a second number of the storage layers share a second chip interconnection path connected to the logic circuit layer.

[0014] Optionally, the testing method includes:

[0015] The storage layers connected to the first chip interconnection path are sequentially selected along a direction from near to far or from far to near relative to the logic circuit layer to execute steps 1 to 3, so as to determine whether the first chip interconnection path between the logic circuit layer and the corresponding storage layer has a fault. If a fault exists, the fault is located in the chip interconnection path between the last two storage layers tested. Moreover, the storage layers connected to the second chip interconnection path are sequentially selected along a direction from near to far or from far to near relative to the logic circuit layer in an order away from the logic circuit layer to execute steps 1 to 3, so as to determine whether the second chip interconnection path between the logic circuit layer and the corresponding storage layer has a fault. If a fault exists, the fault is located in the second chip interconnection path between the last two storage layers tested.

[0016] Optionally, the global readout amplifier circuit includes a latch, wherein in the step 2, the data written into the Mth storage layer is temporarily stored in the corresponding latch of the global readout amplifier circuit.

[0017] Optionally, in the step 2, when performing a read and write test on the Mth storage layer, the frequency of the test clock used is lower than the frequency of the working clock used in the working mode of the three-dimensional integrated memory chip.

[0018] Optionally, the frequency of the working clock is 400 MHz, and the frequency of the test clock is between 40 MHz and 60 MHz.

[0019] Optionally, the chip interconnection path includes TSVs arranged in the logic circuit layer and the 1st to (N-1)th storage layers to connect the front and back structures of the corresponding layers, and also includes a metal structure for connecting the logic circuit layer and the first storage layer and a metal structure for connecting two adjacent storage layers.

[0020] On the other hand, the present invention provides a control device for controlling a three-dimensional integrated memory chip, wherein the control device executes the above-mentioned test method when testing whether the chip interconnection path in the three-dimensional integrated memory chip has a fault.

[0021] Optionally, when testing whether there is a fault in the chip interconnection path in the three-dimensional integrated memory chip, the control device sets the three-dimensional integrated memory chip to enter a test mode of the chip interconnection path; and in response to entering the test mode of the chip interconnection path, the data transmission path between the global read-out amplifier circuit for receiving write data in the N storage layers and the corresponding storage array is disconnected, and / or each of the storage layers includes P storage cells, P is an integer greater than 1, and in response to entering the test mode of the chip interconnection path, the data transmission paths between N*P global read-out amplifier circuits in the N storage layers and the corresponding storage array are all disconnected.

[0022] In the test method and control device for a three-dimensional integrated memory chip provided by the present invention, to determine whether a fault exists in the chip interconnect path, a chip select signal is sent to select the Mth memory layer. Then, read and write operations are performed on the Mth memory layer through the IO interface of the logic circuit layer, and the consistency of the read data with the written data is determined. Because a fault in the chip interconnect path between the Mth memory layer and the logic circuit layer can affect data transmission, causing the read data to differ from the written data, and because the data transmission path between the global sense amplifier circuit of the Mth memory layer and the corresponding memory array is disconnected, if the read data differs from the written data, a fault is determined in the chip interconnect path between the logic circuit layer and the Mth memory layer. Furthermore, the test method or control device can be used to test two or more memory layers sharing a chip interconnect path one by one to locate the fault in the chip interconnect path. Because the written data is stored in the global sense amplifier circuit of the Mth memory layer and not written into the memory array, the impact of memory array faults on the test results is eliminated, improving the accuracy of the test results and contributing to improvements in the manufacturing process of three-dimensional integrated memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a three-dimensional integrated memory chip according to an embodiment of the present invention.

[0024] Figure 2 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional integrated memory chip in another embodiment of the present invention.

[0025] Figure 3 FIG. 1 is a schematic diagram of a three-dimensional integrated memory chip storing data in a working mode according to an embodiment of the present invention.

[0026] Figure 4 It is a flow chart of a method for testing a three-dimensional integrated memory chip according to an embodiment of the present invention.

[0027] Figure 5 yes Figure 3The three-dimensional integrated memory chip is shown as a schematic diagram showing that the data transmission path between the global sense amplifier circuit of the M-th memory layer and the corresponding memory array is disconnected in step 2.

[0028] Figure 6 This is a timing diagram of multiple signals when testing a three-dimensional integrated memory chip in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following is a detailed description of the test method and control device for a three-dimensional integrated memory chip of the present invention, in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0030] For ease of understanding, the three-dimensional integrated memory chip involved in the embodiment of the present invention is first described below.

[0031] Reference Figure 1 The three-dimensional integrated memory chip 100 includes a logic circuit layer D0 and a first memory layer D1 to an Nth memory layer DN sequentially stacked on one side of the logic circuit layer D0 , where N is an integer greater than 1. Figure 1 Taking N=4 as an example, the first storage layer D1, the second storage layer D2, the third storage layer D4, and the fourth storage layer D1 are shown as examples. In the three-dimensional integrated memory chip 100, the logic circuit layer D0 and the first through Nth storage layers D1 through D4 are, for example, bare chips (dies). The front surfaces of the bare chips with devices formed thereon face, for example, in the same direction, and the back surfaces face, for example, in the same direction. The first through Nth storage layers D1 through D4 are, for example, stacked on the back surface of the logic circuit layer D0.

[0032] The first storage layer D1 to the Nth storage layer DN are used to store data. Each storage layer includes P storage units (such as Figure 1 DUs (the positions and numbers of DUs shown in the figure are examples only) are used to store data, where P is an integer greater than 1. Each memory unit DU is, for example, a "BANK," which includes a memory array having 16K word lines and 16K bit lines, capable of storing 128M bits (i.e., 32M bytes) of data. However, this is not limiting, and the number of word lines and bit lines in the memory array need not be equal. For example, a "BANK" may include a memory array having 2K word lines and 16K bit lines, capable of storing 32M bits (i.e., 4M bytes) of data.

[0033] The logic circuit layer D0 is formed with a logic circuit. When controlling the operation of the storage layer or testing the performance of the storage layer, signals are usually input / output from the IO port on the side of the logic circuit layer D0 away from the first storage layer D1. There is more than one IO port. Depending on the specific settings, these IO ports can be used to transmit power signals, control signals, and data, etc. For example, an independent chip select signal can be sent from the logic circuit layer D0 to each storage layer through a designated IO port.

[0034] like Figure 1 As shown, in a three-dimensional integrated memory chip 100, the logic circuit layer D0 and each memory layer are vertically interconnected via at least one chip interconnection path 10 to form an overall circuit system. The chip interconnection path 10 may include TSVs disposed in the logic circuit layer D0 and the first to (N-1)th memory layers to connect the front and back structures of the corresponding layers. Figure 1 In the embodiment shown, the Nth storage layer DN is, for example, the 4th storage layer D4, i.e., N=4. In addition, the logic circuit layer D0 and the 1st storage layer D1, as well as the two adjacent storage layers, are bonded, such as by a microbump (μBump) connection or a hybrid bonding (HB) connection. The chip interconnect path 10 also includes a metal structure for connecting the logic circuit layer D0 and the 1st storage layer D1, as well as a metal structure for the two adjacent storage layers. In the following embodiments, hybrid bonding is used between the logic circuit layer D0 and the 1st storage layer D1, as well as between the two adjacent storage layers. The hybrid bonding area is as follows: Figure 1 As shown in “HB”.

[0035] Each storage layer also has an IO interface (such as Figure 1 As shown in the "IO" marked in the 1st storage layer D1 to the 4th storage layer D4 in the figure), the IO interface on the storage layer can be connected to the logic circuit layer D0 through the corresponding chip interconnection path 10, and there can be more than one IO interface on the storage layer. Depending on the specific settings, these IO ports can be used to obtain power signals, control signals, data, etc.

[0036] Reference Figure 1 In one embodiment, the stacked structure of the logic circuit layer D0 and the first storage layer D1 to the Nth storage layer DN (for example, N=4) has a chip interconnection path 10 passing therethrough, and the first storage layer D1 to the Nth storage layer DN are connected to the logic circuit layer D0 through the shared chip interconnection path 10.

[0037] The present invention is not limited thereto, and each storage layer in the three-dimensional integrated memory chip of the present invention may not all share the chip interconnection path connected to the logic circuit layer. Figure 2In another embodiment, the three-dimensional integrated memory chip 101 includes a logic circuit layer D0 and a first memory layer D1 to an Nth memory layer DN sequentially stacked on one side (e.g., the back side) of the logic circuit layer D0, where N is an integer greater than 1. Figure 1 The difference between the three-dimensional integrated memory chip 100 shown in FIG1 is that part of the memory layers (such as the first memory layer D1 and the second memory layer D2) in the three-dimensional integrated memory chip 101 share the first chip interconnection path 11 to connect to the logic circuit layer D0, and another part of the memory layers (such as the third memory layer D3 and the fourth memory layer D4) share the second chip interconnection path 12 to connect to the logic circuit layer D0. Figure 1 In the three-dimensional integrated memory chip 100 and the three-dimensional integrated memory chip 101 in the illustrated embodiment, signals can be transmitted from the logic circuit layer D0 to the two memory layers simultaneously through the first chip interconnection path 11 and the second chip interconnection path 12, thereby increasing bandwidth. Figure 2 The bandwidth of the three-dimensional integrated memory chip 101 including the first chip interconnection path 11 and the second chip interconnection path 12 is, for example, Figure 1 The bandwidth of the three-dimensional integrated memory chip 100 shown includes only the chip interconnection path 10, which is twice as large.

[0038] In order to write data into each storage unit DU of each storage layer or read data from the storage unit DU, each storage layer in the above-mentioned three-dimensional integrated storage chip 100 or three-dimensional integrated storage chip 101 may be provided with a corresponding circuit to form a data transmission path. Figure 3 , the storage array in the storage unit DU may include multiple array sections, each array section has a corresponding local sense amplifier (local SA), and corresponding to one storage unit DU, the storage layer is also formed with a write controller, a global sense amplifier (global SA, also known as SSA), a data channel (datapath), a row decoder and a column decoder. In some embodiments, each storage layer includes P storage units DU, and each storage unit DU may be provided with a write controller, a global sense amplifier, a data channel, a row decoder and a column decoder for enabling the storage array inside the storage unit DU to implement read and write operations, and the clock signal may be input through the column decoder. In addition, the storage layer may also be formed with a clock module to provide a clock signal during read and write operations. The write controller, global sense amplifier, row decoder, column decoder and clock module may be formed in a metal layer (such as an RDL layer) in the corresponding storage layer. As Figure 3As shown, a COLEN low-pass high-lock signal can be input from the clock module side to write data into the global sense amplifier circuit, and the RDQS signal is used to read data. The present invention is not limited to this, and the specific circuit design for performing read and write tests can also adopt known technologies. The specific structure of the write controller, global sense amplifier circuit, row decoder, column decoder and clock module, as well as the process of writing data into or reading data from the memory unit DU, can refer to known technologies. As an example, after the chip is powered on, in order to write data into the memory unit DU, the data is transmitted to the specified memory unit of the specified memory layer through the logic circuit layer D0 and the above-mentioned chip interconnection path. The data is first written into the global sense amplifier circuit via the data channel through the write controller of the specified memory unit. Then, based on the address of the memory array selected by the row decoder and column decoder, the data is written into the corresponding memory array through the data transmission path between the global sense amplifier circuit and the memory array.

[0039] The following further describes a test method for a three-dimensional integrated memory chip according to an embodiment of the present invention. As described above, the three-dimensional integrated memory chip includes a logic circuit layer D0 and a first memory layer D1 to an Nth memory layer DN stacked sequentially on one side of the logic circuit layer D0, where N is an integer greater than 1. The logic circuit layer D0 and each memory layer are vertically interconnected via a chip interconnection path. Each memory layer includes a global sense amplifier circuit (global SA or SSA) connected to the logic circuit layer D0 via a corresponding chip interconnection path, and a memory array that obtains data through the global sense amplifier circuit. Figure 3 The testing method of the three-dimensional integrated memory chip according to the embodiment of the present invention may include the following steps:

[0040] Step 1 (S1) sends a chip select signal CS to the Mth storage layer through the logic circuit layer D0 to select the Mth storage layer, where M is an integer and 1≦M≦N. The remaining storage layers in the three-dimensional integrated memory chip are shielded by the chip select signal CS.

[0041] Step 2 (S2) performs read and write operations on the Mth storage layer through the IO interface of the logic circuit layer D0, and disconnects the data transmission path between the global read / write amplifier circuit of the Mth storage layer that receives the written data and the corresponding storage array, so that the data written by the read and write operations is isolated in the global read / write amplifier circuit, and then is read out and returned to the logic circuit layer D0;

[0042] Step three (S3) determines whether the read data is consistent with the written data. If they are consistent, the chip interconnection path between the logic circuit layer D0 and the Mth storage layer is normal. If they are inconsistent, the chip interconnection path between the logic circuit layer D0 and the Mth storage layer is faulty.

[0043] Reference Figure 1 Taking M=1 as an example, when executing the above-described test method, in step 1, a chip select signal is sent to the first storage layer D1 to select the first storage layer D1. In step 2, read and write operations are performed on the selected first storage layer D1 via the IO interface of the logic circuit layer D0. Furthermore, corresponding control signals are sent by the logic circuit layer D0 to disconnect the data transmission path between the global sense amplifier circuit in the first storage layer D1 that receives the write data and the corresponding storage array during the read and write operations (if necessary, the data transmission path between all global sense amplifier circuits in the first storage layer D1 and the corresponding storage array may also be disconnected; if necessary, the data transmission path between all global sense amplifier circuits in the N storage layers D1-DN and the corresponding storage array may also be disconnected). This is to prevent the write data from being written into any storage array, thereby preventing the storage array from affecting the test results. Thus, during the read and write operations, the written data is isolated from the global sense amplifier circuit that receives the data. After the data is written, a read operation is performed, so that the data isolated in the global sense amplifier circuit is read and returned to the logic circuit layer D0 through the corresponding data channel and chip interconnection path. It can be seen that if there is a fault in the chip interconnection path 10 between the first storage layer D1 and the logic circuit layer D0, the written data will be inconsistent with the read data. Since the written data will not pass through the storage array of the first storage layer D1, the influence of the storage array on the test result is eliminated. When the read data is different from the written data, the possibility of a fault in the storage array is eliminated. The comparison result of the read data and the written data can reflect whether there is a fault in the chip interconnection path between the logic circuit layer D0 and the first storage layer. Step three can be performed in the logic circuit layer D0 or through a processing device outside the chip to determine whether the data read out of the read and write operations in step two are consistent with the written data. If they are consistent, the chip interconnection path 10 between the logic circuit layer D0 and the first storage layer D1 is not faulty. If they are inconsistent, there is a fault in the chip interconnection path 10 between the logic circuit layer D0 and the first storage layer D1.

[0044] It should be noted that in the above-mentioned test method for the three-dimensional integrated memory chip, step three is only executed on the premise that the operation of sending the chip select signal described in step one and the operations of writing and reading data described in step two are both executed effectively. Since the transmission of the chip select signal and data both pass through the chip interconnection path, if the sending of the chip select signal is invalid, the writing of data is invalid, or the reading of data is invalid, it can be directly concluded that the corresponding chip interconnection path is faulty or there is a problem with the test setting, and the test can be terminated or further confirmation can be made.

[0045] The value of M can be set as needed and steps 1 through 3 can be performed to obtain information about whether the chip interconnect path between logic circuit layer D0 and the corresponding M-th storage layer is faulty. When M>1 and the above steps indicate a fault in the chip interconnect path between logic circuit layer D0 and the M-th storage layer, since this chip interconnect path also connects logic circuit layer D0 and the storage layer between logic circuit layer D0 and the M-th storage layer, to further locate the fault in the chip interconnect path, it is also necessary to determine whether the chip interconnect path between the storage layer below the M-th storage layer and the logic circuit layer D0 is faulty.

[0046] Reference Figure 1 In one embodiment, in a three-dimensional integrated memory chip 100, the N global sense amplifier circuits, respectively disposed in the first to Nth storage layers DN, are connected to the logic circuit layer D0 via a shared chip interconnect path 10. To detect faults in the chip interconnect path 10 and locate the specific location of the faults, the testing method sets M to gradually increase from 1 (maximum N) or gradually decrease from N (minimum 1), and loops through steps 1 to 3 to determine whether the chip interconnect path 10 between the logic circuit layer D0 and the Mth storage layer has faults. Optionally, when M is greater than 1 and the chip interconnect path 10 between the logic circuit layer D0 and the (M-1)th storage layer is fault-free, but the chip interconnect path 10 between the logic circuit layer D0 and the Mth storage layer is faulty, the fault is located in the chip interconnect path 10 between the (M-1)th storage layer and the Mth storage layer.

[0047] Reference Figure 2In another embodiment, in a three-dimensional integrated memory chip 101, a first number of global sense amplifier circuits respectively arranged in a first number of memory layers (such as the first memory layer D1 and the second memory layer D2) share a first chip interconnection path 11 connected to the logic circuit layer D0, and a second number of global sense amplifier circuits respectively arranged in a second number of memory layers (such as the third memory layer D3 and the fourth memory layer D4) share a second chip interconnection path 12 connected to the logic circuit layer D0. In this case, it is necessary to test and locate the fault position for the first chip interconnection path 11 and the second chip interconnection path 12 respectively. Specifically, the following process may be included: along the direction from near to far or from far to near relative to the logic circuit layer D0, select The memory layer connected to the first chip interconnect path 11 is selected to perform steps 1 to 3 to determine whether the first chip interconnect path 11 between the logic circuit layer D0 and the corresponding memory layer has a fault. If a fault exists, the fault is located in the first chip interconnect path 11 between the last two memory layers tested. Furthermore, the memory layers connected to the second chip interconnect path 12 are selected sequentially from near to far or from far to near relative to the logic circuit layer D0, and steps 1 to 3 are repeatedly performed to determine whether the second chip interconnect path 12 between the logic circuit layer D0 and the corresponding memory layer has a fault. If a fault exists, the fault is located in the second chip interconnect path 12 between the last two memory layers tested. The above fault detection for the first chip interconnect path 11 and the second chip interconnect path 12 can be performed independently.

[0048] In the above-mentioned test method, in step 2, by disconnecting the data transmission path between the global sense amplifier circuit of the Mth storage layer that receives the write data and the corresponding storage array, the data written by the read and write operations is isolated in the global sense amplifier circuit and will not be written into the storage array of the Mth storage layer. This can eliminate the influence of the storage array on the test results. Figure 5 Shown Figure 3 The three-dimensional integrated memory chip shown is a schematic diagram of a data transmission path between the global sense amplifier (SSA) of the M-th memory layer and the corresponding memory array being disconnected in step 2. Figure 5 As shown, in this embodiment, in order to eliminate the possibility that the read data is different from the written data and that there is a fault in the storage array, before writing data, the data transmission path between the global sense amplifier circuit of the Mth storage layer that receives the write data and the corresponding storage array is disconnected. This can be done by disconnecting the connection between the row decoder and the global sense amplifier circuit and the data channel ( Figure 5The cross in the figure indicates a cutoff position, disconnecting the data transmission path between the corresponding global sense amplifier circuit and the corresponding memory array. Thus, during read and write operations in step 2, data is transmitted only to the global sense amplifier circuit via the chip interconnect pathway and the circuitry on the Mth memory layer, and is not written into the corresponding memory array. The global sense amplifier circuit, for example, includes a latch. In step 2, data written into the Mth memory layer is temporarily stored in the latch of the corresponding global sense amplifier circuit.

[0049] Furthermore, to eliminate read / write errors caused by circuit timing, which could result in inconsistencies between the read and written data detected in step three, and to reduce the risk of falsely diagnosing a fault in the chip interconnect path, the test clock period used when performing read / write operations on the Mth storage layer through the IO interface of logic circuit layer D0 can be relaxed compared to the operating clock frequency used in the operating mode of the three-dimensional integrated memory chip. This can reduce the possibility of read / write errors caused by circuit timing. In one embodiment, when performing read / write tests on the Mth storage layer in step two, the test clock frequency used is lower than the operating clock frequency used in the operating mode of the three-dimensional integrated chip (e.g., during normal reading and writing). For example, the operating clock frequency is 400 MHz, and the test clock frequency is between 40 MHz and 60 MHz, for example, 50 MHz.

[0050] In order to execute the above-mentioned test method, the three-dimensional integrated memory chip to be tested can be connected to the test mainboard, and then the read and write modes can be configured, such as setting the timing, address mapping mode, and clock signals for read and write operations, and then data can be written and read through the programmer or the debugging interface on the test mainboard. Figure 6 The diagram shows the timing of multiple signals when testing a three-dimensional integrated memory chip. Figure 6 As an example, when executing step 1, based on the clock signal CLK (for example, a test clock with a frequency lower than the working clock), the chip select signal DU0_CS corresponding to the Mth storage layer is controlled to change from a low level to a high level, and the Mth storage layer is selected. When executing step 2, the write enable signal DU0_WE is first set to a high level to write data to the Mth storage layer. Moreover, while the write enable signal DU0_WE is at a high level, the DU0_COLEN low-pass high-lock is also controlled to write data to the latch of the above-mentioned global sense amplifier circuit. Figure 6 MC0_SSA represents the state of the latch; thereafter, the write enable signal DU0_WE becomes low, the read enable signal DU0_RE is high, and the falling edge of the pulse of the DU0_RDQS signal reads the data in the latch to the corresponding IO port (such as the DIO (digital IO) port) of the logic circuit layer D0. Figure 6 DU0_DIO indicates the data status of the DIO port.

[0051] The test method for a three-dimensional integrated memory chip described in the above embodiment can detect faults in the chip interconnect path between the Mth memory layer and the logic circuit layer D0. This eliminates the impact of memory array faults on test results, improving test accuracy. By testing continuously for M values, the fault location can also be located. The test results obtained using this test method can help improve the manufacturing process of three-dimensional integrated memory chips.

[0052] Embodiments of the present invention also relate to a control device, for example, for controlling a three-dimensional integrated memory chip. When testing whether a chip interconnect path within the three-dimensional integrated memory chip is faulty, the control device executes the three-dimensional integrated memory chip testing method described in the above embodiments. The concept of the testing method can be referred to the description of the above embodiments.

[0053] When testing the chip interconnect pathways in the three-dimensional integrated memory chip for faults, the control device can, through parameter settings, cause the three-dimensional integrated memory chip to enter a test mode for the chip interconnect pathways. In one embodiment, in response to entering the test mode (TSV / HB test mode) for the chip interconnect pathways, the data transmission paths between the global sense amplifier circuits for receiving write data and the corresponding memory arrays in the N memory layers of the three-dimensional integrated memory chip are disconnected. In another embodiment, each memory layer of the three-dimensional integrated memory chip further includes P memory units DU (P is an integer greater than 1). In response to entering the test mode (TSV / HB test mode) for the chip interconnect pathways, the data transmission paths between N*P global sense amplifier circuits in the N memory layers and the corresponding memory arrays are disconnected. In certain embodiments, the entire three-dimensional integrated memory chip can be caused to enter the test mode (TSV / HB test mode) for the chip interconnect pathways by configuring parameters in a mode register (MR) in the three-dimensional integrated memory chip.

[0054] The control device may include a processor and a storage medium, wherein the storage medium stores executable instructions corresponding to the test method, and when the processor executes the executable instructions, the test method is executed.

[0055] The control device of the embodiment of the present invention can execute the above-mentioned test method, can realize fault detection of chip interconnection paths and facilitate determination of fault locations, and can be used to improve the manufacturing process of three-dimensional integrated memory chips.

[0056] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for testing a three-dimensional integrated memory chip, characterized in that: The three-dimensional integrated memory chip includes a logic circuit layer and a first memory layer to an Nth memory layer stacked sequentially on one side of the logic circuit layer, where N is an integer greater than 1. The logic circuit layer and each memory layer are vertically interconnected via at least one chip interconnection path. Each memory layer includes a global sense amplifier circuit connected to the logic circuit layer via a corresponding chip interconnection path and a memory array that obtains data via the global sense amplifier circuit. The testing method includes: Step 1: Sending a chip select signal to the Mth storage layer through the logic circuit layer to select the Mth storage layer, where M is an integer and 1≦M≦N, and the remaining storage layers are shielded by the chip select signal; Step 2: Performing read and write operations on the Mth storage layer through the IO interface of the logic circuit layer, and disconnecting the data transmission path between the global sense amplifier circuit of the Mth storage layer that receives the written data and the corresponding storage array, so that the data written by the read and write operations is isolated in the global sense amplifier circuit, and then read out and returned to the logic circuit layer; Step three, determine whether the read data is consistent with the written data. If they are consistent, the chip interconnection path between the logic circuit layer and the Mth storage layer is faulty. If they are inconsistent, the chip interconnection path between the logic circuit layer and the Mth storage layer is faulty.

2. The testing method according to claim 1, wherein: The N global readout amplifier circuits respectively arranged in the first storage layer to the Nth storage layer are connected to the logic circuit layer using a common chip interconnection path, wherein the data of the read and write operations are written and read through the chip interconnection path between the Mth storage layer and the logic circuit layer.

3. The testing method according to claim 2, wherein: include: Set M to gradually increase from 1 or gradually decrease from N, and loop through steps 1 to 3 to determine one by one whether there is a fault in the chip interconnection path between the logic circuit layer and the Mth storage layer.

4. The testing method according to claim 3, wherein: When M is greater than 1 and the chip interconnection path between the logic circuit layer and the (M-1)th storage layer has no faults but the chip interconnection path between the logic circuit layer and the Mth storage layer has a fault, the fault is located in the chip interconnection path between the (M-1)th storage layer and the Mth storage layer.

5. The testing method according to claim 1, wherein: In the 1st storage layer to the Nth storage layer, a first number of the global read-out amplifier circuits respectively arranged in the first number of the storage layers share a first chip interconnection path connected to the logic circuit layer, and a second number of the global read-out amplifier circuits respectively arranged in the second number of the storage layers share a second chip interconnection path connected to the logic circuit layer.

6. The testing method according to claim 5, wherein: sequentially selecting the storage layers connected to the first chip interconnection path from near to far or from far to near relative to the logic circuit layer to perform steps 1 to 3 to determine whether the first chip interconnection path between the logic circuit layer and the corresponding storage layer has a fault, and if a fault exists, locating the fault in the chip interconnection path between the last two storage layers tested; Furthermore, along a direction from near to far or from far to near relative to the logic circuit layer, in order of distance from the logic circuit layer, the storage layers connected to the second chip interconnection path are sequentially selected to execute steps 1 to 3 to determine whether there is a fault in the second chip interconnection path between the logic circuit layer and the corresponding storage layer. If a fault exists, the fault is located in the second chip interconnection path between the last two storage layers tested.

7. The testing method according to claim 1, wherein: The global sense amplifier circuit includes a latch, wherein in the step 2, the data written into the Mth storage layer is temporarily stored in the corresponding latch of the global sense amplifier circuit.

8. The testing method according to claim 1, wherein: In the step 2, when performing a read and write test on the Mth storage layer, the frequency of the test clock used is lower than the frequency of the working clock used in the working mode of the three-dimensional integrated memory chip.

9. The testing method according to claim 8, wherein: The frequency of the working clock is 400 MHz, and the frequency of the test clock is between 40 MHz and 60 MHz.

10. The testing method according to any one of claims 1 to 9, characterized in that: The chip interconnection path includes TSVs arranged in the logic circuit layer and the first to (N-1)th storage layers to connect the front and back structures of the corresponding layers, and also includes a metal structure for connecting the logic circuit layer and the first storage layer and a metal structure for connecting two adjacent storage layers.

11. A control device, characterized in that: Used to control a three-dimensional integrated memory chip, wherein when testing whether the chip interconnection path in the three-dimensional integrated memory chip has a fault, the control device executes the testing method according to any one of claims 1 to 10.

12. The control device according to claim 11, wherein: When testing whether there is a fault in the chip interconnection path in the three-dimensional integrated memory chip, the control device sets the three-dimensional integrated memory chip to enter a test mode of the chip interconnection path; and in response to entering the test mode of the chip interconnection path, the data transmission path between the global read-out amplifier circuit for receiving write data in the N storage layers and the corresponding storage array is disconnected, and / or each storage layer includes P storage cells, P is an integer greater than 1, and in response to entering the test mode of the chip interconnection path, the data transmission paths between N*P global read-out amplifier circuits in the N storage layers and the corresponding storage array are all disconnected.

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