Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present application discloses a method for manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a silicon carbide substrate having a plurality of first mask structures formed on one side; forming a second mask structure on the exposed surface of the first mask structure; and etching the silicon carbide substrate using the second mask structure and the first mask structure as masks to form a high-aspect-ratio etched structure having a certain etch depth in the silicon carbide substrate. The second mask structure is made of the same hard mask material as the first mask structure. At the end of the etching, the second mask structure is completely etched away, exposing the surface of the remaining first mask structure. The present application can compensate for the insufficient thickness of the original mask, reduce damage, improve the protection of the silicon carbide substrate surface, and compensate for defects caused by the original mask itself, ensuring an ideal final etched morphology while achieving a larger etch depth-to-width ratio.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a semiconductor structure manufacturing method and a semiconductor structure. Background Art

[0002] As semiconductor devices develop toward higher integration and higher performance, silicon carbide (SiC), a wide-bandgap semiconductor material, has been widely used in high-power, high-frequency, and high-temperature electronic devices due to its excellent physical and chemical properties. However, during SiC plasma etching, especially at high aspect ratios, the protective effect of the mask layer on the SiC surface is often insufficient, resulting in suboptimal SiC trench morphology during etching. Therefore, research is needed to improve the protective effect of the surface mask layer to achieve the desired SiC trench morphology. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned problems existing in the prior art and to provide a semiconductor structure manufacturing method and a semiconductor structure to improve the protection effect of the mask layer and obtain an ideal silicon carbide etching morphology.

[0004] To achieve the above objectives, the technical solutions of this application are as follows:

[0005] According to a first aspect of the present application, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing a silicon carbide substrate, wherein a plurality of first mask structures are formed on one side of the silicon carbide substrate, and an opening is provided between two adjacent first mask structures to expose a surface of the silicon carbide substrate;

[0007] Depositing a second mask layer on the exposed surface of the first mask structure, wherein the deposition thickness of the second mask layer on the top surface of the first mask structure is greater than the deposition thickness on a single side surface of the first mask structure and the exposed surface of the silicon carbide substrate, so as to form a second mask structure in direct contact with the top surface and the side surface of the first mask structure;

[0008] Using the second mask structure and the first mask structure as masks, etching the silicon carbide substrate to form a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate;

[0009] In which, the material of the second mask structure and the material of the first mask structure are the same hard mask material, and the second mask structure is used to compensate for the original thickness of the first mask structure to reduce the original etching consumption of the first mask structure; at the end point of etching, the second mask structure is completely etched away to expose the remaining surface of the first mask structure.

[0010] In some embodiments, the second mask structure is further used to modify the surface of the first mask structure to improve morphological defects when etching the silicon carbide substrate.

[0011] In some embodiments, further comprising:

[0012] The etching depth is compared with the target depth. When the etching depth is less than the target depth, the process of depositing the second mask layer on the exposed surface of the first mask structure and etching the silicon carbide substrate using the second mask structure and the first mask structure as masks is repeated until the etching depth is consistent with the target depth.

[0013] In some embodiments, the number of times of depositing the second mask layer and etching the silicon carbide substrate is 1 to 3 times.

[0014] In some embodiments, when the silicon carbide substrate is etched multiple times, the etching amount of each etching decreases sequentially.

[0015] In some embodiments, when the silicon carbide substrate is etched multiple times, the etching time of each etching is reduced successively.

[0016] In some embodiments, after etching the silicon carbide substrate, the remaining thickness of the first mask structure is greater than 1 / 3 of the sum of the original thickness of the second mask structure and the original thickness of the first mask structure.

[0017] In some embodiments, a ratio of an original thickness of the second mask structure to an original thickness of the first mask structure is 1:10 to 1:2.

[0018] In some embodiments, the material of the first mask structure and the material of the second mask structure include silicon oxide.

[0019] In some embodiments, the silicon carbide substrate is etched using an anisotropic etching process.

[0020] In some embodiments, when depositing the second mask layer, the temperature is -10°C to 30°C, the pressure is 10mtorr to 200mtorr, the source power is 100W to 2000W, and the bias power is 10W to 100W.

[0021] In some embodiments, when etching the silicon carbide substrate, the temperature is -10°C to 30°C, the pressure is 10mtorr to 100mtorr, the source power is 100W to 3000W, and the bias power is 10W to 1000W.

[0022] In some embodiments, the high aspect ratio etch structure has an aspect ratio of 5:1 or greater.

[0023] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, which is obtained using the semiconductor structure manufacturing method provided by any embodiment of the first aspect above.

[0024] The embodiments of the present application may or at least have the following advantages:

[0025] (1) A new mask layer (second mask layer) is covered on the top and side surfaces of the first mask structure (original mask structure), and the deposition thickness of the second mask layer on the top surface of the first mask structure is greater than the deposition thickness on the single side surface of the first mask structure and the exposed surface of the silicon carbide substrate, so as to form a second mask structure in direct contact with the top and side surfaces of the first mask structure, and form a composite mask structure with the first mask structure. In this way, when the silicon carbide substrate is etched, on the one hand, when the thinner second mask layer located on the surface of the silicon carbide substrate is first etched away, the second mask layer located on the top of the first mask structure can retain a larger margin during the synchronous etching, so that the impact on the material consumption of the second mask layer on the top of the composite mask structure is very small, and thus sufficient consumption of the composite mask structure material in the subsequent etching process can be provided, so that the mask thickness that can be consumed is increased, which is equivalent to improving the etching selectivity between the original mask structure and the silicon carbide substrate, so that the remaining thickness of the original mask structure after etching is significantly increased compared with the existing process, thereby The invention effectively solves the problem of protection failure caused by insufficient mask layer thickness during high aspect ratio etching of silicon carbide, resulting in tilted silicon carbide trench angles and significant loss of trench critical dimensions. On the other hand, by forming a second mask layer on the exposed surface of the first mask structure after the first mask structure is formed, the original surface of the first mask structure is modified. This not only pre-improves the defects generated during patterning of the first mask structure, so that the morphology of the composite mask structure formed after the deposition of the second mask layer is good (i.e., the mask defects are completely eliminated), but also avoids the problem of mask etching defects that will eventually arise when directly depositing a second mask layer on the film layer before the formation of the first mask structure to increase the thickness of the original mask and then etching together to form a composite mask structure. Therefore, the ideal final etching morphology can be ensured. In addition, because the second mask layer is deposited relatively thinly on the side of the first mask structure and is gradually consumed during the etching of the silicon carbide substrate, it has little impact on the etching critical dimensions, thereby ensuring the final accuracy of the etching dimensions.

[0026] (2) By covering the original mask structure with a new mask structure, not only the original mask structure can be protected, but also the substrate material can be protected more effectively, forming a double protection mechanism. On the basis of ensuring the uniformity and accuracy of the etching morphology, the flexibility and reliability of the etching process are improved.

[0027] (3) It is easy to be compatible with existing processes, reduce manufacturing costs, and improve process flexibility.

[0028] (4) By covering the original mask structure with a new mask structure, the etching selectivity between the original mask layer and silicon carbide is improved, thereby achieving a larger etching depth-to-width ratio (the depth-to-width ratio can reach more than 10:1, and the current level is about 5:1).

[0029] Other advantages of the present application will be described in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a flow chart of a semiconductor structure manufacturing method according to a preferred embodiment of the present application.

[0031] Figure 2 A schematic structural diagram of a preferred embodiment of the present application after a first mask layer and a third mask layer are sequentially formed on a substrate.

[0032] Figure 3 A schematic structural diagram of a preferred embodiment of the present application after the third mask layer is patterned to form a third mask structure.

[0033] Figure 4 A schematic structural diagram of a preferred embodiment of the present application after the first mask layer is patterned to form a first mask structure.

[0034] Figure 5 A schematic diagram of the structure after removing the third mask structure provided in a preferred embodiment of the present application.

[0035] Figure 6 A schematic structural diagram of a composite mask structure after formation provided by a preferred embodiment of the present application.

[0036] Figure 7 A schematic diagram of the structure after grooves are formed on the surface of a substrate provided in a preferred embodiment of the present application.

[0037] In the figure, 10. silicon carbide substrate; 11. first mask layer; 111. first mask structure; 12. third mask layer; 121. third mask structure; 13. opening; 14. second mask layer; 141. second mask structure; 15. composite mask structure; 16. trench. DETAILED DESCRIPTION

[0038] Current silicon carbide etching processes can meet the requirements for etching structures with an aspect ratio of 5:1. To improve performance, a larger trench aspect ratio is required (for example, an aspect ratio of 10:1 or greater). For etching high-aspect-ratio silicon carbide trenches, high-energy plasma is required due to the extremely high chemical stability and mechanical strength of silicon carbide itself. However, using a traditional silicon oxide mask layer as an etch mask often results in the following drawbacks:

[0039] (1) Since the etching time of silicon carbide high aspect ratio trenches is long, silicon oxide is easily corroded during the long etching process, resulting in mask failure and inability to effectively protect the silicon carbide material underneath, which ultimately leads to problems such as the tilt of the silicon carbide trench angle and large loss of the critical trench dimensions.

[0040] (2) The original silicon oxide mask morphology may have morphological defects, such as micro-trench and footing, which will eventually be transferred to the silicon carbide trench.

[0041] (3) When exposed to long-term high-energy plasma, silicon oxide can easily form micro-masks or polymer deposits on the sidewalls, increasing the roughness of the sidewalls and transferring this roughness to the underlying silicon carbide material. Alternatively, after a long period of plasma etching, there is no longer enough silicon oxide to protect the underlying silicon carbide, which can also increase the sidewall roughness of the silicon carbide trench, thereby affecting device performance and stability.

[0042] (4) A large amount of heat is generated during the etching process. When the amount of effective silicon oxide is insufficient, it is easy to cause local temperature rise, which in turn causes mask deformation, resulting in abnormal morphology of the formed silicon carbide trench.

[0043] To address the above problems, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0044] Providing a silicon carbide substrate, wherein a plurality of first mask structures are formed on one side of the silicon carbide substrate, and an opening is provided between two adjacent first mask structures to expose a surface of the silicon carbide substrate;

[0045] Depositing a second mask layer on the exposed surface of the first mask structure, and utilizing different deposition selectivities so that the deposition thickness of the second mask layer on the top surface of the first mask structure is greater than the deposition thickness on a single side surface of the first mask structure and the exposed surface of the silicon carbide substrate, thereby forming a second mask structure in direct contact with the top surface and side surface of the first mask structure;

[0046] Using the second mask structure and the first mask structure as masks, etching the silicon carbide substrate to form a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate;

[0047] In which, the material of the second mask structure and the material of the first mask structure are the same hard mask material, and the second mask structure is used to compensate for the original thickness of the first mask structure to reduce the original etching consumption of the first mask structure; at the end point of etching, the second mask structure is completely etched away to expose the remaining surface of the first mask structure.

[0048] The embodiment of the present application forms a second mask structure by covering the top surface and side surfaces of the original first mask structure to form a composite mask structure, which can reduce damage to the original first mask structure during the etching process and significantly improve the protection effect on the surface of the silicon carbide substrate. This effectively solves the problem that the silicon oxide mask is easily corroded during the long etching process due to the long etching time of the silicon carbide high aspect ratio groove, resulting in mask failure and inability to effectively protect the silicon carbide material underneath, which ultimately leads to a large loss of the silicon carbide groove angle and critical groove dimensions.

[0049] Moreover, the second mask structure formed can make up for the defects brought by the original first mask structure itself, and can compensate for the insufficient thickness of the first mask structure to avoid mask deformation, thereby reducing the side wall roughness during the etching process, obtaining a vertical angle, ensuring the ideal final etching morphology, and improving device performance and stability.

[0050] Therefore, the embodiment of the present application can form a dual protection mechanism for the original first mask structure and the silicon carbide substrate material by covering a new second mask structure on the original first mask structure. It can improve the flexibility and reliability of the process while ensuring the uniformity and accuracy of the etching morphology, facilitate compatibility with existing processes, reduce manufacturing costs, and at the same time achieve a larger etching depth-to-width ratio.

[0051] The embodiment of the present application also provides a semiconductor structure obtained using the semiconductor structure manufacturing method provided by the embodiment of the present application.

[0052] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0053] refer to Figure 1 The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0054] Step S11: providing a silicon carbide substrate.

[0055] refer to Figure 2In some embodiments, a silicon carbide (SiC) substrate 10 (i.e., the substrate is made of silicon carbide) is used to manufacture a semiconductor structure according to an embodiment of the present application. However, it is understood that the semiconductor structure manufacturing method provided in the embodiment of the present application can also be applied to substrates other than silicon carbide.

[0056] In some embodiments, the silicon carbide substrate 10 may be undoped.

[0057] In some embodiments, the silicon carbide substrate 10 may be doped, for example, the silicon carbide substrate 10 may be N-type doped or P-type doped, to provide the silicon carbide substrate 10 with required electrical properties.

[0058] In some embodiments, a specific doping region, such as an N-type doping region or a P-type doping region, may be further formed on the silicon carbide substrate 10. The doping regions may have the same doping concentration or different doping concentrations.

[0059] In some embodiments, an integrated circuit, such as a transistor structure, may be fabricated on the silicon carbide substrate 10 .

[0060] Step S12: forming a first mask layer and a third mask layer in sequence on the surface of the silicon carbide substrate.

[0061] refer to Figure 2 In some embodiments, a hard mask layer deposition technique used in conventional SiC high-aspect-ratio etching processes is first used to deposit a first mask layer 11 (i.e., the material of the first mask layer 11 is a hard mask material) on the upper surface of the silicon carbide substrate 10. Then, a spin coating technique is used to form a third mask layer 12 on the upper surface of the first mask layer 11.

[0062] In some embodiments, a PECVD deposition process is used to deposit a first dielectric layer as the first mask layer 11 on the upper surface of the silicon carbide substrate 10. The deposition thickness of the first dielectric layer is the same as the deposition thickness of a dielectric hard mask layer used in a conventional SiC high aspect ratio etching process.

[0063] In some embodiments, the first dielectric layer material includes silicon oxide (SiO2). A silicon oxide deposition process, typically used in conventional SiC high-aspect-ratio etching processes, is used to deposit a first silicon oxide dielectric layer on the upper surface of the silicon carbide substrate 10, thereby forming a first mask layer 11 of silicon oxide. However, it should be understood that the material of the first mask layer 11 is not limited to silicon oxide. The semiconductor structure manufacturing method provided by the present invention will be further described below using a first mask layer 11 of silicon oxide as an example.

[0064] In some embodiments, a photoresist layer serving as third mask layer 12 is formed on the upper surface of first mask layer 11 using a spin coating process and then dried. The thickness of the photoresist layer is comparable to that used in conventional SiC high-aspect-ratio etching processes. Therefore, the material of third mask layer 12 is different from that of first mask layer 11, and thus the material of the subsequently formed third mask structure is also different from that of the first mask structure.

[0065] Step S13: patterning the third mask layer to form a third mask structure.

[0066] refer to Figure 3 In some embodiments, a photolithography process is used to pattern the photoresist layer serving as the third mask layer 12, forming a plurality of parallel photoresist patterns on the upper surface of the first silicon oxide dielectric layer (first mask layer 11), each photoresist pattern serving as a third mask structure 121. That is, the material of the third mask structure 121 includes photoresist.

[0067] It should be noted that Figure 3 The figure schematically illustrates the formation of three photoresist patterns (third mask structure 121) on the upper surface of the first silicon oxide dielectric layer. However, it is understood that at least two photoresist patterns, for example, two photoresist patterns, three photoresist patterns, four photoresist patterns, ten photoresist patterns, etc., may be formed on the upper surface of the first silicon oxide dielectric layer, and the present invention is not limited thereto.

[0068] Step S14: using the third mask structure as a mask, patterning the first mask layer to form a first mask structure, and then removing the third mask structure.

[0069] refer to Figure 4 In some embodiments, a hard mask opening process is employed, using the photoresist pattern serving as the third mask structure 121 as a mask, to etch and pattern the first dielectric layer of silicon oxide serving as the first mask layer 11, thereby forming a plurality of silicon oxide patterns on the upper surface of the silicon carbide substrate 10, each of which serves as a first mask structure 111. That is, the material of the first mask structure 111 includes silicon oxide.

[0070] After forming multiple first mask structures 111 on the upper surface of the silicon carbide substrate 10, an opening 13 is formed between any two adjacent first mask structures 111, exposing the upper surface of the silicon carbide substrate 10 at the bottom of the opening 13. The opening 13 serves as a window for subsequent etching of the silicon carbide substrate 10.

[0071] In some embodiments, the process of etching and patterning the first silicon oxide dielectric layer serving as the first mask layer 11 includes a plasma dry etching process.

[0072] In some embodiments, the process of etching and patterning the first silicon oxide dielectric layer serving as the first mask layer 11 uses process gases including, but not limited to, fluorine-based gases, O 2 , Ar, and the like.

[0073] In some embodiments, the fluorine-based gas includes at least one of CHF3, CF4, and C4F8.

[0074] In some embodiments, the temperature of the etching and patterning process for the first silicon oxide dielectric layer serving as the first mask layer 11 is 10° C. to 40° C. For example, the temperature may be 10° C., 15° C., 20° C., 25° C., 30° C., 35° C., or 40° C., or any value between any two of the aforementioned temperature values.

[0075] In some embodiments, the pressure during the etching and patterning process of the first silicon oxide dielectric layer serving as the first mask layer 11 is 5 mTorr to 50 mTorr. For example, the pressure may be 5 mTorr, 6 mTorr, 7 mTorr, 8 mTorr, 9 mTorr, 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, or 50 mTorr, or any value between any two of the aforementioned pressure values.

[0076] In some embodiments, the source power for etching and patterning the first silicon oxide dielectric layer serving as the first mask layer 11 is 100 W to 2000 W. For example, the source power may be 100 W, 200 W, 300 W, 600 W, 800 W, 1000 W, 1200 W, 1500 W, or 2000 W, or any value between any two of the foregoing source power values.

[0077] In some embodiments, the bias power for etching and patterning the first silicon oxide dielectric layer serving as the first mask layer 11 is 10 W to 1000 W. For example, the bias power may be 10 W, 20 W, 60 W, 95 W, 100 W, 200 W, 300 W, 500 W, 700 W, or 1000 W, or any value between any two of the foregoing bias power values.

[0078] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer serving as the first mask layer 11, the RF source for generating bias power has a fixed RF frequency, for example, the RF frequency may be fixed at 13.56 MHz, but is not limited thereto.

[0079] In some embodiments, a high temperature stripping process (asher process) is used to remove the photoresist, that is, to remove the photoresist pattern serving as the third mask structure 121. After removing the photoresist pattern, the top surface and side surfaces of the first mask structure 111 are exposed, and the structure thereof is as follows: Figure 5shown.

[0080] In some embodiments, when a high-temperature stripping process is used to remove the photoresist pattern serving as the third mask structure 121 , the process gas used includes at least one of O 2 , FG (a mixture of H 2 and N 2 ), N 2 , etc., but is not limited thereto.

[0081] In some embodiments, when a high-temperature stripping process is used to remove the photoresist pattern serving as the third mask structure 121, the temperature is 100° C. to 300° C. For example, the temperature can be 100° C., 120° C., 150° C., 180° C., 200° C., 230° C., 270° C., or 300° C., or any value between any two of the foregoing temperature values.

[0082] In some embodiments, when a high-temperature stripping process is used to remove the photoresist pattern serving as the third mask structure 121, the pressure is between 100 mTorr and 1000 mTorr. For example, the pressure can be 100 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, 500 mTorr, 600 mTorr, 700 mTorr, 800 mTorr, 900 mTorr, or 1000 mTorr, or any value between any two of the foregoing pressure values.

[0083] In some embodiments, when a high-temperature stripping process is used to remove the photoresist pattern serving as the third mask structure 121, the source power is 100 W to 5000 W. For example, the source power can be 100 W, 200 W, 500 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, 4000 W, 4500 W, or 5000 W, or any value between any two of the foregoing source power values.

[0084] In some embodiments, when a high-temperature stripping process is used to remove the photoresist pattern serving as the third mask structure 121 , the bias power is zero.

[0085] Step S15: forming a second mask layer on the exposed surface of the first mask structure to form a second mask structure, and forming a composite mask structure consisting of the first mask structure and the second mask structure.

[0086] refer to Figure 6 In some embodiments, a PECVD deposition process is used to deposit a second dielectric layer serving as the second mask layer 14 on the exposed upper surface of the silicon carbide substrate 10 and the surface (top surface and side surfaces) of the first mask structure 111 .

[0087] In some embodiments, the material of the second dielectric layer is the same as that of the first dielectric layer, that is, the material of the second mask structure to be formed subsequently is the same as that of the first mask structure 111 , and they are the same hard mask material.

[0088] In some embodiments, when the first dielectric layer is made of silicon oxide, the second dielectric layer is also made of silicon oxide. The semiconductor structure manufacturing method provided by the present invention is further described below using the silicon oxide second dielectric layer as the second mask layer 14 as an example.

[0089] In some embodiments, a second silicon oxide dielectric layer is deposited on the upper surface of the silicon carbide substrate 10 and the surface of the first mask structure 111 to form the second mask layer 14. During deposition, the second silicon oxide dielectric layer (second mask layer 14) is preferentially deposited on the top surface of the silicon carbide substrate 10, the top surface of the first mask structure 111, and the side surfaces of the first mask structure 111, utilizing the different deposition selectivities of the second silicon oxide dielectric layer (second mask layer 14) on the upper surface of the silicon carbide substrate 10, the top surface of the first mask structure 111, and the side surfaces of the first mask structure 111. This results in the second silicon oxide dielectric layer being deposited at a thickness significantly greater on the top surface of the first mask structure 111 than on a single side surface of the first mask structure 111 and the upper surface of the silicon carbide substrate 10. This results in the second silicon oxide dielectric layer being completely coated on the surfaces (top and side surfaces) of the first mask structure 111, thereby forming a composite mask structure 15 of silicon oxide material (i.e., the composite mask structure 15 is made entirely of the same silicon oxide material) formed by the first mask structure 111 and the second mask structure 141 in direct and intimate contact. The second mask structure 141 located on the side of the first mask structure 111 extends downward along the side of the first mask structure 111 until it contacts the upper surface of the silicon carbide substrate 10. In addition, the second dielectric layer of silicon oxide deposited on the upper surface of the silicon carbide substrate 10 is not a component of the second mask structure 141.

[0090] Silicon carbide material itself has extremely high chemical stability and mechanical strength, so high-energy plasma is required during the etching process. When using a traditional silicon oxide mask layer (equivalent to the first mask layer) as an etching mask, due to the long etching time of the high aspect ratio silicon carbide trench, the silicon oxide mask material is easily corroded during the long etching process, resulting in mask failure and inability to effectively protect the silicon carbide material underneath, ultimately leading to problems such as tilted silicon carbide trench angles and significant loss of critical trench dimensions. In addition, the original silicon oxide mask (equivalent to the first mask structure) may have morphological defects such as micro-trench and footing, which will eventually be transferred to the silicon carbide trench. Moreover, under the bombardment of high-energy plasma for a long time, the original silicon oxide mask is prone to forming micro-masks or polymer deposits on the sidewalls, resulting in increased sidewall roughness and transfer to the silicon carbide material below. Alternatively, after a long plasma etch, there may not be enough silicon oxide mask to protect the underlying silicon carbide, which can increase the sidewall roughness of the silicon carbide trench, thereby affecting device performance and stability. Furthermore, the etching process generates a large amount of heat. When the amount of effective silicon oxide mask is insufficient, it can easily lead to local temperature increases, which in turn can cause mask deformation, resulting in abnormal morphology of the resulting silicon carbide trench.

[0091] In view of this, the embodiments of the present application utilize a new mask structure (second mask structure 141) overlying the original mask structure (first mask structure 111). By forming a composite mask structure 15, damage to the original mask structure during the etching process is reduced, significantly improving the protection of the surface of the silicon carbide substrate 10. This effectively addresses the problem of ineffective mask layer protection during high-aspect-ratio etching, resulting in tilted silicon carbide trench angles and significant loss of critical trench dimensions. Furthermore, by overlaying the new second mask structure 141 over the first mask structure 111 to modify the surface of the first mask structure 111, defects that may exist in the first mask structure 111 during patterning are effectively improved, and the insufficient thickness of the first mask structure 111 is compensated, thereby reducing the etching consumption of the original first mask structure 111. This reduces sidewall roughness, achieves a perpendicular angle, and thus improves topographical defects during etching of the silicon carbide substrate 10, ensuring an ideal final etched topography. At the same time, the second mask structure 141 can not only protect the original first mask structure 111, but also play a dual protective role of more effectively protecting the silicon carbide substrate 10 material, thereby improving the flexibility and reliability of the etching process while ensuring the uniformity and accuracy of the etching morphology.

[0092] In some embodiments, when depositing the second silicon oxide dielectric layer, the process gas used includes a combination of HBr, SiCl 4 , SiF 4 O 2 , and Ar.

[0093] It should be noted that during the deposition of the second silicon oxide dielectric layer, the components generated by the reaction of the process gas are more Si and O, so it is easier to deposit on the surface of the first mask structure 111 of the silicon oxide material than on the silicon carbide interface, especially preferentially deposited on the top surface of the first mask structure 111, while the actual deposition amount on the upper surface of the silicon carbide substrate 10 is very small, and the deposition amount on the side of the first mask structure 111 is also small. Figure 6 The purpose of this deposition step is to thicken the overall mask layer (composite mask structure 15 ) so that during the subsequent etching process of the silicon carbide substrate 10 , the underlying silicon carbide etching material can be better protected to obtain a better etching morphology.

[0094] It should also be noted that the purpose of depositing the second mask layer 14 and forming the second mask structure 141 in the embodiment of the present application is not simply to increase the thickness of the first mask structure 111. Otherwise, it is only necessary to directly increase the deposition thickness of the first mask layer 11, or to continue to deposit the second mask layer 14 on the basis of the first mask layer 11, and then etch to form the mask structure in one step to achieve the purpose of increasing the mask thickness. Instead, it is to modify the surface of the first mask structure 111 by depositing the second mask layer 14 on the already formed first mask structure 111, so as to pre-improve the defects generated by the first mask structure 111 during patterning, so that the morphology of the composite mask structure 15 formed after the deposition of the second mask layer 14 is good (that is, the mask defects are eliminated), thereby ensuring the acquisition of the final ideal etching morphology.

[0095] In some embodiments, when depositing the second silicon oxide dielectric layer serving as the second mask layer 14 , the temperature is between −10° C. and 30° C. For example, the temperature may be −10° C., −5° C., 0° C., 5° C., 10° C., 20° C., or 30° C., or any value between any two of the aforementioned temperature values.

[0096] In some embodiments, the pressure during deposition of the second silicon oxide dielectric layer is between 10 mtorr and 200 mtorr. For example, the pressure may be 10 mtorr, 20 mtorr, 30 mtorr, 50 mtorr, 70 mtorr, 100 mtorr, 120 mtorr, 150 mtorr, 180 mtorr, or 200 mtorr, or any value between any two of the aforementioned pressure values.

[0097] In some embodiments, when depositing the second silicon oxide dielectric layer, the source power is 100 W to 2000 W. For example, the source power can be 100 W, 300 W, 500 W, 700 W, 900 W, 1000 W, 1300 W, 1500 W, or 2000 W, or any value between any two of the foregoing source power values.

[0098] In some embodiments, when depositing the second silicon oxide dielectric layer, the bias power is 10 W to 100 W. For example, the bias power can be 10 W, 20 W, 30 W, 40 W, 50 W, 60 W, 70 W, 80 W, 90 W, or 100 W, or any value between any two of the foregoing bias power values.

[0099] In some embodiments, when depositing the second silicon oxide dielectric layer, the RF source used to generate source power has a fixed RF frequency, for example, the RF frequency used to generate source power may be fixed at 13.56 MHz, but is not limited thereto.

[0100] In some embodiments, when depositing the second silicon oxide dielectric layer, the RF source used to generate bias power has a fixed RF frequency, for example, the RF frequency used to generate bias power may be fixed at 13.56 MHz, but is not limited thereto.

[0101] In some embodiments, when depositing the second silicon oxide dielectric layer, the RF frequency of the RF source used to generate the source power is the same as the RF frequency of the RF source used to generate the bias power. For example, the RF frequency of the RF source used to generate the source power and the RF frequency of the RF source used to generate the bias power are 13.56 MHz, but this is not limited to this.

[0102] In some embodiments, when depositing the second silicon oxide dielectric layer, the deposition time is optimized and adjusted according to the thickness of the original mask layer (first mask layer 11 ), and the deposition time is proportional to the deposition thickness of the second mask layer 14 (second dielectric layer) on the top surface of the first mask structure 111 .

[0103] In some embodiments, the ratio of the deposition thickness of the second mask layer 14 on the top surface of the first mask structure 111 to the deposition thickness of the second mask layer 14 on the upper surface of the silicon carbide substrate 10 is not less than 10:3, not less than 10:2 or not less than 10:1, etc., but is not limited thereto.

[0104] By adopting the above-mentioned process gas system and selecting and combining the values of various process parameters within the above-mentioned temperature, pressure, source power, and bias power ranges, a second mask layer 14 of the required thickness and high quality can be formed on the top surface of the first mask structure 111, so as to form the required second mask structure 141 by coating on the surface of the first mask structure 111, and together with the first mask structure 111 below, form a composite mask structure 15, which can significantly improve the protection effect of the entire mask layer on the silicon carbide substrate 10, effectively improve the defects of the first mask structure 111, and compensate for the insufficient original thickness of the first mask structure 111, reduce the sidewall roughness, obtain a vertical angle, and avoid mask deformation caused by high temperature, thereby laying the foundation for subsequently obtaining an ideal silicon carbide etching morphology.

[0105] In some embodiments, the ratio of the thickness (original thickness) of the second mask structure 141 to the thickness (original thickness) of the first mask structure 111 in a direction perpendicular to the upper surface of the silicon carbide substrate 10 is 1:10 to 1:2. For example, the ratio of the thickness of the second mask structure 141 to the thickness of the first mask structure 111 is 1:10, 1:9, 1:8, 1:7, 1:6, 1:5, 1:4, 1:3, or 1:2, or any ratio between any two of the foregoing ratios.

[0106] It's worth noting that if the existing first mask layer 11 (first mask structure 111) is sufficiently thick, only a thinner second mask layer 14 (second mask structure 141) needs to be deposited on top of the first mask structure 111; vice versa. When etching the silicon carbide substrate 10, the second mask layer 14 acts as a dielectric protection layer. Its primary function is to prevent poor etched material morphology due to the insufficient thickness of the existing mask layer during high-aspect-ratio etching. Therefore, the thickness of the second mask layer 14 is intended to appropriately compensate for the thickness of the existing mask layer, but it does not completely replace it.

[0107] Step S16: using the composite mask structure as a mask, etching the silicon carbide substrate to form a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate.

[0108] refer to Figure 7 In some embodiments, a plasma dry etching process is used to etch downward the silicon carbide substrate 10 using the composite mask structure 15 as a mask, thereby forming a silicon carbide high aspect ratio etching structure located in the silicon carbide substrate 10 and having a certain etching depth on the upper surface of the silicon carbide substrate 10 (i.e., the bottom surface of the opening 13) between any two adjacent composite mask structures 15 of silicon oxide material.

[0109] It should be noted that when etching downwards on the silicon carbide substrate 10, it is necessary to first etch away a small amount of silicon oxide (the second dielectric layer) located on the bottom surface of the opening 13, and then continue etching the exposed silicon carbide substrate 10. Because the silicon oxide (the second dielectric layer) located on the bottom surface of the opening 13 is very thin, a large amount of the silicon oxide second dielectric layer located on the top of the composite mask structure 15 remains during the etching process, and the impact on the consumption of the silicon oxide second dielectric layer on the top of the composite mask structure 15 is minimal. Therefore, sufficient consumption of the silicon oxide material of the composite mask structure 15 can be ensured during the etching process, avoiding the problem of insufficient remaining silicon oxide mask material at the etching endpoint.

[0110] In some embodiments, the silicon oxide material of the composite mask structure 15 is gradually consumed during the etching process. Therefore, when the etching process reaches the end point, the thickness of the remaining composite mask structure 15 is less than the thickness of the original first mask structure 111. In other words, at the end point of the etching process, at least the second mask structure 141 located on the top surface of the first mask structure 111 is removed, exposing the remaining top surface of the first mask structure 111.

[0111] In some embodiments, at the end point of etching, the second mask structure 141 is completely etched away, exposing the top surface and side surfaces of the remaining first mask structure 111 .

[0112] By coating the second mask layer 14 on the first mask structure 111 to form the second mask structure 141, the thickness of the resulting composite mask structure 15 is increased compared to the thickness of the original first mask structure 111, thereby increasing the available mask thickness for consumption. This is equivalent to improving the etching selectivity between the silicon oxide of the original mask layer and the silicon carbide substrate 10 (i.e., reducing the ratio of the silicon oxide consumption of the original mask layer to the consumption of the silicon carbide substrate 10). This significantly increases the remaining thickness of the silicon oxide mask material after etching in the embodiment of the present application compared to the remaining thickness of the silicon oxide mask material in the existing process, thereby avoiding significant damage to the critical dimensions at the top of the etching, thereby ensuring the verticality of the etching angle. It also avoids defects such as rough sidewalls caused by significant damage to the mask layer during the etching process. This prevents these defects from being directly transferred to the underlying silicon carbide etched material during the subsequent etching process, resulting in poor sidewall roughness of the etched material.

[0113] In some embodiments, the high aspect ratio etched structure includes a deep trench, deep via, or through via with an aspect ratio of 5:1 or greater. The following describes the embodiments of the present application in detail, taking the high aspect ratio etched structure being the trench 16 as an example.

[0114] In some embodiments, an anisotropic etching process is performed to etch the silicon carbide substrate 10 to form the trench 16. The process gas used includes at least one of SF6, SiCl4, and SiF4, as well as O2. In addition, at least one of N2, He, Ar, HBr, and BCl3 may also be used simultaneously. N2 and He are used as common dilution dissociation gases, while Ar and BCl3 are used as dissociation gases with a certain bombardment capability. Furthermore, the etching method is primarily anisotropic etching (as opposed to the isotropic etching of the Bosch process used for deep silicon etching).

[0115] In some embodiments, after etching the silicon carbide substrate 10 , the remaining thickness of the first mask structure 111 is greater than 1 / 3 of the sum of the original thickness of the second mask structure 141 and the original thickness of the first mask structure 111 (ie, the original thickness of the composite mask structure 15 ).

[0116] In some embodiments, when etching the silicon carbide substrate 10 , process gases used include SF 6 , BCl 3 , O 2 , N 2 , Ar, and He.

[0117] In particular, when a very high aspect ratio is required, for example, when the aspect ratio reaches 10:1 or greater, when etching the silicon carbide substrate 10 , the process gas used includes HBr and at least one of SiCl 4 and SiF 4 .

[0118] In some embodiments, when etching the silicon carbide substrate 10 , the temperature is -10° C. to 30° C. For example, the temperature can be -10° C., -5° C., -1° C., 0° C., 3° C., 5° C., 10° C., 20° C., or 30° C., or any value between any two of the foregoing temperature values.

[0119] In some embodiments, the pressure during etching of the silicon carbide substrate 10 is 10 mtorr to 100 mtorr. For example, the pressure may be 10 mtorr, 20 mtorr, 30 mtorr, 40 mtorr, 50 mtorr, 60 mtorr, 70 mtorr, 80 mtorr, 90 mtorr, or 100 mtorr, or any value between any two of the aforementioned pressure values.

[0120] In some embodiments, when etching the silicon carbide substrate 10 , the source power is 100 W to 3000 W. For example, the source power can be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the foregoing source power values.

[0121] In some embodiments, when etching the silicon carbide substrate 10 , the bias power is 10 W to 1000 W. For example, the bias power can be 10 W, 50 W, 100 W, 200 W, 300 W, 400 W, 500 W, 600 W, 700 W, 800 W, 900 W, or 1000 W, or any value between any two of the foregoing bias power values.

[0122] In some embodiments, when etching the silicon carbide substrate 10, the RF source used to generate source power has a fixed RF frequency, for example, the RF frequency used to generate source power may be fixed at 13.56 MHz, but is not limited thereto.

[0123] In some embodiments, when etching the silicon carbide substrate 10, the RF source used to generate bias power uses a variable frequency RF frequency. For example, the RF frequency used to generate bias power can be alternately switched between 13.56 MHz and 400 kHz to obtain a trench 16 with a higher aspect ratio (e.g., greater than 10:1), but the present invention is not limited thereto.

[0124] Step S17: Compare the etching depth with the target depth. When the etching depth reaches the target depth, execute step S18; when the etching depth is less than the target depth, return to execute step S15.

[0125] After the etching process is performed and the silicon carbide substrate 10 is etched once, the etched depth of the formed trench 16 is compared with the target depth, and a determination is made to determine whether to terminate the etching process on the silicon carbide substrate 10. If the etching depth has reached the target depth, the process is terminated (step S18). Conversely, if the etching depth is less than the target depth, the process returns to repeating the process of depositing the second mask layer 14 (step S15) and etching the silicon carbide substrate 10 (step S16). Specifically, the process of depositing the second mask layer 14 on the exposed surface of the first mask structure 111 and etching the silicon carbide substrate 10 using the second mask structure 141 and the first mask structure 111 as masks is repeated until the etching depth (total etching depth, i.e., the total depth of the formed trench 16) is consistent with the target depth. At this point, the entire etching process on the silicon carbide substrate 10 is terminated, completing the fabrication of the semiconductor structure (i.e., completing step S18).

[0126] The above-mentioned deposition process of depositing the second mask layer 14 on the top surface of the first mask structure 111 and forming the second mask structure 141, and the process of etching the silicon carbide substrate 10 can be used as two process steps (process links) in the overall process of etching silicon carbide high aspect ratio trenches. Therefore, they can be included in the process menu for silicon carbide high aspect ratio trench etching for control and can be completed in the same plasma etching chamber (equipment).

[0127] It should be noted that during the repeated deposition of the second silicon oxide dielectric layer (second mask layer 14), a small amount of the second silicon oxide dielectric layer is also deposited on the inner wall of the already formed trench 16. During the subsequent etching step, the small amount of the second silicon oxide dielectric layer deposited on the inner wall of the already formed trench 16 can also provide a certain degree of protection for the sidewalls of the trench 16 during the etching process, thereby preventing the sidewalls of the trench 16 from being over-etched, thereby avoiding problems such as increased roughness of the sidewalls of the trench 16 and non-perpendicular angles of the trench 16.

[0128] In some embodiments, the number of cycles for depositing the second mask layer 14 and etching the silicon carbide substrate 10 is 1 to 5, 1 to 4, or 1 to 3. For example, the number of cycles can be 1, 2, 3, 4, or 5. The number of cycles can be determined based on the thickness of the original mask layer and the required increase in aspect ratio. When the thickness of the original mask layer is relatively small, the number of cycles needs to be relatively increased. When the aspect ratio increases, the number of cycles also needs to be relatively increased.

[0129] In some embodiments, when the number of etching cycles on the silicon carbide substrate 10 is multiple, after each etching process on the silicon carbide substrate 10 is performed, the remaining thickness of the composite mask structure 15 is greater than 1 / 3 of the original thickness of the composite mask structure 15. For example, after any one cyclic etching process is performed, the remaining thickness of the composite mask structure 15 is greater than 3 / 9, greater than 4 / 9, greater than 4 / 9, greater than 4.5 / 9, greater than 6 / 9, greater than 7 / 9, or greater than 8 / 9 of the original thickness of the composite mask structure 15, but is not limited thereto.

[0130] In some embodiments, when the silicon carbide substrate 10 is etched for multiple cycles, the etching amount (depth) of each cycle is different, but the total etching depth after multiple etchings should be consistent with the target depth.

[0131] In some embodiments, when the silicon carbide substrate 10 is etched for multiple cycles, the etching amount of each cycle decreases sequentially, but the total etching depth after multiple etchings should be consistent with the target depth.

[0132] In some embodiments, when the silicon carbide substrate 10 is etched multiple times, the etching time of each etching cycle is different, but the total etching time of the multiple etching cycles should be consistent with the overall etching setting time in the process menu of the silicon carbide high aspect ratio trench etching process.

[0133] In some embodiments, when the silicon carbide substrate 10 is etched multiple times, the etching time of each etching cycle decreases sequentially. However, the total etching time of the multiple etchings should be consistent with the overall etching setting time in the process menu of the silicon carbide high aspect ratio trench etching process.

[0134] Step S18: End.

[0135] When the etching depth reaches the target depth so that the aspect ratio of the formed trench 16 meets the requirement, etching of the silicon carbide substrate 10 can be stopped, and the high aspect ratio etching process for the silicon carbide substrate 10 is completed.

[0136] In some embodiments, after etching is completed, the polymer produced by etching can be completely removed by conventional wet processing (such as chemical cleaning) or desizing process to ensure the integrity of the final silicon carbide etching morphology.

[0137] In some embodiments, the aspect ratio of the resulting trench 16 is at least 5:1. For example, current silicon carbide etching processes can form trenches with an aspect ratio of 5:1. However, using the semiconductor structure manufacturing method provided in the embodiments of the present application, the aspect ratio of the formed trench 16 can be increased to 10:1 or greater.

[0138] An embodiment of the present application further provides a semiconductor structure, which is obtained using the semiconductor structure manufacturing method corresponding to the above embodiment.

[0139] refer to Figure 7 In some embodiments, the semiconductor structure includes a silicon carbide substrate 10 , and a trench 16 formed on the silicon carbide substrate 10 using the semiconductor structure manufacturing method of the above embodiment to form a silicon carbide device.

[0140] In some embodiments, the aspect ratio of the trench 16 in the semiconductor structure is at least 5:1.

[0141] In some embodiments, the aspect ratio of the trench 16 on the semiconductor structure is greater than 10:1.

[0142] In some embodiments, the trench 16 on the semiconductor structure may be a silicon carbide super junction trench structure.

[0143] In some embodiments, the silicon carbide device formed by the semiconductor structure can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), or other types of memory.

[0144] In a third aspect, embodiments of the present application further provide a plasma processing apparatus for performing the semiconductor structure manufacturing method corresponding to the above embodiments to manufacture the semiconductor structure corresponding to the above embodiments. The plasma processing apparatus may be, for example, an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus.

[0145] In other aspects, embodiments of the present application further provide an electronic device comprising the semiconductor structure of the above embodiments or a semiconductor structure obtained using the semiconductor structure manufacturing method of the above embodiments. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, or the like.

[0146] In summary, the embodiment of the present application forms a composite mask structure 15 by forming a second mask structure 141 overlying the original first mask structure 111. This reduces damage to the first mask structure 111 during the etching process, significantly improving the protection of the surface of the silicon carbide substrate 10. Furthermore, the formed second mask structure 141 can compensate for defects inherent in the original first mask structure 111 and compensate for insufficient thickness of the second mask structure 141, thereby avoiding mask deformation and ensuring an ideal final etched profile. This improves device performance and stability, enhances process flexibility and reliability while ensuring uniformity and precision in the etched profile, facilitates compatibility with existing processes, reduces manufacturing costs, and achieves a larger etch aspect ratio.

[0147] The above are only preferred embodiments of the present application, and the embodiments are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made using the description and drawings of the present application should also be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a silicon carbide substrate, wherein a plurality of first mask structures are formed on one side of the silicon carbide substrate, and an opening is provided between two adjacent first mask structures to expose a surface of the silicon carbide substrate; Depositing a second mask layer on the exposed surface of the first mask structure, wherein the deposition thickness of the second mask layer on the top surface of the first mask structure is greater than the deposition thickness on a single side surface of the first mask structure and the exposed surface of the silicon carbide substrate, so as to form a second mask structure in direct contact with the top surface and the side surface of the first mask structure; Using the second mask structure and the first mask structure as masks, etching the silicon carbide substrate to form a silicon carbide high aspect ratio etching structure located in the silicon carbide substrate and having a certain etching depth on the bottom surface of the opening; The second mask structure is made of the same hard mask material as the first mask structure, and the second mask structure is used to compensate for the insufficient thickness of the first mask structure, thereby increasing the thickness of the mask provided for consumption and reducing the original etching consumption of the first mask structure. At the end point of etching, the second mask structure is completely etched away, exposing the remaining surface of the first mask structure. The second mask structure is also used to modify the surface of the first mask structure to eliminate mask defects and improve morphological defects when etching the silicon carbide substrate; the material of the first mask structure and the material of the second mask structure are silicon oxide, forming a composite mask structure of an integral silicon oxide material composed of the first mask structure and the second mask structure; the ratio of the original thickness of the second mask structure to the original thickness of the first mask structure is 1:10 to 1:

2. After etching the silicon carbide substrate, the remaining thickness of the composite mask structure is less than the original thickness of the first mask structure, so that the remaining thickness of the first mask structure is more than 1 / 3 of the sum of the original thickness of the second mask structure and the original thickness of the first mask structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: The etching depth is compared with the target depth. When the etching depth is less than the target depth, the process of depositing the second mask layer on the exposed surface of the first mask structure and etching the silicon carbide substrate using the second mask structure and the first mask structure as masks is repeated until the etching depth is consistent with the target depth.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The number of times the second mask layer is deposited and the silicon carbide substrate is etched is 1 to 3 times; and / or when the silicon carbide substrate is etched multiple times, the etching amount of each time decreases successively; and / or when the silicon carbide substrate is etched multiple times, the etching time of each time decreases successively.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The silicon carbide substrate is etched using an anisotropic etching process.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: When depositing the second mask layer, the temperature is -10°C to 30°C, the pressure is 10mtorr to 200mtorr, the source power is 100W to 2000W, and the bias power is 10W to 100W; and / or, when etching the silicon carbide substrate, the temperature is -10°C to 30°C, the pressure is 10mtorr to 100mtorr, the source power is 100W to 3000W, and the bias power is 10W to 1000W; and / or, the aspect ratio of the high aspect ratio etching structure is greater than 5:

1.

6. A semiconductor structure, characterized in that The method for manufacturing a semiconductor structure is used as claimed in any one of claims 1 to 5.

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