Three-dimensional integrated chip, heat dissipation structure and preparation method thereof

Abstract

The invention provides a three-dimensional integrated chip, a heat dissipation structure and a preparation method thereof. The preparation method of the heat dissipation structure comprises the following steps: providing a first wafer and a second wafer; forming a first dielectric layer on one surface of the first wafer; a groove is formed in the first dielectric layer through etching, and the groove penetrates through the two ends of the first dielectric layer in the length direction; forming a second dielectric layer on the surface, opposite to the first dielectric layer, of the second wafer; carrying out heterogeneous integration on the second dielectric layer and the first dielectric layer; and aligning and connecting the two ends of the groove with the inlet and the outlet of the circulating heat dissipation pipeline of the packaging substrate respectively, and packaging. The micro-channel texturing is performed on the bonding surface of the wafer, so that the quality and the reliability of the bonding interface are effectively improved, and meanwhile, the heat dissipation channel is arranged at the nearest position close to the chip function layer, so that the heat management capability of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular, to a three-dimensional integrated chip, a heat dissipation structure and a preparation method thereof. Background Art

[0002] With the increasing chip size and integration degree of functions, the internal interconnection structure of the chip is gradually miniaturized, and the number of nanoscale metal interconnection layers is as high as 13-14 layers. This not only has a greater impact on the electrical power consumption of the chip, but also the heat dissipation problem of the chip gradually becomes prominent. Therefore, for three-dimensional integrated circuits, the heat dissipation problem is an important research topic at present. In the prior art, the heat dissipation function of the chip is usually realized by arranging heat dissipation channels or heat dissipation components outside the chip. In this way, heat dissipation and cooling can only be carried out outside the chip. For three-dimensional integrated chips, it is very difficult to dissipate the internal heat of the chip. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, an embodiment of the present invention provides a three-dimensional integrated chip, a heat dissipation structure and a preparation method thereof, so that the heat dissipation structure is close to the functional layer of the chip, and the heat dissipation effect of the three-dimensional integrated chip is improved.

[0004] An embodiment of the first aspect of the present invention provides a preparation method for a heat dissipation structure of a three-dimensional integrated chip, including:

[0005] Providing a first wafer and a second wafer;

[0006] Forming a first dielectric layer on one surface of the first wafer;

[0007] Etching a groove in the first dielectric layer, and the groove penetrates through both ends of the first dielectric layer along the length direction;

[0008] Forming a second dielectric layer on the surface of the second wafer opposite to the first dielectric layer;

[0009] Heterogeneously integrating the second dielectric layer and the first dielectric layer;

[0010] Aligning and connecting the two ends of the groove with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate respectively and packaging.

[0011] In some embodiments, the way of heterogeneously integrating the second dielectric layer and the first dielectric layer is surface-activated heterogeneous integration or plasma-activated heterogeneous bonding.

[0012] In some embodiments, the circulating heat dissipation pipeline of the packaging substrate is a liquid circulating heat dissipation pipeline or a gas circulating heat dissipation pipeline.

[0013] A heat dissipation structure for a three-dimensional integrated chip according to a second aspect embodiment of the present invention includes: a first wafer and a second wafer. One surface of the first wafer has a first dielectric layer, and a groove formed by etching is provided on the first dielectric layer. The groove penetrates through both ends of the first dielectric layer along the length direction, and both ends of the groove are adapted to be respectively aligned and packaged with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate; the surface of the second wafer has a second dielectric layer, and the second dielectric layer is opposite to the first dielectric layer and is heterogeneously integrated.

[0014] In some embodiments, a plurality of the grooves are provided and arranged in parallel.

[0015] In some embodiments, the materials of the first dielectric layer and the second dielectric layer are SiO2 or a stack of SiO2 and Al2O3.

[0016] In some embodiments, the depth of the groove is equal to the depth of the first dielectric layer.

[0017] In some embodiments, the width of the groove is 100um - 500um, and the interval between adjacent two grooves is 1mm - 5mm.

[0018] In some embodiments, the thicknesses of both the first dielectric layer and the second dielectric layer are 500nm - 2000nm.

[0019] A three-dimensional integrated chip according to a third aspect embodiment of the present invention includes the above heat dissipation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings.

[0021] Wherein:

[0022] Figure 1 is a schematic structural diagram of the heat dissipation structure of the three-dimensional integrated chip in the embodiment of the present invention;

[0023] Figure 2 is a flowchart of the preparation method of the heat dissipation structure of the three-dimensional integrated chip in the embodiment of the present invention;

[0024] Reference Signs:

[0025] 1. Second wafer; 2. Dielectric layer after heterogeneous integration; 3. First wafer; 4. Groove. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0027] The three-dimensional integrated chip, heat dissipation structure and preparation method thereof according to the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0028] As Figure 2 shown, an embodiment of the first aspect of the present invention proposes a preparation method for a heat dissipation structure of a three-dimensional integrated chip, including:

[0029] S1. Provide a first wafer 3 and a second wafer 1. The first wafer 3 is a target substrate for heterogeneous integration, and the second wafer 1 is a wafer for fabricating devices and integrated circuits.

[0030] S2. Form a first dielectric layer on the upper surface of the first wafer 3;

[0031] S3. Etch a groove 4 in the first dielectric layer. The groove 4 penetrates through the front and rear ends of the first dielectric layer along the length direction;

[0032] S4. Form a second dielectric layer on the lower surface of the second wafer 1;

[0033] S5. Perform heterogeneous integration of the second dielectric layer and the first dielectric layer to obtain a heterogeneous integrated dielectric layer 2;

[0034] S6. Align and connect the two ends of the groove 4 with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate respectively and perform packaging.

[0035] By texturing the wafer bonding surface in the embodiments of the present invention, not only the quality and reliability of the bonding interface are effectively improved, but also a heat dissipation channel is provided at the position closest to the chip functional layer, improving the thermal management ability of the chip.

[0036] It should be noted that the fabrication of devices and integrated circuits can be carried out before or after the heterogeneous integration of the first wafer 3 and the second wafer 1.

[0037] Further, in steps S2 and S4, a silicon oxide dielectric layer is deposited on the surfaces of the first wafer 3 and the second wafer 1 respectively by plasma enhanced chemical vapor deposition process.

[0038] Further, in step S3, the etching process is a dry etching process.

[0039] In some embodiments, the method of performing heterogeneous integration of the second dielectric layer and the first dielectric layer is surface-activated heterogeneous integration or plasma-activated heterogeneous bonding.

[0040] In some embodiments, the circulating heat dissipation pipeline of the packaging substrate is a liquid circulating heat dissipation pipeline or a gas circulating heat dissipation pipeline.

[0041] As Figure 1As shown in the figure, an embodiment of the second aspect of the present invention provides a heat dissipation structure for a three-dimensional integrated chip, including: a first wafer 3 and a second wafer 1. The upper surface of the first wafer 3 has a first dielectric layer, and a groove 4 formed by etching is provided on the first dielectric layer. The groove 4 penetrates through the front and rear ends of the first dielectric layer along the length direction, and both ends of the groove 4 are adapted to be respectively aligned and packaged with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate. The lower surface of the second wafer 1 has a second dielectric layer, and the second dielectric layer is opposite to the first dielectric layer and is heterogeneously integrated.

[0042] In some embodiments, a plurality of grooves 4 are provided and arranged in parallel.

[0043] In some embodiments, the materials of the first dielectric layer and the second dielectric layer are one or more laminations of SiO2, Al2O3, and Si3N4.

[0044] In some embodiments, the materials of the first dielectric layer and the second dielectric layer are SiO2 or a lamination of SiO2 and Al2O3.

[0045] In some embodiments, the depth of the groove 4 is equal to the depth of the first dielectric layer.

[0046] In some embodiments, the width of the groove 4 is 100um - 500um, preferably 100um, 300um, or 500um, and the interval between two adjacent grooves 4 is 1mm - 5mm, preferably 1mm, 3mm, or 5mm.

[0047] In some embodiments, the thicknesses of both the first dielectric layer and the second dielectric layer are 500nm - 2000nm, preferably 500nm, 1000nm, or 2000nm.

[0048] An embodiment of the third aspect of the present invention provides a three-dimensional integrated chip, including the above heat dissipation structure.

[0049] The following further elaborates on the present invention through specific embodiments.

[0050] Embodiment 1

[0051] Provide a first wafer 3 and a second wafer 1.

[0052] By plasma enhanced chemical vapor deposition process, silicon oxide dielectric layers are respectively deposited on the surfaces of the first wafer 3 and the second wafer 1 to obtain the first dielectric layer and the second dielectric layer, and their thicknesses are both 500nm.

[0053] Using a dry etching process, grooves 4 are etched on the first dielectric layer of the first wafer 3. The grooves 4 penetrate through both ends of the first dielectric layer along the length direction. The depth of the grooves 4 is 500nm, the width is 100um, and the interval between two adjacent grooves 4 is 1mm.

[0054] The surfaces of the first dielectric layer and the second dielectric layer are plasma-activated and then aligned for bonding.

[0055] The second wafer 1 is thinned to about 200 nm and then integrated circuit processes are performed for preparation.

[0056] The groove 4 of the aforementioned chip containing the integrated circuit is aligned with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate and then packaged.

[0057] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the present invention.

[0058] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0059] In the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", "connected to", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or communicable with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the horizontal height of the first feature is less than that of the second feature.

[0061] In the present invention, the terms "an embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0062] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a heat dissipation structure of a three-dimensional integrated chip, characterized in that, Comprising: Providing a first wafer and a second wafer; Forming a first dielectric layer on one surface of the first wafer; Etching a groove in the first dielectric layer, the groove penetrating through both ends of the first dielectric layer along the length direction; Forming a second dielectric layer on the surface of the second wafer opposite to the first dielectric layer; Heterogeneously integrating the second dielectric layer with the first dielectric layer; Aligning and connecting the two ends of the groove with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate respectively and packaging.

2. The preparation method according to claim 1, characterized in that, The method of heterogeneously integrating the second dielectric layer with the first dielectric layer is surface-activated heterogeneous integration or plasma-activated heterogeneous bonding.

3. The preparation method according to claim 1, characterized in that The circulating heat dissipation pipeline of the packaging substrate is a liquid circulating heat dissipation pipeline or a gas circulating heat dissipation pipeline.

4. A heat dissipation structure for a three-dimensional integrated chip, characterized in that, Comprising: A first wafer, one surface of the first wafer having a first dielectric layer, the first dielectric layer having a groove formed by etching, the groove penetrating through both ends of the first dielectric layer along the length direction, and the two ends of the groove being adapted to be respectively aligned and connected with the inlet and outlet of the circulating heat dissipation pipeline of the packaging substrate and packaged; A second wafer, the surface of the second wafer having a second dielectric layer, the second dielectric layer being opposite to the first dielectric layer and heterogeneously integrated.

5. The heat dissipation structure of the three-dimensional integrated chip according to claim 4, wherein A plurality of the grooves are provided and arranged in parallel.

6. The heat dissipation structure of the three-dimensional integrated chip according to claim 4, wherein The materials of the first dielectric layer and the second dielectric layer are SiO2 or a stack of SiO2 and Al2O3.

7. The heat dissipation structure of the three-dimensional integrated chip according to claim 4, characterized in that The depth of the groove is equal to the depth of the first dielectric layer.

8. The heat dissipation structure of the three-dimensional integrated chip according to claim 4, wherein The width of the groove is 100um - 500um, and the distance between adjacent two grooves is 1mm - 5mm.

9. The heat dissipation structure of the three-dimensional integrated chip according to claim 4, wherein The thicknesses of both the first dielectric layer and the second dielectric layer are 500nm - 2000nm.

10. A three-dimensional integrated chip, characterized in that, Comprising the heat dissipation structure according to any one of claims 4 - 9.

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