Semiconductor device and method of manufacturing shaped IPD-cow

Abstract

A semiconductor device and a method of manufacturing a shaped IPD-CoW are provided. A semiconductor device has an integrated passive device (IPD) wafer that includes an IPD formed on the IPD wafer. A semiconductor die is mounted on the IPD wafer. An interconnect structure is mounted on the IPD wafer. The IPD wafer is singulated to provide an IPD die having an IPD, a semiconductor die, and an interconnect structure. An encapsulant is deposited over the IPD die, wherein the interconnect structure is exposed from the encapsulant. A shielding layer is formed over the encapsulant.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device and a method of fabricating a chip-on-wafer (CoW) device or module with integrated passive devices (IPDs) on a wafer. Background Art

[0002] Semiconductor devices are common in modern electronic products. Semiconductor devices perform a variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electrical energy, and creating visual images for a television display. Semiconductor devices are found in the fields of communication, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices can also be found in military applications, aviation, motor vehicles, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are constantly striving to manufacture smaller semiconductor devices to meet the needs of both electronic device manufacturers and consumers. When packaging multiple die together, one way to shrink the end device is to directly mount a smaller die on the semiconductor wafer of a larger die. This is known as chip-on-wafer (CoW). However, the prior art for CoW devices is lacking in many important aspects. Therefore, there is a need to improve CoW devices. Brief Description of the Drawings

[0004] Figures 1a - 1c A semiconductor wafer having a plurality of semiconductor die separated by saw streets is shown;

[0005] Figures 2a - 2k A CoW device having a semiconductor die formed on an IPD wafer is shown;

[0006] Figure 3 A complete CoW device is shown;

[0007] Figure 4a and Figure 4b An embodiment of exposing solder bumps through a sealant using laser drilling is shown;

[0008] Figure 5a and Figure 5b An embodiment having embedded conductive posts is shown;

[0009] Figure 6a and Figure 6b An embodiment having an embedded PCB unit is shown;

[0010] Figure 7a and Figure 7b Grounding through external interconnections is shown;

[0011] Figure 8a andFigure 8b shows a backside RDL plane with a mesh vent for EMI; and

[0012] Figure 9a and Figure 9b shows an electronic device with a CoW device. DETAILED DESCRIPTION

[0013] With reference to the figures, the present invention is described in one or more embodiments below, where like reference numerals represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purposes of the present invention, those skilled in the art will appreciate that the present invention is intended to cover substitutions, modifications, and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents (which are supported by the following disclosure and drawings). The features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numeral in the figures have similar functions and descriptions. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word and can thus refer to both a single semiconductor device and multiple semiconductor devices.

[0014] Semiconductor devices are typically fabricated using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors establish relationships between the voltages and currents necessary to perform circuit functions.

[0015] Back-end manufacturing refers to cutting or singulating a finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is scribed and broken along non-functional regions of the wafer called saw streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on top of the semiconductor die are connected to the contact pads within the package. The electrical connection can be made using a conductive layer, bumps, columnar bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, and the functionality of the semiconductor device is made available to other system components.

[0016] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active, inter-die wafer regions or saw streets 106. The saw streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 - 450 millimeters (mm).

[0017] Figure 1b A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or non-active surface 108 and an active surface 110 that contains analog or digital circuitry, which is implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement an analog circuit or a digital circuit such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a memory, or other signal processing circuitry. The semiconductor die 104 can also contain IPDs for RF signal processing such as inductors, capacitors, and resistors.

[0018] A conductive layer 112 is formed over the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic electroplating, electroless plating, sputtering, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 serves as contact pads for electrically connecting to the circuitry on the active surface 110.

[0019] Deposit conductive bump material over the conductive layer 112 using evaporation, electroplating, electroless plating, drop ball, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, and optionally a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. Bond the bump material to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, reflow the bump material by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed over a bump-under-metalization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. Interconnect structures can also use bond wires, conductive paste, columnar bumps, micro bumps, or other electrical interconnections.

[0020] In Figure 1c a, a semiconductor wafer 100 is singulated into individual semiconductor dice 104 by sawing through saw streets 106 using a saw blade or a laser cutting tool 119. The individual semiconductor dice 104 can be inspected and electrically tested to identify known good dice or units after singulation.

[0021] Figures 2a - 2k Illustrated is a process for forming a chip-on-wafer (CoW) device using the semiconductor die 104 as a chip on an integrated passive device (IPD) wafer 120. Figure 2a A partial cross-section of the IPD wafer 120 is illustrated. The IPD wafer 120 is similar to the wafer 100 and includes a body typically formed of bulk semiconductor material 122. Silicon is most commonly used for the IPD wafer because the manufacturing equipment used to form the IPD over the wafer has been configured to process silicon wafers. However, other embodiments use wafers of other materials such as polymers, glass, metals, or other semiconductors. Any suitable substrate material can be used in other embodiments.

[0022] The wafer 120 includes an active surface 124, where in Figure 2aPrior to the steps shown in , an IPD is formed over the active surface. The IPD is also optionally formed over the back surface 125. The IPD is formed by successively depositing and patterning conductive and insulating layers to form the desired shape and structure required for the IPD. For example, the conductive structure can be shaped as a coil to form an inductor, or shaped as fingers and plates to form a capacitor. Resistors can be formed by artificially increasing the trace length or by using different materials with increased resistance. Any suitable passive device or combination of passive devices can be formed on the active surface 124 and electrically interconnected to perform the desired electrical function, such as a radio frequency (RF) filter. The IPD wafer 120 optionally also has active devices formed in the active surface 124, but more commonly, the semiconductor die 104 relies on the active electrical functions, while the IPD wafer only provides passive electrical components.

[0023] Conductive vias 126 are formed through the IPD wafer 120 to provide electrical connection between the active surface 124 and the back surface 125. The conductive vias 126 are formed by drilling through the wafer 120 using, for example, chemical etching, laser drilling, mechanical drilling, or another suitable process, and filling the resulting openings by sputtering, electroplating, or otherwise depositing a conductive material into the openings. The conductive vias 126 can be formed only partially through the IPD wafer 120 and then exposed by back-grinding the IPD wafer.

[0024] Although only two IPD dies 130 are shown formed in the IPD wafer 120, the IPD wafer is typically large enough to form dozens or hundreds of cells in the IPD wafer for processing together. Each of the IPD dies 130 is surrounded by a saw street 128 and separated from adjacent IPD dies. The IPD wafer 120 will be singulated through the saw streets 128 to divide the IPD dies 130 into individual CoW devices.

[0025] In Figure 2b , a conductive layer 132 is formed over the active surface 124. The conductive layer 132 is formed using any of the materials and processes described above for the conductive layer 112. The conductive layer 132 is patterned to include contact pads for subsequent electrical interconnection with the underlying IPD and conductive vias 126, contact pads for mounting additional electrical components, and conductive traces for fan-in or fan-out electrical connections from the underlying IPD to the contact pads, if necessary. The conductive layer 132 can also include conductive traces to interconnect the underlying IPDs of the active surface 124 into a functional circuit, but typically the same conductive layers used to form the IPDs are used to interconnect them together, or prior to the start of the encapsulation in Figure 2a , the original manufacturer of the IPD wafer will have formed any additional necessary electrical connections.

[0026] Figure 2cIn this case, solder bumps 136 are formed on the contact pads of the conductive layer 132. The solder bumps 136 are formed as described above for the solder bumps 112. The conductive layer 132 optionally has an UBM formed of multiple conductive layers, and the UBM includes a wetting layer, a barrier layer, and an adhesion layer, and the solder bumps 136 will be disposed at the adhesion layer. In other embodiments, other types of interconnect structures are used in place of the solder bumps 136.

[0027] In Figure 2d this case, the semiconductor die 104, the discrete component 138, and any other desired components are mounted or disposed on the contact pads of the conductive layer 132. The semiconductor die 104 is picked up and placed with the solder bumps 114 oriented towards the IPD wafer 120. The semiconductor die 104 is placed downward such that the bumps 114 physically contact the conductive layer 132, and then the bumps are reflowed to physically and electrically connect the semiconductor die 104 to the IPD wafer 120.

[0028] The discrete component 138 is similarly picked up and placed onto the conductive layer 132. Solder paste can be printed onto the components or the conductive layer 132 to provide a secure physical and electrical connection after reflow. The discrete component 138 can be any desired active or passive component. The discrete component 138 is illustrated as a two-terminal device as seen from the front, so only one terminal is visible. The discrete component 138 can also have three or more terminals and can have any suitable package type.

[0029] One or more semiconductor dies 104 can be mounted for each CoW device being formed. The semiconductor dies 104 can all be the same, or complementary semiconductor dies can be used on each CoW device (such as a processor and a memory chip). Any number and type of electrical components can be mounted onto the IPD wafer 120 to achieve the desired electrical functions.

[0030] In Figure 2e this case, a single IPD wafer 120 is diced through the saw street 128 using a laser or other suitable cutting tool 139 to separate the individual IPD dies 130 from each other. In Figure 2f this case, the diced IPD dies 130 are picked up and placed onto a temporary substrate or carrier 140 having a double-sided tape or an interface layer 142. The IPD dies 130 are placed such that the back surface 125 is on the carrier 140, and the solder bumps 136 extend upward away from the carrier.

[0031] The carrier 140 includes a sacrificial substrate, such as silicon, polymer, beryllium oxide, glass, or other low-cost rigid materials suitable for structural support. An interface layer or double-sided tape 142 is formed or disposed on the carrier 140 as a temporary bonding film, an etch stop layer, a thermal release layer, or a UV release layer. The carrier 140 can be a circular or rectangular panel with the ability to process multiple IPD die 130 at one time. Although only two IPD die 130 are shown, dozens, hundreds, or more modules can be processed together on a common carrier 140. In some embodiments, the gap between the IPD die 130 on the carrier 140 is greater than the saw street 128.

[0032] In Figure 2g , a sealant or molding compound 144 is deposited over and around the carrier 140, IPD die 130, solder bumps 136, semiconductor die 104, and discrete components 138 using screen printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 144 can be a liquid or particulate polymer composite, such as an epoxy resin, an epoxy acrylate, or a polymer, with or without added fillers. In another embodiment, the sealant 144 is a laminated molding sheet or molding film with or without fillers. The sealant 144 is non-conductive, provides structural support, and environmentally protects the IPD die 130 and semiconductor die 104 from external elements and contaminants. The sealant 144 completely covers the previously exposed outer surface of the solder bumps 136. In other embodiments, the sealant 144 is deposited such that the top of the solder bumps 136 is slightly exposed, or the top surface of the sealant is coplanar with the top surface of an alternative interconnect structure.

[0033] In Figure 2h , the carrier 140 is peeled and removed from the panel of bridge die IPD die 130 and sealant 144. In some embodiments, the adhesion characteristics of the interface layer 142 are reduced by thermal, ultraviolet, laser, or other energy applications prior to mechanically removing the carrier 140 from the panel. Figure 2h The panel in

[0034] In Figure 2i , the sealant 140 is backgrinded using a grinder 148, chemical mechanical planarization, chemical etching, or another suitable process to reduce the thickness of the sealant and thereby expose the top of the solder bumps 136. A portion of each bump 136 is also removed to flatten the bumps and make the top surface of the bumps coplanar with the sealant 144. In Figure 2jIn this case, the IPD die 130 is singulated into individual IPD-CoW devices 150 by cutting through the sealant 144 in the saw street 146 using a laser cutting tool, a saw blade, or other suitable tool 149.

[0035] After singulation, the IPD-CoW device 150 is flipped and placed on another or the same carrier, with the back surface 125 oriented upward or otherwise exposed. To address electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, and other inter-device interferences, a shielding layer 152 is formed over the back surface 125 of the IPD die 130 and the top and side surfaces of the sealant 144. The shielding layer 152 is deposited, printed, sputtered, electroplated, or otherwise formed. Electroplating can be performed by CVD, PVD, other sputtering methods, electroplating, electroless plating, or another suitable metal deposition process. The shielding layer 152 includes one or more layers of Al, Ti, Cu, Sn, Ni, Au, Ag, stainless steel, or other suitable conductive materials.

[0036] Singulating through the sealant 144 to form individual IPD-CoW devices 150 before forming the shielding layer 152 allows the shielding layer to be formed along the side surfaces of the package, which is optional but helps prevent laterally incident EMI. The shielding layer 152 is formed directly on the surface of the conductive vias 126 exposed to the back surface 125. The conductive vias 126 and the solder bumps 136 formed over each via allow the shielding layer to be connected to ground, thus improving shielding performance.

[0037] Figure 2k The IPD-CoW device 150 in this case is a complete semiconductor package, which is ready to be incorporated into a larger electronic device or stored in a tape-and-reel for delivery to a device manufacturer. Optionally, as Figure 3 shown in this case, an additional portion of solder paste 156 can be printed or otherwise placed onto each exposed solder bump 136 to create a composite or compound bump that extends continuously from the conductive layer 132 over the surface of the sealant 144. The solder paste 156 can be reflowed with the solder bumps 136 during manufacturing. The solder paste 156 extending over the sealant 144 provides some spacing to make it easier to mount the IPD-CoW device 150 onto the PCB or substrate of a larger electronic device.

[0038] The IPD-CoW device 150 is a chip-on-wafer device, where passive components that are IPDs are formed on the wafer side of the chip-on-wafer, and an EMI shield is formed over the package. Additional passive components and semiconductor dies are flip-chip attached or surface-mount attached onto the IPD die 130. Due to the use of existing fan-out wafer-level packaging manufacturing equipment, the IPD-CoW device 150 can be manufactured at a relatively low cost and complexity.

[0039] Figure 4a and Figure 4b shows an alternative embodiment continuing from Figure 2h In Figure 4a , a laser 162 is used to form an opening 160 through the sealant 144 to expose the solder bumps 136. The opening 160 can also be formed by chemical etching, mechanical drilling, or another suitable means. In Figure 4b , additional solder bumps or solder paste 164 are disposed in the openings 160 over each bump 136. The bumps 136 and 164 can optionally be reflowed together at this stage to form a single continuous solder body. As shown in Figure 2j and Figure 2k , manufacturing continues to complete the semiconductor package with solder bumps 164.

[0040] Figure 5a and Figure 5b show an alternative embodiment where the IPD-CoW device 170 has solder bumps 136 replaced by conductive pillars 172. During the steps shown in Figure 2c , the conductive pillars 172 are mounted to the contact pads of the conductive layer 132, but otherwise, the manufacturing process is as shown in Figures 2a - 2k . The conductive pillars 172 can be formed separately and then attached to the conductive layer 132 through a thin solder layer. Alternatively, the conductive pillars 172 can be grown on or as part of the conductive layer 132 by electroplating or another suitable process. The sealant 144 is optionally co-planarly deposited with the conductive pillars 172 by film-assisted molding or another suitable process, rather than backgrinding as shown in Figure 2i . As described above for the bumps 114 on the conductive layer 112, solder bumps 174 are formed on the conductive pillars 172 in Figure 5b . In either of the above or below embodiments, the solder bumps 136 can be replaced by conductive pillars 172.

[0041] Figure 6a and Figure 6b show a similar embodiment, but where the IPD-CoW device 180 has a PCB unit 182 instead of the conductive pillars 172. The PCB unit 182 is essentially a small PCB having one or more insulating layers 184 stacked together with one or more conductive layers 186. The insulating layer 184 can include a core insulating board and additional insulating layers deposited on top of the core board. The conductive layer 186 can include conductive vias formed through the insulating layer 184 and contact pads formed on the insulating layer. Although typically only vertically oriented, some PCB units 182 can have lateral conductive traces for electrical interconnection.

[0042] The PCB unit 182 can have only a single electrical contact coupled to one contact pad of the conductive layer 132, or a single PCB unit can extend a length having one or more rows or one or more columns of contacts. Before depositing the sealant 144, the PCB unit 182 is mounted to the contact pad of the conductive layer 132 using solder or solder paste. As described above for the solder bumps 114, solder bumps 188 are mounted on Figure 6b the exposed contacts of the PCB unit 182 in. In either of the above or below embodiments, the solder bumps 136 and the conductive posts 172 can be replaced by the PCB unit 182.

[0043] Figure 7a and Figure 7b shows an embodiment in which the PCB unit is used for the shielding layer 152 to be grounded, as an alternative to grounding through the conductive vias 126. Figure 7a shows the IPD-CoW device 190. The IPD die 130 is formed without the conductive vias 126. To provide grounding for the shielding layer 152, during the steps shown in Figure 2f , the PCB unit 192 is disposed on the carrier 140 together with the CoW die 130. In one embodiment, the PCB unit 192 has multiple contacts along the length of the IPD die 130 and is placed along one or more sides of the IPD die 130. In another embodiment, multiple individual contact PCB units can be placed along one or more sides of the IPD die 130. Conductive bars or conductive posts can be used instead of the PCB unit.

[0044] The formation and structure of the PCB unit 192 are as described above for the PCB unit 182. During the steps shown in Figure 2g , the sealant 144 is deposited over both the IPD die 130 and the PCB unit 192. The manufacturing is carried out otherwise as described above. The conductive posts 172 are shown, but the solder bumps 136 or the PCB unit 182 can be used instead.

[0045] Figure 7b shows a similar embodiment, but an interconnect structure 202 is formed over the IPD-CoW device 200. The interconnect structure 202 includes a conductive layer 204 formed on the PCB unit 192, the conductive posts 172, and the sealant 144. The conductive layer 204 includes contact pads at the exposed conductive structures and at the locations where the solder bumps 208 are to be formed. The conductive traces of the conductive layer 204 interconnect the contact pads as desired, for example, by assigning a single ground electrical connection to both the PCB unit 192 and the IPD die 130.

[0046] A solder mask, passivation layer, or insulating layer 206 is formed over the conductive layer 204. The insulating layer 206 and any of the insulating layers mentioned above or below can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation, and include one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder mask, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. A portion of the insulating layer 206 is removed using an etching process or laser direct ablation (LDA) to expose the conductive layer 204. Solder bumps 208 are formed on the conductive layer 204 in the openings of the insulating layer 206, as described above for solder bumps 114.

[0047] The interconnect structure 202 can be referred to as a stacked interconnect structure because the interconnect structure is formed by stacking alternating insulating layers and conductive layers one on top of another. The traces of the interconnect structure 202 can be made more complex by stacking multiple interconnect conductive layers that are staggered between the insulating layers.

[0048] Figure 8a and Figure 8b An embodiment with a backside-embedded ground layer 212 is shown. The backside-embedded ground layer 212 can be formed on a carrier. First, an insulating support layer 214 is deposited and patterned. The insulating support layer 214 is typically formed from the materials used for the insulating layers above and using the processes used for the insulating layers above. A conductive ground layer 216 is formed on the insulating support layer 214. The conductive ground layer 216 includes a plurality of openings below the IPD die 130 as a mesh vent hole, where the insulating layer 218 is visible in the Figure 8b plan view. The conductive ground layer 216 is formed as described above for the conductive layer. In one embodiment, the ground layer 216 is formed of a Ti layer and a Cu layer, with an optional NiFe layer formed on top of the Cu layer. In other embodiments, any suitable conductive shielding material can be used.

[0049] The conductive bar 220 is mounted onto the backside-embedded ground layer 212 using solder 222. The conductive bar 220 can be a single cylindrical bar with a vertical orientation, or can extend continuously or in multiple discrete portions along one or more sides of the IPD die 130. The interconnect structure 202 or bumps 174 are formed on the conductive bar 220 and the posts 172.

[0050] Figure 9a and Figure 9b An illustration shows the integration of the semiconductor package described above (e.g., the IPD-CoW device 150) into a larger electronic device 300. Figure 7aA partial cross-section of the IPD-CoW device 150 mounted as part of an electronic device 300 on a printed circuit board (PCB) or other substrate 302 is shown. The bumps 136 and 156 are reflowed together and onto the conductive layer 304 of the PCB 302 to physically attach and electrically connect the IPD-CoW device 150 to the PCB. In other embodiments, thermocompression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the IPD-CoW device 150 and the PCB 302. The semiconductor die 104 and the IPD die 130 are electrically coupled to the conductive layer 304 through the bumps 136 / 156 and the conductive layer 132.

[0051] Figure 7b An electronic device 300 having a chip carrier substrate or PCB 302 is shown, with a plurality of semiconductor packages, including the IPD-CoW device 150, disposed on the surface of the PCB 302. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0052] The electronic device 300 can be an independent system that performs one or more electrical functions using semiconductor packages. Alternatively, the electronic device 300 can be a sub-component of a larger system. For example, the electronic device 300 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, the electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices can be reduced to achieve higher density. The PCB 302 can have a more irregular shape to facilitate assembly into a more ergonomic and smaller device enclosure.

[0053] In Figure 7b the PCB 302 provides a common substrate for the structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 304 are formed on or within the surface of the PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. The traces 304 also provide power connections and ground connections for each semiconductor package.

[0054] In some embodiments, a semiconductor device has two levels of packaging. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first-level packaging, where the die is mechanically and electrically directly disposed on the PCB.

[0055] For illustrative purposes, several types of first-level packaging are shown on the PCB 302, including wire-bond packaging 346 and flip chip 348. Additionally, several types of second-level packaging, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, quad flat no-lead package (QFN) 360, quad flat package 362, and embedded wafer-level ball grid array (eWLB) 364, are shown disposed on the PCB 302. In one embodiment, the eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0056] Depending on system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level packaging styles and other electrical components can be connected to the PCB 302. In some embodiments, the electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, less expensive components and pipeline manufacturing processes can be used to manufacture the electronic devices. The resulting devices are less likely to malfunction and are less expensive to manufacture, thereby resulting in reduced consumer costs.

[0057] Although one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to these embodiments without departing from the scope of the present invention as set forth in the following claims.

Claims

1. A method of manufacturing a semiconductor device, comprising: Providing an integrated passive device (IPD) wafer including an IPD formed on the IPD wafer; Mounting a semiconductor die on the IPD wafer; Mounting an interconnect structure on the IPD wafer; Scribing the IPD wafer to provide an IPD die having the IPD, the semiconductor die, and the interconnect structure; Depositing a sealant over the IPD die, wherein the interconnect structure is exposed from the sealant; And Forming a shielding layer over the sealant.

2. The method according to claim 1, further comprising: Providing a second interconnect structure adjacent to the IPD die; And Depositing the sealant over the IPD die and the second interconnect structure.

3. The method according to claim 1, further comprising forming a build-up interconnect structure over the IPD die and the sealant.

4. The method according to claim 1, wherein the IPD die includes a conductive via formed through the IPD die.

5. The method according to claim 1, further comprising forming the shielding layer as an embedded backside RDL plane having a plurality of mesh-shaped vent holes.

6. The method according to claim 1, further comprising depositing solder or solder paste over the interconnect structure after depositing the sealant.

7. A semiconductor device, comprising: An integrated passive device (IPD) die including an IPD formed on the IPD die; A semiconductor die mounted on the IPD die; An interconnect structure mounted on the IPD die; A sealant deposited over the IPD die, wherein the interconnect structure is exposed from the sealant; And A shielding layer formed over the sealant.

8. The semiconductor device according to claim 7, further comprising a second interconnect structure provided adjacent to the IPD die, wherein the sealant is deposited over the IPD die and the second interconnect structure.

9. The semiconductor device according to claim 7, further comprising a build-up interconnect structure formed over the IPD die and the sealant.

10. The semiconductor device according to claim 7, wherein the IPD die includes a conductive via formed through the IPD die.

11. A semiconductor device, comprising: An integrated passive device (IPD) die; A semiconductor die mounted on the IPD die; A sealant deposited over the IPD die; And A shielding layer formed over the sealant.

12. The semiconductor device according to claim 11, further comprising an interconnect structure provided adjacent to the IPD die, wherein the sealant is deposited over the IPD die and the interconnect structure.

13. The semiconductor device according to claim 11, further comprising a build-up interconnect structure formed over the IPD die and the sealant.

14. The semiconductor device according to claim 11, further comprising: An interconnect structure provided over the IPD die; And Solder or solder paste provided over the interconnect structure.

15. The semiconductor device according to claim 11, wherein the shielding layer includes a backside RDL plane.

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