Chip packaging structure and preparation method thereof, power module and power conversion circuit
By forming two package layers outside the silicon carbide transistor, the inner layer material has high adhesion and low thermal expansion coefficient, and the outer layer material has low water vapor transmittance, which solves the packaging reliability problem, realizes stress buffering and water vapor isolation, and improves the stability and reliability of the packaging.
Patent Information
- Application Number
- CN202510236462.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-07-08
AI Technical Summary
How to improve the packaging reliability of silicon carbide transistors to reduce the risk of device failure during reliability temperature cycle testing.
Two-layer packaging layers are formed on the outside of the silicon carbide transistor by using two injection molding processes. The inner packaging material has high adhesion and low thermal expansion coefficient, the outer packaging material has low water vapor transmission rate, the inner layer plays a stress buffering role, and the outer layer isolates water vapor, improving the stability and reliability of the packaging.
Through the combination of two packaging layers, the risk of stress damage caused by temperature changes is reduced, water vapor intrusion is prevented, the reliability of the packaging structure is improved, and the risk of device failure is reduced.
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Figure CN120280355A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and particularly relates to a chip packaging structure and a preparation method thereof, a power module, and a power conversion circuit. Background Art
[0002] For silicon carbide transistor (SiC MOSFET) products to meet market needs, reliability temperature cycling (TC) tests are required. How to improve the packaging reliability of chips to reduce the risk of device failure during testing has become an urgent problem in the field. Summary of the Invention
[0003] This application provides a chip packaging structure and a preparation method thereof, a power module, and a power conversion circuit, aiming to improve the packaging reliability.
[0004] To achieve the above object, the embodiments of this application provide the following technical solutions:
[0005] On the one hand, a preparation method of a chip packaging structure is provided. The preparation method includes: providing a chip, a first mold, and a second mold, where the chip includes a silicon carbide transistor. A first packaging layer is formed through the first mold, the first packaging layer covers at least part of the silicon carbide transistor, and the first packaging layer includes a first packaging material. A second packaging layer is formed through the second mold, the second packaging layer covers at least part of the first packaging layer, and the second packaging layer includes a second packaging material. Wherein, the adhesion of the first packaging material is greater than that of the second packaging material; and / or, the thermal expansion coefficient of the first packaging material is less than that of the second packaging material; and / or, the water vapor transmission rate of the first packaging material is greater than that of the second packaging material.
[0006] In the above preparation method, through two injection molding processes, a first packaging layer and a second packaging layer are sequentially formed outside the silicon carbide transistor, and the first packaging layer and the second packaging layer form a two-layer combined packaging structure.
[0007] Moreover, the materials of the second packaging layer and the first packaging layer are different. During the reliability temperature cycling (TC) test, the change in temperature will cause the materials to thermally expand and generate internal stress. The inner first packaging layer plays a role in stress buffering, which can reduce the stress on the silicon carbide transistor, avoid damage to the silicon carbide transistor caused by stress, and reduce the risk of stress failure of the device. The outer second packaging layer plays a role in isolating external water vapor, avoiding damage to the silicon carbide transistor caused by water vapor intrusion, and improving the packaging reliability.
[0008] In some embodiments, forming the first encapsulation layer through the first mold includes: injecting the first encapsulation material into the first mold. Forming the second encapsulation layer through the second mold includes: injecting the second encapsulation material into the second mold.
[0009] In some embodiments, the first encapsulation material includes one or more of a polyimide film material containing a cyano group, a modified epoxy resin, an epoxy resin filled with spherical fused silica powder, or a negative thermal expansion filler composite epoxy resin; the second encapsulation material includes one or more of a silica-filled epoxy resin, an alumina-filled epoxy resin, an organic / inorganic hybrid polymer, or a modified epoxy resin.
[0010] In some embodiments, a third encapsulation layer is formed through a third mold, and the third encapsulation layer covers at least part of the second encapsulation layer. Wherein, the third encapsulation layer includes a third encapsulation material, and the adhesion of the first encapsulation material is greater than that of the third encapsulation material; and / or, the thermal expansion coefficient of the first encapsulation material is less than that of the third encapsulation material; and / or, the water vapor transmission rate of the first encapsulation material is greater than that of the third encapsulation material.
[0011] In some embodiments, the first encapsulation layer covers a part of the silicon carbide transistor, and the second encapsulation layer covers another part of the silicon carbide transistor.
[0012] On the other hand, a chip packaging structure is provided, which includes a silicon carbide transistor, a first encapsulation layer, and a second encapsulation layer. The first encapsulation layer covers at least part of the silicon carbide transistor, and the first encapsulation layer includes a first encapsulation material. The second encapsulation layer covers the first encapsulation layer, and the second encapsulation layer is located on the side of the first encapsulation layer away from the silicon carbide crystal, and the second encapsulation layer includes a second encapsulation material. Wherein, the adhesion of the first encapsulation material is greater than that of the second encapsulation material; and / or, the thermal expansion coefficient of the first encapsulation material is less than that of the second encapsulation material; and / or, the water vapor transmission rate of the first encapsulation material is greater than that of the second encapsulation material.
[0013] In the above embodiments of the present application, the chip packaging structure includes a silicon carbide transistor, a first encapsulation layer covering the silicon carbide transistor, and a second encapsulation layer covering the first encapsulation layer, and the materials of the second encapsulation layer and the first encapsulation layer are different.
[0014] During the TC test of the chip packaging structure, temperature changes can cause the materials to thermally expand and generate internal stress. The inner first packaging layer plays a role in stress buffering, which can reduce the stress on the silicon carbide transistor, avoid damage to the silicon carbide transistor caused by stress, and reduce the risk of stress failure of the device. The outer second packaging layer plays a role in isolating external water vapor, preventing water vapor intrusion from damaging the silicon carbide transistor, and improving the reliability of the packaging.
[0015] In some embodiments, the material of the first packaging layer includes one or more of a polyimide film material containing a cyano group, a modified epoxy resin, an epoxy resin filled with spherical fused silica powder, or a negative thermal expansion filler composite epoxy resin; the material of the second packaging layer includes one or more of a silica-filled epoxy resin, an alumina-filled epoxy resin, an organic / inorganic hybrid polymer, or a modified epoxy resin.
[0016] On the other hand, a power module is provided, which includes a substrate and the chip packaging structure according to any of the above embodiments, and the substrate is used to carry the chip packaging structure.
[0017] On another aspect, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the chip packaging structure according to any of the above embodiments, and the chip packaging structure is electrically connected to the circuit board.
[0018] On yet another aspect, a vehicle is provided, which includes a load and the power conversion circuit according to the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.
[0019] The above power module, power conversion circuit, and vehicle have the same structure and beneficial technical effects as the chip packaging structure provided in some of the above embodiments, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:
[0021] Figure 1 is a structural diagram of a chip packaging structure provided by an embodiment of the present application;
[0022] Figures 2 to 7 are diagrams of each step for preparing the chip packaging structure provided by an embodiment of the present application;
[0023] Figure 8 is a structural diagram of another chip packaging structure provided by an embodiment of the present application;
[0024] Figures 9 to 11 These are the step diagrams for fabricating the chip packaging structure provided by the embodiments of this application;
[0025] Figure 12 This is the structural diagram of another chip packaging structure provided by the embodiments of this application;
[0026] Figure 13 This is the schematic structural diagram of the power module provided by the embodiments of this application;
[0027] Figure 14 This is the schematic structural diagram of the power conversion circuit provided by the embodiments of this application;
[0028] Figure 15 This is the schematic structural diagram of the vehicle provided by the embodiments of this application. Detailed implementation manners
[0029] Next, in combination with the accompanying drawings, the technical solutions in some embodiments of this application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments provided by this application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of this application.
[0030] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to".
[0031] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of this application, unless otherwise stated, the meaning of "a plurality" is two or more.
[0032] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.
[0033] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond the stated ones.
[0034] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.
[0035] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.
[0036] Examples of the embodiments are shown in the drawings, where like or similar reference numerals designate like or similar elements or elements having like or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.
[0037] An embodiment of the present application provides a chip packaging structure. Figure 1 It is a structural diagram of a chip packaging structure provided by an embodiment of the present application.
[0038] See Figure 1 , the chip packaging structure 1 includes a silicon carbide transistor (chip) 2, a first packaging layer 3, and a second packaging layer 4.
[0039] Exemplarily, the chip packaging structure 1 further includes a first carrier 5, a second carrier 6, bonding wires 7, and pins 8. The silicon carbide transistor 2 is disposed on the first carrier 5, the pins 8 are disposed on the second carrier 6, and the silicon carbide transistor 2 is electrically connected to the pins 8 through the bonding wires 7.
[0040] Continuing to refer to Figure 1 , the first packaging layer 3 covers at least a part of the silicon carbide transistor 2, and the first packaging layer 3 includes a first packaging material. Exemplarily, the first packaging layer 3 covers the entire silicon carbide transistor 2, that is, the first packaging layer 3 wraps the silicon carbide transistor 2.
[0041] The second packaging layer 4 covers the first packaging layer 3, and the second packaging layer 4 is located on the side of the first packaging layer 3 away from the silicon carbide crystal 2, that is, the second packaging layer 4 covers the outside of the first packaging layer 3, and the second packaging layer 4 includes a second packaging material. Exemplarily, the second packaging layer 4 wraps the first packaging layer 3.
[0042] Exemplarily, at least a part of the pin 8 should be exposed in both the first encapsulation layer 3 and the second encapsulation layer 4, so that the chip packaging structure 1 can be connected to an external circuit through the pin 8.
[0043] In the above embodiments of the present application, the chip packaging structure 1 includes a silicon carbide transistor 2, a first encapsulation layer 3 covering the silicon carbide transistor 2, and a second encapsulation layer 4 covering the first encapsulation layer 3. It can be set that the adhesion of the first encapsulation material is greater than that of the second encapsulation material, that is, the adhesion of the first encapsulation material in contact with the chip is relatively high, which is beneficial to the tight combination of the first encapsulation material and the chip, and improves the stability of the encapsulation.
[0044] Alternatively, it can also be set that the coefficient of thermal expansion of the first encapsulation material is less than that of the second encapsulation material. During the reliability temperature cycling (TC) test of the chip packaging structure 1, the change in temperature will cause the material to thermally expand and generate internal stress. By setting the coefficient of thermal expansion of the inner first encapsulation material to be smaller, the thermal expansion of the first encapsulation layer 3 can be reduced, the internal stress can be reduced, and a stress buffering effect can be achieved. The stress on the silicon carbide transistor 2 can be reduced, the damage to the silicon carbide transistor 2 caused by stress can be avoided, and the risk of stress failure of the device can be reduced.
[0045] Or, it can also be set that the water vapor transmission rate of the first encapsulation material is greater than that of the second encapsulation material, that is, the water vapor transmission rate of the outer second encapsulation material is relatively low. The second encapsulation layer 4 plays a role in isolating external water vapor, avoiding damage to the silicon carbide transistor 2 caused by water vapor intrusion, and improving the reliability of the encapsulation.
[0046] Regarding the above three parameter relationships between the first encapsulation material and the second encapsulation material, the embodiments of the present application can meet any one of the conditions, or any two of the conditions, or all of the above three conditions. The present application does not limit this.
[0047] In some embodiments, referring to Figure 1 , the material of the first encapsulation layer 3 includes one or more of a polyimide film material containing a cyano group, a modified epoxy resin, an epoxy resin filled with spherical fused silica powder, or a negative thermal expansion filler composite epoxy resin.
[0048] Among them, the polyimide film material containing a cyano group refers to a homopolymer or copolymer polyimide polymer in which the main chain of the polyimide contains a cyano group and the main chain is a rigid chain, which has both relatively high adhesion and a low coefficient of linear expansion.
[0049] The modified epoxy resin refers to: by introducing specific modifiers or fillers into the epoxy resin, its adhesion can be improved. For example, using a matrix resin that is not easily oxidized and adding additives to inhibit oxidation.
[0050] In the epoxy resin filled with spherical fused silica powder, the coefficient of thermal expansion of the spherical fused silica powder is very low, about 0.5×10 -6 / °C, which is much lower than 100×10 -6 / °C of the epoxy resin. Adding it as a filler to the epoxy resin can significantly reduce the coefficient of thermal expansion of the EMC.
[0051] Negative thermal expansion filler composite epoxy resin: By compounding negative thermal expansion fillers with thermal conductive fillers, epoxy resin and curing agents, an epoxy resin composite material with both low coefficient of thermal expansion, high thermal conductivity and good fluidity is prepared.
[0052] The materials of the first encapsulation layer 3 mentioned above have high adhesiveness, ensuring good adhesion between the first encapsulation layer 3 and the silicon carbide transistor 2. Moreover, the coefficient of thermal expansion of these materials is low. During the reliability temperature cycle test, as the temperature rises, the volume expansion rate of the first encapsulation layer 3 is small, avoiding encapsulation failure caused by excessive volume expansion of the first encapsulation layer 3.
[0053] Continue to refer to Figure 1 , the materials of the second encapsulation layer 4 include one or more of silica-filled epoxy resin, alumina-filled epoxy resin, organic / inorganic hybrid polymer or modified epoxy resin.
[0054] Among them, silica-filled epoxy resin: Silica powder has the characteristics of good water absorption rate and excellent dielectric properties. As a filler for EMC, it can effectively reduce the water absorption of EMC. For example, when spherical fused silica powder is used as a filler, its filling amount can reach 75% - 80%. While improving the performance of EMC, it can also reduce water absorption.
[0055] Alumina-filled epoxy resin: Alumina has excellent water resistance. Adding it as a filler to the epoxy resin can significantly improve the water vapor barrier performance of EMC.
[0056] Organic / inorganic hybrid polymer: This material combines organic polymers with inorganic fillers to form a composite structure, which can effectively reduce the water vapor transmission rate. For example, mixing siloxane raw materials with coupling agents, coating and curing them on the alumina and silica water vapor barrier layers, and finally reducing the water vapor transmission rate by an order of magnitude.
[0057] Modified epoxy resin: By introducing specific modifiers into the epoxy resin, its water vapor barrier performance can be improved. For example, using a matrix resin that is not easily oxidized and adding additives to inhibit oxidation, thereby enhancing the water resistance of EMC.
[0058] The material of the second encapsulation layer 4 described above has good water vapor barrier performance, which can prevent water vapor from invading and damaging the silicon carbide transistor 2, and improve the reliability of the encapsulation.
[0059] The embodiment of the present application also provides a preparation method of the above chip encapsulation structure. Figures 2 to 7 It is a schematic diagram of each step for preparing the chip encapsulation structure provided by the embodiment of the present application.
[0060] The preparation method of the chip encapsulation structure includes the following steps S1 to S3:
[0061] S1: Refer to Figure 2 and Figure 5 , provide a chip (the chip includes a silicon carbide transistor 2), a first mold 9 and a second mold 12.
[0062] S2: Refer to Figures 2 to 4 , form a first encapsulation layer 3 through the first mold 9, the first encapsulation layer 3 covers at least part of the silicon carbide transistor 2, and the first encapsulation layer 3 includes a first encapsulation material 30.
[0063] Exemplarily, refer to Figure 2 , place the silicon carbide transistor 2 in the first mold 9, the first mold 9 has one or more first injection cavities 90, each first injection cavity 90 can accommodate a silicon carbide transistor 2, and the silicon carbide transistor 2 is electrically connected to the pin 8 through a bonding wire 7.
[0064] Exemplarily, refer to Figure 3 and Figure 4 , inject the first encapsulation material 30 into the first mold 9 to form the first encapsulation layer 3. The first encapsulation layer 3 covers at least part of the silicon carbide transistor 2 to form a first encapsulation structure 10.
[0065] For example, refer to Figure 3 , the first mold 9 has a first injection port 91, and the first injection port 91 is communicated with the first injection cavity 90. Inject the first encapsulation material 30 through the first injection port 91, and a first press head 11 is further arranged in the first injection port 91, and compressed air is used to press the first encapsulation material 30 into the first injection cavity 90.
[0066] Exemplarily, the first encapsulation material 30 includes one or more of a polyimide film material containing a cyano group, a modified epoxy resin, an epoxy resin filled with spherical fused silica powder, or a negative thermal expansion filler composite epoxy resin.
[0067] Refer to Figure 3 and Figure 4, the first encapsulation material 30 wraps the silicon carbide transistor 2, and after cooling and solidifying, the first encapsulation layer 3 is formed. The silicon carbide transistor 2 and the first encapsulation layer 3 together constitute the first encapsulation structure 10. Then, the first mold 9 is opened, and the first encapsulation structure 10 is taken out to complete demolding.
[0068] S3: Refer to Figures 5 to 7 , the second encapsulation layer 4 is formed through the second mold 12. The second encapsulation layer 4 covers at least part of the first encapsulation layer 3, and the second encapsulation layer 4 includes a second encapsulation material.
[0069] Exemplarily, refer to Figure 5 , the first encapsulation structure 10 is placed in the second mold 12. The second mold 12 has one or more second injection cavities 120, and each second injection cavity 120 can accommodate one first encapsulation structure 10.
[0070] Exemplarily, refer to Figure 6 and Figure 7 , the second encapsulation material 40 is injected into the second mold 12 to form the second encapsulation layer 4. The second encapsulation layer 4 covers at least part of the first encapsulation structure 10 to form the second encapsulation structure 13, and the second encapsulation material 40 is different from the first encapsulation material 30.
[0071] For example, refer to Figure 6 , the second mold 12 has a second injection port 121, and the second injection port 121 is communicated with the second injection cavity 120. The second encapsulation material 40 is injected through the second injection port 121, and a second press head 14 is further provided in the second injection port 121. Compressed air is passed through the second press head 14 to press the second encapsulation material 40 into the second injection cavity 120.
[0072] Refer to Figure 6 and Figure 7 , the second encapsulation material 40 wraps the first encapsulation structure 10, and after cooling and solidifying, the second encapsulation layer 4 is formed. The first encapsulation structure 10 and the second encapsulation layer 4 together constitute the second encapsulation structure 13. Then, the second mold 12 is opened, and the second encapsulation structure 13 is taken out to complete demolding.
[0073] Exemplarily, the second encapsulation layer 4 covers the first encapsulation layer 3, and the second encapsulation layer 4 is located on the side of the first encapsulation layer 3 away from the silicon carbide crystal 2, that is, the second encapsulation layer 4 covers the outside of the first encapsulation layer 3. For example, the second encapsulation layer 4 wraps the first encapsulation layer 3.
[0074] Exemplarily, the second encapsulation material 40 includes one or more of silica-filled epoxy resin, alumina-filled epoxy resin, organic / inorganic hybrid polymer, or modified epoxy resin.
[0075] The manufacturing method provided by the above embodiments of the present application forms a first encapsulation layer 3 and a second encapsulation layer 4 in sequence on the outer side of the silicon carbide transistor 2 through multiple epoxy molding compound (EMC) injection molding processes. For example, through two EMC injection molding processes, the first encapsulation layer 3 and the second encapsulation layer 4 form a two-layer combined EMC encapsulation structure.
[0076] Moreover, the adhesiveness of the first encapsulation material 30 is greater than that of the second encapsulation material 40, that is, the adhesiveness of the first encapsulation material 30 in contact with the chip is relatively high, which is conducive to the tight combination of the first encapsulation material 30 and the chip, improving the stability of the encapsulation.
[0077] Alternatively, it is also possible to set the coefficient of thermal expansion of the first encapsulation material 30 to be less than that of the second encapsulation material 40. During the reliability temperature cycling (TC) test of the chip encapsulation structure 1, the change in temperature will cause the material to thermally expand and generate internal stress. By setting the coefficient of thermal expansion of the inner first encapsulation material 30 to be smaller, the thermal expansion of the first encapsulation layer 3 can be reduced, the internal stress can be lowered, and a stress buffering effect can be achieved. The stress on the silicon carbide transistor 2 can be reduced, the damage to the silicon carbide transistor 2 caused by stress can be avoided, and the stress failure risk of the device can be reduced.
[0078] Or, it is also possible to set the water vapor transmission rate of the first encapsulation material 30 to be greater than that of the second encapsulation material 40, that is, the water vapor transmission rate of the outer second encapsulation material 40 is relatively low. The second encapsulation layer 4 plays a role in isolating external water vapor, avoiding damage to the silicon carbide transistor 2 caused by water vapor intrusion, and improving the reliability of the encapsulation.
[0079] The embodiments of the present application also provide another chip encapsulation structure. Figure 8 It is a structural diagram of another chip encapsulation structure provided by the embodiments of the present application.
[0080] See Figure 8 and Figure 1 The difference from the chip encapsulation structure 1 in Figure 8 is that the chip encapsulation structure 1 in
[0081] also includes a third encapsulation layer 15. The third encapsulation layer 15 covers the second encapsulation layer 4, and the third encapsulation layer 15 is located on the side of the second encapsulation layer 4 away from the silicon carbide crystal 2, that is, the third encapsulation layer 15 covers the outside of the second encapsulation layer 4, which can further improve the reliability of the encapsulation.Among them, the adhesion of the first encapsulation material can be set to be greater than that of the third encapsulation material, or the thermal expansion coefficient of the first encapsulation material can be set to be less than that of the third encapsulation material, or the water vapor transmission rate of the first encapsulation material can be set to be greater than that of the third encapsulation material. That is, the water vapor transmission rate of the outermost third encapsulation material is relatively low, and the third encapsulation layer 15 plays a role in isolating external water vapor, preventing water vapor intrusion from damaging the silicon carbide transistor 2, and improving the reliability of the encapsulation.
[0082] Regarding the above three parameter relationships between the first encapsulation material and the third encapsulation material, the embodiments of the present application can meet any one of the conditions, or any two of the conditions, or all of the above three conditions. The present application does not limit this.
[0083] Exemplarily, the third encapsulation layer 15 wraps the second encapsulation layer 4.
[0084] Exemplarily, the first encapsulation layer 3, the second encapsulation layer 4, and the third encapsulation layer 15 should all expose at least part of the pin 8, so that the chip packaging structure 1 can be connected to an external circuit through the pin 8.
[0085] Exemplarily, since the third encapsulation layer 15 is located on the outermost side, the material of the third encapsulation layer 15 can also include one or more of silica-filled epoxy resin, alumina-filled epoxy resin, organic / inorganic hybrid polymer, or modified epoxy resin, so that the third encapsulation layer 15 has better water vapor isolation performance, which can further prevent water vapor intrusion from damaging the silicon carbide transistor 2 and improve the reliability of the encapsulation.
[0086] The embodiments of the present application also provide a method for manufacturing the above chip packaging structure. Figures 9 to 11 These are the step diagrams for manufacturing the chip packaging structure provided by the embodiments of the present application.
[0087] After Figure 7 the steps shown, the method for manufacturing the chip packaging structure further includes the following step S4:
[0088] S4: Refer to Figures 9 to 11 , form the third encapsulation layer 15 through the third mold 16, and the third encapsulation layer 15 covers at least part of the second encapsulation layer 4.
[0089] Exemplarily, refer to Figure 9 , place the second packaging structure 13 in the third mold 16. The third mold 16 has one or more third injection cavities 160, and each third injection cavity 160 can accommodate one second packaging structure 13.
[0090] Exemplarily, refer to Figure 10 and Figure 11, the third encapsulation material 150 is injected into the third mold 16 to form the third encapsulation layer 15, and the third encapsulation layer 15 covers at least part of the second encapsulation structure 13. The first encapsulation material 30, the second encapsulation material 40, and the third encapsulation material 150 are all different.
[0091] For example, refer to Figure 10 , the third mold 16 has a third injection port 161, and the third injection port 161 is communicated with the third injection chamber 160. The third encapsulation material 150 is injected through the third injection port 161, and a third press head 17 is further arranged in the third injection port 161. Compressed air is passed through the third press head 17 to press the third encapsulation material 150 into the third injection chamber 160.
[0092] Refer to Figure 10 and Figure 11 , the third encapsulation material 150 wraps the second encapsulation structure 13, and after cooling and solidifying, the third encapsulation layer 15 is formed. The second encapsulation structure 13 and the third encapsulation layer 15 together form the chip encapsulation structure 1. Then, the third mold 16 is opened, and the chip encapsulation structure 1 is taken out to complete the demolding.
[0093] Exemplarily, the third encapsulation layer 15 covers the second encapsulation layer 4, and the third encapsulation layer 15 is located on the side of the second encapsulation layer 4 away from the silicon carbide crystal 2, that is, the third encapsulation layer 15 covers the outside of the second encapsulation layer 4. For example, the third encapsulation layer 15 wraps the second encapsulation layer 4.
[0094] Exemplarily, the third encapsulation material 150 includes one or more of silica-filled epoxy resin, alumina-filled epoxy resin, organic / inorganic hybrid polymer, or modified epoxy resin.
[0095] An embodiment of the present application further provides another chip encapsulation structure. Figure 12 It is a structural diagram of another chip encapsulation structure provided by the embodiment of the present application.
[0096] Refer to Figure 12 , the chip encapsulation structure 1 includes a silicon carbide transistor 2, a first encapsulation layer 3, and a second encapsulation layer 4.
[0097] Exemplarily, the chip encapsulation structure 1 further includes a first carrier plate 5, a second carrier plate 6, bonding leads 7, and pins 8. The silicon carbide transistor 2 is arranged on the first carrier plate 5, the pins 8 are arranged on the second carrier plate 6, and the silicon carbide transistor 2 is electrically connected to the pins 8 through the bonding leads 7.
[0098] Continue to refer to Figure 12 , the first encapsulation layer 3 covers a part of the silicon carbide transistor 2, and the second encapsulation layer 4 covers another part of the silicon carbide transistor 2.
[0099] Exemplarily, at least a part of the pins 8 should be exposed in both the first encapsulation layer 3 and the second encapsulation layer 4, so that the chip encapsulation structure 1 can be connected to an external circuit through the pins 8.
[0100] In the above embodiments of the present application, the first encapsulation layer 3 covers a part of the silicon carbide transistor 2, and the second encapsulation layer 4 covers another part of the silicon carbide transistor 2. The first encapsulation layer 3 and the second encapsulation layer 4 respectively wrap half of the silicon carbide transistor 2. It can be understood that the first encapsulation layer 3 and the second encapsulation layer 4 form a semi - enclosed combined EMC encapsulation structure.
[0101] For example, Figure 12 in [description not provided], the ambient temperature at the left end of the silicon carbide transistor 2 changes greatly, and there is more ambient water vapor at the right end. Based on this, the first encapsulation layer 3 is covered at the left end of the silicon carbide transistor 2. The material of the first encapsulation layer 3 has a low coefficient of thermal expansion. As the temperature rises, the volume expansion rate of the first encapsulation layer 3 is small, avoiding encapsulation failure caused by excessive volume expansion of the first encapsulation layer 3.
[0102] The second encapsulation layer 4 is covered at the right end of the silicon carbide transistor 2. The material of the second encapsulation layer 4 has good water - vapor isolation performance, which can avoid damage to the silicon carbide transistor 2 caused by water - vapor intrusion and improve the reliability of the encapsulation.
[0103] The embodiments of the present application also provide a power module. Figure 13 It is a schematic structural diagram of the power module provided by the embodiments of the present application.
[0104] As Figure 13 shown, the power module 200 includes a substrate 201 and the chip encapsulation structure 1 in any of the above embodiments. The substrate 201 is used to carry the chip encapsulation structure 1.
[0105] Exemplarily, the power module 200 can be used as a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure stable and efficient distribution of power to different parts of an electronic device. The power regulator is used to regulate the power output to meet the requirements of specific applications.
[0106] On the other hand, the embodiments of the present application also provide a power conversion circuit. Figure 14 It is a schematic structural diagram of the power conversion circuit provided by the embodiments of the present application.
[0107] As Figure 14As shown, the power conversion circuit 300 includes a circuit board 301 and the chip packaging structure 1 in any of the above embodiments. The chip packaging structure 1 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion, or power factor correction.
[0108] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit. Among them, the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.
[0109] On the other hand, an embodiment of the present application also provides a vehicle. Figure 15 It is a schematic structural diagram of the vehicle provided by the embodiment of the present application.
[0110] As Figure 15 shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment. After the power conversion circuit 300 converts alternating current into direct current, converts alternating current into alternating current, converts direct current into direct current, or converts direct current into alternating current, it is input to the load 401 to supply power to the load 401.
[0111] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, thinking of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.
Claims
1. A method for preparing a chip packaging structure, characterized in that Comprising: Providing a chip, a first mold, and a second mold, wherein the chip includes a silicon carbide transistor; Forming a first encapsulation layer through the first mold, the first encapsulation layer covering at least a portion of the silicon carbide transistor; the first encapsulation layer includes a first encapsulation material; Forming a second encapsulation layer through the second mold, the second encapsulation layer covering at least a portion of the first encapsulation layer; the second encapsulation layer includes a second encapsulation material; Wherein, the adhesion of the first encapsulation material is greater than the adhesion of the second encapsulation material; and / or, the coefficient of thermal expansion of the first encapsulation material is less than the coefficient of thermal expansion of the second encapsulation material; And / or, the water vapor transmission rate of the first encapsulation material is greater than the water vapor transmission rate of the second encapsulation material.
2. The preparation method according to claim 1, wherein Forming the first encapsulation layer through the first mold includes: injecting the first encapsulation material into the first mold; Forming the second encapsulation layer through the second mold includes: injecting the second encapsulation material into the second mold.
3. The preparation method according to claim 1, characterized in that, The first encapsulation material includes one or more of a polyimide film material containing a cyano group, a modified epoxy resin, an epoxy resin filled with spherical fused silica powder, or a negative thermal expansion filler composite epoxy resin; The second encapsulation material includes one or more of an epoxy resin filled with silica, an epoxy resin filled with alumina, an organic / inorganic hybrid polymer, or a modified epoxy resin.
4. The preparation method according to claim 1, characterized in that, After forming the second encapsulation layer, the preparation method further includes: Forming a third encapsulation layer through a third mold, the third encapsulation layer covering at least a portion of the second encapsulation layer; Wherein, the third encapsulation layer includes a third encapsulation material, the adhesion of the first encapsulation material is greater than the adhesion of the third encapsulation material; and / or, the coefficient of thermal expansion of the first encapsulation material is less than the coefficient of thermal expansion of the third encapsulation material; and / or, the water vapor transmission rate of the first encapsulation material is greater than the water vapor transmission rate of the third encapsulation material.
5. The preparation method according to claim 1, characterized in that, The first encapsulation layer covers a part of the silicon carbide transistor, and the second encapsulation layer covers another part of the silicon carbide transistor.
6. A chip packaging structure, characterized in that, Comprising: A silicon carbide transistor; A first encapsulation layer covering at least a portion of the silicon carbide transistor; The first encapsulation layer includes a first encapsulation material; A second encapsulation layer covering the first encapsulation layer, and the second encapsulation layer is located on a side of the first encapsulation layer away from the silicon carbide crystal; the second encapsulation layer includes a second encapsulation material; Wherein, the adhesion of the first encapsulation material is greater than the adhesion of the second encapsulation material; and / or, the coefficient of thermal expansion of the first encapsulation material is less than the coefficient of thermal expansion of the second encapsulation material; And / or, the water vapor transmission rate of the first encapsulation material is greater than the water vapor transmission rate of the second encapsulation material.
7. The chip package structure according to claim 6, wherein The material of the first encapsulation layer includes one or more of a polyimide film material containing a cyano group, a modified epoxy resin, an epoxy resin filled with spherical fused silica powder, or a negative thermal expansion filler composite epoxy resin; The material of the second encapsulation layer includes one or more of silica-filled epoxy resin, alumina-filled epoxy resin, organic / inorganic hybrid polymer, or modified epoxy resin.
8. A power module, characterized in that, Comprising: At least one chip encapsulation structure as claimed in claim 6 or 7; A substrate for carrying the chip encapsulation structure.
9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one chip encapsulation structure as claimed in claim 6 or 7, and the chip encapsulation structure is electrically connected to the circuit board.
10. A vehicle, characterized in that, Comprising: A load and a power conversion circuit as claimed in claim 9, and the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current and then inputting it to the load.