Three-dimensional high-density interconnection method of substrate and IC chip

Abstract

The invention relates to a three-dimensional high-density interconnection method for a substrate and an IC chip, and the method comprises the following steps: carrying out the multi-layer dielectric composite processing of a preset silicon substrate, and obtaining a silicon through hole array structure with a preset depth-to-width ratio; performing metal filling on the silicon through hole array structure to obtain a three-dimensional interconnection conductive path; performing surface treatment on the three-dimensional interconnection conductive path to obtain a micro bump structure with gradient metallization; performing laser-assisted bonding on the micro bump structure to obtain a silicon bridge-substrate temporary structural body; carrying out bottom filling on the silicon bridge-substrate temporary structure body through a supercritical fluid auxiliary injection technology to obtain a packaging structure body with a stress release function; and a preset IC chip and the packaging structure body are assembled and fixed to obtain a three-dimensional high-density interconnection packaging body, and the technical problem that a traditional two-dimensional plane interconnection method is difficult to meet the requirement of high-density integration is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of IC chips, and particularly to a three-dimensional high-density interconnection method for a substrate and an IC chip. Background Art

[0002] In the development process of modern electronic packaging technology, the demand for smaller-sized, higher-performance, and more reliable electronic products is increasing day by day. Especially in the field of interconnection between integrated circuit (IC) chips and substrates, traditional two-dimensional planar interconnection methods have been difficult to meet the requirements of high-density integration. As Moore's Law gradually approaches the physical limit, the method of simply reducing the chip feature size to improve performance has faced huge challenges. Therefore, exploring three-dimensional high-density interconnection technology has become one of the important ways to improve the overall performance of the system.

[0003] However, in the process of realizing three-dimensional high-density interconnection, multiple technical problems are faced. On the one hand, how to precisely manufacture microstructures such as through-silicon vias (TSVs) while maintaining or improving electrical performance is a key issue. On the other hand, the stress problem caused by the mismatch of thermal expansion coefficients between different materials and the resulting reliability problem also need to be solved urgently. In addition, traditional electroplating filling methods often have the problem of uneven filling, which affects the electrical performance and mechanical stability of the interconnection structure, further restricting the application and development of three-dimensional integration technology.

[0004] In response to the above challenges, although existing research and technical solutions have made certain progress, there are still deficiencies. For example, the choice of surface treatment technology has a direct impact on the formation and quality of micro-bumps, and existing treatment methods may not be able to meet the requirements of high efficiency, low cost, and environmental friendliness at the same time. Another example is that parameter control in the laser-assisted bonding process is crucial for the quality of the finally formed temporary structure, but the current optimization strategies in this regard are not yet mature. The existence of these problems has prompted researchers to continuously explore new methods and technologies to overcome the current limitations and promote the development of three-dimensional high-density interconnection technology to a higher level. Summary of the Invention

[0005] The main object of the present invention is to provide a three-dimensional high-density interconnection method for a substrate and an IC chip, which solves the technical problem that traditional two-dimensional planar interconnection methods are difficult to meet the requirements of high-density integration.

[0006] To achieve the above object, the present invention provides a three-dimensional high-density interconnection method for a substrate and an IC chip, including the following steps: Perform multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon via array structure with a preset aspect ratio; The silicon through-hole array structure is filled with metal by bipolar pulse electroplating to obtain a three-dimensional interconnected conductive path; The surface of the three-dimensional interconnected conductive path is treated by high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization; The micro-bump structure is subjected to laser-assisted bonding to obtain a silicon bridge-substrate temporary structure; The bottom of the silicon bridge-substrate temporary structure is filled by supercritical fluid-assisted injection technology to obtain a packaged structure with stress release function; A preset IC chip is assembled and fixed with the packaged structure to obtain a three-dimensional high-density interconnected package.

[0007] Further, the multi-layer dielectric composite treatment of the preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio includes: The silicon substrate is subjected to high-frequency electromagnetic field-assisted ion bombardment treatment to obtain an etched pretreatment layer with surface activation characteristics; The etched pretreatment layer is subjected to SF6 / O2 mixed gas directional etching by a dual-frequency radio frequency source to obtain a silicon through-hole basic structure with anisotropic characteristics; The silicon through-hole basic structure is subjected to multi-layer dielectric composite treatment by atomic layer deposition to obtain a silicon through-hole array structure with a preset aspect ratio, wherein the silicon through-hole array structure includes a first conductive layer, a second conductive layer, and an insulating dielectric layer located between the first conductive layer and the second conductive layer.

[0008] Further, the filling of the silicon through-hole array structure with metal by bipolar pulse electroplating to obtain a three-dimensional interconnected conductive path includes: The silicon through-hole array structure is subjected to high-frequency magnetron sputtering treatment to obtain a metal seed layer structure with nanoscale roughness; The metal seed layer structure is directionally filled by bipolar pulse electroplating to obtain a metal filling body with a columnar crystal structure; The surface of the metal filling body is planarized by ultrasonic-assisted chemical mechanical polishing to obtain a conductive path base body with nanoscale flatness; The conductive path base body is irradiated and annealed by high-energy ion beams to obtain the three-dimensional interconnected conductive path, wherein the three-dimensional interconnected conductive path includes vertical interconnected metal columns, horizontal interconnected metal layers, and a stress release buffer layer.

[0009] Further, the surface treatment of the three-dimensional interconnected conductive path by high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization includes: Perform high-frequency electrochemical impedance spectroscopy analysis on the three-dimensional interconnected conductive pathways to obtain an activated pretreatment layer with surface electrochemical characteristics; Perform selective de-passivation treatment on the activated pretreatment layer through pulsed reverse current to obtain a metallized base layer with directional growth characteristics; Perform gradient metallization treatment on the metallized base layer through alternating magnetic field-assisted electroplating to obtain a multi-layer metal composite structure; Perform high-energy plasma surface modification treatment on the multi-layer metal composite structure to obtain a surface functional layer with nano-scale roughness; Perform precise regulation on the surface functional layer through electrochemical atomic layer deposition to obtain an interface transition structure with controllable thickness; Perform surface modification on the interface transition structure through high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization; wherein, the micro-bump structure includes a bottom metallization layer, an intermediate transition layer, and a surface functional layer.

[0010] Further, perform laser-assisted bonding on the micro-bump structure to obtain a silicon bridge-substrate temporary structure, including: Perform femtosecond laser surface pretreatment on the micro-bump structure to obtain a surface activation layer with nano-scale periodic structure; Perform precise patterning on the surface activation layer through two-photon lithography to obtain a bonding preform layer with a micro-nano composite structure; Perform interface bonding on the bonding preform layer through femtosecond laser-induced plasma bonding to obtain a primary bonding structure; Perform high-frequency surface acoustic wave-assisted treatment on the primary bonding structure to obtain an interface enhancement layer with acousto-optic coupling characteristics; Perform precise positioning on the interface enhancement layer through near-field optical scanning to obtain a temporary fixing structure with multi-layer interconnect characteristics; Perform interface strengthening on the temporary fixing structure through picosecond laser heat treatment to obtain the silicon bridge-substrate temporary structure, wherein the silicon bridge-substrate temporary structure includes a multi-layer interconnect region, a stress buffer region, and an interface transition region.

[0011] Further, perform bottom filling on the silicon bridge-substrate temporary structure through supercritical fluid-assisted injection technology to obtain a packaging structure with stress release function, including: Perform plasma surface modification on the silicon bridge-substrate temporary structure to obtain a surface activation structure with super-hydrophilic characteristics; Perform precursor coating on the surface activation structure through vacuum plasma-assisted chemical vapor deposition to obtain a filling guiding layer with a nano-porous structure; The bottom filling of the filling guiding layer is carried out by supercritical fluid assisted injection technology to obtain a primary filling structure; The primary filling structure is subjected to microwave plasma curing treatment to obtain a cured matrix with a crosslinked network structure; The cured matrix is subjected to interface strengthening by high-frequency electromagnetic field assisted treatment to obtain a reinforced structure with multi-layer composite characteristics; The reinforced structure is subjected to stress release by vacuum annealing treatment to obtain the encapsulation structure, wherein the encapsulation structure includes a thermal stress buffer layer, an interface strengthening layer and a sealing protection layer.

[0012] Furthermore, the preset IC chip and the encapsulation structure are assembled and fixed to obtain a three-dimensional high-density interconnect package, including: The encapsulation structure and the IC chip are respectively subjected to radio frequency plasma surface activation treatment to obtain an activated pretreatment layer with high surface energy; The surface polarity of the activated pretreatment layers of the IC chip and the encapsulation structure is regulated by high-frequency electromagnetic field assistance to obtain an interface prefabricated layer with directional bonding characteristics; The IC chip and the encapsulation structure are precisely aligned by atomic scale bonding to obtain an IC chip-encapsulation structure positioning structure with nanoscale accuracy; The IC chip-encapsulation structure positioning structure is subjected to high-energy ion beam surface modification to obtain an IC chip-encapsulation structure bonding intermediate with multi-layer composite characteristics; The interface of the IC chip-encapsulation structure bonding intermediate is strengthened by microwave plasma assisted treatment to obtain an IC chip-encapsulation structure fixing matrix with a gradient structure; The structure of the IC chip-encapsulation structure fixing matrix is stabilized by vacuum annealing treatment to obtain the three-dimensional high-density interconnect package, wherein the three-dimensional high-density interconnect package includes a chip interconnect layer, a signal transmission layer and a heat dissipation function layer.

[0013] The present invention also provides a three-dimensional high-density interconnect system for a substrate and an IC chip, including: A composite module for performing multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio; A first filling module for filling the silicon through-hole array structure with metal by bipolar pulse electroplating to obtain three-dimensional interconnect conductive paths; A surface treatment module for performing surface treatment on the three-dimensional interconnect conductive paths by high-frequency ultrasonic assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization; A bonding module for performing laser-assisted bonding on the micro-bump structure to obtain a silicon bridge-substrate temporary structure; A second filling module for bottom filling the silicon bridge-substrate temporary structure by supercritical fluid-assisted injection technology to obtain a packaged structure with stress release function; A fixing module for assembling and fixing a preset IC chip to the packaged structure to obtain a three-dimensional high-density interconnection package.

[0014] The present invention also provides a computer device, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps of the method described in any one of the above are implemented.

[0015] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0016] The three-dimensional high-density interconnection method for a substrate and an IC chip provided by the present invention includes the following steps: performing multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio; performing metal filling on the silicon through-hole array structure to obtain three-dimensional interconnection conductive paths; performing surface treatment on the three-dimensional interconnection conductive paths to obtain a micro-bump structure with gradient metallization; performing laser-assisted bonding on the micro-bump structure to obtain a silicon bridge-substrate temporary structure; performing bottom filling on the silicon bridge-substrate temporary structure by supercritical fluid-assisted injection technology to obtain a packaged structure with stress release function; assembling and fixing a preset IC chip to the packaged structure to obtain a three-dimensional high-density interconnection package, solving the technical problem that the traditional two-dimensional planar interconnection method is difficult to meet the requirements of high-density integration, realizing the assembly and fixing of a preset IC chip to the packaged structure, and realizing the construction of a three-dimensional high-density interconnection package. This method not only improves the integration degree of the chip, but also increases the flexibility in the design and manufacturing process, laying a foundation for the development of smaller-sized and higher-performance electronic devices. Description of the Drawings

[0017] Figure 1 is a schematic diagram of the steps of the three-dimensional high-density interconnection method for a substrate and an IC chip in an embodiment of the present invention; Figure 2 is a block diagram of the structure of the three-dimensional high-density interconnection system for a substrate and an IC chip in an embodiment of the present invention; Figure 3 is a schematic block diagram of the structure of a computer device in an embodiment of the present invention.

[0018] The realization, functional characteristics and advantages of the object of the present invention will be further described with reference to the embodiments and the drawings. Detailed implementation manners

[0019] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] As Figure 1 shown Figure 1 is a schematic diagram of the steps of a three-dimensional high-density interconnection method for a substrate and an IC chip in an embodiment of the present invention; An embodiment of the present invention provides a three-dimensional high-density interconnection method for a substrate and an IC chip, including the following steps: Step S1, perform multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio.

[0021] Specifically, performing multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio is one of the key steps in implementing the three-dimensional high-density interconnection method. Specifically, first, a suitable silicon substrate needs to be selected as the base material, and this silicon substrate is usually processed precisely to meet the requirements of subsequent processes. Then, dielectric layers are formed on the silicon substrate through multi-layer dielectric composite treatment technology. These dielectric layers not only play an insulating and protective role but also provide a stable support structure for the subsequent manufacturing of silicon through-holes. In order to achieve a silicon through-hole array structure with a preset aspect ratio, advanced technologies such as deep reactive ion etching (DRIE) are usually used. This method can accurately etch vertical and uniform through-holes in the silicon substrate while ensuring that its aspect ratio meets the design requirements. For example, in the packaging scenario of high-performance computing chips, the aspect ratio of silicon through-holes directly affects the signal transmission efficiency and thermal management effect, so it must be strictly controlled. In addition, multi-layer dielectric composite treatment also includes depositing appropriate dielectric materials on the inner walls of the through-holes to improve their electrical performance and prevent the generation of leakage current. Through the above steps, the finally formed silicon through-hole array structure not only has the characteristics of a high aspect ratio but also can meet the requirements of subsequent metal filling and gradient metallization treatment, thus laying a solid foundation for realizing three-dimensional interconnection conductive paths. The application scenarios of this technology can be extended to the packaging fields of 5G communication devices or artificial intelligence chips, where high-density interconnection and signal integrity are core requirements, and high-quality silicon through-hole array structures are important guarantees for achieving these goals.

[0022] Step S2, perform metal filling on the silicon through-hole array structure by bipolar pulse electroplating to obtain three-dimensional interconnection conductive paths.

[0023] Specifically, metal filling of the silicon via array structure is carried out by bipolar pulse electroplating, aiming to obtain three-dimensional interconnect conductive paths, which is crucial for realizing high-density electronic packaging. First, before metal filling, the inner walls of the silicon vias need to be pretreated to enhance their surface activity, which usually involves cleaning and activation steps to ensure uniform attachment of metal during subsequent electroplating. Then, bipolar pulse electroplating technology is adopted. This technology uses alternating positive and negative current pulses to promote the effective deposition of metal ions inside the silicon vias. Compared with traditional direct current electroplating, bipolar pulse electroplating can reduce the formation of voids and cracks while increasing the filling rate and quality. This is because the positive pulse helps the rapid deposition of metal ions, while the negative pulse can effectively remove impurities and loose particles on the electrode surface, thus ensuring the density and uniformity of the filling layer. For example, in the packaging application of high-performance computing chips, high-quality metal filling is one of the key factors to ensure signal integrity and reduce resistance. By optimizing the parameters of bipolar pulses, such as frequency, duty cycle, and current density, the effect of metal filling can be precisely controlled, and finally, three-dimensional interconnect conductive paths with good electrical performance are formed. This technology not only improves the reliability of the interconnection but also provides an ideal substrate for subsequent high-frequency ultrasonic-assisted electrochemical processing technology to further process and obtain micro-bump structures with gradient metallization, meeting the requirements of modern electronic devices for high integration and high performance. Therefore, this step plays an indispensable role in realizing three-dimensional high-density interconnection.

[0024] Step S3: The surface of the three-dimensional interconnect conductive path is processed by high-frequency ultrasonic-assisted electrochemical processing technology to obtain a micro-bump structure with gradient metallization.

[0025] Specifically, the surface of the three-dimensional interconnected conductive path is treated by a high-frequency ultrasonic-assisted electrochemical treatment technique to obtain a microbump structure with gradient metallization. This process plays a crucial role in three-dimensional high-density interconnect packaging. Specifically, after metal filling, the surface characteristics of the three-dimensional interconnected conductive path are crucial for subsequent bonding and packaging performance, and the high-frequency ultrasonic-assisted electrochemical treatment technique is the core means to optimize these surface characteristics. In actual operation, the role of high-frequency ultrasonic waves can not only accelerate the flow of the electrolyte inside the through holes but also effectively remove the surface oxide layer and impurities, thereby improving the quality of metal deposition. At the same time, the electrochemical treatment technique can form a microbump structure with gradient metallization on the surface of the conductive path by controlling parameters such as current density, electrolyte composition, and treatment time. The characteristic of this gradient metallization is that the metal composition or thickness gradually changes from the bottom to the top, thereby enhancing the mechanical strength and electrical performance of the microbump. For example, in the packaging scenario of high-performance computing chips, this microbump structure can significantly improve the connection reliability between the chip and the substrate. Especially in a high-temperature and high-pressure working environment, its anti-fatigue and conductivity performance are particularly prominent. In addition, this method can also reduce the stress problem caused by the mismatch of the coefficient of thermal expansion and provide a more ideal bonding interface for subsequent laser-assisted bonding. Therefore, the gradient metallization microbump structure achieved by the high-frequency ultrasonic-assisted electrochemical treatment technique not only improves the overall performance of three-dimensional interconnection but also lays a solid foundation for finally forming a stable silicon bridge-substrate temporary structure, meeting the stringent requirements of modern electronic devices for high density and high reliability.

[0026] Step S4: Perform laser-assisted bonding on the microbump structure to obtain a silicon bridge-substrate temporary structure.

[0027] Specifically, laser-assisted bonding of the microbump structure to obtain a silicon bridge-substrate temporary structure is a key step in achieving efficient and reliable three-dimensional high-density interconnect packaging. This process first relies on precise laser technology. By controlling parameters such as the energy density, pulse width, and wavelength of the laser, local heating is applied to the microbump structure. During laser-assisted bonding, the laser beam precisely irradiates the preset microbump positions, causing the microbump materials to rapidly heat up and reach their softened or molten state without causing unnecessary thermal effects on the surrounding materials. The purpose of this is to enable the microbumps to form a solid metallurgical bond with the corresponding bonding surfaces (such as the silicon bridge or substrate), thereby ensuring the reliability of electrical connections and the strength of mechanical connections. In this process, the advantage of laser-assisted bonding is that it can provide a highly controllable local heating effect, which is particularly crucial for dealing with connections between materials with different coefficients of thermal expansion. For example, in the application scenario of high-performance computing chips, the connection between the chip and the substrate requires extremely high precision and stability to ensure the integrity of signal transmission and the long-term reliability of the device. Through laser-assisted bonding, not only can the stress problems that may be introduced by traditional welding methods be reduced, but also the production efficiency and the yield can be effectively improved. In addition, this technology also supports smaller-size and higher-density interconnect designs, providing greater innovation space for future electronic devices. Finally, the silicon bridge-substrate temporary structure formed through this process step not only has excellent electrical performance and mechanical stability, but also is ready for further underfilling and packaging processes, ensuring the reliability and durability of the entire three-dimensional high-density interconnect package.

[0028] Step S5: Perform underfilling on the silicon bridge-substrate temporary structure through supercritical fluid-assisted injection technology to obtain a packaged structure with stress relief function.

[0029] Specifically, the bottom filling of the silicon bridge-substrate temporary structure is carried out by supercritical fluid assisted injection technology, aiming to obtain a packaging structure with stress release function, which is an important step in realizing efficient and reliable three-dimensional high-density interconnect packaging. First of all, supercritical fluid (such as carbon dioxide) exhibits unique properties that are neither gaseous nor liquid under specific temperature and pressure conditions, which enables it to effectively penetrate into tiny spaces, such as the fine gaps formed between the silicon bridge and the substrate. During the actual operation process, supercritical fluid is used to carry the filling material (usually a low-viscosity thermosetting resin). Due to its extremely low viscosity and excellent diffusion ability, these filling materials can be evenly distributed in all the gaps of the silicon bridge-substrate temporary structure, including those hard-to-reach corners and small voids. The key advantage of using supercritical fluid assisted injection technology is that it can complete precise and comprehensive filling without damaging the silicon bridge or the substrate. This method not only avoids the problems of bubbles and voids that may occur in traditional filling processes, but also can significantly reduce the internal stress accumulation caused by the difference in thermal expansion coefficients. For example, in the packaging application of high-performance computing chips, the application of this technology is crucial for improving the stability and reliability of the overall packaging structure. When the filling material solidifies, it can not only provide physical support, but also effectively absorb the mechanical stress caused by factors such as temperature changes, thus protecting the internal precision electronic components from damage. In addition, supercritical fluid assisted injection technology can also adjust the composition and properties of the filling material according to specific requirements to further optimize the performance of the packaging structure, such as enhancing thermal conductivity or improving electrical insulation. Finally, through this series of delicate operations, a packaging structure with excellent stress release function is obtained, laying a solid foundation for the subsequent assembly and fixation of the preset IC chip with the packaging structure, and ensuring the long-term stable operation of the three-dimensional high-density interconnect package.

[0030] Step S6: Assemble and fix the preset IC chip with the packaging structure to obtain a three-dimensional high-density interconnect package.

[0031] Specifically, assembling and fixing a preset IC chip to the encapsulation structure to obtain a three-dimensional high-density interconnect package is the final implementation stage of the entire three-dimensional high-density interconnect method and a key step to ensure the performance and reliability of the package. In this process, first, the encapsulation structure that has undergone underfill treatment and has a stress relief function needs to be accurately aligned with the preset IC chip. This alignment usually relies on high-precision automated equipment, such as an optical alignment system or a micron-level positioning platform, to ensure that the pads on the IC chip can accurately match the microbumps on the encapsulation structure. Then, the IC chip is firmly fixed to the encapsulation structure through thermocompression bonding, reflow soldering, or other suitable connection technologies. In the application scenario of high-performance computing chips, special attention needs to be paid to the quality of the connection interface during this assembly process because any minor deviation may lead to a decrease in signal transmission efficiency or electrical performance instability. In addition, to further improve the effect of assembly and fixation, auxiliary materials such as conductive adhesives or low-melting-point alloys can be introduced at the connection interface. These materials can not only enhance the mechanical connection strength but also improve the electrical contact performance. For example, in high-end application scenarios such as 5G communication devices or artificial intelligence accelerators, the connection between the IC chip and the encapsulation structure must meet the requirements of high-frequency signal transmission and efficient heat dissipation. Therefore, the design of the assembly process must take into account electrical performance, thermal management, and mechanical stability. After the assembly is completed, the entire package forms a compact and highly integrated three-dimensional structure, in which the silicon bridge, substrate, IC chip, and the interconnection paths between each layer together form a complete circuit system. This three-dimensional high-density interconnect package not only significantly improves the functional density and performance of electronic devices but also provides technical support for future smaller and higher-performance electronic devices. Finally, through this series of precise operations, the seamless connection from individual components to the overall package is achieved, laying an important foundation for the development of modern electronic packaging technology.

[0032] In a specific embodiment, the multi-layer dielectric composite treatment of the preset silicon substrate to obtain a silicon via array structure with a preset aspect ratio includes: Performing high-frequency electromagnetic field-assisted ion bombardment treatment on the silicon substrate to obtain an etched pretreatment layer with surface activation characteristics; Performing directional etching on the etched pretreatment layer with a SF6 / O2 mixed gas through a dual-frequency radio frequency source to obtain a silicon via basic structure with anisotropic characteristics; Performing multi-layer dielectric composite treatment on the silicon via basic structure through atomic layer deposition to obtain a silicon via array structure with a preset aspect ratio, where the silicon via array structure includes a first conductive layer, a second conductive layer, and an insulating dielectric layer located between the first conductive layer and the second conductive layer.

[0033] Specifically, in modern electronic packaging technology, in order to achieve a more efficient and higher-density interconnect structure, multi-layer dielectric composite treatment of a preset silicon substrate to obtain a silicon via hole array structure with a preset aspect ratio has become one of the key steps. This process first requires high-frequency electromagnetic field-assisted ion bombardment treatment of the silicon substrate, the purpose of which is to activate the surface of the silicon substrate through this high-energy treatment method to form an etching pretreatment layer with surface activation characteristics. The operation at this stage is crucial because only the surface-activated silicon substrate can better react with the chemicals in the subsequent process to ensure the smooth progress of the subsequent etching and deposition processes. For example, in the manufacturing process of high-performance computing chips, this step can significantly improve the compatibility between the silicon substrate and other materials, laying the foundation for building an efficient three-dimensional interconnect structure. Next, a dual-frequency radio frequency source is used to perform directional etching on the etching pretreatment layer with an SF6 / O2 mixed gas to obtain a silicon via hole basic structure with anisotropic characteristics. In this process, choosing the appropriate frequency combination is crucial for obtaining high-quality silicon via holes. The application of a dual-frequency radio frequency source enables precise adjustment of the etching rate and direction on the basis of controlling plasma characteristics to ensure that the formed silicon via holes not only have a moderate depth but also smooth and vertical walls, meeting the requirements of high-density integration. In addition, using an SF6 / O2 mixed gas as the etching medium can effectively balance the strong etching effect of fluorine atoms on silicon materials and the passivation effect of oxygen, avoiding over-etching or under-etching problems. In actual operation, for example, when producing chips suitable for 5G communication devices, precise silicon via hole etching is crucial for ensuring the quality and efficiency of signal transmission, so the technical details of this link cannot be ignored. Subsequently, atomic layer deposition (ALD) technology is used to perform multi-layer dielectric composite treatment on the silicon via hole basic structure to finally obtain a silicon via hole array structure with a preset aspect ratio. Atomic layer deposition is an advanced thin film growth technology that grows single atomic layers on the surface in turn by alternately exposing to different precursors, thus achieving extremely high film thickness control accuracy and uniformity. In this process, the first conductive layer, the second conductive layer, and the insulating dielectric layer located between the two are deposited in sequence. These conductive layers are usually composed of metal materials such as copper or aluminum, while the insulating dielectric layer is selected from silicon dioxide or other low dielectric constant materials to reduce parasitic capacitance and improve circuit performance. It should be noted that the selection of each layer of material needs to consider factors such as its electrical performance, thermal stability, and mechanical strength to meet the requirements of specific application scenarios. For example, in the design of artificial intelligence accelerators, by optimizing the selection and arrangement of the materials inside the silicon via holes, not only can the data processing speed be improved, but also the energy consumption can be effectively reduced and the overall performance of the system can be enhanced. The entire process starts from the high-frequency electromagnetic field-assisted ion bombardment treatment of the silicon substrate and finally completes the multi-layer dielectric composite treatment through atomic layer deposition to form a complete silicon via hole array structure.This series of complex technological steps work together to not only achieve the precise manufacturing of through-silicon vias but also provide an ideal physical basis for subsequent processes such as metal filling, micro-bump structure formation, and laser-assisted bonding. Especially in the current development trend of electronic products towards miniaturization and multi-functionality, the application of this three-dimensional high-density interconnect technology is particularly important. For example, when developing a new generation of smart wearable devices, the three-dimensional interconnect package constructed through the above technical route can significantly reduce the device size while increasing its functional density and operating efficiency, meeting the dual requirements of consumers for portability and performance. In short, through the careful design and strict control of every technical detail, we can effectively promote the development of electronic packaging technology towards a more advanced and reliable direction.

[0034] In a specific embodiment, the metal filling of the through-silicon via array structure by bipolar pulse electroplating to obtain a three-dimensional interconnect conductive path includes: Performing high-frequency magnetron sputtering treatment on the through-silicon via array structure to obtain a metal seed layer structure with nanoscale roughness; Performing directional filling on the metal seed layer structure by bipolar pulse electroplating to obtain a metal filling body with a columnar crystal structure; Performing surface planarization treatment on the metal filling body by ultrasonic-assisted chemical mechanical polishing to obtain a conductive path substrate with nanoscale flatness; Performing high-energy ion beam irradiation annealing on the conductive path substrate to obtain the three-dimensional interconnect conductive path, where the three-dimensional interconnect conductive path includes vertical interconnect metal columns, horizontal interconnect metal layers, and stress release buffer layers.

[0035] Specifically, in modern electronic packaging technology, metal filling of the through-silicon via (TSV) array structure by bipolar pulse electroplating to obtain three-dimensional interconnect conductive pathways is a key technology. First, the TSV array structure is subjected to high-frequency magnetron sputtering treatment to form a metal seed layer structure with nanoscale roughness. This process utilizes high-frequency magnetic fields and ion bombardment to precisely control the deposition of sputtering materials (such as copper or aluminum) on the surface of the TSVs, ensuring that the seed layer not only uniformly covers the entire inner wall of the vias but also has a certain roughness to enhance the adhesion of the subsequent electroplated layer. For example, in the manufacturing process of high-performance computing chips, the preparation of such a high-precision seed layer is crucial for ensuring the quality of subsequent metal filling, as it directly affects the reliability and electrical performance of the finally formed vertical interconnect metal pillars. Next, the metal seed layer structure is directionally filled by bipolar pulse electroplating to obtain a metal filling body with a columnar crystal structure. In this step, the bipolar pulse electroplating technology plays a key role. Compared with traditional direct current electroplating, bipolar pulse electroplating can more effectively reduce the generation of voids and cracks and helps to form a denser and more uniform filling effect. Specifically, the forward pulse is used to accelerate the deposition of metal ions, while the reverse pulse helps to remove impurities and loose particles during the deposition process, enabling a columnar crystal structure to form inside the filling body. This structure not only improves the overall strength of the filling body but also optimizes its conductive performance. For example, in the application scenario of 5G communication devices, high-quality metal filling is the basis for achieving efficient signal transmission, so this step is particularly critical for enhancing the overall performance of the device. Subsequently, ultrasonic-assisted chemical mechanical polishing is used to perform surface planarization on the metal filling body to obtain a conductive via substrate with nanoscale flatness. Ultrasonic-assisted chemical mechanical polishing is an advanced surface treatment technology that combines the advantages of ultrasonic vibration and chemical reaction. It can effectively remove the tiny protrusions and irregularities on the surface of the metal filling body without damaging the underlying structure, thereby obtaining an extremely smooth surface. This is very important for subsequent process steps, such as laser-assisted bonding, because any surface unevenness may lead to poor contact or increased resistance. In the design of artificial intelligence accelerators, such high-precision surface treatment can significantly improve the connection quality between chips, thereby enhancing data processing speed and efficiency. Finally, the conductive via substrate is subjected to high-energy ion beam irradiation annealing to obtain the three-dimensional interconnect conductive pathway. This process uses high-energy ion beams to locally heat the conductive via substrate, promoting the rearrangement of metal atoms and eliminating possible stress concentration points. After high-energy ion beam irradiation annealing treatment, the formed three-dimensional interconnect conductive pathway includes vertical interconnect metal pillars, horizontal interconnect metal layers, and stress release buffer layers. These components work together to not only achieve efficient electrical interconnection but also effectively relieve the internal stress problem caused by differences in thermal expansion coefficients.For example, in the design of smart wearable devices, the three-dimensional interconnected package constructed through the above series of precise processing steps can not only significantly reduce the device size, but also remarkably improve its functional density and operating stability, meeting the dual requirements of users for portability and performance. In summary, starting from the high-frequency magnetron sputtering treatment of the through-silicon via array structure to the final completion of the construction of the three-dimensional interconnected conductive path through high-energy ion beam irradiation annealing, each step requires careful design and strict control. This not only ensures good connection between layers, but also provides a solid foundation for subsequent packaging and integration. Especially in the current trend of miniaturization and multi-functionality of electronic products, the application of this advanced three-dimensional high-density interconnect technology is particularly important. By continuously optimizing the technical details of each step, we can further promote the development of electronic packaging technology towards a more advanced and reliable direction, paving the way for more innovative applications in the future.

[0036] In a specific embodiment, the surface treatment of the three-dimensional interconnected conductive path by the high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization includes: Performing high-frequency electrochemical impedance spectroscopy analysis on the three-dimensional interconnected conductive path to obtain an activated pretreatment layer with surface electrochemical characteristics; Performing selective de-passivation treatment on the activated pretreatment layer through pulsed reverse current to obtain a metallized base layer with directional growth characteristics; Performing gradient metallization treatment on the metallized base layer through alternating magnetic field-assisted electroplating to obtain a multi-layer metal composite structure; Performing high-energy plasma surface modification treatment on the multi-layer metal composite structure to obtain a surface functional layer with nano-scale roughness; Performing precise regulation on the surface functional layer through electrochemical atomic layer deposition to obtain an interfacial transition structure with controllable thickness; Performing surface modification on the interfacial transition structure through the high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization; wherein, the micro-bump structure includes a bottom metallization layer, an intermediate transition layer, and a surface functional layer.

[0037] Specifically, in modern electronic packaging technology, the surface treatment of the three-dimensional interconnected conductive pathways by high-frequency ultrasonic-assisted electrochemical processing technology to obtain a micro-bump structure with gradient metallization is a complex and precise process. First, high-frequency electrochemical impedance spectroscopy analysis is performed on the three-dimensional interconnected conductive pathways, aiming to obtain an activated pretreatment layer with surface electrochemical characteristics. This analysis method can accurately measure and evaluate the electrochemical characteristics of the material surface, providing basic data support for subsequent steps. For example, in actual operation, the electrochemical impedance spectroscopy analysis can identify the differences in electrochemical activity in different regions, which is crucial for achieving uniform and efficient activation. Research shows that the activated pretreatment layer after this step can significantly improve the adhesion and uniformity in the subsequent electroplating process. Next, selective de-passivation treatment is performed on the activated pretreatment layer through pulsed reverse current, aiming to obtain a metallized base layer with directional growth characteristics. The pulsed reverse current technology can effectively remove surface oxides and other impurities, while promoting the deposition of metal ions at specific positions. This method not only improves the deposition efficiency but also ensures the directionality and uniformity of the deposited layer. For example, in the manufacturing process of high-performance computing chips, the pulsed reverse current technology can control the thickness of the metallized base layer at the nanoscale (such as 50 - 100 nm), which greatly improves the stability and reliability of subsequent processes. Subsequently, gradient metallization treatment is performed on the metallized base layer by alternating magnetic field-assisted electrodeposition to form a multi-layer metal composite structure. The application of the alternating magnetic field can introduce an additional energy source during the electrodeposition process, enabling metal atoms to be arranged orderly in a predetermined direction to form a multi-layer structure with gradient changes. For example, when constructing a package suitable for 5G communication devices, a multi-layer composite structure composed of different metals such as copper and nickel can be obtained through this method, and its thickness can vary from a few nanometers to several hundred nanometers (such as the thickness of each layer is about 20 - 50 nm), which can not only ensure good electrical conductivity but also effectively relieve the stress problem caused by the mismatch of the coefficient of thermal expansion. After that, high-energy plasma surface modification treatment is performed on the multi-layer metal composite structure to obtain a surface functional layer with nanoscale roughness. The high-energy plasma surface modification technology uses high-energy particles to bombard the material surface, changing its physical and chemical properties. This process can not only increase the surface roughness but also introduce specific functional elements to improve the hydrophilicity or hydrophobicity of the surface. For example, in the design of artificial intelligence accelerators, the roughness of the surface functional layer can reach dozens of nanometers (such as 30 - 50 nm) through this technology, thus significantly improving the bonding strength in the subsequent bonding process. Immediately afterwards, precise regulation is performed on the surface functional layer through electrochemical atomic layer deposition to obtain an interface transition structure with controllable thickness.Electrochemical atomic layer deposition is a highly precise thin-film deposition technique that allows for the layer-by-layer deposition of materials, with the thickness of each layer precisely controllable at the single-atomic layer level (about 0.1 - 0.5 nm). Therefore, when manufacturing high-performance electronic products, an extremely thin yet highly uniform interfacial transition layer can be constructed through this method, which is very important for reducing contact resistance and enhancing the stability of electrical connections. Finally, the surface of the interfacial transition structure is modified by high-frequency ultrasonic-assisted electrochemical treatment technology to finally obtain a micro-bump structure with gradient metallization. The role of high-frequency ultrasonic waves is to accelerate the flow of the electrolyte, ensure that metal ions in the solution can be evenly distributed on the micro-bump structure, and promote its good bonding with the substrate. For example, in the design of smart wearable devices, a micro-bump structure with a diameter of about 5 - 10 μm and a height of 2 - 5 μm can be prepared through this technology. The combined action of its bottom metallization layer, intermediate transition layer, and surface functional layer not only enhances the mechanical strength but also optimizes the electrical performance. In summary, through the above series of precise processing steps, a high-quality gradient metallization micro-bump structure can be achieved, providing strong support for the development of modern electronic packaging technology.

[0038] In a specific embodiment, laser-assisted bonding of the micro-bump structure is performed to obtain a silicon bridge - substrate temporary structure, including: Femtosecond laser surface pretreatment is performed on the micro-bump structure to obtain a surface activation layer with a nano-scale periodic structure; Precise patterning treatment is performed on the surface activation layer through two-photon lithography to obtain a bonding preform layer with a micro-nano composite structure; Interface bonding of the bonding preform layer is performed through femtosecond laser-induced plasma bonding to obtain a primary bonding structure; High-frequency surface acoustic wave-assisted treatment is performed on the primary bonding structure to obtain an interface enhancement layer with acousto-optic coupling characteristics; Precise positioning treatment is performed on the interface enhancement layer through near-field optical scanning to obtain a temporary fixation structure with multi-layer interconnection characteristics; Interface strengthening of the temporary fixation structure is performed through picosecond laser heat treatment to obtain the silicon bridge - substrate temporary structure, where the silicon bridge - substrate temporary structure includes a multi-layer interconnection region, a stress buffer region, and an interface transition region.

[0039] Specifically, in modern electronic packaging technology, laser-assisted bonding of the microbump structure to obtain a silicon bridge-substrate temporary structure is a complex and precise process. First, femtosecond laser surface pretreatment is performed on the microbump structure to obtain a surface activation layer with a nanoscale periodic structure. Femtosecond lasers, with their extremely short pulse widths and high peak powers, can achieve fine processing without damaging the material, forming periodic structures on the nanoscale (about 10 - 50 nm). This structure can not only significantly improve the bonding strength in subsequent processes but also enhance the physical and chemical activity of the material surface. For example, in the manufacturing process of high-performance computing chips, this surface pretreatment can ensure a more stable connection between the chip and the substrate, thereby improving the reliability of the overall package. Next, two-photon lithography is used to precisely pattern the surface activation layer to obtain a bonding preform layer with a micro-nano composite structure. Two-photon lithography is a high-precision pattern transfer technology that uses the two-photon absorption effect to achieve sub-micron resolution. This step can create complex three-dimensional structures on the surface activation layer, which usually have micron-scale (such as 1 - 5 μm) and nanoscale feature sizes, jointly constituting the bonding preform layer. In the application scenario of 5G communication devices, such micro-nano composite structures help improve signal transmission efficiency while providing mechanical support, ensuring the stability of the interconnect structure. Subsequently, femtosecond laser-induced plasma bonding is used to perform interface bonding on the bonding preform layer to form a primary bonded structure. Femtosecond laser-induced plasma bonding uses the high-temperature and high-pressure plasma generated by laser pulses to instantaneously melt and re-solidify the material surface, forming a strong metallurgical bond. This process is not only fast and efficient but also capable of achieving non-destructive bonding, especially suitable for processing sensitive materials. For example, in the design of artificial intelligence accelerators, seamless docking between different materials can be achieved through this method, and the thickness of the bonding area can be controlled within a few microns (such as 3 - 8 μm), ensuring both electrical performance and mechanical stability. Then, high-frequency surface acoustic wave (SAW) assistance is performed on the primary bonded structure to obtain an interface enhancement layer with acousto-optic coupling characteristics. High-frequency surface acoustic wave (SAW) technology applies acoustic wave vibrations at a specific frequency to induce local stress changes within the material, thereby optimizing the interface bonding quality. This treatment method can not only eliminate possible bubbles or voids at the interface but also introduce beneficial acousto-optic coupling effects to improve signal transmission efficiency. For example, in the development of smart wearable devices, the interface enhancement layer after high-frequency surface acoustic wave treatment can effectively reduce signal loss and enhance the user experience. After that, near-field optical scanning is used to precisely position the interface enhancement layer to obtain a temporary fixed structure with multi-layer interconnect characteristics. Near-field optical scanning uses an ultra-high-resolution optical system to achieve precise positioning and detection at the nanoscale. This step is crucial for ensuring the correct arrangement of the multi-layer interconnect structure.For example, when constructing a package suitable for Internet of Things (IoT) devices, precise positioning with an error of no more than 10 nm between interconnect structures can be achieved through near-field optical scanning, thus ensuring efficient communication and collaborative work between layers. Finally, the interface of the temporary fixing structure is strengthened by picosecond laser heat treatment to finally obtain the silicon bridge-substrate temporary structure. Picosecond laser heat treatment is a non-contact heating method that can selectively heat a local area of the material by precisely controlling the energy density and action time of the laser. This method can not only effectively relieve thermal stress but also enhance the interfacial bonding strength. For example, in the packaging of high-end server chips, picosecond laser heat treatment can optimize the multi-layer interconnect area, stress buffer area, and interface transition area of the silicon bridge-substrate temporary structure, where the thickness of the stress buffer area can be controlled within dozens of micrometers (such as 20 - 50 μm) to ensure the stability and reliability of the entire structure under extreme environments. In summary, through a series of precise processing steps for the micro-bump structure, from femtosecond laser surface pretreatment to picosecond laser heat treatment, each link lays the foundation for the final formation of a high-quality silicon bridge-substrate temporary structure. The comprehensive application of these technologies not only improves the overall performance of electronic packaging but also provides technical support for future smaller and higher-performance electronic products. For example, in the construction of future data centers, this advanced packaging technology can significantly improve the working efficiency and energy efficiency ratio of servers to meet the growing data processing requirements.

[0040] In a specific embodiment, bottom filling of the silicon bridge-substrate temporary structure is performed by supercritical fluid-assisted injection technology to obtain a package structure with stress release function, including: Performing plasma surface modification treatment on the silicon bridge-substrate temporary structure to obtain a surface-activated structure with superhydrophilic characteristics; Coating a precursor on the surface-activated structure by vacuum plasma-assisted chemical vapor deposition to obtain a filling guiding layer with a nanoporous structure; Performing bottom filling on the filling guiding layer by supercritical fluid-assisted injection technology to obtain a primary filling structure; Performing microwave plasma curing treatment on the primary filling structure to obtain a cured matrix with a crosslinked network structure; Performing interface strengthening on the cured matrix by high-frequency electromagnetic field-assisted treatment to obtain a reinforced structure with multi-layer composite characteristics; Performing stress release on the reinforced structure by vacuum annealing treatment to obtain the package structure, where the package structure includes a thermal stress buffer layer, an interface strengthening layer, and a sealing protection layer.

[0041] Specifically, in modern electronic packaging technology, bottom filling the silicon bridge-substrate temporary structure by supercritical fluid assisted injection technology to obtain a packaging structure with stress release function is a key step. First, the silicon bridge-substrate temporary structure is subjected to plasma surface modification treatment, aiming to obtain a surface activation structure with superhydrophilic characteristics. This process uses high-energy particles in the plasma to bombard the material surface, changing its physical and chemical properties, making its surface extremely hydrophilic, thus improving the wettability and adhesion of the subsequent filling material. For example, in the application scenario of high-performance computing chips, this surface modification treatment can reduce the contact angle to less than 10 degrees, ensuring that the filling material can evenly cover the entire structure. Next, the surface activation structure is coated with a precursor by vacuum plasma assisted chemical vapor deposition (PECVD), aiming to obtain a filling guiding layer with a nanoporous structure. In this process, the PECVD technology can convert gas precursors into solid thin films in a highly controlled vacuum environment, forming nanoporous structures with a nanoscale size (about 20-50 nm). These nanoporous structures not only provide a larger surface area but also promote the penetration of the filling material. For example, in the design of 5G communication devices, this nanoporous structure can significantly improve the bonding strength between the filling material and the substrate, enhancing the mechanical stability of the overall package. Subsequently, the filling guiding layer is bottom filled by supercritical fluid assisted injection technology to obtain a primary filling structure. Supercritical fluids (such as carbon dioxide) exhibit unique properties that are neither like gases nor like liquids under specific conditions, which enables them to carry low-viscosity filling materials deep into tiny gaps. For example, in the manufacturing process of artificial intelligence accelerators, the supercritical fluid assisted injection technology can achieve precise and defect-free filling, and the thickness of the filling layer can be controlled within a few micrometers (such as 3-8 μm), effectively avoiding the problems of bubbles and voids that may occur in traditional filling methods. Then, the primary filling structure is subjected to microwave plasma curing treatment to obtain a cured matrix with a cross-linked network structure. The microwave plasma curing technology uses microwave energy to activate the reactants in the plasma environment, promoting cross-linking reactions inside the filling material to form a stable three-dimensional network structure. This structure not only improves the mechanical strength of the material but also enhances its thermal stability and chemical corrosion resistance. For example, in the design of smart wearable devices, the filling material after microwave plasma curing can maintain good performance in extreme environments, and its cross-linking density can reach millions of cross-linking points per cubic millimeter (about 5-10 million / mm³). Then, the cured matrix is subjected to interface strengthening by high-frequency electromagnetic field assistance to obtain a reinforced structure with multi-layer composite characteristics. The role of the high-frequency electromagnetic field is to promote the interaction between molecules, further enhancing the interfacial bonding force between the filling material and the substrate.For example, in the packaging of high-end server chips, by this method, the bonding strength at the interface can be significantly improved, enabling the bonding force between the filling material and the substrate to increase to several hundred megapascals (such as 300 - 500 MPa), ensuring the overall stability of the packaging structure. Finally, stress release of the enhanced structure is performed through vacuum annealing treatment to finally obtain the packaged structure body. Vacuum annealing is an effective heat treatment method that eliminates internal stress by heating the material in a vacuum environment while avoiding problems such as oxidation. For example, during the long-term operation of data center servers, the packaged structure body treated by vacuum annealing can effectively relieve the thermal stress caused by temperature changes, and the thickness of its stress buffer layer can be controlled within dozens of micrometers (such as 20 - 40 μm), thereby extending the service life of the device and improving reliability. In summary, through a series of precise processing steps for the silicon bridge - substrate temporary structure body, from plasma surface modification treatment to vacuum annealing treatment, each link lays the foundation for the final formation of a high-quality packaged structure body. The comprehensive application of these technologies not only improves the overall performance of electronic packaging but also provides technical support for future smaller and higher-performance electronic products. For example, in the construction of future data centers, this advanced packaging technology can significantly improve the working efficiency and energy efficiency ratio of servers, meeting the growing data processing requirements. In addition, by optimizing the technical details of each process step, the reliability and durability of the packaged structure body can be further improved, ensuring its stable operation in complex environments.

[0042] In a specific embodiment, the assembling and fixing of the preset IC chip with the packaged structure body to obtain a three-dimensional high-density interconnect package includes: Performing radio frequency plasma surface activation treatment on the packaged structure body and the IC chip respectively to obtain an activation pretreatment layer with high surface energy; Regulating the surface polarity of the activation pretreatment layers of the IC chip and the packaged structure body through high-frequency electromagnetic field assistance to obtain an interface prefabricated layer with directional bonding characteristics; Performing precise alignment treatment on the IC chip and the packaged structure body through atomic-scale bonding to obtain an IC chip - packaged structure body positioning structure with nanoscale accuracy; Performing high-energy ion beam surface modification on the IC chip - packaged structure body positioning structure to obtain an IC chip - packaged structure body bonding intermediate with multi-layer composite characteristics; Performing interface strengthening on the IC chip - packaged structure body bonding intermediate through microwave plasma-assisted treatment to obtain an IC chip - packaged structure body fixing matrix with a gradient structure; The structure of the fixed substrate of the IC chip-packaging structure is stabilized by vacuum annealing treatment to obtain the three-dimensional high-density interconnect packaging body, wherein the three-dimensional high-density interconnect packaging body includes a chip interconnect layer, a signal transmission layer, and a heat dissipation functional layer.

[0043] Specifically, in modern electronic packaging technology, assembling and fixing a preset IC chip with a packaging structure to obtain a three-dimensional high-density interconnect packaging body is a complex and precise process. First, the packaging structure and the IC chip are respectively subjected to radio frequency plasma surface activation treatment, aiming to obtain an activated pretreatment layer with high surface energy. This process uses high-energy particles in the radio frequency plasma to bombard the material surface, removing surface contaminants and introducing active groups, thereby increasing its surface energy. For example, in the application scenario of high-performance computing chips, this surface activation treatment can reduce the contact angle to less than 5 degrees, ensuring good bonding between materials during the subsequent bonding process. Next, the surface polarity of the activated pretreatment layers of the IC chip and the packaging structure is regulated by means of high-frequency electromagnetic fields to obtain an interface prefabricated layer with directional bonding characteristics. The role of the high-frequency electromagnetic field is to adjust the charge distribution on the material surface, making it easier to interact with other materials. This treatment not only improves the surface activity but also enhances the bonding strength between materials. For example, in the design of 5G communication devices, the interface prefabricated layer after surface polarity regulation can significantly improve the bonding quality between the IC chip and the packaging structure, and its surface polarity value can increase to dozens of millicoulombs per square meter (such as 30 - 50 mC / m²), providing a good basis for subsequent precise alignment. Subsequently, atomic-scale bonding is used to perform precise alignment processing on the IC chip and the packaging structure, aiming to obtain an IC chip-packaging structure positioning structure with nanoscale accuracy. The atomic-scale bonding technology can achieve sub-nanometer alignment accuracy, ensuring an ideal electrical connection between the IC chip and the packaging structure. For example, in the design of artificial intelligence accelerators, precise positioning with an alignment error of no more than 10 nm can be achieved by this method, which not only improves the signal transmission efficiency but also enhances the mechanical stability. Then, the IC chip-packaging structure positioning structure is subjected to high-energy ion beam surface modification to obtain an IC chip-packaging structure bonding intermediate with multi-layer composite characteristics. High-energy ion beam surface modification uses ion beams to bombard the material surface, promoting atomic rearrangement to form a denser and more uniform structure. For example, during the manufacturing process of smart wearable devices, after high-energy ion beam surface modification, the bonding force between the IC chip and the packaging structure can increase to several hundred megapascals (such as 300 - 500 MPa), ensuring the overall reliability of the packaging structure. Finally, the interface of the IC chip-packaging structure bonding intermediate is strengthened by microwave plasma-assisted treatment to obtain an IC chip-packaging structure fixing matrix with a gradient structure. Microwave plasma-assisted treatment can further enhance the interface bonding strength without damaging the material.For example, in the packaging of high-end server chips, the fixed substrate after microwave plasma treatment can maintain good performance in extreme environments, and its interfacial bonding strength can reach millions of Newtons per square centimeter (such as 2-3 million N / cm²), significantly improving the durability of the packaging structure. Finally, the fixed substrate of the IC chip-packaging structure body is subjected to structural stabilization through vacuum annealing treatment, and finally the three-dimensional high-density interconnect packaging body is obtained. Vacuum annealing is an effective heat treatment method that eliminates internal stress by heating materials in a vacuum environment while avoiding problems such as oxidation. For example, during the long-term operation of data center servers, the packaging structure body treated by vacuum annealing can effectively relieve the thermal stress caused by temperature changes, and the thickness of its stress buffer layer can be controlled within dozens of micrometers (such as 20-40μm), thereby extending the service life of the device and improving reliability. In summary, through a series of precise processing steps for the packaging structure body and the IC chip, from radio frequency plasma surface activation treatment to vacuum annealing treatment, each link lays the foundation for the final formation of a high-quality three-dimensional high-density interconnect packaging body. The comprehensive application of these technologies not only improves the overall performance of electronic packaging but also provides technical support for future smaller and higher-performance electronic products. For example, in the construction of future data centers, this advanced packaging technology can significantly improve the working efficiency and energy efficiency ratio of servers, meeting the growing data processing requirements. In addition, by optimizing the technical details of each process step, the reliability and durability of the packaging structure body can be further improved to ensure its stable operation in complex environments. Especially in the field of high-performance computing, this packaging technology can not only reduce the device size but also significantly increase its functional density and operating efficiency, paving the way for more future innovative applications.

[0044] The three-dimensional high-density interconnect method between the substrate and the IC chip in the embodiments of the present invention has been described above. Next, the three-dimensional high-density interconnect system between the substrate and the IC chip in the embodiments of the present invention will be described. Please refer to Figure 2 , an embodiment of the three-dimensional high-density interconnect system between the substrate and the IC chip in the embodiments of the present invention includes: A composite module 21, configured to perform multi-layer dielectric composite processing on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio; A first filling module 22, configured to perform metal filling on the silicon through-hole array structure through bipolar pulse electroplating to obtain a three-dimensional interconnect conductive path; A surface treatment module 23, configured to perform surface treatment on the three-dimensional interconnect conductive path through a high-frequency ultrasonic-assisted electrochemical processing technology to obtain a micro-bump structure with gradient metallization; A bonding module 24, configured to perform laser-assisted bonding on the micro-bump structure to obtain a silicon bridge-substrate temporary structure; A second filling module 25, configured to perform underfilling on the silicon bridge-substrate temporary structure by means of supercritical fluid assisted injection technology to obtain a packaged structure with stress relief function; A fixing module 26, configured to assemble and fix a preset IC chip to the packaged structure to obtain a three-dimensional high-density interconnect package.

[0045] In this embodiment, for the specific implementation of each unit in the above system embodiment, please refer to the description in the above method embodiment, and details are not described herein again.

[0046] Refer to Figure 3 , this embodiment of the present invention also provides a computer device, the internal structure of which can be as Figure 3 shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor of the computer design is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program, when executed by the processor, implements the above method.

[0047] Those skilled in the art can understand that Figure 3 the structure shown in

[0048] is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0049] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium provided by the present invention and used in the embodiments can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0050] It should be noted that in this article, the terms "including", "comprising", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, device, article, or method including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, device, article, or method. Without further limitation, elements defined by the statement "including one..." do not exclude the existence of additional identical elements in the process, device, article, or method including such an element.

[0051] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the present invention, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A three-dimensional high-density interconnection method for a substrate and an IC chip, characterized in that It includes the following steps: Perform multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio; Perform metal filling on the silicon through-hole array structure by bipolar pulse electroplating to obtain a three-dimensional interconnect conductive path; Perform surface treatment on the three-dimensional interconnect conductive path by high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization; Perform laser-assisted bonding on the micro-bump structure to obtain a silicon bridge-substrate temporary structure; Perform underfilling on the silicon bridge-substrate temporary structure by supercritical fluid-assisted injection technology to obtain a packaged structure with stress release function; Assemble and fix a preset IC chip with the packaged structure to obtain a three-dimensional high-density interconnect package.

2. The three-dimensional high-density interconnection method of the substrate and the IC chip according to claim 1, characterized in that, The performing multi-layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through-hole array structure with a preset aspect ratio includes: Perform high-frequency electromagnetic field-assisted ion bombardment treatment on the silicon substrate to obtain an etched pretreatment layer with surface activation characteristics; Perform SF6 / O2 mixed gas directional etching on the etched pretreatment layer by a dual-frequency radio frequency source to obtain a silicon through-hole basic structure with anisotropic characteristics; Perform multi-layer dielectric composite treatment on the silicon through-hole basic structure by atomic layer deposition to obtain a silicon through-hole array structure with a preset aspect ratio, wherein the silicon through-hole array structure includes a first conductive layer, a second conductive layer, and an insulating dielectric layer located between the first conductive layer and the second conductive layer.

3. The three-dimensional high-density interconnection method of a substrate and an IC chip according to claim 1, wherein The performing metal filling on the silicon through-hole array structure by bipolar pulse electroplating to obtain a three-dimensional interconnect conductive path includes: Perform high-frequency magnetron sputtering treatment on the silicon through-hole array structure to obtain a metal seed layer structure with nanoscale roughness; Perform directional filling on the metal seed layer structure by bipolar pulse electroplating to obtain a metal filling body with a columnar crystal structure; Perform surface planarization treatment on the metal filling body by ultrasonic-assisted chemical mechanical polishing to obtain a conductive path base body with nanoscale flatness; Perform high-energy ion beam irradiation annealing on the conductive path base body to obtain the three-dimensional interconnect conductive path, wherein the three-dimensional interconnect conductive path includes vertical interconnect metal columns, horizontal interconnect metal layers, and a stress release buffer layer.

4. The three-dimensional high-density interconnection method for a substrate and an IC chip according to claim 1, wherein The performing surface treatment on the three-dimensional interconnect conductive path by high-frequency ultrasonic-assisted electrochemical treatment technology to obtain a micro-bump structure with gradient metallization includes: Perform high-frequency electrochemical impedance spectroscopy analysis treatment on the three-dimensional interconnect conductive path to obtain an activated pretreatment layer with surface electrochemical characteristics; Perform selective de-passivation treatment on the activated pretreatment layer by pulse reverse current to obtain a metallized base layer with directional growth characteristics; Perform gradient metallization treatment on the metallized base layer by alternating magnetic field-assisted electro-deposition to obtain a multi-layer metal composite structure; Perform high-energy plasma surface modification treatment on the multi-layer metal composite structure to obtain a surface functional layer with nanoscale roughness; Perform precise regulation on the surface functional layer by electrochemical atomic layer deposition to obtain an interface transition structure with controllable thickness; The surface of the interfacial transition structure is modified by a high-frequency ultrasonic-assisted electrochemical treatment technique to obtain a micro-bump structure with gradient metallization; wherein, the micro-bump structure includes a bottom metallization layer, an intermediate transition layer, and a surface functional layer.

5. The three-dimensional high-density interconnection method for a substrate and an IC chip according to claim 1, characterized in that The micro-bump structure is subjected to laser-assisted bonding to obtain a silicon bridge-substrate temporary structure, including: The surface of the micro-bump structure is pretreated by femtosecond laser to obtain a surface activation layer with a nano-scale periodic structure; The surface activation layer is precisely patterned by two-photon lithography to obtain a bonding preform layer with a micro-nano composite structure; The bonding preform layer is subjected to interfacial bonding by femtosecond laser-induced plasma bonding to obtain a primary bonding structure; The primary bonding structure is subjected to high-frequency surface acoustic wave-assisted treatment to obtain an interfacial enhancement layer with acousto-optic coupling characteristics; The interfacial enhancement layer is precisely positioned by near-field optical scanning to obtain a temporary fixing structure with multi-layer interconnection characteristics; The interface of the temporary fixing structure is strengthened by picosecond laser heat treatment to obtain the silicon bridge-substrate temporary structure, wherein the silicon bridge-substrate temporary structure includes a multi-layer interconnection region, a stress buffer region, and an interfacial transition region.

6. The three-dimensional high-density interconnection method of a substrate and an IC chip according to claim 1, characterized in that The bottom of the silicon bridge-substrate temporary structure is filled by a supercritical fluid-assisted injection technique to obtain a packaging structure with stress release function, including: The surface of the silicon bridge-substrate temporary structure is modified by plasma surface modification to obtain a surface activation structure with super-hydrophilic characteristics; The surface activation structure is coated with a precursor by vacuum plasma-assisted chemical vapor deposition to obtain a filling guiding layer with a nano-porous structure; The filling guiding layer is bottom-filled by a supercritical fluid-assisted injection technique to obtain a primary filling structure; The primary filling structure is cured by microwave plasma curing to obtain a cured matrix with a cross-linked network structure; The interface of the cured matrix is strengthened by high-frequency electromagnetic field-assisted treatment to obtain a reinforced structure with multi-layer composite characteristics; The stress of the reinforced structure is released by vacuum annealing treatment to obtain the packaging structure, wherein the packaging structure includes a thermal stress buffer layer, an interfacial enhancement layer, and a sealing protection layer.

7. The three-dimensional high-density interconnection method for a substrate and an IC chip according to claim 1, wherein A preset IC chip is assembled and fixed to the packaging structure to obtain a three-dimensional high-density interconnection package, including: The packaging structure and the IC chip are respectively subjected to radio frequency plasma surface activation treatment to obtain an activation pretreatment layer with high surface energy; The surface polarity of the activation pretreatment layers of the IC chip and the packaging structure is regulated by high-frequency electromagnetic field assistance to obtain an interface preform layer with directional bonding characteristics; The IC chip and the packaging structure are precisely aligned by atomic-scale bonding to obtain an IC chip-packaging structure positioning structure with nano-scale accuracy; The surface of the IC chip-packaging structure positioning structure is modified by high-energy ion beam to obtain an IC chip-packaging structure bonding intermediate with multi-layer composite characteristics; The bonding intermediate of the IC chip - package structure is subjected to interface strengthening through microwave plasma - assisted treatment to obtain a fixed substrate of the IC chip - package structure with a gradient structure; The fixed substrate of the IC chip - package structure is subjected to structure stabilization through vacuum annealing treatment to obtain the three - dimensional high - density interconnect package body, wherein the three - dimensional high - density interconnect package body includes a chip interconnect layer, a signal transmission layer, and a heat dissipation functional layer.

8. A three-dimensional high-density interconnection system for a substrate and an IC chip, characterized in that, Comprising: A composite module for performing multi - layer dielectric composite treatment on a preset silicon substrate to obtain a silicon through - hole array structure with a preset aspect ratio; A first filling module for performing metal filling on the silicon through - hole array structure through bipolar pulse electroplating to obtain three - dimensional interconnect conductive paths; A surface treatment module for performing surface treatment on the three - dimensional interconnect conductive paths through a high - frequency ultrasonic - assisted electrochemical treatment technique to obtain a micro - bump structure with gradient metallization; A bonding module for performing laser - assisted bonding on the micro - bump structure to obtain a silicon bridge - substrate temporary structure; A second filling module for performing bottom filling on the silicon bridge - substrate temporary structure through supercritical fluid - assisted injection technology to obtain a package structure with a stress - release function; A fixing module for assembling and fixing a preset IC chip with the package structure to obtain a three - dimensional high - density interconnect package body.

9. A computer device, comprising a memory and a processor, wherein a computer program is stored in the memory, characterized in that When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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