Silver-gold alloy bump structure, preparation method thereof and semiconductor device

Abstract

The embodiment of the invention provides a silver-gold alloy bump structure, a preparation method of the silver-gold alloy bump structure and a semiconductor device. Providing a semiconductor device; sequentially forming a TiW seed layer and an Au seed layer on the welding pad of the semiconductor device; forming a barrier layer on the Au seed layer; forming a silver-gold alloy bump on the barrier layer; wherein the blocking layer is used for blocking metal silver in the silver-gold alloy bump from diffusing to the Au seed layer. In the preparation process of the silver-gold alloy bump structure, the barrier layer is formed on the Au seed layer and then the silver-gold alloy bump is formed on the barrier layer, and the barrier layer can prevent metal silver in the silver-gold alloy bump from diffusing to the Au seed layer, so that the problem of poor binding force between the silver-gold alloy bump and the seed layer is solved; the reliability of the silver-gold alloy bump structure is improved, and the reliability of the semiconductor device is further improved.

Description

Technical Field

[0001] Embodiments of the present disclosure belong to the technical field of semiconductor packaging, and specifically relate to a silver-gold alloy bump structure, a preparation method thereof, and a semiconductor device. Background Art

[0002] Traditional chip packaging uses leads to achieve electrical connection between the chip PAD and the frame, while advanced packaging uses bumps to replace the leads for connection, thereby shortening the current path and physical size, and achieving advantages such as reduced size, high I / O density, high-frequency operation, and low parasitic inductance.

[0003] Currently, common bump metals include gold, copper, and copper-nickel-gold, etc. Among them, gold bumps are widely used in the field of display driver packaging due to their excellent stability, conductivity, and thermal conductivity, but gold bumps have the problem of excessively high cost.

[0004] Silver-gold alloy bumps are a development direction as an alternative material to gold bumps due to their excellent conductivity, thermal conductivity, and relatively low cost.

[0005] In the current silver-gold alloy bump structure, the bumps cannot operate for a long time in a high-temperature environment during the testing process. The bonding force between the bumps and the seed layer is poor under high-temperature conditions, and cracks will occur in the bottom seed layer.

[0006] The seed layer of the existing silver-gold alloy bump structure is composed of a TiW layer and an Au layer. However, the bonding force between TiW and Au is strong, and an oxide layer of temperature has formed on the surface of the titanium alloy. The high ductility of Au can penetrate into the oxide layer to form a strong bonding interface. The actual reason for the crack generation is that Ag diffuses to the interface between the Au layer and the TiW layer under high-temperature baking. The bonding force between Ag and W is poor, and the oxide layer of Ag will reduce the interfacial wettability, resulting in insufficient bonding strength. Under temperature changes, cracks are formed due to the difference in the coefficient of thermal expansion of metals.

[0007] Due to the limitations of the metal properties of Ag, simply adjusting the ratio of the silver-gold alloy is difficult to completely improve the bonding force and the difference in the coefficient of thermal expansion between Ag and TiW. Among the existing bump solutions, using silver-gold is the best option considering the comprehensive cost and performance. Using a pure gold solution has too high a cost, and pure copper and copper-nickel-gold solutions have too poor corrosion resistance.

[0008] In view of the above problems, it is necessary to propose a silver-gold alloy bump structure, a preparation method thereof, and a semiconductor device that are reasonably designed and can effectively solve the above problems. Summary of the Invention

[0009] Embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art, and provide a silver-gold alloy bump structure, a preparation method thereof, and a semiconductor device.

[0010] One aspect of the embodiments of the present disclosure provides a method for fabricating a silver-gold alloy bump structure, the method comprising:

[0011] Providing a semiconductor device;

[0012] Successively forming a TiW seed layer and an Au seed layer on the bonding pad of the semiconductor device;

[0013] Forming a barrier layer on the Au seed layer;

[0014] Forming a silver-gold alloy bump on the barrier layer; wherein the barrier layer is used to prevent the metal silver in the silver-gold alloy bump from diffusing into the Au seed layer.

[0015] Optionally, forming the barrier layer on the Au seed layer includes:

[0016] Electroplating a Pd barrier layer on the Au seed layer.

[0017] Optionally, the thickness range of the formed Pd barrier layer is 0.2 μm to 2 μm.

[0018] Optionally, forming the silver-gold alloy bump on the barrier layer includes:

[0019] Electroplating the silver-gold alloy bump on the Pd barrier layer, wherein the gold content range in the silver-gold alloy bump is 10% to 30%.

[0020] Optionally, the thickness range of the formed silver-gold alloy bump is 3 μm to 20 μm.

[0021] Another aspect of the embodiments of the present disclosure provides a silver-gold alloy bump structure, comprising:

[0022] A TiW seed layer for being disposed on the bonding pad of a semiconductor device;

[0023] An Au seed layer disposed on the TiW seed layer;

[0024] A barrier layer disposed on the Au seed layer;

[0025] A silver-gold alloy bump disposed on the barrier layer, wherein the barrier layer is used to prevent the metal silver in the silver-gold alloy bump from diffusing into the Au seed layer.

[0026] Optionally, the barrier layer is a Pd barrier layer.

[0027] Optionally, the thickness range of the Pd barrier layer is 0.2 μm to 2 μm.

[0028] Optionally, the gold content in the silver-gold alloy bump ranges from 10% to 30%, and the thickness of the silver-gold alloy bump ranges from 3 μm to 20 μm.

[0029] Another aspect of the embodiments of the present disclosure provides a semiconductor device, including the silver-gold alloy bump structure described above.

[0030] In the silver-gold alloy bump structure and its preparation method and semiconductor device according to the embodiments of the present disclosure, during the preparation process of the silver-gold alloy bump structure, after forming a barrier layer on the Au seed layer, a silver-gold alloy bump is formed on the barrier layer. The barrier layer can prevent the metal silver in the silver-gold alloy bump from diffusing to the Au seed layer, improve the problem of poor bonding force between the silver-gold alloy bump and the seed layer, improve the reliability of the silver-gold alloy bump structure, and further improve the reliability of the semiconductor device. Description of the Drawings

[0031] Figure 1 It is a schematic flowchart of a method for preparing a silver-gold alloy bump structure according to an embodiment of the present disclosure;

[0032] Figures 2 to 8 It is a schematic diagram of a preparation process of a silver-gold alloy bump structure according to another embodiment of the present disclosure;

[0033] Figure 9 It is a schematic structural diagram of a silver-gold alloy bump structure according to another embodiment of the present disclosure. Detailed Embodiments

[0034] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following further describes the embodiments of the present disclosure in detail with reference to the drawings and specific embodiments.

[0035] As Figure 1 shown, one aspect of the embodiments of the present disclosure provides a method S100 for preparing a silver-gold alloy bump structure, and the method S100 includes:

[0036] S110. Provide a semiconductor device.

[0037] As Figure 2 shown, provide a semiconductor device 200. Specifically, in this embodiment, the semiconductor device 200 is described by taking a chip as an example. As Figure 2 shown, a solder pad 210 and a passivation layer 220 are provided on the functional surface of the chip, and among them, the passivation layer 220 has an opening corresponding to the solder pad 210.

[0038] S120. Sequentially form a TiW seed layer and an Au seed layer on the solder pad of the semiconductor device.

[0039] As Figure 3As shown, a TiW seed layer 110 is formed in the passivation layer 220 and the opening window by sputtering. Among them, the thickness range of the TiW seed layer 110 is

[0040] Then, an Au seed layer 120 is formed on the TiW seed layer 110 by sputtering. Among them, the thickness range of the Au seed layer 120 is

[0041] It should be noted that the TiW seed layer 110 can also be replaced by a Ti seed layer.

[0042] S130. Form a barrier layer on the Au seed layer.

[0043] First, a photoresist layer 130 is formed on the Au seed layer 120.

[0044] Specifically, as Figure 4 shown, a photoresist layer 130 is coated on the Au seed layer 120. Among them, the photoresist layer 130 can be a positive photoresist or a negative photoresist, which can be selected according to actual needs and is not specifically limited in this embodiment.

[0045] Secondly, the photoresist layer 130 is exposed and developed to form an opening 131 in the photoresist layer 130.

[0046] Specifically, as Figure 5 shown, a mask plate is provided and placed above the photoresist layer 130. Using the mask plate as a mask, the photoresist layer 130 is exposed and developed to form an opening 131 at the position corresponding to the solder pad 210 in the photoresist layer 130.

[0047] Thirdly, a barrier layer 140 is formed at the opening 131 by electroplating.

[0048] In this embodiment, the barrier layer 140 is preferably a Pd barrier layer. That is to say, as Figure 6 shown, a Pd barrier layer is formed at the opening 131 by palladium electroplating. The formed Pd barrier layer can better prevent the metal silver in the silver-gold alloy bump 150 from diffusing into the Au seed layer 120.

[0049] It should be noted that in this embodiment, the reason for using the Pd barrier layer for the barrier layer 140 is as follows: As shown in Tables 1 and 2, the lattice matching degree of Au and Ag is extremely high, and the two metals can be completely mutually soluble, resulting in a relatively fast diffusion between the silver-gold alloy bump 150 and the Au seed layer 120; the lattice matching degree of Pd and Ag / Au is medium, and the metals can be partially mutually soluble, the diffusion rate is relatively slow, and the bonding force is also slightly poor, but the bonding force is better than that of Au-TiW and can meet the packaging requirements. In addition, the Pd element has good electrical conductivity, thermal conductivity, and corrosion resistance, which are relatively close to those of Au, ensuring the packaging performance of the silver-gold alloy bump structure.

[0050] Table 1 Comparison of lattice constants of three metal elements

[0051]

[0052] Table 2 Comparison of bonding forces between different metal pairs

[0053] Metal pair Lattice mismatch degree Miscibility Bonding strength Ag - Au 0.5％ Completely miscible Strongest Ag - Pd 8％ Partially miscible Medium Au - Pd 8％ Partially miscible Medium Au - TiW 24％ Low miscibility Poor

[0054] Exemplarily, in this embodiment, the thickness range of the formed Pd barrier layer is 0.2 μm to 2 μm. Among them, the thickness of the Pd barrier layer needs to be higher than 0.2 μm to ensure the barrier performance against Ag. At the same time, it cannot be higher than 2 μm to avoid excessive stress in the Pd barrier layer, resulting in damage to the bottom passivation layer and reducing costs.

[0055] S140. Form a silver-gold alloy bump on the barrier layer; wherein, the barrier layer is used to block the diffusion of metallic silver in the silver-gold alloy bump to the Au seed layer.

[0056] As Figure 7 shown, the silver-gold alloy bump 150 is electroplated on the Pd barrier layer by using a silver-gold alloy electroplating process.

[0057] It should be noted that compared with the normal gold bump process, the silver-gold alloy bump 150 needs to be electroplated with two different plating solutions. The two plating solutions need to be produced on the same electroplating machine to avoid cross-contamination between different metal layers. At the same time, there is a risk of cross-contamination between these two plating solutions, and a gas isolation design needs to be carried out between different plating tanks of the electroplating machine.

[0058] Since the properties of Ag are similar to those of Au and more active, a suitable etching solution needs to be selected for the etching of the Au seed layer 120 to ensure that the etching selectivity of the etching solution for the Au seed layer 120 is higher than that for the silver-gold alloy and Pd.

[0059] Due to the catalytic effect of Ag and Pd on the titanium-tungsten etching solution at high temperatures, the operating temperature of the titanium-tungsten etching solution needs to be controlled below 50 °C.

[0060] Exemplarily, the gold content in the formed silver-gold alloy bump 150 ranges from 10% to 30%. If the Au content is too high, the hardness of the silver-gold alloy bump 150 will be too high and the morphology will be too rough. If the Au content is too low, the hardness of the silver-gold alloy bump 150 will be too low. Therefore, the gold content in the silver-gold alloy bump 150 is controlled to be 10% to 30% to control the hardness and morphology of the silver-gold alloy bump 150.

[0061] Table 3 shows the hardness of the silver-gold alloy bump 150 corresponding to different gold contents. Since the general requirement for hardness in the COG chip packaging of the display driver IC is 90 ± 20 HV, it is recommended to select the gold content in the silver-gold alloy bump 150 between 10% and 30%. If there are other packaging hardness requirements in the future, the gold content range can be adjusted.

[0062] Table 3 Hardness of silver-gold alloy bump corresponding to different gold contents

[0063] Gold content Hardness 10％ 73HV 15％ 76HV 20％ 100HV 30％ 112HV 50％ 160HV

[0064] Exemplarily, in this embodiment, the thickness of the formed silver-gold alloy bump 150 ranges from 3 μm to 20 μm.

[0065] Exemplarily, after forming the silver-gold alloy bump 150 on the barrier layer 140, the method further includes:

[0066] Removing part of the TiW seed layer 110 and the Au seed layer 120 so that the remaining seed layer is only connected to the barrier layer 140.

[0067] As Figure 8 shown, first, the remaining photoresist layer 130 can be removed by processes such as etching.

[0068] Secondly, part of the TiW seed layer 110 and the Au seed layer 120 can be removed by processes such as etching so that the remaining seed layer is only connected to the Pd barrier layer, preventing short circuits due to the presence of seed layers in other positions of the semiconductor device 200 and affecting the reliability of the semiconductor device 200.

[0069] Thirdly, the silver-gold alloy bump 150 is annealed so that the hardness of the formed silver-gold alloy bump structure 100 reaches the preset hardness, forming the silver-gold alloy bump structure 100 as Figure 9 shown.

[0070] The method for preparing a silver-gold alloy bump structure according to an embodiment of the present disclosure forms a barrier layer on the Au seed layer and then forms a silver-gold alloy bump on the barrier layer during the preparation of the silver-gold alloy bump structure. The barrier layer can prevent the metal silver in the silver-gold alloy bump from diffusing into the Au seed layer, improve the problem of poor bonding force between the silver-gold alloy bump and the seed layer, improve the reliability of the silver-gold alloy bump structure, and further improve the reliability of the semiconductor device.

[0071] As Figure 9 shown, on the other hand, an embodiment of the present disclosure provides a silver-gold alloy bump structure 100, including a TiW seed layer 110, an Au seed layer 120, a barrier layer 140, and a silver-gold alloy bump 150.

[0072] The TiW seed layer 110 is used to be disposed on the solder pad 210 of the semiconductor device 200.

[0073] The Au seed layer 120 is disposed on the TiW seed layer 110.

[0074] The barrier layer 140 is disposed on the Au seed layer 120.

[0075] The silver-gold alloy bump 150 is disposed on the barrier layer 140, wherein the barrier layer 140 is used to prevent the metal silver in the silver-gold alloy bump 150 from diffusing into the Au seed layer 120.

[0076] In the silver-gold alloy bump structure according to an embodiment of the present disclosure, by providing a barrier layer between the Au seed layer and the silver-gold alloy bump 150, the barrier layer can prevent the metal silver in the silver-gold alloy bump from diffusing into the Au seed layer, improve the problem of poor bonding force between the silver-gold alloy bump and the seed layer, improve the reliability of the silver-gold alloy bump structure, and further improve the reliability of the semiconductor device.

[0077] Exemplarily, in this embodiment, the barrier layer 140 can be a Pd barrier layer. The Pd barrier layer can better prevent the metal silver in the silver-gold alloy bump 150 from diffusing into the Au seed layer 120.

[0078] The lattice matching degree between Pd and Ag / Au is medium, the metals can be partially miscible with each other, the diffusion rate is relatively slow, and the bonding force is also slightly poor, but the bonding force is better than that of Au-TiW, which can meet the packaging requirements. In addition, the Pd barrier layer has good electrical conductivity, thermal conductivity, and corrosion resistance, which are relatively close to those of the Au seed layer 120, ensuring the packaging performance of the silver-gold alloy bump structure 100.

[0079] Exemplarily, in this embodiment, the thickness range of the Pd barrier layer is 0.2 μm to 2 μm. Among them, the thickness of the Pd barrier layer needs to be higher than 0.2 μm to ensure the barrier performance against Ag. At the same time, it cannot be higher than 2 μm to avoid excessive stress in the Pd barrier layer, which may cause damage to the bottom passivation layer and reduce costs.

[0080] Exemplarily, in this embodiment, the gold content in the silver-gold alloy bump 150 ranges from 10% to 30%, and the thickness range of the silver-gold alloy bump 150 is 3 μm to 20 μm to control the hardness and morphology of the silver-gold alloy bump 150.

[0081] The silver-gold alloy bump structure 100 is subjected to a reliability test, and the reliability test results are shown in Table 4. It can be seen from Table 4 that the silver-gold alloy bump structure 100 of the present disclosure embodiment has high reliability and can meet the reliability requirements of chip packaging.

[0082] Table 4 Reliability test results of the silver-gold alloy bump structure

[0083]

[0084] Another aspect of the present disclosure embodiment provides a semiconductor device, including the silver-gold alloy bump structure 100 described above. The structural features of the silver-gold alloy bump structure 100 have been described in detail above and will not be repeated here.

[0085] It should be noted that the semiconductor device can be a chip or the like. The type of the semiconductor device is not specifically limited in this embodiment and can be selected according to actual needs.

[0086] The semiconductor device of the present disclosure embodiment adopts the silver-gold alloy bump structure described above, which improves the reliability of the semiconductor device.

[0087] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure embodiments. However, the present disclosure embodiments are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure embodiments, and these modifications and improvements are also regarded as the protection scope of the present disclosure embodiments.

Claims

1. A preparation method of a silver-gold alloy bump structure, characterized in that, The method includes: providing a semiconductor device; successively forming a TiW seed layer and an Au seed layer on a pad of the semiconductor device; forming a barrier layer on the Au seed layer; forming a silver-gold alloy bump on the barrier layer; wherein, the barrier layer is used to prevent the metal silver in the silver-gold alloy bump from diffusing into the Au seed layer.

2. The method according to claim 1, characterized in that, The forming of the barrier layer on the Au seed layer includes: electroplating to form a Pd barrier layer on the Au seed layer.

3. The method according to claim 2, characterized in that, The thickness range of the formed Pd barrier layer is 0.2 μm to 2 μm.

4. The method according to claim 2, characterized in that, The forming of the silver-gold alloy bump on the barrier layer includes: electroplating to form the silver-gold alloy bump on the Pd barrier layer, wherein the gold content range in the silver-gold alloy bump is 10% to 30%.

5. The method according to claim 4, wherein The thickness range of the formed silver-gold alloy bump is 3 μm to 20 μm.

6. A silver-gold alloy bump structure, characterized in that, including: a TiW seed layer, for being disposed on a pad of a semiconductor device; an Au seed layer, disposed on the TiW seed layer; a barrier layer, disposed on the Au seed layer; a silver-gold alloy bump, disposed on the barrier layer, wherein the barrier layer is used to prevent the metal silver in the silver-gold alloy bump from diffusing into the Au seed layer.

7. The silver-gold alloy bump structure according to claim 6, wherein The barrier layer is a Pd barrier layer.

8. The silver-gold alloy bump structure according to claim 7, wherein The thickness range of the Pd barrier layer is 0.2 μm to 2 μm.

9. The silver-gold alloy bump structure according to claim 6, wherein, The gold content range in the silver-gold alloy bump is 10% to 30%, and the thickness range of the silver-gold alloy bump is 3 μm to 20 μm.

10. A semiconductor device, characterized in that, including the silver-gold alloy bump structure according to any one of claims 6 to 9.

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